JP5118875B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting device including a semiconductor layer including a photoactive layer, and a method for manufacturing such a semiconductor light emitting device.

  A semiconductor light emitting element is an element that generates light in a photoactive layer and outputs the light. Among them, a semiconductor light emitting device having a ridge portion on a semiconductor layer including a photoactive layer is selected at a lower portion of the ridge portion in the photoactive layer, with the upper surface of the ridge portion being electrically connected to the electrode. A light emitting part is generated. In addition, a plurality of ridge portions may be arranged in parallel on the semiconductor layer with a groove portion interposed therebetween (see Patent Document 1). Such a semiconductor light emitting element including a plurality of ridges arranged in parallel is used in, for example, a laser printer.

Compared with a buried structure in which a photoactive region has a waveguide structure and is embedded in a semiconductor layer, a ridge-type semiconductor light emitting device is easy to manufacture and can be reduced in cost. The emission width is about several μm, and the horizontal spread angle of the emitted light is as small as about 10 degrees. Also, compared to the case where bump connection is made to the submount with junction down, when the submount is assembled with junction up and wire connection is made, stress during connection is avoided, and the emitted light is Polarization characteristics are stable.
JP-A-11-135893

  In a semiconductor light emitting device that includes a plurality of ridge portions arranged in parallel and is assembled in a junction-up manner, an electrode pad portion for wire connection is provided on the semiconductor layer corresponding to each ridge portion. The electrode pad is usually provided outside the peripheral region of the semiconductor chip, that is, the plurality of ridge portions arranged in parallel. When the first ridge portion and the second ridge portion are referred to in order from the electrode pad portion among the plurality of ridge portions, the electrical wiring between the electrode pad portion corresponding to the second ridge portion and the second ridge portion is as follows. Thus, the first ridge portion and the element isolation groove existing between the two are provided.

  However, the undesired portion is electrically connected to the electric wiring layer to be connected to the second ridge portion because the insulating layer is peeled off at the undesired portion during the manufacturing process or a film formation failure occurs. May end up. In this case, in the photoactive layer, a light emitting portion is generated at the same time not only under the second ridge portion but also under the undesired portion. And the beam quality of the light output from the semiconductor light emitting device is deteriorated.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor light emitting device capable of suppressing light emission under an undesired portion. Moreover, it aims at providing the method which can manufacture such a semiconductor light-emitting device.

A semiconductor light emitting device according to the present invention is provided in parallel with each other, a semiconductor layer formed on a substrate and including a photoactive layer, an electrode pad portion provided on the semiconductor layer, and a groove portion on the semiconductor layer. And a plurality of ridge portions including a first ridge portion and a second ridge portion in order from the electrode pad portion. The semiconductor light emitting device according to the present invention includes (1) a side wall surface of one adjacent ridge portion to a side wall surface of the other ridge portion among the plurality of ridge portions, and the electrode pad portion side of the first ridge portion. A first insulating layer formed from the side wall surface to the electrode pad portion, and (2) a first metal formed from the bottom surface of the groove portion on one side to the bottom surface of the groove portion on the other side across each of the plurality of ridge portions. A layer, (3) a second insulating layer formed from the bottom of the groove on the electrode pad side of the second ridge to the electrode pad, and (4) a groove on the opposite side of the electrode pad from the second ridge And a second metal layer formed from the bottom surface to the electrode pad portion in order. Further, in the semiconductor light emitting device according to the present invention, the second metal layer is electrically connected to the upper surface of the second ridge portion via the first metal layer, and between the first ridge portion and the second ridge portion. Each of the first metal layer and the second insulating layer electrically connected to the second ridge portion overlaps each other on the bottom surface of the groove portion. Further, it is preferable that an element isolation groove reaching the substrate is formed on the bottom surface of the groove portion, and the first insulating layer and the second insulating layer are formed on the inner wall surface and the bottom surface of the element isolation groove.

A method of manufacturing a semiconductor light emitting device according to the present invention includes: a semiconductor layer formed on a substrate and including a photoactive layer; an electrode pad portion provided on the semiconductor layer; and a semiconductor layer on the semiconductor layer in order from the electrode pad portion. A method of manufacturing a semiconductor light emitting device including a plurality of ridge portions including a first ridge portion and a second ridge portion and arranged in parallel with each other across a groove portion, and (1) adjacent to the plurality of ridge portions A first insulating layer that forms a first insulating layer from the side wall surface of the matching ridge portion to the side wall surface of the other ridge portion and from the side wall surface of the first ridge portion on the electrode pad portion side to the electrode pad portion, respectively. And (2) a first metal layer forming step for forming a first metal layer from the bottom surface of the groove portion on one side to the bottom surface of the groove portion on the other side across each of the plurality of ridge portions, and (3) a second ridge. Electrode pad from the bottom of the groove on the electrode pad side Until, at the bottom of the trench between the first ridge portion and the second ridge portion, the second forming a second insulating layer a first metal layer and a part electrically connected to the second ridge portion overlap each other 2 (4) electrically connected to the upper surface of the second ridge portion through the first metal layer from the bottom surface of the groove portion on the opposite side of the electrode pad portion side of the second ridge portion to the electrode pad portion; And a second metal layer forming step of forming the second metal layer. In addition, after forming the element isolation groove reaching the substrate at the bottom surface of the groove portion, the first insulating layer forming step, the first metal layer forming step, the second insulating layer forming step, and the second metal layer forming step are sequentially performed. In the insulating layer forming step, it is preferable to form the first insulating layer also on the inner wall surface and the bottom surface of the element isolation groove, and in the second insulating layer forming step, it is preferable to form the second insulating layer also on the inner wall surface and the bottom surface of the element isolation groove. It is.

  The present invention provides a second metal layer to be electrically connected to the second ridge portion when the first ridge portion and the second ridge portion are formed in order from the electrode pad portion, and below the second metal layer The first insulating layer, the first metal layer, and the second insulating layer in FIG.

  In the first insulating layer forming step, the first insulating layer can be removed at least on the upper surface of each ridge portion by exposing and developing the resist by the self-alignment method. At this time, the first insulating layer is formed even in an undesired portion. May be removed. However, in the subsequent second insulating layer forming step, the second insulating layer can be formed in a predetermined region by using a mask having a predetermined pattern instead of the self-alignment method and exposing and developing the resist. The desired portion is covered with the second insulating layer.

  Further, in the second insulating layer forming step, since the partial region of the second insulating layer overlaps with the partial region of the first metal layer on the bottom surface of the groove, removal of the first insulating layer is prevented. Therefore, it is avoided that the second metal layer is electrically connected to the semiconductor layer.

  Further, since the second metal layer is formed, peeling of the second insulating layer from the first metal layer is prevented. In addition, if the second metal layer is a metal film having a plurality of layers and the lowermost layer is a Ti film, the adhesion between the second insulating layer and the second metal layer is good. Peeling is further prevented.

  According to the present invention, it is possible to suppress the emission of light below an undesired portion.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a perspective view of a semiconductor light emitting device 1 according to this embodiment. FIG. 2 is a plan view of the semiconductor light emitting device 1 according to the present embodiment. The semiconductor light-emitting device 1 shown in FIG. 1 is assembled in a junction-up on the sub-mount 2, a metal layer _{72d 4} on the electrode pads 41 and 42 and the wire ₃ 1 to 3 ₄ It is connected. Each metal layer _{72d 4} has a substantially rectangular pattern when viewed in plan view.

The semiconductor light emitting device 1 includes four ridge portions 31 to 34 provided in parallel on a semiconductor layer formed on a substrate and including a photoactive layer, and a peripheral region of the semiconductor chip on the ridge portion 31 side. The electrode pad portion 41 is provided, and the electrode pad portion 42 is provided in the peripheral region of the semiconductor chip on the ridge portion 34 side. Metal layer 74 ₁ is electrically connected to the semiconductor layer at the ridge portion 31, it is wire 3 ₁ electrically connected to the electrode pad portion 41. Metal layer 74 ₂ is electrically connected to the semiconductor layer at the ridge portion 32, it is wire 3 ₂ electrically connected to the electrode pad portion 41. The metal layer ₇₄₃ is electrically connected to the semiconductor layer at the ridge portion 33, it is wire 3 ₃ electrically connected to the electrode pad portion 42. The metal layer 74 ₄ is electrically connected to the semiconductor layer at the ridge portion 34, it is wire 3 ₄ electrically connected to the electrode pad portion 42.

  The semiconductor light emitting device 1 includes a groove 51 provided between the electrode pad 41 and the ridge 31, a groove 52 provided between the ridge 31 and the ridge 32, and the ridge 32 and ridge. A groove 53 provided between the ridge 33, a groove 54 provided between the ridge 33 and the ridge 34, a groove 55 provided between the ridge 34 and the electrode pad 42, Is provided. Further, the semiconductor light emitting element 1 is provided in the element isolation layer 61 provided in the groove 51, the element isolation layer 62 provided in the groove 52, the element isolation layer 63 provided in the groove 53, and the groove 54. An element isolation layer 64 and an element isolation layer 65 provided in the groove 55 are provided. The electrode pad portions 41 and 42 are higher than the adjacent groove portions 51 and 55 in this embodiment, but may be the same height as the groove portions 51 and 55.

  The semiconductor light emitting device 1 has a symmetrical structure with a central device isolation layer 63 as the center. Therefore, hereinafter, the cross-sectional structure and the manufacturing method will be mainly described between the central element isolation layer 63 and the electrode pad portion 41.

  FIG. 3 is a cross-sectional view of the semiconductor light emitting device 1 according to this embodiment. FIG. 2A shows a cross section along the line AA in FIG. FIG. 2B shows a cross section along the line BB in FIG.

  As shown in FIGS. 3A and 3B, the semiconductor light emitting device 1 includes an n-type cladding layer 12, a photoactive layer 13, and a p-type cladding layer 14 on one main surface of the n-type substrate 10. The semiconductor layer 11 is formed in order, and the p-type cap layers 21 to 23 are formed on the semiconductor layer 11. A metal layer 15 is formed on the other main surface of n-type substrate 10.

  Each of the cap layers 21 to 23 is provided so as to extend in a direction in which two opposing end surfaces of the substrate 10 are connected to each other, and the upper surface is substantially flat and the heights are substantially equal to each other. Each of the cap layers 21 to 23 extends in a direction perpendicular to the two opposite end surfaces of the substrate 10. Among them, the cap layer 21 is an element constituting the ridge portion 31. The cap layer 22 is an element constituting the ridge portion 32. The cap layer 23 is an element constituting the electrode pad portion 41. The ridge portions 31 to 34 may have an inverted mesa shape or a forward mesa shape.

  A groove portion 51 is provided between the electrode pad portion 41 and the ridge portion 31. Further, a groove portion 52 is provided between the ridge portion 31 and the ridge portion 32. Each of the grooves 51 to 55 has a substantially flat bottom surface and a substantially equal depth. In addition, element isolation grooves 61 to 65 reaching the substrate 10 are formed on the bottom surfaces of the groove portions 51 to 55. These element isolation grooves 61 to 65 extend in parallel with the extending direction of each ridge portion.

  For example, the composition of the n-type substrate 10 is GaAs. The n-type cladding layer 12 has a composition of AlGaAs and a thickness of 1.0 μm. The photoactive layer 13 has a composition of AlGaAs and a thickness of 0.1 μm. The p-type cladding layer 14 is composed of AlGaAs and has a thickness of 1.0 μm. The p-type cap layers 21 to 23 have a composition of GaAs and a thickness of 1.0 μm. The width of the upper surface of each of the ridge portions 31 to 34 is 10 μm, and the width of the lower portion is 8 μm. Moreover, the width | variety of each bottom face of the groove parts 51-55 is 20 micrometers.

In the configuration of the semiconductor light emitting device 1 including the ridge portions 31 to 34 and the electrode pad portions 41 and 42, a first insulating layer 71, a first metal layer 72, a second insulating layer 73, and a second insulating layer 71 are further formed thereon. A metal layer 74 is formed in order. However, the p-type cap layer 21 electrically connected to the second metal layer 74 _first part of the cross section (cross section taken along the line A-A in FIG. 2) in the ridge section 31, p-type in the ridge portion 32 in the electrically connected to the second metal layer 74 _second part of the cross section (cross section taken along the line B-B in FIG. 2) in the cap layer 22, configuration is different.

  As shown in FIG. 3A, in the cross section taken along the line AA in FIG. 2, the first insulating layer 71 is a side wall surface of one of the adjacent ridge portions among the four ridge portions 31 to 34. From the side wall surface of the ridge portion 31 on the electrode pad portion 41 side to the electrode pad portion 41, and the side of the ridge portion 34 on the electrode pad portion 42 side. It is formed from the wall surface to the electrode pad portion 42. The first insulating layer 71 is also formed on the inner wall surface and the bottom surface of each of the element isolation grooves 61 to 65. The first insulating layer 71 is not formed on the upper surfaces of the ridge portions 31 to 34.

  The first metal layer 72 is formed from the bottom surface of the groove portion on one side to the bottom surface of the groove portion on the other side across the four ridge portions 31 to 34. That is, the first metal layer 72 is formed on each of the upper surfaces and both side wall surfaces of the four ridge portions 31 to 34 and a part of the bottom surface of the groove portion that continues from the side wall surfaces. The first metal layer 72 is not formed on the inner wall surface and the bottom surface of each of the element isolation grooves 61 to 65.

  The second insulating layer 73 is formed from the bottom surface of the groove portion 52 on the electrode pad portion 41 side of the ridge portion 32 to the electrode pad portion 41, and from the bottom surface of the groove portion 54 on the electrode pad portion 42 side of the ridge portion 33 to the electrode. The pad part 42 is formed. The second insulating layer 73 is also formed on the inner wall surface and the bottom surface of each of the element isolation grooves 61 to 65. The second insulating layer 73 is not formed on the upper surface and both side wall surfaces of the ridge portions 32 and 33 and a part of the bottom surface of the groove portion continuing from the side wall surface.

The second metal layer 74 ₂ is formed from the bottom surface of the electrode pad portion 41 side and the opposite side of the groove 53 of the ridge portion 32 to the electrode pad portion 41, and the second metal layer 74 _2, the ridge portion 33 The electrode pad portion 42 is formed from the bottom surface of the groove portion 53 on the opposite side to the electrode pad portion 42 side. The second metal layer 74 ₂ has been also formed on the inner wall surface and the bottom surface of each element isolation trench 61,62,64,65, it is not formed in the inner wall surface and the bottom surface of the isolation trench 63.

The second metal layer 74 ₂ is electrically connected to the upper surface of the p-type cap layer 22 of the ridge portion 32 through the first metal layer 72. However, the second metal layer 74 _2, the p-type cap layer 21 of the ridge 31 not electrically connected, also the p-type cap layer 23 of the electrode pad portions 41 are electrically connected Absent. A part of each of the first metal layer 72 and the second insulating layer 73 overlaps with each other on the bottom surface of each of the grooves 51 to 55.

  As shown in FIG. 3B, in the cross section taken along the line BB in FIG. 2, each of the first insulating layer 71 and the first metal layer 72 is the same as that shown in FIG. It is formed in the same range. The second insulating layer 73 is formed from the bottom surface of the groove portion 51 to the electrode pad portion 41, formed from the bottom surface of the groove portion 52 to the bottom surface of the groove portion 54, and formed from the bottom surface of the groove portion 55 to the electrode pad portion 42. The second insulating layer 73 is also formed on the inner wall surface and the bottom surface of each of the element isolation grooves 61 to 65. The second insulating layer 73 is not formed on the upper surface and both side wall surfaces of the ridge portions 31 and 34 and a part of the bottom surface of the groove portion continuing from the side wall surface.

The second metal layer 74 ₁ is formed from the bottom surface of the groove portion 52 to the electrode pad portion 41. The second metal layer 74 ₁ is also formed on the inner wall surface and the bottom surface of the isolation groove 61. The second metal layer 74 ₁ is electrically connected to the upper surface of the p-type cap layer 21 of the ridge portion 31 through the first metal layer 72. However, the second metal layer 74 _1, the p-type cap layer 22 of the ridge portion 32 not electrically connected, also the p-type cap layer 23 of the electrode pad portions 41 are electrically connected Absent.

Each of the first metal layer 72 and the second metal layer 74 is preferably composed of a plurality of layers of metal films. In particular, the second metal layer 74 is preferably a plurality of metal films, and the lowermost layer is preferably a Ti film. For example, each of the first insulating layer 71 and the second insulating layer 73 is preferably made of SiN, SiO ₂ , α-Si, or AlN. The first metal layer 72 is preferably made of a metal film having a plurality of layers of Ti / Al / Au, Ti / Au, or Cr / Au. The second metal layer 74 is preferably made of a multi-layer metal film of Ti / Au or Cr / Au. For example, the thickness of the first insulating layer 71 is 1000 mm, the thickness of the first metal layer 72 is 3500 mm, the thickness of the second insulating layer 73 is 1000 mm, and the thickness of the second metal layer 74 is 5500 mm. is there.

In this semiconductor light-emitting device 1, the first metal layer 72 and the second metal layer ₇₄ to 72d ₄ is a p-type electrode, the metal layer 15 is n-type electrode. When a voltage is applied between the second metal layer 74 ₁ and the metal layer 15, the light second metal layer 74 ₁ is in the lower part of the ridge portion 31 which is electrically connected to the p-type cap layer 21 A light emitting portion is generated in the region of the active layer 13. Similarly, when a voltage is applied between the second metal layer 74 ₂ and the metal layer 15, the light emitting portion is generated in the area of the photoactive layer 13 located below the ridge portion 32. When a voltage is applied between the second metal layer ₇₄₃ and the metal layer 15, the light emitting portion is generated in the area of the photoactive layer 13 located below the ridge portion 33. Further, when a voltage is applied between the second metal layer 74 ₄ and the metal layer 15, the light emitting portion is generated in the area of the photoactive layer 13 located below the ridge portion 34.

In each of these light emitting portions, light is generated by recombination of electrons and holes by voltage application. Further, in this semiconductor light emitting device 1, a Fabry-Perot resonator is constituted by two end faces perpendicular to the extending direction of each of the ridge portions 31 to 34, and laser oscillation is generated by this resonator. In addition, since a voltage can be independently applied to each of the second metal layers 74 ₁ to 74 _{4 with} respect to the common metal layer 15, it is independent in the region of the photoactive layer 13 in the lower portion of each of the ridge portions 31 to 34. A light emitting part may be generated.

Further, in the semiconductor light emitting device 1, in the cross-sectional structure shown in FIG. 3A, the first insulating layer 71 may be peeled off during manufacture near the corner between the upper surface of the ridge 31 and the side wall surface. even or cause poor film formation, since it is formed further second insulating layer 73, it is avoided _{that 2} second metal layer 74 is electrically connected to the p-type cap layer of the undesired portion . Therefore, when the voltage between the second metal layer 74 ₂ and the metal layer 15 is applied, in the region of the photoactive layer 13 at the lower part of the undesired portion is prevented from unintended emission portion is produced The Thereby, the beam quality of the light output from the semiconductor light emitting device 1 is improved.

  Next, an example of a method for manufacturing the semiconductor light emitting device 1 according to this embodiment will be described. 4 to 7 are process diagrams illustrating the method for manufacturing a semiconductor light emitting device according to this embodiment. In the following, a method for manufacturing a cross-sectional structure along the line AA in FIG. 2 (that is, the structure shown in FIG. 3A) will be mainly described. When manufacturing a cross-sectional structure along the line B-B in FIG. 2 (that is, the structure shown in FIG. 3B), the range in which each layer is formed may be different. The manufacturing method is the same between the central element isolation layer 63 and the electrode pad portion 41 and between the element isolation layer 63 and the electrode pad portion 42.

  First, an n-type cladding layer 12, a photoactive layer 13, and a p-type cladding layer 14 are sequentially formed on one main surface of the n-type substrate 10 by epitaxial growth to form a semiconductor layer 11, and further, a semiconductor layer A p-type cap layer 20 is formed on the substrate 11 (FIG. 4A). These layers are formed on the entire main surface of one of the n-type substrates 10.

  Then, a resist is applied on the entire surface of the p-type cap layer 20, and a resist layer 81 is formed in a predetermined region on the p-type cap layer 20 by exposure and development using a mask having a predetermined pattern (FIG. 4 ( b)). Etching is performed using the resist layer 81 as a mask (FIG. 4C), and then the resist layer 81 is removed (FIG. 4D). Thus, the p-type cap layer constituting each ridge portion, the p-type cap layer constituting each electrode pad portion, the groove portion between two adjacent ridge portions, and the groove portion between the ridge portion and the electrode pad portion Is formed.

  At this time, the p-type cap layer constituting each ridge portion may have an inverted mesa shape or a forward mesa shape. In addition, after etching, a part of the cap layer 20 may remain in each groove portion, or the entire cap layer 20 may be removed and the upper surface of the p-type cladding layer 14 may be exposed. A part of the p-type cladding layer 14 may be removed.

  Subsequently, a resist is applied to the entire surface, and a resist layer 82 is formed in a predetermined region by exposure and development using a mask having a predetermined pattern (FIG. 4E). Etching is performed using the resist layer 82 as a mask (FIG. 4F), and then the resist layer 82 is removed (FIG. 5A). Thereby, element isolation grooves 61 to 65 reaching the substrate 10 are formed on the bottom surfaces of the groove parts 51 to 55.

  After the formation of the element isolation trench, a first insulating layer 71 is formed on the entire surface by CVD (FIG. 5B), and a resist 83 is further applied on the entire surface (FIG. 5C). At this time, the thickness of the resist layer 83 is relatively thin on the upper surface of each ridge portion, and is relatively thick on the upper surface of each electrode pad portion and the bottom surface of each groove portion. Therefore, the resist 83 on the upper surface of each ridge portion is selectively removed by exposure and development by a self-alignment method without using a mask. On the other hand, the resist 83 remains on the side wall surfaces on both sides of each ridge portion, the top and side surfaces of each electrode pad portion, and the bottom surface of each groove portion (including the inner wall surface and bottom surface of each element isolation groove) (FIG. 5 ( d)). By adopting this self-alignment method, it is easy to manufacture even a narrow ridge portion.

  The remaining resist 83 is used as a mask to perform dry etching. Thereby, the first insulating layer 71 is removed on the upper surface of each ridge portion. On the other hand, the first insulating layer 71 remains on the side wall surfaces on both sides of each ridge portion, the upper surface and the side wall surface of each electrode pad portion, and the bottom surface of each groove portion (including the inner wall surface and the bottom surface of the element isolation groove). (FIG. 5 (e)). Thereafter, the resist 83 is removed (FIG. 5F). The first insulating layer 71 is formed in a predetermined region by the steps so far (first insulating layer forming step).

  After the first insulating layer 71 is thus formed in a predetermined region, a resist is applied to the entire surface, and a resist layer 84 is formed by exposure and development using a mask having a predetermined pattern (FIG. 6A). ). At this time, the resist layer 84 includes the upper surface and the side wall surface of each electrode pad portion, the bottom surface of the groove portion adjacent to each electrode pad portion (including the inner wall surface and the bottom surface of the element isolation groove), and two adjacent ridge portions. Is formed on the bottom surface of the groove portion (including the inner wall surface and the bottom surface of the element isolation groove).

  A first metal layer 72 is formed thereon by vapor deposition (FIG. 6B), and the resist layer 84 and the portion of the first metal layer 72 thereon are removed by lift-off (FIG. 6C). ). As a result, the first metal layer 72 remains on the upper surface and both side wall surfaces of each ridge portion, and the bottom surface of the groove portion following the side wall surface. The first metal layer 72 is formed in a predetermined region by the steps so far (first metal layer forming step).

  After the first metal layer 72 is formed in the predetermined region in this way, the second insulating layer 73 is formed on the entire surface by the CVD method (FIG. 6 (d)), and a resist is further applied on the entire surface. A resist layer 85 is formed by exposure and development using a mask (FIG. 6E). At this time, the resist layer 85 is formed on the upper surface and side wall surface of each electrode pad portion, the upper surface and both side wall surfaces of the ridge portions 31 and 34, and the bottom surface of each groove portion (including the inner wall surface and bottom surface of the element isolation groove). ing. The resist layer 85 is not formed on the upper surface and both side wall surfaces of the ridge portions 32 and 33 and a partial region of the bottom surface of the groove portion following the side wall surface.

  The remaining resist layer 85 is used as a mask for dry etching. As a result, the second insulating layer 73 is removed in the upper surface and both side wall surfaces of the ridge portions 32 and 33 and in a partial region of the bottom surface of the groove portion following the side wall surface. The remaining second insulating layer 73 is formed on the upper surface and side wall surface of each electrode pad portion, the upper surface and both side wall surfaces of the ridge portions 31 and 34, and the bottom surface of each groove portion (including the inner wall surface and bottom surface of the element isolation groove). Has been. The remaining partial region of the second insulating layer 73 is formed so as to overlap with the partial region of the first metal layer 72 on the bottom surface of the groove (FIG. 6F). Thereafter, the resist layer 85 is removed (FIG. 7A). The second insulating layer 73 is formed in a predetermined region by the steps so far (second insulating layer forming step).

  After the second insulating layer 73 is thus formed in a predetermined region, a resist is applied to the entire surface, and a resist layer 86 is formed by exposure and development using a mask having a predetermined pattern (FIG. 7B). ). At this time, the resist layer 86 is formed in a region in the vicinity of the element isolation layer 63 among the region on the chip end side of each electrode pad portion, the inner wall surface and the bottom surface of the central element isolation layer 63, and the bottom surface of the groove portion 53. Yes. A second metal layer 74 is formed thereon by vapor deposition (FIG. 7C). Then, the resist layer 86 and the portion of the second metal layer 74 thereon are removed by lift-off (FIG. 7D). As a result, the second metal layer 74 remains from each electrode pad portion to the vicinity of the element isolation layer 63. The second metal layer 74 is formed in a predetermined region by the steps so far (second metal layer forming step).

  And the metal layer 15 is formed in the other main surface of the n-type board | substrate 10, and the semiconductor light-emitting device 1 which has the structure shown by FIGS. 1-3 is manufactured (FIG.7 (e)).

  The semiconductor light emitting device 1 manufactured as described above has a ridge structure, and is manufactured through exposure and development by a self-alignment method, so that the light emission width can be about several μm.

By the way, in the semiconductor light emitting device manufacturing method according to the present embodiment described above, in the vicinity of the corner between the top surface of each ridge portion and the side wall surface, in the vicinity of the corner portion between the top surface of each electrode pad portion and the side wall surface. In addition, in the vicinity of the corner between the inner wall surface of each element isolation groove and the bottom surface of the groove, the first insulating layer 71 may be peeled off or a film formation defect may occur during the manufacturing. In particular, the resist 83 on the upper surface of each ridge portion is selectively removed by exposure and development using a self-alignment method (FIG. 5D), and then the first insulating layer 71 on the upper surface of each ridge portion is selectively removed. At the time of removal (FIG. 5E), the resist 83 and the first insulating layer 71 are formed in the upper portion of the side wall surface of each ridge portion, in the vicinity of the corner portion of each electrode pad portion, and in the vicinity of the corner portion of each element isolation groove. May be removed to expose the p-type cap layer. If, when the immediate second metal layer 74 ₂ is formed in this state is electrically connected to the second metal layer 74 ₂ to be only for p-type cap layer 22 constituting the ridge portion 32 The p-type cap layer is also electrically connected to the upper portion of the side wall surface of the other ridge portion, the vicinity of the corners of the electrode pad portions, and the vicinity of the corner portions of the element isolation grooves.

Therefore, in order to cope with such a problem, the second insulating layer 73 is further provided in the present embodiment. When the second insulating layer 73 is formed, the resist is exposed and developed using a mask having a predetermined pattern instead of the self-alignment method, so that the upper portion of the side wall surface of each ridge portion and each electrode pad portion are formed. The second insulating layer 73 does not peel off at the upper portion of the side wall surface and the inner wall surface of each element isolation groove. Thus, p in the second metal layer 74 ₂ formed on the second insulating layer 73 is electrically connected only to the p-type cap layer 22 constituting the ridge portion 32, the other undesired portion There is no electrical connection to the mold cap layer, avoiding light emission below the undesired portion.

  In the semiconductor light emitting device manufacturing method according to the present embodiment described above, the second insulating layer 73 and the first insulating layer 73 are temporarily formed when the second insulating layer 73 is formed (FIGS. 6D to 6F). When the first insulating layer 71 is exposed without overlapping with the metal layer 72, the resist layer 85 is used during dry etching performed using the resist layer 85 as a mask (FIG. 6F). The region of the first insulating layer 71 that is not covered with is also removed. If a metal layer is further formed in this state, the metal layer is electrically connected to the semiconductor layer at the groove.

  Therefore, in order to cope with such a problem, in this embodiment, a partial region of the second insulating layer 73 is formed so as to overlap with a partial region of the first metal layer 72 on the bottom surface of the groove. By doing so, the first insulating layer 71 is not removed during dry etching (FIG. 6F) performed using the resist layer 85 as a mask. Therefore, the second metal layer 74 formed on the second insulating layer 73 is not electrically connected to the semiconductor layer at the groove.

  As described above, the partial region of the second insulating layer 73 is formed so as to overlap the partial region of the first metal layer 72 on the bottom surface of the groove. However, in general, the adhesion between the metal layer (usually the uppermost layer is Au) and the insulating layer is poor. Therefore, in the overlapping region between the first metal layer 72 and the second insulating layer 73, the second insulating layer is assumed. When 73 is exposed, the second insulating layer 73 is easily peeled off from the first metal layer 72.

Therefore, in order to cope with such a problem, in the present embodiment, the second metal layer 74 ₂ is formed from the bottom surface of the groove 53 to the electrode pad portion 41, the first metal layer 72 second insulating layer 73 It is also formed in the overlapping region. By doing so, peeling of the second insulating layer 73 from the first metal layer 72 is prevented. Further, if the second metal layer 74 is a multi-layer metal film and the lowermost layer is a Ti film, the adhesion between the second insulating layer 73 and the second metal layer 74 is good. The peeling of the two insulating layers 73 is further prevented.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, the pattern of the second metal layer 74 in the semiconductor light emitting device may be such that a plan view is shown in FIGS. Compared with the pattern of the second metal layer 74 shown in FIG. 2, in the semiconductor light emitting device shown in FIG. 8, the second metal layers 74 ₁ to 74 ₄ are respectively extended from the corresponding ridge portions 31 to 34. It is electrically connected to the p-type cap layer over a wide range that continues along the direction. In the semiconductor light emitting device shown in FIG. 9, each of the second metal layers 74 ₁ to 74 ₄ is electrically connected to the p-type cap layer in each range divided into two along the extending direction of the corresponding ridge portions 31 to 34. Connected. 9, the second metal layer 74 _2, from above the ridge portion 32, passes between the second metal layer 74 ₁ are divided by two on the ridge portion 31 is formed to the electrode pad portion 41, the second metal layer ₇₄₃ from the upper ridge 33, passes between the second metal layer 74 ₄ which is divided into two on the ridge portion 34 is formed to the electrode pad portion 42. These either case, the cross-sectional structure of a _{portion 2} the second metal layer 74 is formed is as shown in FIG. 3 (a), also, the cross-sectional structure of a _{portion 1} second metal layer 74 is formed Is as shown in FIG.

1 is a perspective view of a semiconductor light emitting device 1 according to an embodiment. 1 is a plan view of a semiconductor light emitting element 1 according to an embodiment. It is sectional drawing of the semiconductor light-emitting device 1 which concerns on this embodiment. It is a 1st process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a 2nd process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a 3rd process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a 4th process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a top view of the semiconductor light emitting element of a modification. It is a top view of the semiconductor light emitting element of another modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor light emitting element, 2 ... Submount, 3 ... Wire, 10 ... N-type substrate, 11 ... Semiconductor layer, 12 ... N-type clad layer, 13 ... Photoactive layer, 14 ... P-type clad layer, 15 ... Metal layer 20-26 ... p-type cap layer, 31-34 ... ridge portion, 41, 42 ... electrode pad portion, 51-55 ... groove portion, 61-65 ... element isolation groove, 71 ... first insulating layer, 72 ... first Metal layer 73 ... second insulating layer 74 ... second metal layer.

Claims (4)

A semiconductor layer formed on a substrate and including a photoactive layer, an electrode pad portion provided on the semiconductor layer, and provided in parallel with each other across a groove on the semiconductor layer and close to the electrode pad portion A plurality of ridge portions including a first ridge portion and a second ridge portion in order,
From the sidewall surface of one adjacent ridge portion to the sidewall surface of the other ridge portion of the plurality of ridge portions, and from the sidewall surface of the first ridge portion on the electrode pad portion side to the electrode pad portion, respectively. A formed first insulating layer;
A first metal layer formed from the bottom surface of the groove portion on one side to the bottom surface of the groove portion on the other side across each of the plurality of ridge portions;
A second insulating layer formed from the bottom surface of the groove portion on the electrode pad portion side of the second ridge portion to the electrode pad portion;
A second metal layer formed from the bottom surface of the groove portion on the opposite side of the electrode pad portion side of the second ridge portion to the electrode pad portion;
Are formed in order,
The second metal layer is electrically connected to the upper surface of the second ridge portion via the first metal layer;
A part of each of the first metal layer and the second insulating layer electrically connected to the second ridge portion is mutually on the bottom surface of the groove portion between the first ridge portion and the second ridge portion. overlapping,
A semiconductor light emitting element characterized by the above. An element isolation groove reaching the substrate at the bottom of the groove is formed,
A first insulating layer and a second insulating layer are formed on an inner wall surface and a bottom surface of the element isolation groove;
The semiconductor light emitting element according to claim 1. A semiconductor layer formed on a substrate and including a photoactive layer, an electrode pad portion provided on the semiconductor layer, and a first ridge portion and a second ridge portion on the semiconductor layer in order from the electrode pad portion. A plurality of ridge portions provided in parallel with each other across a groove portion, and a method of manufacturing a semiconductor light emitting device comprising:
From the sidewall surface of one adjacent ridge portion to the sidewall surface of the other ridge portion of the plurality of ridge portions, and from the sidewall surface of the first ridge portion on the electrode pad portion side to the electrode pad portion, respectively. A first insulating layer forming step of forming a first insulating layer;
A first metal layer forming step of forming a first metal layer from the bottom surface of the groove portion on one side to the bottom surface of the groove portion on the other side across each of the plurality of ridge portions;
In the bottom surface of the groove portion between the first ridge portion and the second ridge portion from the bottom surface of the groove portion on the electrode pad portion side of the second ridge portion to the electrode pad portion , the second ridge portion A second insulating layer forming step of forming a second insulating layer partially overlapping with the first metal layer to be electrically connected ;
Second electrically connected to the upper surface of the second ridge portion through the first metal layer from the bottom surface of the groove portion on the opposite side of the electrode pad portion side of the second ridge portion to the electrode pad portion. A second metal layer forming step of forming a metal layer;
A method for manufacturing a semiconductor light emitting device, wherein the steps are sequentially performed. After forming an element isolation groove reaching the substrate at the bottom of the groove, the first insulating layer forming step, the first metal layer forming step, the second insulating layer forming step, and the second metal layer forming step are sequentially performed. Done
In the first insulating layer forming step, the first insulating layer is also formed on the inner wall surface and the bottom surface of the element isolation groove,
In the second insulating layer forming step, the second insulating layer is also formed on the inner wall surface and the bottom surface of the element isolation groove.
The method of manufacturing a semiconductor light emitting element according to claim 3.

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