JP2008277360A - Method for mounting electronic part - Google Patents

Method for mounting electronic part Download PDF

Info

Publication number
JP2008277360A
JP2008277360A JP2007116276A JP2007116276A JP2008277360A JP 2008277360 A JP2008277360 A JP 2008277360A JP 2007116276 A JP2007116276 A JP 2007116276A JP 2007116276 A JP2007116276 A JP 2007116276A JP 2008277360 A JP2008277360 A JP 2008277360A
Authority
JP
Japan
Prior art keywords
flux
electronic component
hole
terminal portions
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007116276A
Other languages
Japanese (ja)
Inventor
Masahiro Mori
正裕 森
Izuru Nakai
出 中井
Koji Funemi
浩司 船見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2007116276A priority Critical patent/JP2008277360A/en
Publication of JP2008277360A publication Critical patent/JP2008277360A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To conduct a junction without a defective soldered joint in a soldered joint on a wiring board using cream solder. <P>SOLUTION: Dripping heated flux when solder melts is made to escape to holes 9 and its spread is prevented by forming the holes 9 in a region held by adjacent joining terminal sections 2a and 2b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、ICチップ、チップコンデンサ、圧電素子等の電子部品を配線基板上に実装して電子回路基板を得るための電子部品実装方法に関するものである。   The present invention relates to an electronic component mounting method for obtaining an electronic circuit board by mounting electronic parts such as an IC chip, a chip capacitor, and a piezoelectric element on a wiring board.

従来、電子部品には配線基板の電極に接合するための接合用電極として、パッケージ周囲にガルウイング状に広がるリード端子を備えるものが知られている。例えばQFP( Quad Flat Pack )などである。この種の電子部品において、パッケージ周囲に広がるリード端子の強度をある程度維持しながらリード端子数(I/O数)を増加させるためには、パッケージサイズを大型化せざるを得ない。   2. Description of the Related Art Conventionally, an electronic component having a lead terminal that spreads in a gull wing shape around a package is known as a bonding electrode for bonding to an electrode of a wiring board. For example, QFP (Quad Flat Pack). In this type of electronic component, in order to increase the number of lead terminals (number of I / Os) while maintaining the strength of the lead terminals spreading around the package to some extent, the package size must be increased.

そこで、近年においては複数の接合用電極をパッケージ下面にアレイ状に配設した下面電極方式の電子部品が主流になりつつなる。例えば、LGA( Land Grid Array )、BGA( Ball Grid Array )、CSP( Chip Size Package )などである。これらの電子部品では扁平な接合用電極をパッケージ下面にアレイ状に配設することにより、パッケージを大型化することなくI/O数を増加させることが出来る。   Therefore, in recent years, electronic components of the lower surface electrode type in which a plurality of bonding electrodes are arranged in an array on the lower surface of the package are becoming mainstream. For example, LGA (Land Grid Array), BGA (Ball Grid Array), CSP (Chip Size Package), and the like. In these electronic components, the number of I / Os can be increased without increasing the size of the package by arranging flat bonding electrodes in an array on the lower surface of the package.

かかる下面電極方式の電子部品については、クリーム半田を用いて配線基板上に実装するのが一般的である。具体的には、先ず、印刷マスクを用いた印刷法により、配線基板の配線パターン内における複数の基板電極上にそれぞれクリーム半田を印刷する。次に電子部品を配線基板上に印刷されたクリーム半田の上に載置する。そしてリフロー工程にて、配線基板を電子部品と共にリフロー炉に入れて加熱して、クリーム半田内の導電性接合材である半田粒を溶融させる。この後、溶融半田を冷却により固化させることで、配線基板上の基板電極と電子部品の接合用電極とを接合する。   Such a bottom electrode type electronic component is generally mounted on a wiring board using cream solder. Specifically, first, cream solder is printed on each of the plurality of substrate electrodes in the wiring pattern of the wiring substrate by a printing method using a printing mask. Next, the electronic component is placed on the cream solder printed on the wiring board. In the reflow process, the wiring board is put into a reflow furnace together with the electronic components and heated to melt the solder grains as the conductive bonding material in the cream solder. Thereafter, the molten solder is solidified by cooling, thereby joining the substrate electrode on the wiring board and the joining electrode of the electronic component.

このような電子部品実装方法では、電子部品の材質と配線基板の材質とで熱膨張率が異なると、加熱を伴うリフロー工程において互いの電極の相対位置がずれることにより、接合位置ズレを引き起こしてしまうおそれがある。電子機器の小型化に伴って、より微細ピッチな接合が求められていく傾向にある近年においては、僅かな熱膨張率の違いが大きな接合位置ズレとなって現れるようになっていくと予想される。   In such an electronic component mounting method, if the coefficient of thermal expansion differs between the material of the electronic component and the material of the wiring board, the relative position of the electrodes in the reflow process accompanied by heating shifts, causing a misalignment of the bonding position. There is a risk that. In recent years, where finer pitch bonding tends to be required as electronic devices become smaller, a slight difference in coefficient of thermal expansion is expected to appear as a large misalignment in the bonding position. The

別の従来の電子部品実装方法としては、クリーム半田だけをレーザ光を照射して溶かして半田付けを行う電子部品実装方法が知られている。この電子部品実装方法によれば、電子部品や配線基板を全体的に加熱するのではなく、電極やその周辺の箇所を局所的に加熱するだけなので、互いの熱膨張率の違いによる接合位置ズレを抑えることが可能である。
特開2006−303356公報
As another conventional electronic component mounting method, an electronic component mounting method is known in which only cream solder is melted by irradiating a laser beam to perform soldering. According to this electronic component mounting method, the electronic component and the wiring board are not heated as a whole, but only the electrode and the surrounding area are heated locally. Can be suppressed.
JP 2006-303356 A

しかしながら、レーザ光を照射してクリーム半田だけを溶かして半田付けを行う電子部品実装方法でも、電子部品と配線基板との接合不良を引き起こしたり、半田不良を発生させるおそれがある。   However, even in an electronic component mounting method in which soldering is performed by irradiating a laser beam to melt only cream solder, there is a risk of causing a bonding failure between the electronic component and the wiring board or causing a solder failure.

一般に、クリーム半田は微小な粒子の半田ボールとフラックスで構成され、フラックスの中に半田ボールが分散している状況にある。フラックスは塗布性の向上と接合面の酸化皮膜除去を目的としている。フラックスは常温では粘度が高く、クリーム半田を塗布した場合、塗布時の形状をほぼ保つことが出来る程度の粘性を持つ。   In general, cream solder is composed of fine particles of solder balls and flux, and the solder balls are dispersed in the flux. The purpose of the flux is to improve applicability and remove the oxide film on the joint surface. Flux has a high viscosity at room temperature, and when cream solder is applied, it has a viscosity that can maintain the shape when applied.

図8(a)に示すように、配線基板1に隣接して設けた接合端子部2a,2bにクリーム半田3を付け、このクリーム半田3をレーザ光4で加熱すると、先ず、クリーム半田3の中のフラックスの粘度が急激に低下し、クリーム半田3を付けた接合端子部2a,2bよりフラックスが滲み広がってしまう。   As shown in FIG. 8A, when the cream solder 3 is attached to the joining terminal portions 2a and 2b provided adjacent to the wiring board 1 and this cream solder 3 is heated with the laser beam 4, first, the cream solder 3 The viscosity of the flux inside drops rapidly, and the flux spreads and spreads from the joining terminal portions 2a and 2b to which the cream solder 3 is attached.

この時、滲み広がったフラックス5は図8(b)に示すように、隣接する接合端子部2a,2bにまで広がることがある。この場合には、フラックス5が広がる際に、クリーム半田3の中の半田粒子6もフラックス5の流れに引き連れられ、隣接する接合端子部2a,2bにまで広がってしまい、図8(c)に示すように接合端子部2aと接合端子部2bの間で半田粒子6が溶融してしまい、本来は開放しておかなければならない部分が半田7で短絡して不良となる。   At this time, the spread flux 5 may spread to the adjacent joining terminal portions 2a and 2b as shown in FIG. 8B. In this case, when the flux 5 spreads, the solder particles 6 in the cream solder 3 are also attracted by the flow of the flux 5 and spread to the adjacent junction terminal portions 2a and 2b, as shown in FIG. As shown, the solder particles 6 are melted between the joining terminal portion 2a and the joining terminal portion 2b, and a portion that should originally be opened is short-circuited by the solder 7 and becomes defective.

短絡してない場合であっても、図8(c)に示すように半田7が溶融すると、レーザ照射部の温度が急激に上昇して、一度広がったクリーム半田は溶融と共に温度の高い領域に凝集し、隣接する接合端子部2aまたは接合端子部2bに未溶融のクリーム半田が存在する場合には、一度広がったクリーム半田の凝集に引きつられるように引き込まれてしまう。そうした場合、図8(d)の接合端子部2aに見られるように、半田7のない(または極端に少ない)接合端子部が発生してしまい、電子部品(図示せず)を載置した場合には実装不良を引き起こしてしまう。   Even if it is not short-circuited, as shown in FIG. 8 (c), when the solder 7 is melted, the temperature of the laser irradiation portion rapidly increases, and the cream solder that has spread once becomes a high temperature region with melting. If there is unmelted cream solder in the adjacent joint terminal portion 2a or joint terminal portion 2b, the solder paste is drawn so as to be attracted by the aggregation of cream solder once spread. In such a case, as seen in the junction terminal portion 2a of FIG. 8D, a junction terminal portion without (or extremely few) solder 7 is generated and an electronic component (not shown) is placed. Will cause poor mounting.

本発明は、電子部品と配線基板との半田不良・接合不良の発生を抑制することのできる電子部品実装方法および配線基板を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic component mounting method and a wiring board that can suppress the occurrence of defective soldering and poor bonding between the electronic component and the wiring board.

本発明の電子部品実装方法は、配線基板に隣接して設けられた接合端子部に付けられたクリーム半田を加熱して溶融させて電子部品を前記基板に実装するに際し、前記配線基板には隣接して設けられた接合端子部で挟まれる領域に、少なくとも1つ以上の孔を予め形成し、加熱によって前記クリーム半田が熱だれを起こし、接合端子部の塗布領域から流れ広がったフフラックスを、前記孔に流して反対側の接合端子部の方に流れ出すことを防止することを特徴とする。   In the electronic component mounting method of the present invention, when the electronic component is mounted on the substrate by heating and melting the cream solder attached to the joining terminal portion provided adjacent to the wiring substrate, the electronic component is adjacent to the wiring substrate. At least one or more holes are formed in advance in the region sandwiched between the joint terminal portions provided as described above, and the cream solder is heated by heating and flows from the application region of the joint terminal portion. It is prevented from flowing into the hole and flowing out toward the opposite junction terminal portion.

本発明の配線基板は、隣接して設けられた接合端子部で挟まれる領域に、前記接合端子部の塗布領域から流れ広がったフラックスを逃がす孔を形成したことを特徴とする。   The wiring board according to the present invention is characterized in that a hole is formed in a region sandwiched between adjacent joint terminal portions to release the flux that has spread from the application region of the joint terminal portion.

この構成によると、加熱による熱だれによって広がり始めたフラックスは、隣接する接合端子部に浸入する前に、接合端子部の間に設けた孔に到達する。この孔に到達したフラックスは、高温状態であるため粘性が低下している。そのため、孔に毛細管現象により溜まって広がらない。   According to this configuration, the flux that has begun to spread due to heat dripping due to heating reaches the hole provided between the joining terminal portions before entering the adjacent joining terminal portions. Since the flux that has reached this hole is in a high temperature state, its viscosity is reduced. Therefore, it does not collect and spread in the hole due to capillary action.

以下、本発明の電子部品実装方法を具体的な実施の形態に基づいて説明する。
(実施の形態1)
図1と図2は本発明の実施の形態1を示す。
The electronic component mounting method of the present invention will be described below based on specific embodiments.
(Embodiment 1)
1 and 2 show Embodiment 1 of the present invention.

図1(a)(b)は本発明の電子部品実装方法の実施に使用する配線基板を示している。
配線基板1の 接合端子部2aと接合端子部2bの間にクリーム半田3を使用して電子部品を実装しようとする場合に、配線基板1には、隣接して設けられた接合端子部2a,2bで挟まれる領域で、隣接する接合端子部2a,2bの間を二等分する線8の上に、貫通した孔9が形成されている。孔9の数は、少なくとも1つ以上であればよい。
1A and 1B show a wiring board used for carrying out the electronic component mounting method of the present invention.
When an electronic component is to be mounted using the cream solder 3 between the junction terminal portion 2a and the junction terminal portion 2b of the wiring board 1, the wiring terminal 1 has the junction terminal portions 2a, A penetrating hole 9 is formed on a line 8 that bisects between adjacent joint terminal portions 2a and 2b in a region sandwiched by 2b. The number of holes 9 may be at least one.

具体的には、接合端子部2a,2bは0.5mm角程度の大きさであり、0.5mm程度の間隔を空けて隣接するように設けられている。孔9は、直径0.2mmのものを8個設けている。   Specifically, the joining terminal portions 2a and 2b have a size of about 0.5 mm square and are provided adjacent to each other with an interval of about 0.5 mm. Eight holes 9 having a diameter of 0.2 mm are provided.

電子部品の実装に際しては、図2(a)に示すように、接合端子部2a,2bの一つの当りに、クリーム半田3を1mg程度塗布する。その後、クリーム半田溶融のための加熱を行う。この時、クリーム半田を用いた半田付けであるため、非接触式の加熱方法が望ましく、本実施例ではレーザ光4を用いて加熱し、クリーム半田3を溶融させた。この時、急激な加熱はクリーム半田3の突沸を招くため段階的な加熱が望ましい。本実施例では、予備加熱と本加熱を設けており、予備加熱では1Wのパワーのレーザ光4を3秒程度照射し、その後、本加熱として4Wのパワーのレーザ光4を3秒程度照射している。   When mounting an electronic component, as shown in FIG. 2A, about 1 mg of cream solder 3 is applied to one of the joint terminal portions 2a and 2b. Then, heating for melting the cream solder is performed. At this time, since the soldering is performed using cream solder, a non-contact heating method is desirable. In this embodiment, the cream solder 3 was melted by heating using the laser beam 4. At this time, since rapid heating causes bumping of the cream solder 3, stepwise heating is desirable. In this embodiment, preheating and main heating are provided. In the preheating, laser light 4 having a power of 1 W is irradiated for about 3 seconds, and then laser light 4 having a power of 4 W is irradiated for about 3 seconds as main heating. ing.

予備加熱の時点でクリーム半田3は、図2(b)に示すように熱だれを起こし、塗布していた領域から流れ広がるが、フラックス5が孔9に達すると、フラックス5が孔9の毛細管現象により孔9に充填されることで、隣接する接合端子部2a,2bにフラックスが流れ出ることがなくなり、本加熱の時点で、半田が溶融し電子部品の半田実装が可能となる。   As shown in FIG. 2 (b), the cream solder 3 drips and spreads from the applied region at the time of preheating, but when the flux 5 reaches the hole 9, the flux 5 becomes a capillary tube of the hole 9. By filling the hole 9 due to the phenomenon, the flux does not flow out to the adjacent joining terminal portions 2a and 2b, and at the time of the main heating, the solder is melted and the electronic component can be mounted by soldering.

また、接合端子部2a,2bの近傍に半田の融点よりも沸点の低いフラックスの溜りができるため、局所的に熱容量が上昇する。そうすることで、別工程での再加熱等の熱履歴に対する耐性が向上するため、半田接合不良を防止することができる。   Further, since a flux having a boiling point lower than the melting point of the solder can be accumulated in the vicinity of the junction terminal portions 2a and 2b, the heat capacity is locally increased. By doing so, since the tolerance with respect to heat histories, such as reheating in another process, improves, it can prevent solder joint failure.

このようにして、図2(c)に示すように接合端子部2a,2bの上に均等に半田7が残った状態を作り出すことができる。したがって、接合端子部2a,2bの上の溶融した半田7に電子部品を押し付けることで、良好に電子部品を接合端子部2a,2bの間に実装することができる。   In this way, it is possible to create a state in which the solder 7 remains evenly on the joining terminal portions 2a and 2b as shown in FIG. Therefore, the electronic component can be favorably mounted between the joining terminal portions 2a and 2b by pressing the electronic component against the molten solder 7 on the joining terminal portions 2a and 2b.

なお、孔9の直径は50〜250μmで良好な効果を確認できたが、0.2mmとすることで、毛細管現象のためにフラックスが孔の深くまで浸入するため、除去できるフラックス52の量を最大にすることができる。また、孔9の数を複数個にすることで、除去できるフラックスの総量を制御しており、接合端子部2aと接合端子部2bの上の総面積に対して、孔9の開口総面積をその30%程度とすることで、隣接する接合端子部に到達するフラックスのみを除去できる。   In addition, although the diameter of the hole 9 was 50-250 micrometers, and the favorable effect was confirmed, since the flux permeates to the depth of a hole by making it 0.2 mm, the quantity of the flux 52 which can be removed is reduced. Can be maximized. Moreover, the total amount of the flux which can be removed is controlled by making the number of the holes 9 into a plurality, and the total opening area of the holes 9 with respect to the total area on the joining terminal portion 2a and the joining terminal portion 2b. By setting it to about 30%, it is possible to remove only the flux that reaches the adjacent joint terminal portion.

0.2mmが一番よいとする根拠を図3〜図5に基づいて説明する。
図3に示すように、一方の接合端子部2bにクリーム半田3を塗布し、この塗布したクリーム半田3にレーザ光4を照射した場合に、接合端子部2bから接合端子部2aに5aで示すようにフラックスが流れ広がらないように一部を孔9に流して、5bで示すようにフラックスを配線基板1に残そうとした場合、孔9の直径が50〜200μmの時の、孔径と孔9に浸入するフラックスの浸入深さの関係を測定すると図4に示す結果が得られた。孔9の直径が大きくなるに伴い、浸入深さも大きくなる。200μmでピークとなり、200μmより大きな直径になると、逆に浸入深さが小さくなっている。
The reason why 0.2 mm is the best will be described with reference to FIGS.
As shown in FIG. 3, when the cream solder 3 is applied to one of the joint terminal portions 2b and the applied cream solder 3 is irradiated with the laser beam 4, the joint terminal portion 2b to the joint terminal portion 2a are indicated by 5a. In order to prevent the flux from flowing and spreading, a part of the hole 9 flows into the hole 9 to leave the flux on the wiring board 1 as shown by 5b. When the hole 9 has a diameter of 50 to 200 μm, the hole diameter and the hole When the relationship of the penetration depth of the flux which penetrates into No. 9 was measured, the result shown in FIG. 4 was obtained. As the diameter of the hole 9 increases, the penetration depth also increases. When it reaches a peak at 200 μm and has a diameter larger than 200 μm, the penetration depth decreases.

次に、孔径と孔9に充填されるフラックス量の関係を図5に示す結果が得られた。フラックスの充填量はフラックスの除去量に相当する。200μmより大きな直径の場合には、充填されるフラックス量に大きな違いは見られないが、孔径が大きくした場合、基板強度の低下につながるため、200μmの孔径がもっとも最適となる。   Next, the result shown in FIG. 5 was obtained for the relationship between the hole diameter and the amount of flux filled in the hole 9. The amount of flux filled corresponds to the amount of flux removed. When the diameter is larger than 200 μm, there is no significant difference in the amount of flux to be filled. However, when the hole diameter is increased, the strength of the substrate is lowered, so that the hole diameter of 200 μm is the most optimal.

また、接合端子部2aと接合端子部2bの上の総面積に対して、孔9の開口総面積をその30%程度とする根拠は、以下の理由による。
0.5mm角の接合端子部2a,2bに、0.1mgのペースト半田を塗布したとき、ペースト半田に含まれる金属は0.85mg程度となり、その体積は15×10−3mm程度となる。ペースト半田に含有するフラックスの体積比率を50%とした場合、フラックスも15×10−3mm程度程度含まれることになる。このフラックスが熱だれにより、隣接する接合端子部に達するように、満遍なくなく四方に広がった場合、隣接する接合端子部の中間に設けた孔9には、その半分程度を充填しなければならないと考えると、約15×10−3mmのフラックスを充填できる孔を設けなければならない。200μm径の孔9を設けた場合、一つの孔9に2mmの深さまでフラックスが充填されると考えると、孔径200μmの孔を8個設ける必要がある。この時、孔9の表面積は、隣接する2つの接合端子部の総面積に対して約30%となる。
The grounds for setting the total opening area of the holes 9 to about 30% of the total area on the joining terminal portion 2a and the joining terminal portion 2b are as follows.
When 0.1 mg of paste solder is applied to the 0.5 mm square joint terminal portions 2a and 2b, the metal contained in the paste solder is about 0.85 mg and the volume is about 15 × 10 −3 mm 3. . When the volume ratio of the flux contained in the paste solder is 50%, the flux is also included in the order of about 15 × 10 −3 mm 3 . When this flux spreads in all directions so that it reaches the adjoining junction terminal part due to heat dripping, the hole 9 provided in the middle of the adjoining junction terminal part must be filled with about half of it. When considered, a hole that can be filled with a flux of about 15 × 10 −3 mm 3 must be provided. When the holes 9 having a diameter of 200 μm are provided, it is necessary to provide eight holes having a diameter of 200 μm, assuming that one hole 9 is filled with the flux to a depth of 2 mm. At this time, the surface area of the hole 9 is about 30% with respect to the total area of two adjacent joining terminal portions.

(実施の形態2)
図6(a)(b)は本発明の実施の形態2を示す。
図6では配線基板1の上に隣接して接合端子部2a,2bが形成されている。それらの接合端子部にはさまれた領域を3等分するような線8a,8b上に、孔9が2列に配置されている。クリーム半田3を溶融させるための加熱の方法は、実施の形態1に同じであるため省略する。
(Embodiment 2)
6 (a) and 6 (b) show a second embodiment of the present invention.
In FIG. 6, the junction terminal portions 2 a and 2 b are formed adjacent to each other on the wiring board 1. The holes 9 are arranged in two rows on the lines 8a and 8b that divide the region sandwiched between these joint terminal portions into three equal parts. Since the heating method for melting the cream solder 3 is the same as that in the first embodiment, a description thereof will be omitted.

本実施例では、接合端子部2a,2bは0.5mm角程度の大きさで0.5mm程度の間隔を空けて隣接するように設けられている。また接合端子部2に挟まれた領域に、配線基板1を貫通する直径0.2mmの孔が4個ずつ2列に合計8個設けられている。   In this embodiment, the joining terminal portions 2a and 2b are provided so as to be adjacent to each other with a size of about 0.5 mm square and an interval of about 0.5 mm. Further, a total of eight holes of 0.2 mm in diameter penetrating the wiring board 1 are provided in two rows in a region sandwiched between the junction terminal portions 2.

隣接する接合端子部2a,2bのどちらか一方を加熱しクリーム半田3を溶融させた後、他方の接合端子部を加熱しクリーム半田を溶融させる場合は、この実施の形態のように接合端子部間に貫通孔を2列に配列させた方がよい。   When either one of the adjacent joining terminal portions 2a and 2b is heated to melt the cream solder 3 and then the other joining terminal portion is heated to melt the cream solder, the joining terminal portion is as in this embodiment. It is better to arrange the through holes in two rows between them.

このことを詳しく説明する。
一方の接合端子部の加熱により、熱だれを起したフラックスが孔9に充填され、加熱を停止すると共に、フラックスの温度も低下し、粘性が高くなる。その後、他方の接合端子部を加熱したときに熱だれによって広がったフラックスが貫通孔の位置に達したとしても、孔9が一列の場合には、粘性が高くなったフラックスが充填されているために毛細管現象による孔9へのフラックスの流れ込みが起こらず、フラックスが過剰に残ってしまい、半田接合不良を引き起こしてしまう。
This will be described in detail.
By heating one of the joining terminal portions, the flux that has caused the heat dripping is filled in the holes 9, and the heating is stopped, the temperature of the flux is lowered, and the viscosity is increased. After that, even when the flux spreading due to the heat reaches the position of the through hole when the other joint terminal portion is heated, if the holes 9 are in one line, the flux with increased viscosity is filled. In addition, the flux does not flow into the hole 9 due to the capillary phenomenon, and the flux remains excessively, resulting in poor solder joints.

孔9を2列に配した場合には、一方の接合端子部の加熱によって熱だれをおこしたフラックスは、加熱した接合端子部に近い側に配列された孔9に優先的に充填されるため、遠い側に配列された孔9にはフラックスが入らない状況となる。その後、他方の接合端子部を加熱し熱だれを起したフラックスはフラックスが未充填の状態の貫通孔に充填されることで、余分なフラックスが除去でき、半田接合不良を防止することができる。   In the case where the holes 9 are arranged in two rows, the flux that has been heated by heating one of the joint terminal portions is preferentially filled into the holes 9 arranged on the side close to the heated joint terminal portion. The flux 9 does not enter the holes 9 arranged on the far side. Thereafter, the flux that has been heated by heating the other joint terminal portion is filled in the through-hole that is not filled with the flux, so that excess flux can be removed and solder joint failure can be prevented.

また、接合部近傍に半田の融点よりも沸点の低いフラックス溜りができるため、局所的に熱容量が上昇する。そうすることで、別工程での再加熱等の熱履歴に対する耐性が向上するため、半田接合不良を防止することができる。   Further, since a flux pool having a boiling point lower than the melting point of the solder can be formed in the vicinity of the joint, the heat capacity is locally increased. By doing so, since the tolerance with respect to heat histories, such as reheating in another process, improves, it can prevent solder joint failure.

上記の各実施の形態において、レーザ光4の照射は、配線基板1の表面側から実施したが、配線基板1がレーザ光透過性の材料から形成されている場合には、図7に示すように配線基板1の裏面側から配線基板1を介してレーザ光4を接合端子部2a,2bに照射して、クリーム半田3を溶解する場合も同様である。   In each of the embodiments described above, the laser beam 4 is irradiated from the surface side of the wiring board 1. However, when the wiring board 1 is formed of a laser light transmissive material, as shown in FIG. The same applies to the case where the solder solder 3 is melted by irradiating the joining terminal portions 2a and 2b with the laser beam 4 from the back surface side of the wiring substrate 1 through the wiring substrate 1.

本発明は、ICチップ、チップコンデンサ、圧電素子等の電子部品を配線基板上に実装した各種の電子回路基板の信頼性の向上に寄与できる。   The present invention can contribute to improving the reliability of various electronic circuit boards in which electronic components such as IC chips, chip capacitors, and piezoelectric elements are mounted on a wiring board.

本発明の実施の形態1における配線基板の正面図と側面図The front view and side view of the wiring board in Embodiment 1 of this invention 同実施の形態の孔の効果の説明図Explanatory drawing of the effect of the hole of the embodiment 同実施の形態の孔の直径とフラックス浸入量,フラックス充填量の実験装置の説明図Explanatory drawing of experimental device of hole diameter, flux penetration amount and flux filling amount of the same embodiment 同実施の形態の孔の直径とフラックス浸入量の測定結果図Measurement result diagram of hole diameter and flux penetration of the same embodiment 同実施の形態の孔の直径とフラックス充填量の測定結果図Measurement result diagram of hole diameter and flux filling amount of the same embodiment 本発明の実施の形態2における配線基板の正面図と側面図Front view and side view of wiring board according to embodiment 2 of the present invention 別の実施の形態を説明する配線基板の正面図Front view of a wiring board for explaining another embodiment 問題点を説明する実装工程説明図Mounting process diagram explaining the problem

符号の説明Explanation of symbols

1 配線基板
2a,2b 接合端子部
3 クリーム半田
4 レーザ光
9 孔
DESCRIPTION OF SYMBOLS 1 Wiring board 2a, 2b Joint terminal part 3 Cream solder 4 Laser beam 9 Hole

Claims (7)

配線基板に隣接して設けられた接合端子部に付けられたクリーム半田を加熱して溶融させて電子部品を前記基板に実装するに際し、
前記配線基板には隣接して設けられた接合端子部で挟まれる領域に、少なくとも1つ以上の孔を予め形成し、
加熱によって前記クリーム半田が熱だれを起こし、接合端子部の塗布領域から流れ広がったフラックスを、前記孔に流して反対側の接合端子部の方に流れ出すことを防止する
電子部品実装方法。
When mounting the electronic component on the board by heating and melting the cream solder attached to the joint terminal portion provided adjacent to the wiring board,
At least one or more holes are formed in advance in a region sandwiched between joint terminal portions provided adjacent to the wiring board,
An electronic component mounting method that prevents the cream solder from dripping due to heating and causing the flux that has flowed and spread from the application region of the joint terminal portion to flow into the hole and to flow toward the opposite joint terminal portion.
孔を、隣接する接合端子部の間を二等分する線上に配置する
請求項1記載の電子部品実装方法。
The electronic component mounting method according to claim 1, wherein the hole is arranged on a line that bisects between adjacent joint terminal portions.
孔を、隣接する接合端子部の間を3等分する線上に2列となるように配列する
請求項1記載の電子部品実装方法。
The electronic component mounting method according to claim 1, wherein the holes are arranged in two rows on a line that equally divides between adjacent joint terminal portions.
隣接する接合端子部の総面積に対して、孔の開口総面積を30%以上にする
請求項1記載の電子部品実装方法。
The electronic component mounting method according to claim 1, wherein the total opening area of the holes is set to 30% or more with respect to the total area of the adjacent joining terminal portions.
孔の直径を、50〜250μmにする
請求項1記載の電子部品実装方法。
The electronic component mounting method according to claim 1, wherein the hole has a diameter of 50 to 250 μm.
隣接して設けられた接合端子部で挟まれる領域に、前記接合端子部の塗布領域から流れ広がったフラックスを逃がす孔を形成した
配線基板。
A wiring board in which a hole is formed in a region sandwiched between adjacent joint terminal portions provided to release the flux that has spread from the application region of the joint terminal portion.
隣接する接合端子部の間隔が0.5mm程度で、孔の直径が、50〜250μmである
請求項6記載の配線基板。
The wiring board according to claim 6, wherein an interval between adjacent joining terminal portions is about 0.5 mm, and a diameter of the hole is 50 to 250 μm.
JP2007116276A 2007-04-26 2007-04-26 Method for mounting electronic part Pending JP2008277360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007116276A JP2008277360A (en) 2007-04-26 2007-04-26 Method for mounting electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007116276A JP2008277360A (en) 2007-04-26 2007-04-26 Method for mounting electronic part

Publications (1)

Publication Number Publication Date
JP2008277360A true JP2008277360A (en) 2008-11-13

Family

ID=40055008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007116276A Pending JP2008277360A (en) 2007-04-26 2007-04-26 Method for mounting electronic part

Country Status (1)

Country Link
JP (1) JP2008277360A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101076385B1 (en) 2011-03-17 2011-10-25 한국기계연구원 Patterning method of substrate by the difference of surface energy
KR101093496B1 (en) 2010-01-19 2011-12-13 한국생산기술연구원 patterning method using of hydrophobic liquid injection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101093496B1 (en) 2010-01-19 2011-12-13 한국생산기술연구원 patterning method using of hydrophobic liquid injection
KR101076385B1 (en) 2011-03-17 2011-10-25 한국기계연구원 Patterning method of substrate by the difference of surface energy

Similar Documents

Publication Publication Date Title
US6076726A (en) Pad-on-via assembly technique
US9545013B2 (en) Flip chip interconnect solder mask
JP5160450B2 (en) Method of mounting semiconductor components on a circuit board
JP4502690B2 (en) Mounting board
JP5897584B2 (en) Lead-free structure in semiconductor devices
TW201237976A (en) Bump-on-lead flip chip interconnection
US6735857B2 (en) Method of mounting a BGA
JP6772232B2 (en) Printed circuit boards and electronic devices
CN102593067B (en) Interconnection structure for LGA (Land grid array) packaging with controllable welding spot height and manufacturing method of interconnection structure
JP2006303392A (en) Printed circuit board and electronic circuit substrate and manufacturing method thereof
JP2008277360A (en) Method for mounting electronic part
JP7350960B2 (en) Printed circuit boards and electronic equipment
JP2011258749A (en) Mounting method of electronic component, removing method of electronic component, and wiring board
JPS63273398A (en) Reflow soldering method for printed substrate
JP3913531B2 (en) Spacer and mounting method using the same
JP2008218552A (en) Mounting substrate and mounting method for electronic part
JP3983972B2 (en) Electronic circuit module
JP6225193B2 (en) Manufacturing method of electronic component mounting body
JP2014175523A (en) Printed wiring board
TW200416987A (en) Controlling adjacent solder pads bridge of BGA IC components
JP2795535B2 (en) Electronic component mounting method on circuit board
JP2006041121A (en) Electronic component with lead terminal and method of packaging electronic component
JP2001085832A (en) Method and device for manufacturing electronic component
JP2006024659A (en) Wiring board manufacturing method
Diepstraten et al. Design Improvements for Selective Soldering Assemblies