JP2006024659A - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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Publication number
JP2006024659A
JP2006024659A JP2004199979A JP2004199979A JP2006024659A JP 2006024659 A JP2006024659 A JP 2006024659A JP 2004199979 A JP2004199979 A JP 2004199979A JP 2004199979 A JP2004199979 A JP 2004199979A JP 2006024659 A JP2006024659 A JP 2006024659A
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Prior art keywords
melting point
conductive paste
pad
alloy
wiring board
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Yuma Otsuka
祐磨 大塚
Satoshi Hirano
聡 平野
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Priority to JP2004199979A priority Critical patent/JP2006024659A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a flip-chip wiring board, wherein electronic components can be surely and firmly mounted on the surface of the body of the board via solder bumps having few bubbles. <P>SOLUTION: The method of manufacturing the wiring board 1 comprises a process of forming conductor pads 6 on the surface of the body 2 of the board, a process of forming, on the pads 6, a conductive paste 8 containing alloy powder having a melting point lower than that of the conductor constituting the pads 6, and a reflow process of heating the conductive paste 8 into the solder bumps 9. The reflow process comprises preheating steps S1 and S2, wherein the pads 6 and the conductive paste 8 are heated at a temperate increase rate of 0.5°C/sec or less, and are preheated in a temperature zone of the melting point of the low melting point alloy ±10°C; and heating steps S3 and S4, wherein, after the preheating steps, the conductive paste 8 is heated up to a temperature higher by 10 to 30°C than the melting point of the low-melting point alloy to be melted and formed into the solder bumps 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、基板本体の表面にICチップなどの電子部品を実装するフリップチップ型の配線基板の製造方法に関する。   The present invention relates to a method of manufacturing a flip-chip type wiring board in which an electronic component such as an IC chip is mounted on the surface of a substrate body.

フリップチップ型の配線基板は、その基板本体の表面に形成した導体からなるパッドの上にハンダバンプをリフローにより形成し、かかるハンダバンプの上にICチップなどの電子部品における外部電極を載置し且つ再度リフローすることにより、上記電子部品の実装が成される。上記ハンダバンプは、上記パッドの導体よりも融点の低い合金粉末およびフラックスを含む導電性ペーストを、上記パッド上に印刷で形成し、これを一旦約150℃程度の温度域に加熱・保持した後、上記合金粉末の融点よりも高い温度に加熱するリフローによって成されている。   In a flip chip type wiring board, a solder bump is formed on a pad made of a conductor formed on the surface of the substrate body by reflow, an external electrode in an electronic component such as an IC chip is placed on the solder bump, and again. The electronic component is mounted by reflowing. The solder bump is formed by printing a conductive paste containing an alloy powder having a melting point lower than the conductor of the pad and a flux on the pad, and once heated and held in a temperature range of about 150 ° C., The reflow is performed by heating to a temperature higher than the melting point of the alloy powder.

ところで、リフロー後のハンダバンプに気泡(ボイド)が含まれていると、配線基板の内部配線と実装された電子部品との導通性を低下させると共に、かかる電子部品の実装強度が低下するため、不用意な外力により電子部品が外れる事態が生じてしまう、という問題があった。
上記ハンダバンプ中の気泡を抑制するため、基板の第1面と第2面とに電子部品を順次実装するに際し、活性作用を有し且つ半田融点温度よりも高い加熱温度の熱硬化性樹脂を含む半田接合ペーストを後で実装対象面となる第2面に限定して用いる実装基板の製造方法が提案されている(例えば、特許文献1参照)。
しかしながら、上記製造方法は、第1面および第2面に電子部品を順次実装する基板を対象とするため、第1面(表面)にのみ電子部品を実装する一般的なフリップチップ型の配線基板には、適用できない、という問題点があった。
By the way, if air bubbles (voids) are included in the solder bump after reflow, the electrical connection between the internal wiring of the wiring board and the mounted electronic component is reduced, and the mounting strength of the electronic component is reduced. There has been a problem that a situation occurs in which an electronic component is detached due to a prepared external force.
In order to suppress air bubbles in the solder bumps, a thermosetting resin having an active action and a heating temperature higher than the solder melting point temperature is included when electronic components are sequentially mounted on the first surface and the second surface of the substrate. There has been proposed a method for manufacturing a mounting substrate in which a solder bonding paste is used only on a second surface which will be a mounting target surface later (see, for example, Patent Document 1).
However, since the above manufacturing method is directed to a substrate on which electronic components are sequentially mounted on the first surface and the second surface, a general flip chip type wiring substrate on which electronic components are mounted only on the first surface (front surface) Has a problem that it cannot be applied.

特開2004−47774号公報(第1〜8頁、図3)JP 2004-47774 A (pages 1 to 8, FIG. 3)

本発明は、前述した背景技術における問題点を解決し、基板本体の表面に気泡の少ないハンダバンプを介してICチップなどの電子部品を確実且つ強固に実装し得るフリップチップ型の配線基板の製造方法を提供する、ことを課題とする。   The present invention solves the above-described problems in the background art, and a method of manufacturing a flip-chip type wiring substrate capable of securely and firmly mounting electronic components such as IC chips on the surface of the substrate body via solder bumps with few bubbles It is an issue to provide.

本発明は、上記課題を解決するため、発明者らの鋭意研究および調査の結果、基板本体の表面に位置するパッド上に形成した導電性ペーストをリフローしてハンダバンプを形成するに際し、かかるリフロー工程の加熱温度履歴を適正化することに着目して成されたものである。
即ち、本発明の配線基板の製造方法は、基板本体の表面に導体からなるパッドを形成する工程と、上記パッドの上に当該パッドを構成する導体の融点よりも低融点の合金粉末を含む導電性ペーストを形成する工程と、かかる導電性ペーストを加熱してハンダバンプに形成するリフロー工程と、を含み、かかるリフロー工程は、上記パッドおよび上記導電性ペーストを、0.5deg℃/秒以下の昇温速度により昇温し且つ上記低融点合金の融点±10℃の温度帯で予熱する予熱ステップと、係る予熱ステップの後に、上記導電性ペーストを溶融させるべく、上記低融点合金の融点よりも10℃乃至30℃高い温度に加熱することにより、上記導電性ペーストをハンダバンプに形成する加熱ステップと、を有する、ことを特徴とする。
In order to solve the above-mentioned problems, the present invention is based on the inventors' diligent research and investigation. As a result, when the conductive paste formed on the pad located on the surface of the substrate body is reflowed to form a solder bump, the reflow process is performed. This was made by paying attention to optimizing the heating temperature history.
That is, the method of manufacturing a wiring board according to the present invention includes a step of forming a pad made of a conductor on the surface of a substrate body, and a conductive material containing an alloy powder having a melting point lower than the melting point of the conductor constituting the pad on the pad. Forming a conductive paste, and a reflow process for heating the conductive paste to form solder bumps. The reflow process is a step of increasing the pad and the conductive paste by 0.5 deg ° C./second or less. A preheating step of heating at a temperature rate and preheating in a temperature range of the melting point ± 10 ° C. of the low melting alloy, and after the preheating step, the melting point of the low melting alloy is 10 A heating step of forming the conductive paste on a solder bump by heating to a temperature higher by 30 ° C. to 30 ° C.

付言すれば、本発明は、前記低融点合金は、Sn−Ag−Cu系合金であると共に、前記予熱温度(S2)は、200℃〜220℃の範囲である、配線基板の製造方法とすることも可能である。
また、上記予熱当初(S1)の昇温速度は、0.05℃/秒〜0.5℃/秒、望ましくは0.1℃/秒〜0.2℃/秒である、配線基板の製造方法とすることも可能である。
In other words, according to the present invention, the low-melting-point alloy is a Sn—Ag—Cu-based alloy, and the preheating temperature (S2) is in the range of 200 ° C. to 220 ° C. It is also possible.
In addition, the wiring board is manufactured at an initial heating rate (S1) of 0.05 ° C./second to 0.5 ° C./second, preferably 0.1 ° C./second to 0.2 ° C./second. It is also possible to use a method.

前記本発明の配線基板の製造方法によれば、ハンダバンプを形成するリフロー工程では、先ず、パッドおよび前記導電性ペーストを、0.5deg℃/秒以下の昇温速度により緩やかに昇温し、且つ上記低融点合金の融点±10℃の温度帯で予熱する予熱ステップが成される。このため、上記導電性ペーストに含まれるフラックスを十分に除去できるので、形成されるハンダバンプ中の気泡を確実に低減できる。しかも、上記予熱時間を管理することで、前記パッドを構成する導体の金属または当該パッドの表面に被覆したメッキ金属と、上記低融点合金の金属元素とが相互に拡散し、両者からなる金属間化合物をパッドとハンダバンプとの接合部付近に生成する事態を抑制することが可能となる。
従って、上記ハンダペースト上にICチップや水晶振動子などの電子部品の外部電極を載置し且つ再リフローする際に、気泡による飛沫を防止して、上記電子部品と配線基板の内部配線との間で十分な導通が取れると共に、外力により電子部品がハンダバンプから不用意に外れる事態を防止することが可能となる。
According to the method for manufacturing a wiring board of the present invention, in the reflow process for forming solder bumps, first, the pad and the conductive paste are gradually heated at a temperature rising rate of 0.5 deg ° C./second or less, and A preheating step of preheating in the temperature range of the melting point of the low melting point alloy ± 10 ° C. is performed. For this reason, since the flux contained in the said electrically conductive paste can fully be removed, the bubble in the solder bump formed can be reduced reliably. In addition, by controlling the preheating time, the metal of the conductor constituting the pad or the plating metal coated on the surface of the pad and the metal element of the low melting point alloy diffuse to each other, and the metal between the two It becomes possible to suppress the situation where the compound is generated near the joint between the pad and the solder bump.
Therefore, when the external electrode of the electronic component such as an IC chip or a crystal resonator is placed on the solder paste and reflowed, splashing due to air bubbles is prevented, and the electronic component and the internal wiring of the wiring board are prevented. Sufficient conduction can be obtained between the two, and it is possible to prevent a situation in which the electronic component is inadvertently detached from the solder bump due to an external force.

尚、前記導電性ペーストに含まれる低融点合金をSn−Ag−Cu系合金とし、且つ前記予熱温度を200℃〜220℃の範囲とすることで、本発明を具体的に実施できると共に、本発明の上述した効果を一層確実に得ることができる。
また、前記予熱当初(S1)の昇温速度を、0.05℃/秒〜0.5℃/秒、望ましくは0.1℃/秒〜0.2℃/秒とすることで、形成されるハンダバンプ中の気泡を確実に低減することが可能となる。しかも、パッドの導体または当該パッドの表面に被覆したメッキ金属と、上記低融点合金の金属元素とが相互拡散し、両者の金属間化合物の生成を抑制することが可能となる。
In addition, while making the low melting-point alloy contained in the said electrically conductive paste into a Sn-Ag-Cu type-alloy, and making the said preheating temperature into the range of 200 to 220 degreeC, this invention can be implemented concretely and this The above-described effects of the invention can be obtained more reliably.
Further, it is formed by setting the temperature rising rate at the beginning of the preheating (S1) to 0.05 ° C./second to 0.5 ° C./second, preferably 0.1 ° C./second to 0.2 ° C./second. It is possible to reliably reduce bubbles in the solder bumps. Moreover, the conductor of the pad or the plating metal coated on the surface of the pad and the metal element of the low-melting-point alloy can be interdiffused to suppress the formation of an intermetallic compound between them.

以下において、本発明を実施するための最良の形態について説明する。
図1は、例えばアルミナを主成分とする複数のセラミック層を積層した基板本体2の表面3付近の断面を示す。かかる基板本体2は、平面視が正方形または長方形を呈し、全体の厚みが約2mmであり、アルミナなどを主成分とする複数のグリーンシートを積層し、それらの間に所定のパッターンで図示しない内部配線を予め形成し、且つこれら全体を焼成したものである。
図1に示すように、基板本体2の表面3には、内部配線とビア導体4を介して導通する複数のパッド6が形成される。かかるパッド6は、WまたはMo粉末を含む導電性ペーストを、各ビア導体4の端面が露出する表面3に、スクリーン印刷して円盤形状に形成した後、上記焼成と同時に焼結したWなどの導体である。
In the following, the best mode for carrying out the present invention will be described.
FIG. 1 shows a cross section in the vicinity of the surface 3 of a substrate body 2 in which a plurality of ceramic layers mainly composed of alumina, for example, are laminated. Such a substrate body 2 has a square or rectangular shape in plan view, has an overall thickness of about 2 mm, and a plurality of green sheets mainly composed of alumina or the like are laminated, and a not-shown internal pattern with a predetermined pattern therebetween. Wiring is formed in advance and the whole is fired.
As shown in FIG. 1, a plurality of pads 6 are formed on the surface 3 of the substrate body 2 so as to be electrically connected to the internal wiring via the via conductors 4. The pad 6 is made of a conductive paste containing W or Mo powder, screen-printed on the surface 3 where the end face of each via conductor 4 is exposed, formed into a disk shape, and then sintered at the same time as the firing. It is a conductor.

次に、各ビア導体4をメッキ電極との導体として、各パッド6の表面に対し、電解Niメッキと電解Auメッキとを順次施し、厚み約4μmのNiメッキ層と厚み約0.1〜0.3μmのAuメッキ(何れも図示せず)とをそれぞれ被覆する。
更に、図2に示すように、スクリーン印刷により、各パッド6の上記メッキ層の上に、導電性ペースト8をほぼ円柱形(平均直径200μm×高さ50μm)にして個別に形成する。かかる導電性ペースト8は、粒径が約6〜12μmであるSn−Ag−Cu系合金(低融点合金)の粉末と、フラックスと、を含んでいる。尚、上記Sn−Ag−Cu系合金の融点は216℃であり、パッド6の導体を構成するWやMoの融点よりも低い。
Next, using each via conductor 4 as a conductor with a plating electrode, electrolytic Ni plating and electrolytic Au plating are sequentially applied to the surface of each pad 6 to form a Ni plating layer having a thickness of about 4 μm and a thickness of about 0.1 to 0. 3 μm Au plating (both not shown) are respectively coated.
Furthermore, as shown in FIG. 2, the conductive paste 8 is individually formed in a substantially cylindrical shape (average diameter 200 μm × height 50 μm) on the plating layer of each pad 6 by screen printing. The conductive paste 8 contains a powder of Sn—Ag—Cu alloy (low melting point alloy) having a particle size of about 6 to 12 μm and a flux. The melting point of the Sn—Ag—Cu alloy is 216 ° C., which is lower than the melting points of W and Mo constituting the conductor of the pad 6.

次いで、各パッド6上に導電性ペースト8が形成された基板本体2を、バッチ式加熱炉またはトンネル式加熱炉(何れも図示せず)に挿入して、上記導電性ペースト8を次述する各ステップ沿って加熱するリフロー工程を行う。
図4に示すように、リフロー工程は、予熱ステップS1,S2、加熱ステップS3,S4、および降温ステップS5からなる。
Next, the substrate body 2 on which the conductive paste 8 is formed on each pad 6 is inserted into a batch-type heating furnace or a tunnel-type heating furnace (both not shown), and the conductive paste 8 is described below. A reflow process of heating along each step is performed.
As shown in FIG. 4, the reflow process includes preheating steps S1 and S2, heating steps S3 and S4, and a temperature lowering step S5.

予熱ステップS1,S2は、常温付近の上記パッド6および導電性ペースト8を、0.5deg℃/秒以下の昇温速度により緩やかに昇温(S1)し、上記Sn−Ag−Cu系合金の融点216℃付近の温度、例えば200℃〜220℃の温度帯で約80〜100秒間(t2)にわたり予熱(S2)するものである。
これによれば、緩い昇温速度(200〜220℃/t1)で加熱し且つ上記温度帯で予熱するため、導電性ペースト8に含まれる前記フラックスをかなり除去できる。この結果、追って形成されるハンダバンプ中の気泡を低減することができる。しかも、予熱時間t2を200秒以下にしているため、パッド6の表面に被覆したメッキ金属:Niと、Sn−Ag−Cu系合金の金属元素:Snと、が相互拡散して両者の金属間化合物:SnNi、SnNi、またはSnNiの生成を抑制することもできる。
In the preheating steps S1 and S2, the pad 6 and the conductive paste 8 near room temperature are gradually heated (S1) at a temperature increase rate of 0.5 deg ° C./second or less, and the Sn—Ag—Cu based alloy is formed. Preheating (S2) is performed for about 80 to 100 seconds (t2) at a temperature around the melting point of 216 ° C, for example, in a temperature range of 200 ° C to 220 ° C.
According to this, since heating is performed at a slow temperature increase rate (200 to 220 ° C./t1) and preheating is performed in the above temperature range, the flux contained in the conductive paste 8 can be considerably removed. As a result, bubbles in the solder bumps to be formed later can be reduced. In addition, since the preheating time t2 is set to 200 seconds or less, the plating metal coated on the surface of the pad 6: Ni and the metal element: Sn of the Sn—Ag—Cu alloy are interdiffused to form a space between the two metals. Formation of compound: SnNi 3 , Sn 2 Ni 3 , or Sn 4 Ni 3 can also be suppressed.

上記予熱ステップの後で行う加熱ステップS3,S4は、図4に示すように、上記パッド6と導電性ペースト8とを上記Sn−Ag−Cu系合金の融点216℃よりも例えば24℃高い温度、240℃に20秒間(t4)加熱するものである。この結果、導電性ペースト8の表層付近におけるSn−Ag−Cu系合金の粉末が完全に溶融するため、図3に示すように、ほぼ半球形状のハンダバンプ9となる。
そして、最後に、上記パッド6およびハンダバンプ9を含む基板本体2を、常温付近に降温させる降温ステップS5が行われる。
以上のリフロー工程により、導電性ペースト8は、図3に示すように、ほぼ半球形状のハンダバンプ9になり、残ったフラックスを洗浄により除去することで、上記ハンダバンプ9を表面3に複数個有する配線基板1を得ることができる。
As shown in FIG. 4, the heating steps S3 and S4 performed after the preheating step are performed at a temperature, for example, by 24 ° C. higher than the melting point 216 ° C. of the Sn—Ag—Cu alloy. , Heated to 240 ° C. for 20 seconds (t4). As a result, the Sn—Ag—Cu-based alloy powder in the vicinity of the surface layer of the conductive paste 8 is completely melted, so that a solder bump 9 having a substantially hemispherical shape is formed as shown in FIG.
Finally, a temperature lowering step S5 is performed for lowering the temperature of the substrate body 2 including the pads 6 and the solder bumps 9 to near room temperature.
As a result of the above reflow process, the conductive paste 8 becomes a substantially hemispherical solder bump 9 as shown in FIG. 3, and the remaining flux is removed by washing, whereby a wiring having a plurality of the solder bumps 9 on the surface 3 is obtained. The substrate 1 can be obtained.

図5は、配線基板1の表面3に水晶振動子(電子部品)10を実装するため、各ハンダバンプ9の上に水晶振動子10の本体12の底面13に設られた外部電極14を載置した状態を示す。かかる状態で、配線基板1と水晶振動子10とをバッチ式加熱炉またはトンネル式加熱炉に挿入し、約210℃〜240℃に加熱する再リフローを行う。尚、上記外部電極14は、例えばCu系合金からなる。
その結果、前記Sn−Ag−Cu系合金の融点216℃よりも高い温度でリフローした場合、図6に示すように、溶けた各ハンダバンプ9の頂部に水晶振動子10の外部電極14が溶着される。尚、上記合金の融点付近の温度で再リフローすると、バンプ9と外部電極14とが接合される。
In FIG. 5, external electrodes 14 provided on the bottom surface 13 of the main body 12 of the crystal resonator 10 are placed on each solder bump 9 in order to mount the crystal resonator (electronic component) 10 on the surface 3 of the wiring board 1. Shows the state. In such a state, the wiring substrate 1 and the crystal unit 10 are inserted into a batch type heating furnace or a tunnel type heating furnace, and re-flow is performed to heat to about 210 ° C. to 240 ° C. The external electrode 14 is made of, for example, a Cu-based alloy.
As a result, when reflowing at a temperature higher than the melting point 216 ° C. of the Sn—Ag—Cu alloy, the external electrode 14 of the crystal unit 10 is welded to the top of each melted solder bump 9 as shown in FIG. The When reflowing is performed at a temperature near the melting point of the alloy, the bump 9 and the external electrode 14 are joined.

前記リフロー工程を経て製造された配線基板1を用いることにより、上記再リフローの際に、各ハンダバンプ9中の気泡が少ないため、水晶振動子10の外部電極14との溶着または接合を強固に行える。しかも、再リフローの加熱に伴い気泡が飛び出す際に発生する前記合金の飛沫を防止できるため、水晶振動子10の底面13に金属片が付着したり、かかる底面13に露出する配線同士間でのショートを確実に防止することができる。   By using the wiring substrate 1 manufactured through the reflow process, since there are few bubbles in each solder bump 9 at the time of the reflow, the welding or bonding with the external electrode 14 of the crystal resonator 10 can be performed firmly. . Moreover, since it is possible to prevent splashing of the alloy that occurs when bubbles blow out with re-reflow heating, metal pieces adhere to the bottom surface 13 of the crystal resonator 10 or between the wirings exposed to the bottom surface 13. Short circuit can be surely prevented.

ここで、本発明の具体的な実施例について、比較例と併せて説明する。
アルミナを主成分とし、縦×横:100mm×100mm・厚み:2mmの外形である基板本体2を同じ製造条件で複数個用意した。これらの基板本体2の表面3には、直径:約100μm×厚み:約20μmでWを主成分とパッド6が縦×横:2×3個ずつ合計6個が格子状の配置で形成されている。
各基板本体2における各パッド6の表面に対し、同じ条件で電解Niメッキを施して、厚みが3.5μmのNiメッキ層を個別に被覆した。更に、かかるNiメッキ層の表面に対し、同じ条件で電解Auメッキを施して、厚みが0.3μmのAuメッキ層を個別に被覆した。
Here, specific examples of the present invention will be described together with comparative examples.
A plurality of substrate main bodies 2 having alumina as a main component and having an outer shape of length × width: 100 mm × 100 mm and thickness: 2 mm were prepared under the same manufacturing conditions. On the surface 3 of these substrate bodies 2, a total of 6 pieces each having a diameter: about 100 μm × thickness: about 20 μm and W as a main component and pads 6 in length × width: 2 × 3 are arranged in a grid pattern. Yes.
The surface of each pad 6 in each substrate body 2 was subjected to electrolytic Ni plating under the same conditions to individually coat a Ni plating layer having a thickness of 3.5 μm. Furthermore, the surface of the Ni plating layer was subjected to electrolytic Au plating under the same conditions, and individually coated with an Au plating layer having a thickness of 0.3 μm.

次に、各基板本体2における各パッド6の上記メッキ層の上に、同じスクリーン印刷により、ほぼ円柱形(平均直径200μm×高さ50μm)の導電性ペースト8を個別に形成した。かかる導電性ペースト8は、Sn−Ag−Cu系合金の粉末を90wt%、フラックスを10wt%を含む。
各パッド6上に導電性ペースト8が形成された各基板本体2を、トンネル式加熱炉に挿入し、表1に示す異なる昇温速度で個別に加熱・昇温(S1)し且つ216℃±10℃に100秒間保持(S2)する前記リフロー工程における予熱ステップS1,S2を施した。
引き続き、上記各基板本体2を240℃で20秒間加熱・保持する前記リフロー工程における加熱ステップS3,S4を施して、前記導電性ペースト8をハンダバンプ9に形成した複数の配線基板(1)を得た。
表1に示す昇温速度別に各配線基板(1)を実施例1〜4と比較例1,2とに区分し、各例ごとに20個の配線基板(1)を製造した。
Next, a substantially cylindrical conductive paste 8 (average diameter 200 μm × height 50 μm) was individually formed on the plated layer of each pad 6 in each substrate body 2 by the same screen printing. The conductive paste 8 contains 90 wt% of Sn—Ag—Cu alloy powder and 10 wt% of flux.
Each substrate body 2 on which the conductive paste 8 is formed on each pad 6 is inserted into a tunnel-type heating furnace, individually heated and heated (S1) at different heating rates shown in Table 1, and 216 ° C. ± Preheating steps S1 and S2 in the reflow process of holding at 10 ° C. for 100 seconds (S2) were performed.
Subsequently, heating steps S3 and S4 in the reflow process of heating and holding each substrate body 2 at 240 ° C. for 20 seconds are performed to obtain a plurality of wiring boards (1) in which the conductive paste 8 is formed on the solder bumps 9. It was.
Each wiring board (1) was divided into Examples 1-4 and Comparative Examples 1 and 2 according to the temperature rising rate shown in Table 1, and 20 wiring boards (1) were manufactured for each example.

各例の配線基板(1)の表面3に水晶振動子(電子部品)10を実装すべく、前記図5に示したように、各ハンダバンプ9の上に水晶振動子10の本体12の底面13に設られけた外部電極14を載置した。かかる状態で、各例の配線基板(1)と水晶振動子10とをトンネル式加熱炉に挿入し、240℃に20秒間加熱する再リフローを行った。
図6に示すように、各例の配線基板(1)の表面3上に実装された水晶振動子10の本体12の上面中央に、接着剤16を介してロッド18を垂直に立設した。
In order to mount the crystal resonator (electronic component) 10 on the surface 3 of the wiring board (1) of each example, the bottom surface 13 of the main body 12 of the crystal resonator 10 is placed on each solder bump 9 as shown in FIG. The external electrode 14 provided on the substrate was placed. In this state, the wiring board (1) of each example and the crystal resonator 10 were inserted into a tunnel-type heating furnace, and re-flowing was performed by heating to 240 ° C. for 20 seconds.
As shown in FIG. 6, a rod 18 was erected vertically with an adhesive 16 in the center of the upper surface of the main body 12 of the crystal resonator 10 mounted on the surface 3 of the wiring board (1) of each example.

各例の配線基板(1)を固定し且つ個々の配線基板(1)ごとに、図6中の矢印で示すように、上記ロッド18に軸方向に沿った荷重を加えて引っ張る破壊試験を行った。そして、何れかの位置で破壊(破断)した際の破壊モードと破断強度とを測定し、それらを表1に示した。
尚、破断強度は、1個の配線基板(1)における6箇所のパッド6、ハンダバンプ9、および外部電極14の接合部の全てが破壊された際における、各例の配線基板(1)での6箇所のパッド6ごとの平均値を算出した。
また、破壊モードは、図7の左側に示すように、パッド6とハンダバンプ9との間で破壊したものをAモード、図7の右側中央寄りに示すように、ハンダバンプ9と外部電極14との間で破壊したものをCモード、図7の右端寄りに示すように、ハンダバンプ9の中間で破壊したものをDモードとして区分した。尚、表1に示すように、上記AモードとCモードとが混在したものをBモードとした。
As shown by the arrows in FIG. 6, a destructive test is performed by fixing the wiring board (1) of each example and pulling the rod 18 by applying a load along the axial direction as indicated by an arrow in FIG. 6. It was. And the fracture mode and fracture strength at the time of fracture (break) at any position were measured, and these are shown in Table 1.
The breaking strength is the same for each wiring board (1) when the joints of the six pads 6, solder bumps 9, and external electrodes 14 in one wiring board (1) are all destroyed. The average value for each of the six pads 6 was calculated.
Further, as shown in the left side of FIG. 7, the destruction mode is an A mode in which the destruction between the pad 6 and the solder bump 9 is performed, and as shown near the right center of FIG. Those broken in between were classified as C mode, and those broken in the middle of the solder bumps 9 were classified as D mode as shown on the right side of FIG. As shown in Table 1, the B mode was defined as a mixture of the A mode and the C mode.

Figure 2006024659
Figure 2006024659

尚、上記破壊する前の各例の配線基板(1)ごとに、ハンダバンプ9中の気泡が発生した割合(%)をX線で測定し、そのうちで直径が30μmを越える気泡の割合(%、平均値)を個別に算出した。それらも表1に示した。
表1によれば、実施例1〜4の配線基板1では、直径が30μm超であるボイドの割合(30μmを越えるボイドが確認されたバンプ数/検査した総バンプ数)が8%以下であった。これは、前記リフロー工程の予熱ステップS1での昇温速度を0.4deg℃/秒以下と低くし且つ前記温度帯で予熱(S2)したため、導電性ペースト8中のフラックス成分を十分除去できたことによるものである。特に、予熱ステップS1での昇温速度が0.04deg℃/秒と最もゆっくり昇温した実施例4では、気泡の発生率は最小となった。
For each wiring board (1) in each example before destruction, the ratio (%) of bubbles generated in the solder bumps 9 was measured by X-rays. Among these, the ratio of bubbles exceeding 30 μm in diameter (%, The average value was calculated individually. They are also shown in Table 1.
According to Table 1, in the wiring boards 1 of Examples 1 to 4, the ratio of voids having a diameter exceeding 30 μm (the number of bumps in which voids exceeding 30 μm were confirmed / the total number of bumps inspected) was 8% or less. It was. This is because the heating rate in the preheating step S1 of the reflow process was lowered to 0.4 deg.degree. C./second or less and preheating (S2) was performed in the temperature range, so that the flux component in the conductive paste 8 could be sufficiently removed. It is because. In particular, in Example 4 where the temperature increase rate in the preheating step S1 was 0.04 deg ° C./second, which was the slowest temperature increase, the bubble generation rate was minimized.

一方、表1に示すように、比較例1,2の配線基板では、ハンダバンプ9中における気泡の発生割合が10%以上となった。これは、予熱ステップS1での昇温速度を0.6deg℃/秒以上と高くしたため、前記温度帯で予熱(S2)したにも拘わらず、導電性ペースト8中のフラックス成分を十分除去できなかったことによるものである。
また、表1によれば、実施例1〜4の配線基板1では、破壊した位置が全てハンダバンプ9と外部電極(チップ)14との間(Cモード)であった。これは、パッド6とハンダバンプ9との接合部付近における金属間化合物の生成が少なかったため、この位置よりも接合強度が低い上記位置で破壊したものである。
On the other hand, as shown in Table 1, in the wiring boards of Comparative Examples 1 and 2, the bubble generation ratio in the solder bumps 9 was 10% or more. This is because the heating rate in the preheating step S1 was increased to 0.6 deg.degree. C./second or more, and thus the flux component in the conductive paste 8 could not be sufficiently removed despite the preheating (S2) in the temperature range. It is because of that.
Further, according to Table 1, in the wiring boards 1 of Examples 1 to 4, all the broken positions were between the solder bumps 9 and the external electrodes (chips) 14 (C mode). This is because the formation of an intermetallic compound in the vicinity of the joint portion between the pad 6 and the solder bump 9 is small, and therefore, the joint is broken at the position where the joint strength is lower than this position.

以上のような実施例1〜4の配線基板1の結果から、本発明の作用が理解され且つその効果が裏付けられた。
尚、表1に示すように、実施例1,3の破断強度は、最少となった。これは、前記リフロー工程の予熱ステップS1での昇温速度を0.4deg℃/秒以下としたため、各パッド6の表面のメッキ金属:Niと、導電性ペースト8中のSn−Ag−Cu系合金の金属元素:Snとが相互拡散し、両者の金属間化合物:SnNiなどがパッド6とハンダバンプ9との接合部付近に生成し、かかる接合部の強度を僅かに低下させたものと推定される。従って、予熱ステップS1,S2での昇温速度と予熱時間とを、破壊試験時に前記CモードよりもAモードで破壊するように、調整することが肝要である。
From the results of the wiring boards 1 of Examples 1 to 4 as described above, the operation of the present invention was understood and the effect was supported.
As shown in Table 1, the breaking strengths of Examples 1 and 3 were minimized. This is because the rate of temperature increase in the preheating step S1 of the reflow process is set to 0.4 deg ° C./second or less, so that the plating metal: Ni on the surface of each pad 6 and the Sn—Ag—Cu system in the conductive paste 8 It is presumed that the metal element of the alloy: Sn is interdiffused, and the intermetallic compound: SnNi 3 is formed in the vicinity of the joint between the pad 6 and the solder bump 9 and the strength of the joint is slightly reduced. Is done. Therefore, it is important to adjust the temperature increase rate and the preheating time in the preheating steps S1 and S2 so as to break in the A mode rather than the C mode in the destructive test.

本発明は、以上において説明した実施の形態および実施例に限定されない。
前記基板本体2は、樹脂または金属製のコア基板と、その表面および裏面の少なくとも一方に形成した複数の樹脂層と、これらの間に設けた内部配線とを含む形態としても良い。
また、前記パッド6は、前記基板本体2の表面3に限らず、これと対向する裏面にも併設しても良く、かかる裏面のパッド6に対しても前記各工程を施して前記ハンダバンプ9を形成しても良い。即ち、本発明の前記「表面」には、基板本体の裏面も包含されている。上記表面3および裏面にパッド6を併設した基板本体2の場合、前記各工程を表・裏面の全てのパッド6に対し同時行っても、表面3と裏面とのパッド6に分けて行っても良い。
更に、前記パッド6は、前記基板本体2の表面3内に凹んで形成され且つ平面視が正方形または長方形を呈するキャビティの底面に形成しても良い。
尚、前記導電性ペーストに粉末として含まれる低融点合金には、前記Sn−Ag−Cu系合金のほか、Sn−Ag系、Pb−Sn系、Sn−Cu系、Sn−Zn系合金などを用いても良い。
The present invention is not limited to the embodiments and examples described above.
The substrate body 2 may include a resin or metal core substrate, a plurality of resin layers formed on at least one of the front surface and the back surface, and internal wiring provided therebetween.
The pad 6 is not limited to the front surface 3 of the substrate body 2 and may be provided on the back surface opposite to the front surface 3. The solder bump 9 is applied to the pad 6 on the back surface by performing the above steps. It may be formed. That is, the “front surface” of the present invention includes the back surface of the substrate body. In the case of the substrate body 2 having the pads 3 on the front surface 3 and the back surface, the above steps may be performed simultaneously for all the pads 6 on the front and back surfaces or may be performed separately for the pads 6 on the front surface 3 and the back surface. good.
Furthermore, the pad 6 may be formed on the bottom surface of a cavity that is recessed in the surface 3 of the substrate body 2 and has a square or rectangular shape in plan view.
In addition to the Sn-Ag-Cu alloy, the Sn-Ag alloy, Pb-Sn alloy, Sn-Cu alloy, Sn-Zn alloy and the like are included in the low melting point alloy contained as a powder in the conductive paste. It may be used.

本発明の製造方法における一工程を示す概略断面図。The schematic sectional drawing which shows 1 process in the manufacturing method of this invention. 図1に続く工程を示す概略断面図。FIG. 2 is a schematic sectional view showing a step following FIG. 1. 図2に続く工程を示す概略断面図。FIG. 3 is a schematic sectional view showing a step following FIG. 2. 本発明のリフロー工程の温度履歴を示す概略図。Schematic which shows the temperature history of the reflow process of this invention. 本発明により得られた配線基板の表面に電子部品を実装する工程を示す概略図。Schematic which shows the process of mounting an electronic component on the surface of the wiring board obtained by this invention. 表面に電子部品を実装した上記配線基板およびその破壊試験を示す概略図。Schematic which shows the said wiring board which mounted the electronic component on the surface, and its destructive test. 上記破壊試験後の実施例および比較例の配線基板を示す概略図。Schematic which shows the wiring board of the Example after the said destructive test, and a comparative example.

符号の説明Explanation of symbols

1……………配線基板
2……………基板本体
3……………表面
6……………パッド
8……………導電性ペースト
9……………ハンダバンプ
S1,S2…予熱ステップ
S3,S4…加熱ステップ
1 …………… Wiring board 2 …………… Board body 3 …………… Surface 6 …………… Pad 8 ……………… Conductive paste 9 …………… Solder bump S1, S2… Preheating step S3, S4 ... Heating step

Claims (1)

基板本体の表面に導体からなるパッドを形成する工程と、
上記パッドの上に当該パッドを構成する導体の融点よりも低融点の合金粉末を含む導電性ペーストを形成する工程と、
上記導電性ペーストを加熱してハンダバンプに形成するリフロー工程と、を含み、
上記リフロー工程は、上記パッドおよび上記導電性ペーストを、0.5deg℃/秒以下の昇温速度により昇温し且つ上記低融点合金の融点±10℃の温度帯で予熱する予熱ステップと、
上記予熱ステップの後に、上記導電性ペーストを溶融させるべく、上記低融点合金の融点よりも10℃乃至30℃高い温度に加熱することにより、上記導電性ペーストをハンダバンプに形成する加熱ステップと、を有する、
ことを特徴とする配線基板の製造方法。
Forming a conductor pad on the surface of the substrate body;
Forming a conductive paste containing an alloy powder having a melting point lower than the melting point of the conductor constituting the pad on the pad;
A reflow step of forming the solder bump by heating the conductive paste,
The reflow step is a preheating step in which the pad and the conductive paste are heated at a temperature rising rate of 0.5 degC / second or less and preheated in a temperature range of the melting point of the low melting point alloy ± 10 ° C.
After the preheating step, in order to melt the conductive paste, a heating step of forming the conductive paste on a solder bump by heating to a temperature higher by 10 ° C. to 30 ° C. than the melting point of the low melting point alloy. Have
A method for manufacturing a wiring board.
JP2004199979A 2004-07-07 2004-07-07 Wiring board manufacturing method Pending JP2006024659A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7838411B2 (en) * 2006-12-04 2010-11-23 Semiconductor Manufacturing International (Shanghai) Corporation Fluxless reflow process for bump formation
JP2019208021A (en) * 2018-05-25 2019-12-05 日亜化学工業株式会社 Method for manufacturing light-emitting module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7838411B2 (en) * 2006-12-04 2010-11-23 Semiconductor Manufacturing International (Shanghai) Corporation Fluxless reflow process for bump formation
JP2019208021A (en) * 2018-05-25 2019-12-05 日亜化学工業株式会社 Method for manufacturing light-emitting module

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