JP2008270538A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2008270538A
JP2008270538A JP2007111737A JP2007111737A JP2008270538A JP 2008270538 A JP2008270538 A JP 2008270538A JP 2007111737 A JP2007111737 A JP 2007111737A JP 2007111737 A JP2007111737 A JP 2007111737A JP 2008270538 A JP2008270538 A JP 2008270538A
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resin layer
spacer
wiring
insulating film
resin
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Kazunari Nagata
一成 永田
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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Abstract

<P>PROBLEM TO BE SOLVED: To form a multilayer wiring by flattening a resin layer. <P>SOLUTION: A spacer 18 is formed at an insulating film 16 which is formed at a semiconductor substrate 10 comprising an integrated circuit 12 and an electrode 14 electrically connected to the integrated circuit 12. A wiring is formed on the spacer 18 from above the insulating film 16, for electrical connection to the electrode 14. A first resin layer 22 covering the wiring is so formed that an upper surface becomes rough corresponding to the step between the insulating film 16 and the spacer 18. By filling the rough of he first resin layer 22, a second resin layer 24 whose upper surface is flat is formed. Etching is started with the upper surface of the second resin layer 24, and is continued until a protruding part of the first resin layer 22 is exposed from the second resin layer 24 and the upper part of the spacer 18 of the wiring is exposed from the first resin layer 22. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

近年、ウエハレベルＣＳＰと呼ばれる、半導体チップ上に配線を形成して外部端子を形成するパッケージが開発されている（特許文献１）。配線の下には樹脂層を形成してあり、半導体装置がマザーボードに実装されたときにマザーボードと半導体チップとの熱膨張係数の差によって配線に生じる応力が分散・吸収されるようになっている。また、多層配線を適用することも知られている。例えば、特許文献２では、１層目の配線を凸部の上に載るように形成し、１層目の配線上に樹脂層を形成し、１層目の配線の凸部上の部分を樹脂層から露出させて、２層目の配線を樹脂層上に形成することが記載されている。しかしながら、特許文献２の方法では、１層目の配線の凸部上の部分を樹脂層から露出させるときに、樹脂層のそれ以外の部分もエッチングされてしまい、樹脂層を平坦化することが難しかった。
特開２００５−１８３５１８号公報 特開２００６−２８７０９４号公報 In recent years, a package called a wafer level CSP has been developed in which wiring is formed on a semiconductor chip to form external terminals (Patent Document 1). A resin layer is formed under the wiring so that when the semiconductor device is mounted on the mother board, the stress generated in the wiring due to the difference in thermal expansion coefficient between the mother board and the semiconductor chip is dispersed and absorbed. . It is also known to apply multilayer wiring. For example, in Patent Document 2, a first layer wiring is formed so as to be placed on a convex portion, a resin layer is formed on the first layer wiring, and a portion on the convex portion of the first layer wiring is resin. It is described that a second-layer wiring is formed on a resin layer by being exposed from the layer. However, in the method of Patent Document 2, when the portion on the convex portion of the first-layer wiring is exposed from the resin layer, other portions of the resin layer are also etched, and the resin layer can be flattened. was difficult.
JP 2005-183518 A JP 2006-287094 A

本発明は、樹脂層を平坦化して多層配線を形成することを目的とする。   An object of the present invention is to form a multilayer wiring by planarizing a resin layer.

（１）本発明に係る半導体装置の製造方法は、
（ａ）電極を有する基板に形成された絶縁膜の上にスペーサを形成する工程と、
（ｂ）前記電極に電気的に接続するように、前記スペーサ上に配線を形成する工程と、
（ｃ）前記絶縁膜及び前記スペーサの段差に対応して上面が凹凸になるように、前記配線を覆う第１の樹脂層を形成する工程と、
（ｄ）前記第１の樹脂層の前記凹凸を埋めて、上面が平坦な第２の樹脂層を形成する工程と、
（ｅ）前記配線の前記スペーサ上の部分が前記第１の樹脂層から露出するまで、前記第１の樹脂層及び前記第２の樹脂層をエッチングする工程と、
を含む。本発明によれば、第１の樹脂層は、絶縁膜及びスペーサの段差に対応して上面が凹凸になるので、逆にいうと、絶縁膜上の部分とスペーサ上の部分の厚みの差が小さい。したがって、第１の樹脂層をこのままエッチングすると、全体的に均等にエッチングされてしまって、絶縁膜上で配線が露出するおそれがある。そこで、本発明では、第１の樹脂層上に、上面が平坦な第２の樹脂層を形成する。こうすることで、第１及び第２の樹脂層の合計厚みを、絶縁膜上では厚く、スペーサ上では薄くすることができるので、配線のスペーサ上の部分のみを露出させて、絶縁膜上の部分を露出させないようにすることができる。
（２）この半導体装置の製造方法において、
前記スペーサを樹脂で形成してもよい。 (1) A method of manufacturing a semiconductor device according to the present invention includes:
(A) forming a spacer on an insulating film formed on a substrate having electrodes;
(B) forming a wiring on the spacer so as to be electrically connected to the electrode;
(C) forming a first resin layer that covers the wiring so that an upper surface thereof is uneven corresponding to the steps of the insulating film and the spacer;
(D) filling the unevenness of the first resin layer to form a second resin layer having a flat upper surface;
(E) etching the first resin layer and the second resin layer until a portion of the wiring on the spacer is exposed from the first resin layer;
including. According to the present invention, since the upper surface of the first resin layer is uneven corresponding to the step between the insulating film and the spacer, conversely, there is a difference in thickness between the portion on the insulating film and the portion on the spacer. small. Therefore, if the first resin layer is etched as it is, the entire resin layer is etched uniformly, and the wiring may be exposed on the insulating film. Therefore, in the present invention, a second resin layer having a flat upper surface is formed on the first resin layer. By doing this, the total thickness of the first and second resin layers can be thick on the insulating film and thin on the spacer, so that only the portion of the wiring on the spacer is exposed, and on the insulating film It is possible to prevent the portion from being exposed.
(2) In this method of manufacturing a semiconductor device,
The spacer may be formed of resin.

図１（Ａ）〜図２は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。本実施の形態に係る半導体装置の製造方法では、半導体基板１０を使用する。半導体基板１０は、最終製品としての半導体装置においては半導体チップであり、製造途中の中間製品においては半導体ウエハである。半導体基板１０には集積回路１２を形成する。詳しくは、半導体基板１０の一方の表層に、周知の半導体プロセスによって集積回路１２（半導体ウエハには複数の集積回路１２）を形成する。   1A to 2 are views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. In the method for manufacturing a semiconductor device according to the present embodiment, a semiconductor substrate 10 is used. The semiconductor substrate 10 is a semiconductor chip in a semiconductor device as a final product, and a semiconductor wafer in an intermediate product being manufactured. An integrated circuit 12 is formed on the semiconductor substrate 10. Specifically, the integrated circuit 12 (a plurality of integrated circuits 12 on the semiconductor wafer) is formed on one surface layer of the semiconductor substrate 10 by a known semiconductor process.

半導体基板１０には、集積回路１２に電気的に接続されるように電極１４を形成する。また、半導体基板１０には絶縁膜（例えばパッシベーション膜）１６を形成する。絶縁膜１６は、電極１４の少なくとも一部が露出するように形成する。言い換えると、集積回路１２から接続された内部配線のうち、絶縁膜１６から露出する部分が電極１４である。絶縁膜１６は無機材料（例えばＳｉＯ２等の無機酸化物）で形成してもよい。 An electrode 14 is formed on the semiconductor substrate 10 so as to be electrically connected to the integrated circuit 12. In addition, an insulating film (for example, a passivation film) 16 is formed on the semiconductor substrate 10. The insulating film 16 is formed so that at least a part of the electrode 14 is exposed. In other words, the portion exposed from the insulating film 16 in the internal wiring connected from the integrated circuit 12 is the electrode 14. The insulating film 16 may be formed of an inorganic material (for example, an inorganic oxide such as SiO 2 ).

図１（Ａ）に示すように、絶縁膜１６上にスペーサ１８を形成する。スペーサ１８は、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）などの樹脂で形成してもよいし、表面を絶縁体で被覆するのであれば金属で形成してもよい。樹脂で形成する場合には、リソグラフィを適用してパターニングしてもよい。   As shown in FIG. 1A, a spacer 18 is formed over the insulating film 16. The spacer 18 may be formed of a resin such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the surface. You may form with a metal, if it coat | covers with an insulator. When forming with resin, you may pattern by applying lithography.

図１（Ｂ）に示すように、電極１４に電気的に接続するように、電極１４上からスペーサ１８上に第１の配線２０を形成する。第１の配線２０は、絶縁膜１６に接触させてもよく、スペーサ１８に接触させてもよい。第１の配線２０は、絶縁膜１６の表面から、スペーサ１８の側面を上がって、スペーサ１８の上面に至る。第１の配線２０は、スペーサ１８の上面で終端してもよいし、さらに延びて絶縁膜１６の表面に至るようになっていてもよい。   As shown in FIG. 1B, a first wiring 20 is formed on the spacer 18 from the electrode 14 so as to be electrically connected to the electrode 14. The first wiring 20 may be in contact with the insulating film 16 or may be in contact with the spacer 18. The first wiring 20 rises from the surface of the insulating film 16 to the side surface of the spacer 18 and reaches the upper surface of the spacer 18. The first wiring 20 may terminate at the upper surface of the spacer 18 or may extend further to reach the surface of the insulating film 16.

図１（Ｃ）に示すように、第１の配線２０を覆うように第１の樹脂層２２を形成する。第１の樹脂層２２の形成には例えばポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）などを使用してもよい。スペーサ１８を樹脂で形成した際、第１の樹脂層２２をスペーサ１８と同じ樹脂を用いて形成してもよい。または、第１の樹脂層２２は、スペーサ１８を形成する材料と同じ弾性率又は熱膨張係数を持つ樹脂で形成してもよい。若しくは、第１の樹脂層２２は、スペーサ１８を形成する材料と同じ弾性率及び熱膨張係数を持つ樹脂で形成してもよい。第１の樹脂層２２は、絶縁膜１６及びスペーサ１８の段差に対応して、上面が凹凸になるように形成する。このため、第１の樹脂層２２は、絶縁膜１６上の部分とスペーサ１８上の部分の厚みの差が小さい。第１の樹脂層２２の形成は、樹脂前駆体のパターニング及びこれを加熱して硬化させることを含む。   As shown in FIG. 1C, a first resin layer 22 is formed so as to cover the first wiring 20. For example, polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or the like may be used for forming the first resin layer 22. Good. When the spacer 18 is formed of resin, the first resin layer 22 may be formed using the same resin as the spacer 18. Alternatively, the first resin layer 22 may be formed of a resin having the same elastic modulus or thermal expansion coefficient as the material forming the spacer 18. Alternatively, the first resin layer 22 may be formed of a resin having the same elastic modulus and thermal expansion coefficient as the material forming the spacer 18. The first resin layer 22 is formed so that the upper surface is uneven corresponding to the step between the insulating film 16 and the spacer 18. For this reason, the first resin layer 22 has a small thickness difference between the portion on the insulating film 16 and the portion on the spacer 18. The formation of the first resin layer 22 includes patterning of the resin precursor and heating and curing the resin precursor.

図１（Ｄ）に示すように、第１の樹脂層２２の凹凸を埋めて、上面が平坦になるように、第２の樹脂層２４を形成する。こうすることで、第１及び第２の樹脂層２２，２４の合計厚みを、絶縁膜１６上では厚く、スペーサ１８上では薄くすることができる。第２の樹脂層２４は、例えば薄膜レジストの塗布によって形成してもよい。   As shown in FIG. 1D, the second resin layer 24 is formed so that the unevenness of the first resin layer 22 is filled and the upper surface becomes flat. By doing so, the total thickness of the first and second resin layers 22 and 24 can be made thick on the insulating film 16 and thin on the spacer 18. The second resin layer 24 may be formed, for example, by applying a thin film resist.

次に、エッチング（Ｏ２プラズマエッチング）を、第２の樹脂層２４の上面に対して開始する。エッチングは、第２の樹脂層２４から第１の樹脂層２２の凸部（スペーサ１８上の部分）が露出し、第１の配線２０のスペーサ１８上の部分が第１の樹脂層２２から露出するまで行う（図１（Ｅ））。また、エッチングは、第２の樹脂層２４の上面と、第１の樹脂層２２の第２の樹脂層２４からの露出面が平坦になるように行う（図１（Ｅ））。 Then, etching (O 2 plasma etch), starts with respect to the upper surface of the second resin layer 24. In the etching, the convex portion (the portion on the spacer 18) of the first resin layer 22 is exposed from the second resin layer 24, and the portion on the spacer 18 of the first wiring 20 is exposed from the first resin layer 22. (FIG. 1E). Etching is performed so that the upper surface of the second resin layer 24 and the exposed surface of the first resin layer 22 from the second resin layer 24 are flat (FIG. 1E).

図２に示すように、第１の配線２０の第１の樹脂層２２からの露出部に電気的に接続（又は接触）するように、第２の配線２６を形成する。第２の配線２６は、第２の樹脂層２４の上面と、第１の樹脂層２２の第２の樹脂層２４からの露出面に形成し、これらに接触させてもよい。第２の配線２６は、第１又は第２の樹脂層２２，２４上に位置するランド２８を含むように形成する。また、第２の配線２６を、そのランド２８の中央部を除いて覆うように、ソルダレジスト層３０を形成する。第２の配線２６のランド２８上に外部端子（ハンダボール）３２を設ける。半導体装置は、上述した製造方法から自明の構成を含む。   As shown in FIG. 2, the second wiring 26 is formed so as to be electrically connected (or contacted) with the exposed portion of the first wiring 20 from the first resin layer 22. The second wiring 26 may be formed on the upper surface of the second resin layer 24 and the exposed surface of the first resin layer 22 from the second resin layer 24, and may be brought into contact therewith. The second wiring 26 is formed so as to include lands 28 located on the first or second resin layers 22 and 24. Also, a solder resist layer 30 is formed so as to cover the second wiring 26 except for the central portion of the land 28. An external terminal (solder ball) 32 is provided on the land 28 of the second wiring 26. The semiconductor device includes a configuration obvious from the manufacturing method described above.

本実施の形態によれば、第１の樹脂層２２は、絶縁膜１６及びスペーサ１８の段差に対応して上面が凹凸になるので、逆にいうと、絶縁膜１６上の部分とスペーサ１８上の部分の厚みの差が小さい。したがって、第１の樹脂層２２をこのままエッチングすると、全体的に均等にエッチングされてしまって、絶縁膜１６上で第１の配線２０が露出するおそれがある。そこで、本実施の形態では、第１の樹脂層２２上に、上面が平坦な第２の樹脂層２４を形成する。こうすることで、第１及び第２の樹脂層２２，２４の合計厚みを、絶縁膜１６上では厚く、スペーサ１８上では薄くすることができるので、第１の配線２０のスペーサ１８上の部分のみを露出させて、絶縁膜１６上の部分を露出させないようにすることができる。   According to the present embodiment, the upper surface of the first resin layer 22 is uneven corresponding to the step between the insulating film 16 and the spacer 18. The difference in thickness of the part is small. Therefore, if the first resin layer 22 is etched as it is, the first wiring layer 20 may be exposed on the insulating film 16 because the first resin layer 22 is etched uniformly. Therefore, in the present embodiment, the second resin layer 24 having a flat upper surface is formed on the first resin layer 22. By doing so, the total thickness of the first and second resin layers 22 and 24 can be thick on the insulating film 16 and thin on the spacer 18, so that the portion of the first wiring 20 on the spacer 18 It is possible to expose only a portion of the insulating film 16 and not to expose a portion on the insulating film 16.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１（Ａ）〜図１（Ｅ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。1A to 1E are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図２は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

符号の説明Explanation of symbols

１０…半導体基板、 １２…集積回路、 １４…電極、 １６…絶縁膜、 １８…スペーサ、 ２０…第１の配線、 ２２…第１の樹脂層、 ２４…第２の樹脂層、 ２６…第２の配線、 ２８…ランド、 ３０…ソルダレジスト層、 ３２…外部端子   DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14 ... Electrode, 16 ... Insulating film, 18 ... Spacer, 20 ... 1st wiring, 22 ... 1st resin layer, 24 ... 2nd resin layer, 26 ... 2nd 28 ... Land, 30 ... Solder resist layer, 32 ... External terminal

Claims (2)

（ａ）電極を有する基板に形成された絶縁膜の上にスペーサを形成する工程と、
（ｂ）前記電極に電気的に接続するように、前記スペーサ上に配線を形成する工程と、
（ｃ）前記絶縁膜及び前記スペーサの段差に対応して上面が凹凸になるように、前記配線を覆う第１の樹脂層を形成する工程と、
（ｄ）前記第１の樹脂層の前記凹凸を埋めて、上面が平坦な第２の樹脂層を形成する工程と、
（ｅ）前記配線の前記スペーサ上の部分が前記第１の樹脂層から露出するまで、前記第１の樹脂層及び前記第２の樹脂層をエッチングする工程と、
を含む半導体装置の製造方法。 (A) forming a spacer on an insulating film formed on a substrate having electrodes;
(B) forming a wiring on the spacer so as to be electrically connected to the electrode;
(C) forming a first resin layer that covers the wiring so that an upper surface thereof is uneven corresponding to the steps of the insulating film and the spacer;
(D) filling the unevenness of the first resin layer to form a second resin layer having a flat upper surface;
(E) etching the first resin layer and the second resin layer until a portion of the wiring on the spacer is exposed from the first resin layer;
A method of manufacturing a semiconductor device including: 請求項１に記載された半導体装置の製造方法において、
前記スペーサを樹脂で形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the spacer is formed of a resin.
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