JP2008258289A - Semiconductor-chip supporter and manufacturing method for semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain a lead sag generated in a process separating a plurality of collectively resin-sealed semiconductor devices, to prevent short-circuit while suppressing an increase in an electric resistance and to provide visually observed control for the lead sag. <P>SOLUTION: A plurality of wirings 3 (lead sections) for device regions 4 are formed so that their widths are narrowed gradually with approaches to a region 5 to be cut from the adjacent section of the region 5 to be cut mutually connecting the device regions 4. That is, the presence of generation of sags and the quantity of sags can be determined by comparing the sectional shapes computed from the sizes of the external-shapes of the extended sections of the wirings 3 and the shapes of the cut surfaces (that is, cut surfaces of the narrow width sections 3a) of wirings after dicing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor chip support and a method for manufacturing a semiconductor device using the same.

  In recent years, high-density mounting of semiconductor components (devices) has been increasingly demanded in order to cope with downsizing and high functionality of electronic devices. For this reason, semiconductor components are rapidly becoming smaller and thinner, and various devices for improving productivity have been made (Patent Documents 1, 2, and 3).

  For example, a lead frame provided with a plurality of device regions (device regions) is used, a semiconductor chip is mounted in each device region, and after electrically connecting, the plurality of device regions are collectively sealed with resin, and dicing is performed. A semiconductor device of QFN (Quad Flat Non leaded package) type is manufactured by cutting into individual pieces. There is also a semiconductor device such as a BGA formed by using a circuit-formed substrate (wiring substrate) instead of a lead frame.

In the semiconductor device of the above type, the cut surface of the lead portion is exposed on the side surface of the device.
However, in the dicing process, an integrated product of the lead portion made of metal and the sealing resin is cut with a dicing blade or the like, so that the metal component is formed on the outer periphery of the cut surface of the lead portion by friction during cutting (dicing stress). A phenomenon called “sagging” occurs (hereinafter referred to as “leading sagging”). This lead sagging appears more prominently when low hardness copper or copper alloy is used as the lead material.

  When the lead sagging protrudes from the mounting surface in QFN, the flatness of the mounting surface of the lead itself deteriorates, the connection strength to the mounting substrate decreases, and the substrate mounting property becomes unstable. When solder plating is applied, the plating film is more likely to sag. Both QFN and BGA may be short-circuited due to read sagging.

In order to cope with this, the thickness of the cut portion of the lead portion cut by dicing is made thinner than other portions, thereby reducing the area of the cut surface, reducing the absolute amount of lead sag, and preventing short circuit Some of them are
JP 2002-246530 A JP 2003-23134 A JP-A-2005-57067

However, if the thickness of the cut portion of the lead portion is made thinner than the other portions as described above, the occurrence of lead sagging can be suppressed and a short circuit can be prevented, but the electrical resistance increases.
On the other hand, since the cut surface of the lead portion and the lead sag are substantially on the same plane, there is a problem that it is difficult to visually recognize and manage the lead sag.

  An object of the present invention is to suppress lead sagging and to suppress an increase in electrical resistance. It is another object of the present invention to make it possible to visually manage lead sagging.

  In order to solve the above problems, a semiconductor chip support according to the present invention includes a plurality of device regions each having a chip mounting portion for mounting a semiconductor chip and a plurality of lead portions arranged at least on the outer peripheral side thereof. A semiconductor chip support connected and arranged in a region, wherein the plurality of lead portions of the device region extend into the cut region and gradually approach the cut region from the vicinity of the cut region. The width is narrowed. According to this, by reducing the width of the lead portion, the area of the cut surface is reduced and not only the lead sagging can be suppressed, but also the width of the lead portion is gradually reduced in the vicinity of the region to be cut, An increase in electrical resistance can be suppressed.

  The plurality of device regions and the region to be cut are provided on the substrate, and the plurality of lead portions of each device region are arranged so as to have connection terminals for the semiconductor chip in the chip mounting portion or outside the chip mounting portion. It may be a so-called wiring board.

  The to-be-cut region has a connecting portion that connects the chip mounting portion of each device region and the plurality of lead portions to the outer frame portion, and the plurality of lead portions of each device region have one end on the chip mounting portion. It may be a so-called lead frame disposed so as to face each other.

  The plurality of lead portions in each device region are preferably formed in a staggered arrangement at the boundary with the region to be cut. The plurality of lead portions in each device region have a cross-sectional shape that gradually narrows along the thickness direction, and the narrow portions are formed so as to be opposite to each other between adjacent lead portions. preferable. In addition, it is preferable that the plurality of lead portions of each device region be bent so that the intervals between the plurality of lead portions at the boundary with the region to be cut are equal when there are wide portions.

  In the wiring board, a bus wiring in which a plurality of lead portions extending from the device region are continuous is formed in the cut region, and the bus wiring is equal to or narrower than the plurality of lead portions in the device region. It is preferable to have a wiring width.

  Further, a protective film is formed to cover the substrate surface by exposing the connection terminals of the lead portions of the plurality of device regions, and further to the outer peripheral end material region of the outermost cut region surrounding the plurality of device regions. The lead portion of the device region extends in the same shape as that at the boundary with the region to be cut, and a recess that exposes the upper surface and both side surfaces of the extended lead portion is formed in the protective film. It is preferable.

  A method of manufacturing a semiconductor device according to the present invention includes a step of preparing the semiconductor chip support, and mounting a semiconductor chip in each of a plurality of device regions of the semiconductor chip support, and a plurality of lead portions in each device region Electrically connecting a plurality of electrodes formed on the semiconductor chip, a step of collectively sealing a plurality of device regions on which the semiconductor chip is mounted and a region to be cut with a sealing resin, and a resin And cutting the region to be cut of the semiconductor chip support after sealing to divide it into semiconductor devices formed for each device region.

  When preparing a semiconductor chip support in which a lead portion is extended to the end material region and a recess is formed to expose the upper surface and both side surfaces of the lead portion, the lead portion is exposed in the recess of the end material region. The method further includes the step of measuring the outer shape of the lead portion and the step of evaluating the cut surface of the lead portion exposed on the side surface of the divided semiconductor device based on the measurement value of the lead portion.

  The semiconductor chip support of the present invention not only reduces the lead sagging by reliably reducing the width of the lead portion in the vicinity of the region to be cut, but also prevents short-circuits, improves the yield, and improves the electrical resistance. The increase can be suppressed and disconnection can be prevented.

  In addition, it is possible to easily observe and manage the amount of sagging by forming a lead part in the end material region to be separated and forming a recess that exposes the upper surface and both side surfaces of the lead part. Become.

Embodiments of the present invention will be described below with reference to the drawings.
First, a method for manufacturing a resin-encapsulated semiconductor device using a wiring substrate which is a semiconductor chip support according to an embodiment of the present invention will be described.

  A wiring board 1 shown in FIG. The wiring substrate 1 includes a plurality of device regions 4 each having a die pad 2 for mounting a semiconductor element and a plurality of wirings 3 (lead portions) for electrical conduction with a semiconductor chip, which are connected by a region to be cut 5. Are arranged. The to-be-cut | disconnected area | region 5 is the grid | lattice form surrounding each of the several device area | region 4 and the whole.

  The wiring 3 has an internal connection terminal (electrode pad; not shown) around the die pad 2 and an external connection terminal (not shown) on the back surface of the substrate, and has a laminated structure here. A protective film 6 is formed on both sides of the substrate to expose and cover the internal connection terminals and external connection terminals of the wiring 3. The wiring board 1 will be described in detail later.

  With respect to the wiring substrate 1, a fixing material such as a silver paste 7 is disposed on the die pad 2 in each device region 4 as shown in FIG. 1B, and a semiconductor chip 8 is provided thereon as shown in FIG. 1C. Next, as shown in FIG. 1 (d), the plurality of electrodes of the semiconductor chip 8 in each device region 4 and the internal connection terminals are electrically connected by the thin metal wires 9.

  Thereafter, as shown in FIG. 2A, the resin sealing portion 10 is formed by a batch molding method in which a sealing region that is slightly larger than the plurality of device regions 4 is covered with one cavity of a mold and molded. As shown in FIG. 2B, external connection electrodes such as solder balls 11 are mounted on the electrode terminals on the back surface of the substrate.

  As shown in FIG. 2 (c), the resin sealing body on which the solder balls 11 are mounted is fixed by adhering the resin surface to the dicing tape 12, and then the dicing blade 13 is placed on the cut region 5 from the back side of the substrate. By applying and dicing, the to-be-cut region 5 is cut out and divided into individual semiconductor devices 14 as shown in FIG.

  FIG. 3 is an enlarged view of a part of the above-described wiring substrate 1, that is, a part of one layer of the wiring layer having a laminated structure. A common bus bar, so-called bus line 16, extending in a direction separating the device regions 4 from each other is formed in the cut region 5. The bus line 16 is used, for example, for plating the above-described internal connection terminal and external connection terminal.

  The plurality of wirings 3 in the device region 4 are extended into the cut region 5 so as to be continuous with the bus line 16. Each of the plurality of wirings 3 is provided with a narrow width portion 3a whose width gradually decreases from the vicinity of the cut region 5 to the connection region, and the extending portion in the cut region 5 has a constant width.

  The to-be-cut area | region 5 is 100-900 micrometers in width, for example, and the bus line 16 is 30-80 micrometers in width, for example. The wiring 3 has, for example, a width of 30 to 60 μm, a mutual interval of 45 to 150 μm, and an end portion (the narrowest portion) of the narrow width portion 3a has a width of about 10 to 30 μm.

  As a material for the wiring 3 and the bus line 16, copper (Ni / Au plating on the terminal portion) is mainly used when a resin is used as a base material, and Ta is mainly used when a ceramic is used as a base material. The effects of the present invention described below are particularly great when copper is the main component.

  When dicing, the above-mentioned dicing blade 13 passes on the bus line 16, the cut region 5 is cut off, and the wiring 3 is cut along the cutting line 17, that is, at the end of the narrow width portion 3a. . For this reason, the contact area with the dicing blade 13 is small as compared with the case where the wiring 3 has a constant width up to the area to be cut 5, and sagging (leading sagging) caused by friction is suppressed.

FIG. 4 is a perspective view of the separated semiconductor device.
A wiring board 1 in which the above-described bus line 16 and a plurality of wirings 3 continuous therewith are formed only in one wiring layer, for example, a wiring board formed only in the first wiring layer from the top in FIG. 1 shows a semiconductor device manufactured using 1.

  The cut surfaces of the wiring 3 cut at the time of dicing are exposed in a line along the edge of the mounting surface on the side surface of the device. The shape of the cut surface of the wiring 3, that is, the cut surface of the narrow width portion 3a is a quadrangle.

  Since the wiring 3 is cut at the end of the narrow width portion 3a as described above, even if the sag 18 is generated as shown in the figure, the absolute amount can be suppressed, and even if it is about 10 to 20 μm, In the example, since the distance between the cut surfaces of the narrow width portion 3a is sufficient at about 90 μm at the maximum, a short circuit due to the sag 18 can be prevented.

  Further, since the narrow width portion 3a is only in the vicinity of the region to be cut 5, an increase in the electrical resistance of the wiring 3 can be minimized, and the reliability of the semiconductor device is not impaired. Furthermore, since the narrow portion 3a has a shape that gradually narrows as it approaches the region to be cut 5, not only can the increase in electrical resistance of the wiring 3 be suppressed, but also the stress on the dicing blade as compared with the shape that narrows in a step shape. It is possible to suppress defects such as disconnection.

Therefore, the reliability and quality of the semiconductor device are improved, and the productivity is improved by eliminating the short-circuit defect.
FIG. 5 is a perspective view of another semiconductor device separated into pieces.

  The above-described bus line 16 and a plurality of wirings 3 continuous therewith are formed in a wiring substrate 1 formed in two wiring layers, for example, in the first and second wiring layers from the top in FIG. The semiconductor device manufactured using the wiring board 1 is shown.

  The cut surface of the wiring 3 cut at the time of dicing is exposed in a staggered arrangement on the side surface of the apparatus. In other words, the wiring 3 of each layer is formed so as to have such an arrangement. Similarly, each of the plurality of cut wirings 3 is provided with a narrow width portion 3a whose width gradually decreases from the vicinity of the cut region 5. The shape of the cut surface of the wiring 3, that is, the cut surface of the narrow width portion 3a is a quadrangle.

  With the staggered arrangement, compared to the semiconductor device shown in FIG. 4, if the distance between the wirings in the direction along the edge of the mounting surface is the same, the actual distance between the cut surfaces can be further increased and the amount of sagging 18 Even when there is more, it is possible to reliably prevent a short circuit. The thickness of the substrate portion is approximately 0.2 mm to 0.45 mm, and a distance between the upper and lower wiring distances of 0.1 mm can be secured. If the wiring 3 is applied as it is, the electrical resistance will not be increased.

FIG. 6 is a perspective view of still another semiconductor device separated into pieces.
A wiring board 1 in which the above-described bus line 16 and a plurality of wirings 3 continuous therewith are formed only in one wiring layer, for example, a wiring board formed only in the first wiring layer from the top in FIG. 1 shows a semiconductor device manufactured using 1.

  The cut surfaces of the wiring 3 cut at the time of dicing are exposed in a line along the edge of the mounting surface on the side surface of the device. Similarly, each of the plurality of cut wirings 3 is provided with a narrow width portion 3a that gradually decreases in width from the vicinity of the cut region 5 to the connection region.

  The feature of this semiconductor device is that the shape of the cut surface of the wiring 3, that is, the cut surface of the narrow width portion 3a, is a triangle. The triangles gradually narrow along the thickness direction (the direction intersecting the mounting surface, the vertical direction in the figure), and the apexes thereof are opposite to each other (upward and downward) on adjacent cut surfaces.

  By having such a triangular cross section, if the distance between wirings in the direction along the edge of the mounting surface is the same as that of the semiconductor device of FIG. Therefore, even when the distance 18 is larger, it is possible to reliably prevent a short circuit.

  If the apex angle is an isosceles triangle having an angle of 60 degrees or less, a wider distance between cut surfaces can be secured. However, as long as the width gradually decreases along the thickness direction, the shape is not limited to a triangle, and may be a trapezoid or the like. Such a shape can be easily obtained by etching.

Next, a method for manufacturing a resin-encapsulated semiconductor device using a lead frame that is a semiconductor chip support according to another embodiment of the present invention will be described.
A lead frame 21 shown in FIG. 7A is prepared. The lead frame 21 is punched from a metal plate mainly made of copper, and includes a die pad 22 for mounting a semiconductor element, a plurality of lead portions 23 arranged so that one end faces the die pad 22, and the die pad 22. A plurality of device regions 24 having suspension lead portions 23 ′ for supporting the outer frame portion 26 are connected to the outer frame portion 26 by a region to be cut 25 (shown by hatching). This is called a multiple lead frame.

  The cut region 25 has a connecting portion 28 extending in a direction for separating the device regions 24 from each other, and the plurality of lead portions 23 of the device region 24 extend into the cut region 25 so as to be continuous with the connecting portion 28. ing. Each of the plurality of lead portions 23 is provided with a narrow width portion 23a whose width gradually decreases from the vicinity of the cut region 25 to the cut region 25, and the extending portion in the cut region 25 has a constant width. It is. For example, the lead portion 23 has a width of 300 to 600 μm, a mutual interval of 350 to 500 μm, and an end portion (the narrowest portion) of the narrow width portion 23a has a width of about 100 to 300 μm.

  As for the lead frame 21, as described for the wiring board, a semiconductor is attached to the die pad 22 in each device region 24 via an adhesive (not shown) such as silver paste as shown in FIG. 7B. The chip 8 is fixed, the plurality of electrodes of the semiconductor chip 8 in each device region 24 and the internal connection terminals of the lead portion 23 are electrically connected by the thin metal wires 9, and the sealing is slightly larger than the plurality of device regions 24. The resin sealing portion 10 is formed and sealed by a batch molding method in which the region is covered with one cavity of the mold and molded.

  As shown in FIG. 2 (c), this resin sealing body is fixed by adhering the resin surface to the dicing tape 12, and then dicing by applying the dicing blade 13 to the cut region 25 from the back side of the substrate. Then, the to-be-cut region 25 is cut and divided into individual semiconductor devices 27 as shown in FIG.

  At the time of dicing, the dicing blade 13 passes over the connecting portion 28 described above, the cut region 25 is cut off, and the lead portion 23 is cut along the cutting line 29, that is, at the end of the narrow width portion 23a. Become. For this reason, the contact area with the dicing blade 13 is small compared to the case where the lead portion 23 has a constant width as a whole, and lead sagging caused by friction is suppressed.

FIGS. 8A and 8B are a perspective view and a partially enlarged view of a semiconductor device separated into individual pieces.
It is a resin-sealed and surface-mounted small semiconductor package, so-called QFN (Quad Flat Non-leaded Package).

  The back surfaces of the plurality of lead portions 23 are exposed side by side along the peripheral edge of the mounting surface of the resin sealing portion 10 formed by a resin mold (peripheral type), and the cut surfaces of the lead portions 23 cut during dicing are In the side surface of the device, that is, the side surface of the resin sealing portion 10, it is exposed in a line along the end side of the mounting surface. The shape of the cut surface of the lead portion 23, that is, the cut surface of the narrow width portion 23a is a quadrangle.

  Also in this semiconductor device 27, the same effect as described in the semiconductor device of FIG. 4 can be obtained. That is, even if the sag 18 occurs on the cut surface of the narrow width portion 23a as shown in the drawing, the absolute amount can be suppressed, and the distance between the cut surfaces of the narrow width portion 23a is sufficient. Short circuit can be prevented.

  Further, since the narrow width portion 23a is only in the vicinity of the region to be cut 25, an increase in electric resistance can be suppressed to a minimum, and the reliability of the semiconductor device is not impaired. Furthermore, since the narrow portion 23a has a shape that gradually narrows as it approaches the region to be cut 5, an increase in electrical resistance can be further suppressed as compared with a shape that narrows in a staircase shape.

Therefore, the reliability and quality of the semiconductor device are improved, and the productivity is improved by eliminating the short-circuit defect.
FIGS. 9A and 9B are a perspective view and a partially enlarged view of the separated semiconductor device.

  The back surfaces of the plurality of lead portions 23 are exposed side by side along the peripheral edge of the mounting surface of the resin sealing portion 10 formed by resin molding, and the cut surfaces of the lead portions 23 cut during dicing are the side surfaces of the device, That is, it is exposed on the side surface of the resin sealing portion 10 in a staggered arrangement. The shape of the cut surface of the lead portion 23, that is, the cut surface of the narrow width portion 23a is a quadrangle.

  As shown in the drawing, a narrow portion 23a is disposed at the lower portion in the thickness direction of one adjacent lead portion 23, and a narrow portion 23a is disposed at the upper portion in the thickness direction of the other lead portion 23. It is realized by arranging.

  By adopting the staggered arrangement, compared to the semiconductor device shown in FIG. 8, if the distance between the lead portions in the direction along the edge of the mounting surface is the same, the actual distance between the cut surfaces can be further increased. A short circuit can be reliably prevented even when the amount is larger.

10A and 10B are a perspective view and a partially enlarged view of an individual semiconductor device.
The back surfaces of the plurality of lead portions 23 are exposed side by side along the peripheral edge of the mounting surface of the resin sealing portion 10 formed by resin molding, and the cut surfaces of the lead portions 23 cut during dicing are the side surfaces of the device, That is, the resin sealing portion 10 is exposed in a row in a direction along the end side of the mounting surface.

  Similar to the semiconductor device described above with reference to FIG. 6, the shape of the cut surface of the lead portion 23, that is, the cut surface of the narrow width portion 23a, is a triangle. The lead portion 23 is a triangle that gradually narrows along the thickness direction (the direction intersecting the mounting surface, the vertical direction in the drawing), and the top portions thereof are opposite to each other (upward and downward) on adjacent cut surfaces.

  By having such a triangular cross section, if the distance between the lead portions in the direction along the edge of the mounting surface is the same as that of the semiconductor device of FIG. The distance between the cut surfaces can be further increased. Therefore, even when the amount of sagging 18 is larger, a short circuit can be reliably prevented.

FIG. 11A is a partially enlarged plan view showing a modified example of the wiring board 1.
The bus line 16 extending in the direction separating the adjacent device regions 4 is formed to have a width narrower than or equal to the width of the wiring 3 (the width of the narrow portion 3a).

  This is because, as exaggeratedly illustrated in FIG. 11B, the connection portion of each wiring 3 to the bus line 16 is rounded and often spreads toward the bus line 16. If the bus line 16 is wide, the wiring width becomes unstable near the cutting line 17 and the distance between wirings (distance between the cutting surfaces) becomes narrow.

  By setting the bus line 16 to the above-described width, it is possible to cut the wiring 3 in a region where the wiring width is stable, and to make the distance between wirings (distance between cut surfaces) constant. As a result, even when sagging occurs, a short circuit can be prevented. Since the bus line 16 is narrow, naturally, the conductor material can be reduced.

FIG. 12 is a partially enlarged plan view showing another modified example of the wiring board 1.
When a part of the plurality of wirings 3 in the device region 4 has a wide part such as the land part 30, the adjacent wiring 3 is bent along the land part 30, thereby reducing the wiring interval at the cutting line 17. Almost equal. If the wiring 3 is formed so as to be evenly spaced from the land portion 30, a portion having an extremely narrow distance between wires (distance between cut surfaces) in the cutting line 17 is formed, which is avoided. . By making the distance between the wirings constant in this way, it is possible to reliably prevent a short circuit even when sagging occurs.

FIG. 13 is a partially enlarged perspective view showing another modified example of the wiring board 1.
A plurality of wirings 3 of the device region 4 are arranged at the boundary with the region to be cut 5 on an end material region (peripheral portion) positioned further on the outer periphery of the outermost region to be cut 5 surrounding the plurality of device regions 4. And a recess 31 is formed in the protective film 6 so as to expose the upper surface and both side surfaces of the extended portion 3 b of the wiring 3. The recessed portion 31 is provided with, for example, 90 μm □ so that both sides of the extending portion 3b are recessed so that the extending portion 3b of the exposed wiring 3 can be visually observed.

  As a result, the external dimensions are measured with the major scope of the extension 3b of the wiring 3 exposed in the recess 31, and the side surface of the divided semiconductor device, that is, the cutting at the cutting line 17 is performed based on the measured value. The cut surface of the wiring 3 exposed on the surface can be evaluated.

  That is, by comparing the cross-sectional shape calculated from the external dimensions of the extension 3b of the wiring 3 and the shape of the cut surface of the wiring 3 after dicing (that is, the cut surface of the narrow width portion 3a), The presence or absence of occurrence and the amount of sag can be ascertained. Then, defects such as wiring shorts can be extracted in a short time. Depending on the evaluation result, defective products are removed, dicing speed is adjusted, and the like.

  By providing the recess 31 and the extended portion 3b of the wiring 3 in the end material region to be separated, the sagging 18 of the wiring 3 on the side surface of the semiconductor device (product) can be easily managed. It is extremely effective for improvement.

  In the above embodiment, the narrow width portions 3a and 23a of the wiring 3 and the lead portion 23 have been described as being gradually narrowed from the vicinity of the cut regions 5 and 25 to the connection region. It will be understood that the occurrence of lead sagging can be suppressed even if the portion narrows in a stepped manner in the vicinity of 5 and 25, that is, literally narrows in a convex shape.

  Further, the semiconductor chip 8 has been described as being connected to the wiring 3 or the lead portion 23 of the wiring substrate 1 or the lead frame 21 with the metal thin wire 9, but the above structure can be applied to the wiring substrate for flip chip connection. Similar effects can be obtained. When the wiring board is used, it is sufficient if there is a region where the semiconductor chip 8 can be mounted, and the die pad is not essential.

  The present invention suppresses lead sagging that occurs in the process of separating a plurality of semiconductor devices that are encapsulated in a single resin, prevents short circuit caused by the process, can be stably supplied, and can prevent defects such as disconnection. This contributes to reducing the size and thickness of electronic devices such as mobile phones and PDAs that use semiconductor devices.

Sectional drawing explaining the first half process of manufacturing a resin sealing type semiconductor device using the wiring board which is a semiconductor chip support body of one Embodiment of this invention. Sectional drawing explaining the latter half process which manufactures a resin-sealed semiconductor device using the wiring board which is a semiconductor chip support body of one Embodiment of this invention. Partial enlarged view of the above wiring board 1 is a perspective view of an example of a semiconductor device manufactured by the method of FIGS. The perspective view of the other example of the semiconductor device manufactured by the method of FIG. 1 and FIG. 1 is a perspective view of still another example of a semiconductor device manufactured by the method of FIGS. The top view and sectional drawing explaining the process of manufacturing a resin-sealed semiconductor device using the lead frame which is the semiconductor chip support body of other embodiment of this invention The perspective view of an example of the semiconductor device manufactured by the method of FIG. The perspective view of the other example of the semiconductor device manufactured by the method of FIG. FIG. 7 is a perspective view of still another example of the semiconductor device manufactured by the method of FIG. The partially expanded plan view which shows the modification of the wiring board of this invention The partially expanded plan view which shows the other modification of the wiring board of this invention The partially expanded perspective view which shows the other modification of the wiring board of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Die pad 3 Wiring 4 Device area 5 Area to be cut 6 Protective film 8 Semiconductor chip 9 Metal fine wire
10 Sealing resin or resin sealing part
13 Dicing blade
14 Semiconductor devices
16 bus lines
17 Cutting line
18 Dare
21 Lead frame
22 Die pad
23 Lead
24 Device area
25 Cut area
26 Outer frame
27 Semiconductor devices
28 Connecting part
29 cutting line
30 Land
31 recess

Claims (10)

  A semiconductor chip support in which a plurality of device regions each having a chip mounting portion for mounting a semiconductor chip and a plurality of lead portions arranged at least on the outer periphery thereof are connected and arranged at a region to be cut. A plurality of lead portions in a region extend into the region to be cut, and the width of the semiconductor chip support gradually decreases from the vicinity of the region to be cut toward the region to be cut.   A plurality of device regions and a region to be cut are provided on the substrate, and a plurality of lead portions of each device region are arranged so as to have a connection terminal for a semiconductor chip inside or outside the chip mounting portion. Item 14. A semiconductor chip support according to Item 1.   The to-be-cut region has a connecting portion that connects the chip mounting portion of each device region and the plurality of lead portions to the outer frame portion, and the plurality of lead portions of each device region have one end on the chip mounting portion. 2. The semiconductor chip support according to claim 1, which is disposed so as to face each other.   4. The semiconductor chip support according to claim 1, wherein a plurality of lead portions of each device region are formed in a staggered arrangement at a boundary portion with a region to be cut. 5.   The plurality of lead portions of each device region have a cross-sectional shape that gradually narrows along the thickness direction, and the narrow portions are formed so as to be opposite to each other between adjacent lead portions. A semiconductor chip support according to claim 3.   The plurality of lead portions of each device region are bent so that the distances between them at the boundary with the region to be cut are equal when there is a wide portion in a part thereof. A semiconductor chip support according to any one of the above.   3. A bus wiring in which a plurality of lead portions extending from the device region are continuous is formed in the cut region, and the bus wiring has a wiring width equal to or narrower than the plurality of lead portions in the device region. The semiconductor chip support according to the description.   A protective film that covers the substrate surface by exposing the connection terminals of the lead portions of the plurality of device regions is formed, and a device is formed on the outer peripheral end material region of the outermost peripheral region surrounding the plurality of device regions. The lead portion of the region is extended in the same shape as that at the boundary with the region to be cut, and the concave portion exposing the upper surface and both side surfaces of the extended lead portion is formed in the protective film. Item 3. A semiconductor chip support according to Item 2. Preparing a semiconductor chip support according to claim 1;
Mounting a semiconductor chip in each of a plurality of device regions of the semiconductor chip support, and electrically connecting a plurality of leads of each device region and a plurality of electrodes formed on the semiconductor chip;
A step of collectively sealing a plurality of device regions on which the semiconductor chip is mounted and a region to be cut with a sealing resin;
A method of manufacturing a semiconductor device, comprising: cutting a region to be cut of the semiconductor chip support after resin sealing and dividing it into semiconductor devices formed for each of the device regions. Preparing a semiconductor chip support according to claim 8;
Mounting a semiconductor chip in each of a plurality of device regions of the semiconductor chip support, and electrically connecting a plurality of leads of each device region and a plurality of electrodes formed on the semiconductor chip;
A step of collectively sealing a plurality of device regions on which the semiconductor chip is mounted and a region to be cut with a sealing resin;
A step of cutting the cut region of the semiconductor chip support after resin sealing and dividing it into semiconductor devices formed for each of the device regions;
Measuring the outer shape of the lead portion exposed in the recess of the end material region of the semiconductor chip support; and
And a step of evaluating a cut surface of the lead portion exposed on the side surface of the divided semiconductor device based on the measurement value of the lead portion.

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