JP2008244026A - Semiconductor device, manufacturing method thereof, and organic wiring board therefor - Google Patents

Semiconductor device, manufacturing method thereof, and organic wiring board therefor Download PDF

Info

Publication number
JP2008244026A
JP2008244026A JP2007080395A JP2007080395A JP2008244026A JP 2008244026 A JP2008244026 A JP 2008244026A JP 2007080395 A JP2007080395 A JP 2007080395A JP 2007080395 A JP2007080395 A JP 2007080395A JP 2008244026 A JP2008244026 A JP 2008244026A
Authority
JP
Japan
Prior art keywords
resin
wiring board
sealing
semiconductor device
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007080395A
Other languages
Japanese (ja)
Inventor
Hyoe Ueda
兵衛 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2007080395A priority Critical patent/JP2008244026A/en
Publication of JP2008244026A publication Critical patent/JP2008244026A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for improving quality by reducing the generation of a board crack at the periphery of a mold resin upon gate cutting when a semiconductor device using an organic wiring board as an interposer is manufactured. <P>SOLUTION: A resin introduction porion 6a connected to a resin introduction path of a metal mold is set up at one or a plurality of corners of a region of a resin sealed portion 6 in the organic wiring board 3, and plated wiring 8 is formed in a region abutted by the resin introduction path of the metal mold so that there is a clearance between the wiring 8 and the resin introduction portion 6a. As a concentration portion of bending stress upon the gate cutting after the molding is dispersed to the tip portion of the plated wiring 8 and the resin introduction portion 6a, the generation of the crack of the wiring board 3 is eliminated so that the disconnection of the metal wiring 2 in the board can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、樹脂封止型の半導体装置、その製造方法、およびそのための有機配線基板に関するものである。   The present invention relates to a resin-encapsulated semiconductor device, a manufacturing method thereof, and an organic wiring substrate therefor.

半導体集積回路が形成された半導体チップを有する半導体装置において、その小形・多ピン化を図る構造の一例として、ＢＧＡ（Ball Grid Array,ＣＳＰ（Chip Scale PackageあるいはChip Size Package）も含む）、ＬＧＡ（Land Grid Array）等のエリアアレイパッケージが知られている。   In a semiconductor device having a semiconductor chip on which a semiconductor integrated circuit is formed, BGA (including a Ball Grid Array, CSP (Chip Scale Package or Chip Size Package)), LGA (as an example of a structure for reducing the size and the number of pins) Land array arrays) are known.

従来のＢＧＡ型の半導体装置を図７（ａ）（ｂ）に示す。素子搭載領域１および金属配線２を形成した有機配線基板３（以下、配線基板３という）の片面に半導体素子（半導体チップ）４を搭載し、半導体素子４の電極端子と配線基板３上の金属配線２の接続端子とを金属細線５で接続し、半導体素子４および金属細線５を保護する封止樹脂部６をトランスファー成形法により形成している。配線基板３の周縁部には封止樹脂部６を設けないタイプである。   A conventional BGA type semiconductor device is shown in FIGS. A semiconductor element (semiconductor chip) 4 is mounted on one side of an organic wiring board 3 (hereinafter referred to as wiring board 3) on which an element mounting area 1 and a metal wiring 2 are formed, and electrode terminals of the semiconductor element 4 and metal on the wiring board 3 are mounted. The connection terminal of the wiring 2 is connected by a thin metal wire 5, and the sealing resin portion 6 that protects the semiconductor element 4 and the thin metal wire 5 is formed by a transfer molding method. This is a type in which the sealing resin portion 6 is not provided at the peripheral portion of the wiring board 3.

配線基板３のもう片面には、外部の実装基板などに接続するために、前記半導体素子４が接続する電極端子にスルーホール等を介して電気的に接続した複数の接続端子を配し、各接続端子上にハンダボール７などの外部接続電極を設けている。図示を一部省略しているが、金属配線２は配線基板３の両面に形成しており、金属配線３の酸化等を防止するための絶縁性の保護膜を前記接続端子の部分を除いて形成している。   On the other side of the wiring board 3, in order to connect to an external mounting board or the like, a plurality of connection terminals electrically connected to the electrode terminals to which the semiconductor element 4 is connected through through holes or the like are arranged. External connection electrodes such as solder balls 7 are provided on the connection terminals. Although illustration is partially omitted, the metal wiring 2 is formed on both surfaces of the wiring substrate 3 and an insulating protective film for preventing oxidation of the metal wiring 3 is excluded except for the connection terminal portion. Forming.

上記の半導体装置を製造する際には、生産性向上のために、図８に示したような、複数の配線基板３の領域（仮想線で囲む）を繋げた短冊状の基板を用いることが多い。各配線基板３の領域に上述の半導体素子４を搭載し、電気的接続を行ない、その後にこの短冊状の基板を加熱したモールド金型にセットし、樹脂封止部６の領域に各々対応する前記金型の複数のキャビティにコーナー部から樹脂を注入する所謂コーナーゲート方式で、複数の配線基板３の樹脂封止部６の領域を個別にかつ一括にモールドし、その後に配線基板３の領域ごとに個片化する。   When manufacturing the above semiconductor device, in order to improve productivity, it is necessary to use a strip-shaped substrate connecting regions of a plurality of wiring substrates 3 (enclosed by virtual lines) as shown in FIG. Many. The above-described semiconductor element 4 is mounted in the area of each wiring board 3, electrical connection is made, and then the strip-shaped board is set in a heated mold die, corresponding to the area of the resin sealing portion 6. In a so-called corner gate method in which resin is injected from a corner portion into a plurality of cavities of the mold, the regions of the resin sealing portions 6 of the plurality of wiring substrates 3 are individually and collectively molded, and then the region of the wiring substrate 3 is formed. Separate into pieces.

モールド工程後には、図９（ａ）に示すように封止樹脂部６外に不要な樹脂Ｒが残る（金型のポット部，ランナー部（およびゲート部）で硬化した樹脂をそれぞれポット痕樹脂Ｒ１，ランナーゲート痕樹脂Ｒ２として示す）。この不要な樹脂Ｒを取り外すために、図９（ｂ）（ｃ）に示すように、配線基板３を樹脂Ｒに対して上方向または下方向に折り曲げることにより、封止樹脂部６に連続したランナーゲート痕樹脂Ｒ２に曲げ応力を発生させ、その応力を利用して樹脂Ｒを分離させるのが最も一般的である。このようにして樹脂Ｒを分離することをゲートカットと呼んでいる。   After the molding step, unnecessary resin R remains outside the sealing resin portion 6 as shown in FIG. 9A (resin cured in the pot portion and runner portion (and gate portion) of the mold) R1, shown as runner gate trace resin R2.) In order to remove this unnecessary resin R, as shown in FIGS. 9B and 9C, the wiring substrate 3 is bent upward or downward with respect to the resin R, thereby continuing to the sealing resin portion 6. Most commonly, a bending stress is generated in the runner gate mark resin R2, and the resin R is separated using the stress. The separation of the resin R in this way is called gate cut.

図９（ｂ）は配線基板３を樹脂Ｒに対して下方向に曲げてゲートカットする状態を示している。ランナーゲート痕樹脂Ｒ２は、樹脂導入部６ａ（モールドラインの一部）上に仮想される封止樹脂部６との境界面の上部、同境界面の下部、基板表面との接続部で順に曲げ応力が発生し、この順に各部から分離されることになり、不要な樹脂Ｒは配線基板３，封止樹脂部６から取り除かれる。図９（ｃ）は配線基板３を樹脂Ｒに対して上方向に曲げてゲートカットする状態を示している。曲げ応力の伝わる順番が配線基板３を下方向に曲げる上述の場合の逆となり、ランナーゲート痕樹脂Ｒ２は、基板表面⇒樹脂導入部６ａ上に仮想される封止樹脂部６の境界面の下部⇒同境界面の上部から順に分離され、取り除かれる。   FIG. 9B shows a state in which the wiring substrate 3 is bent downward with respect to the resin R and gate-cut. The runner gate trace resin R2 is bent in order at the upper part of the boundary surface with the sealing resin part 6 hypothesized on the resin introduction part 6a (part of the mold line), the lower part of the boundary surface, and the connection part with the substrate surface. Stress is generated and separated from each part in this order, and unnecessary resin R is removed from the wiring board 3 and the sealing resin part 6. FIG. 9C shows a state where the wiring board 3 is bent upward with respect to the resin R and gate-cut. The order in which the bending stress is transmitted is the reverse of the above-described case where the wiring board 3 is bent downward, and the runner gate trace resin R2 is lower than the boundary surface of the sealing resin part 6 virtually imagined on the substrate surface → the resin introduction part 6a. ⇒Separated from the top of the boundary surface and removed.

この際に樹脂Ｒが配線基板３から容易に剥離するように、配線基板３のコーナー部に、すなわち金型の溝状のランナー部およびゲート部が当接する位置に、メッキ配線８を形成するのが一般的である（図７、図８参照）。図１０（ａ）（ｂ）に示すように、メッキ配線８は通常、封止樹脂部６の領域内に幾分入り込むように形成される。その理由は、樹脂Ｒと配線基板３上の上述の保護膜とは非常に密着力が強く、図１１（ａ）に示すようにメッキ配線がない場合には、ゲートカット時に、図１１（ｂ）に示すように半導体装置側に樹脂Ｒが残るからである。メッキ配線８を存在させることで、配線基板３上への樹脂Ｒ残りを抑えることが可能である。
特開2000-114427公報 At this time, the plated wiring 8 is formed at the corner portion of the wiring substrate 3, that is, at the position where the grooved runner portion and the gate portion of the mold come into contact so that the resin R is easily peeled off from the wiring substrate 3. Is common (see FIGS. 7 and 8). As shown in FIGS. 10A and 10B, the plated wiring 8 is usually formed so as to slightly enter the region of the sealing resin portion 6. The reason is that the resin R and the above-described protective film on the wiring substrate 3 have a very strong adhesion, and when there is no plated wiring as shown in FIG. This is because the resin R remains on the semiconductor device side as shown in FIG. The presence of the plated wiring 8 can suppress the resin R remaining on the wiring board 3.
JP 2000-114427 JP

しかし上記した従来の半導体装置の構造では、ゲートカット時に、図１２（ａ）に示す樹脂導入部６ａに曲げ応力が集中する。配線基板３を、図１２（ｂ）に示すように樹脂Ｒに対して下方向に曲げる場合も、図１２（ｃ）に示すように上方向に曲げる場合も、同様である。そのため、配線基板３における樹脂導入部６ａとの境界部や周辺のモールドライン６ｂに沿って、またその延長線上に、図１２（ｄ）に示すようにクラックＣが発生することがある。このクラックＣは、時には、配線基板３内部の金属配線２やコア材まで達し、最悪の場合、金属配線２が切断してしまうこともある。   However, in the structure of the conventional semiconductor device described above, bending stress concentrates on the resin introduction portion 6a shown in FIG. The same applies when the wiring board 3 is bent downward with respect to the resin R as shown in FIG. 12B and when it is bent upward as shown in FIG. 12C. Therefore, a crack C may occur along the boundary part with the resin introduction part 6a in the wiring board 3 and the peripheral mold line 6b and on the extension line as shown in FIG. The crack C sometimes reaches the metal wiring 2 and the core material inside the wiring board 3, and in the worst case, the metal wiring 2 may be cut.

金属配線２の切断が起こると、電気特性不良が発生し、半導体装置として致命的な欠陥となる。ゲートカット後の初期に半導体装置に電気特性不良が発生しなくても、半導体装置を外部基板へ実装した際にクラックが進行し、断線することも懸念される。   When the metal wiring 2 is cut, an electrical characteristic defect occurs, which becomes a fatal defect as a semiconductor device. Even if an electrical characteristic defect does not occur in the semiconductor device in the initial stage after the gate cut, there is a concern that cracks may progress and disconnect when the semiconductor device is mounted on an external substrate.

本発明は、上記問題に鑑みなされたもので、ゲートカット時の基板クラックの発生を抑えることを目的とする。   The present invention has been made in view of the above problems, and an object thereof is to suppress the occurrence of substrate cracks during gate cutting.

上記課題を解決するために、本発明の有機配線基板は、配線パターンと、半導体素子を搭載する素子搭載領域と、前記素子搭載領域を含む樹脂封止領域と、前記樹脂封止領域の周囲の非封止領域とを有した有機配線基板において、前記樹脂封止領域の１または複数のコーナー部に、モールド金型の樹脂導入路に接続する樹脂導入部が設定され、前記樹脂導入部との間に間隙を有するように、前記非封止領域における前記モールド金型の樹脂導入路が当接する部位にメッキ部が形成されたことを特徴とする。   In order to solve the above problems, an organic wiring board of the present invention includes a wiring pattern, an element mounting area for mounting a semiconductor element, a resin sealing area including the element mounting area, and a periphery of the resin sealing area. In an organic wiring board having a non-sealing region, a resin introduction portion connected to a resin introduction path of a mold is set at one or a plurality of corner portions of the resin sealing region. A plating portion is formed in a portion where the resin introduction path of the mold die contacts in the non-sealing region so as to have a gap therebetween.

本発明の半導体装置は、半導体素子を有機配線基板の片面に搭載し、電気的に接続し、前記半導体素子およびその電気的接続部を樹脂モールドした半導体装置であって、前記有機配線基板は、配線パターンと、半導体素子を搭載する素子搭載領域と、前記素子搭載領域を含む樹脂封止領域と、前記樹脂封止領域の周囲の非封止領域とを有しており、前記樹脂封止領域の１または複数のコーナー部に、モールド金型の樹脂導入路に接続する樹脂導入部が設定され、前記樹脂導入部との間に間隙を有するように、前記非封止領域における前記モールド金型の樹脂導入路が当接する部位にメッキ部が形成されていることを特徴とする。   The semiconductor device of the present invention is a semiconductor device in which a semiconductor element is mounted on one side of an organic wiring board and electrically connected, and the semiconductor element and its electrical connection portion are resin-molded. A wiring pattern; an element mounting area for mounting a semiconductor element; a resin sealing area including the element mounting area; and a non-sealing area around the resin sealing area. The mold mold in the non-sealing region is provided with a resin introduction section connected to a resin introduction path of the mold mold at one or a plurality of corner sections of the mold, and has a gap between the resin introduction section. A plating portion is formed at a portion where the resin introduction path contacts.

本発明の半導体装置の製造方法は、半導体素子を有機配線基板の片面に搭載し、電気的に接続し、前記半導体素子およびその電気的接続部を樹脂モールドした半導体装置の製造方法であって、配線パターンと、半導体素子を搭載する素子搭載領域と、前記素子搭載領域を含む樹脂封止領域と、前記樹脂封止領域の周囲の非封止領域と、前記樹脂封止領域の１または複数のコーナー部に設定された樹脂導入部との間に間隙を有するように前記非封止領域における前記モールド金型の樹脂導入路が当接する部位に形成されたメッキ部とを有する前記有機配線基板に、前記半導体素子を搭載し、電気的接続を行なう第１の工程と、前記第１の工程の後に、前記有機配線基板の樹脂封止領域をモールド金型を用いて樹脂モールドする第２の工程と、前記第２の工程の後に、前記非封止領域における前記モールド金型の樹脂導入路に残った樹脂を、前記樹脂に対して前記有機配線基板をその基板面の上下方向に相対移動させることにより分離することを特徴とする。   The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a semiconductor element is mounted on one side of an organic wiring board and electrically connected, and the semiconductor element and its electrical connection portion are resin-molded. One or more of a wiring pattern, an element mounting area for mounting a semiconductor element, a resin sealing area including the element mounting area, a non-sealing area around the resin sealing area, and the resin sealing area The organic wiring board having a plating portion formed at a portion where the resin introduction path of the mold die contacts in the non-sealing region so as to have a gap between the resin introduction portion set at the corner portion A first step of mounting the semiconductor element and performing electrical connection; and a second step of resin-molding the resin-sealed region of the organic wiring substrate using a mold after the first step. And before After the second step, the resin remaining in the resin introduction path of the molding die in the non-sealing region is separated by moving the organic wiring substrate relative to the resin in the vertical direction of the substrate surface. It is characterized by doing.

上記構成によれば、有機配線基板に、樹脂封止領域の樹脂導入部との間に間隙を有するようにメッキ部を形成しているので、樹脂モールド後に封止樹脂外に残る不要な樹脂を分離するゲートカットの際に発生する曲げ応力を、前記樹脂導入部とメッキ部の端部とに分散させることができ、基板クラックの発生を抑えることができる。   According to the above configuration, since the plating part is formed on the organic wiring board so as to have a gap between the resin introduction part of the resin sealing region, unnecessary resin remaining outside the sealing resin after the resin molding is formed. The bending stress generated at the time of the gate cut to be separated can be distributed to the resin introduction portion and the end portion of the plating portion, and the occurrence of substrate cracks can be suppressed.

上記の有機配線基板において、樹脂封止領域の樹脂導入部に対向するメッキ部の端部は、平面視して、矩形、Ｖ形に突出した形状、あるいはＶ形に窪んだ形状であってよい。メッキ部のメッキ材料は、Ａｕ、Ｐｄ、あるいはこれらの金属と封止樹脂に対する密着力が同等の材料であってよい。   In the above-mentioned organic wiring board, the end portion of the plating portion facing the resin introduction portion in the resin sealing region may have a rectangular shape, a V-shaped protruding shape, or a V-shaped recessed shape in plan view. . The plating material of the plating portion may be Au, Pd, or a material having an adhesive force equivalent to those metals and the sealing resin.

本発明によれば、有機配線基板に、樹脂封止領域の樹脂導入部との間に間隙を有するようにメッキ部を形成することにより、樹脂モールド後に封止樹脂外に残った不要な樹脂を分離するゲートカットの際に発生する曲げ応力を、前記樹脂導入部とメッキ部の端部とに分散させることができるので、従来、樹脂導入部への応力集中で発生していた基板クラック、断線を防止することができる。よって、断線に起因する電気特性不良を回避し、品質の安定を図ることができる。   According to the present invention, an unnecessary resin remaining outside the sealing resin after the resin molding is formed by forming a plating portion on the organic wiring substrate so as to have a gap between the resin introduction portion of the resin sealing region. Since the bending stress generated during the gate cut to be separated can be distributed to the resin introduction portion and the end portion of the plating portion, the substrate cracks and breaks that have conventionally occurred due to the stress concentration on the resin introduction portion Can be prevented. Therefore, it is possible to avoid electrical characteristic defects due to disconnection and to stabilize the quality.

以下、本発明の実施の形態を、図面を参照して具体的に説明する。
本発明の実施の形態１の半導体装置は、先に図７を用いて説明した従来のものと概ね同様の構成を有しているので、図７を援用して説明する。 Embodiments of the present invention will be specifically described below with reference to the drawings.
Since the semiconductor device according to the first embodiment of the present invention has substantially the same configuration as that of the conventional device described above with reference to FIG. 7, it will be described with reference to FIG.

図７（ａ）（ｂ）に示すＢＧＡ型の半導体装置において、素子搭載領域１および金属配線２を形成した有機配線基板３（以下、配線基板３）の片面に半導体素子４を搭載し、半導体素子４の電極端子と配線基板３上の金属配線２の接続端子とを金属細線５で接続し、半導体素子４および金属細線５を保護する封止樹脂部６をトランスファー成形法により設けている。配線基板３の周縁部には封止樹脂部６を設けないタイプである。   In the BGA type semiconductor device shown in FIGS. 7A and 7B, a semiconductor element 4 is mounted on one side of an organic wiring substrate 3 (hereinafter referred to as a wiring substrate 3) on which an element mounting region 1 and a metal wiring 2 are formed. The electrode terminal of the element 4 and the connection terminal of the metal wiring 2 on the wiring substrate 3 are connected by a thin metal wire 5, and a sealing resin portion 6 for protecting the semiconductor element 4 and the thin metal wire 5 is provided by a transfer molding method. This is a type in which the sealing resin portion 6 is not provided at the peripheral portion of the wiring board 3.

配線基板３のもう片面には、外部の実装基板などに接続するために、前記半導体素子４が接続する電極端子にスルーホール等を介して電気的に接続した複数の接続端子を配し、各接続端子上にハンダボール７などの外部接続電極を設けている。つまりこの配線基板３はインターポーザーとして機能する。図示を一部省略しているが、金属配線２は配線基板３の両面に形成しており、金属配線３の酸化等を防止するための絶縁性の保護膜を前記接続端子の部分を除いて形成している。   On the other side of the wiring board 3, in order to connect to an external mounting board or the like, a plurality of connection terminals electrically connected to the electrode terminals to which the semiconductor element 4 is connected through through holes or the like are arranged. External connection electrodes such as solder balls 7 are provided on the connection terminals. That is, the wiring board 3 functions as an interposer. Although illustration is partially omitted, the metal wiring 2 is formed on both surfaces of the wiring substrate 3 and an insulating protective film for preventing oxidation of the metal wiring 3 is excluded except for the connection terminal portion. Forming.

ただし、この半導体装置では、従来のものと異なって、図１（ａ）（ｂ）に示すように、配線基板３における封止樹脂部６の領域への樹脂導入路に形成されたメッキ配線８が、前記封止樹脂部６の領域との間に間隙Ｌを有している。   However, in this semiconductor device, unlike the conventional one, as shown in FIGS. 1A and 1B, the plated wiring 8 formed in the resin introduction path to the region of the sealing resin portion 6 in the wiring substrate 3. However, a gap L is formed between the sealing resin portion 6 and the region.

つまり、配線基板３における封止樹脂部６の領域の１つ（複数でもよい）のコーナー部に樹脂導入部６ａが設定されており、この樹脂導入部６ａに接続するモールド金型の溝状のゲート部，ランナー部が当接する基板表面にメッキ配線８が形成されているのであるが、このメッキ配線８が樹脂導入部６ａとの間に間隙Ｌを有するように形成されているのである。   That is, the resin introducing portion 6a is set at one (or a plurality of) corner portions of the sealing resin portion 6 in the wiring substrate 3, and the groove shape of the mold connected to the resin introducing portion 6a is set. The plated wiring 8 is formed on the surface of the substrate on which the gate portion and the runner portion are in contact. The plated wiring 8 is formed so as to have a gap L between the resin introducing portion 6a.

図示したメッキ配線８は、端部の形状が平面視で矩形であって、メッキ配線８への対向辺は、樹脂導入部６ａに平行であり、かつ樹脂導入部６ａとの間隙Ｌは５０〜５００ミクロン程度である。メッキ配線８の効果については後述する。   The illustrated plated wiring 8 has a rectangular end shape in plan view, the opposite side to the plated wiring 8 is parallel to the resin introducing portion 6a, and the gap L with the resin introducing portion 6a is 50 to 50. It is about 500 microns. The effect of the plated wiring 8 will be described later.

なお配線基板３において、有機基材はガラスエポキシ基板、ポリィミドテープ等が用いられ、金属配線２として、銅線が形成され、そのボンディングパッド部にニッケル＋金のメッキが施される。金属細線５は金線、アルミニウム線等が用いられ、封止樹脂部６にはエポキシ樹脂が用いられる。メッキ配線８は、金やパラジウムなど、封止樹脂部６の樹脂材料との密着力が弱い材料で形成される。   In the wiring substrate 3, a glass epoxy substrate, polyimide tape, or the like is used as the organic base material, a copper wire is formed as the metal wiring 2, and nickel + gold plating is applied to the bonding pad portion. The metal thin wire 5 is a gold wire, an aluminum wire or the like, and the sealing resin portion 6 is an epoxy resin. The plated wiring 8 is formed of a material having a weak adhesion with the resin material of the sealing resin portion 6 such as gold or palladium.

図２を参照して、上記の半導体装置の製造方法を説明する。
図２（ａ）に示すように、生産性向上のために、先に図８を用いて説明したのと同様の、複数の配線基板３の領域（仮想線で囲む）を繋げた短冊状の基板１１を用いる。各配線基板３の領域は上述の構造を有している。この基板１１の各配線基板３の素子搭載領域１に半導体素子４を搭載し、図２（ｂ）に示すように、半導体素子４と金属配線２とを金属細線５で電気的に接続する。 With reference to FIG. 2, a method of manufacturing the semiconductor device will be described.
As shown in FIG. 2A, in order to improve productivity, a strip-like shape connecting regions (surrounded by virtual lines) of a plurality of wiring boards 3 similar to that described above with reference to FIG. A substrate 11 is used. The area of each wiring board 3 has the above-described structure. A semiconductor element 4 is mounted on the element mounting region 1 of each wiring board 3 of the substrate 11, and the semiconductor element 4 and the metal wiring 2 are electrically connected by a thin metal wire 5 as shown in FIG.

次に、図２（ｃ）に示すように、電気的接続を終えた短冊状の基板１１を加熱したモールド金型１２にセットし、モールド金型１２の複数のキャビティ１６にコーナー部から樹脂を注入する所謂コーナーゲート方式で、各配線基板３上の樹脂封止部（６）の領域を個別にかつ一括にモールドする。形成される樹脂封止部６は、図２（ｄ）に示すように、配線基板３の端辺よりも若干内側に位置することとなる。   Next, as shown in FIG. 2 (c), the strip-shaped substrate 11 that has been electrically connected is set in a heated mold 12, and resin is applied to the plurality of cavities 16 of the mold 12 from the corners. In a so-called corner gate method of injecting, the region of the resin sealing portion (6) on each wiring substrate 3 is molded individually and collectively. The formed resin sealing portion 6 is located slightly inside the end side of the wiring board 3 as shown in FIG.

その後に、図２（ｅ）に示すように、各配線基板３の領域の反対面に、ハンダボール７などの外部接続電極を搭載する。また配線基板３の領域の外周縁部をクランプ金型１５でクランプし、切断刃１９により配線基板３の領域ごとに切断して、図２（ｆ）に示すような、個片の半導体装置を得る。   After that, as shown in FIG. 2E, external connection electrodes such as solder balls 7 are mounted on the opposite surface of each wiring board 3 region. Further, the outer peripheral edge portion of the area of the wiring board 3 is clamped by the clamp die 15 and is cut for each area of the wiring board 3 by the cutting blade 19 so that the individual semiconductor device as shown in FIG. obtain.

上記のモールドの際に用いる封止金型１２は、短冊状の基板を挟みこむ上型１３と下型１４とを有しており、上型１３に、樹脂封止部６に相応するキャビティ１６を形成する凹部が形成されている。図示を省略するが、上型１３のキャビティ１６の１つのコーナー部に、ゲート部およびランナー部が連絡しており、ゲート部と対角のコーナー部にエアベント部が連絡している。   The sealing mold 12 used in the above molding has an upper mold 13 and a lower mold 14 that sandwich a strip-shaped substrate, and a cavity 16 corresponding to the resin sealing portion 6 is formed in the upper mold 13. A recess for forming is formed. Although illustration is omitted, the gate portion and the runner portion are in communication with one corner portion of the cavity 16 of the upper mold 13, and the air vent portion is in communication with the corner portion on the opposite side of the gate portion.

このため、キャビティ１６内に樹脂を注入する際に、キャビティ１６内のエアはエアベント部を通じてスムーズに排出され、キャビティ１６内に樹脂の未充填箇所が生じることなく、樹脂封止部６が良好な成形性で形成される。   For this reason, when the resin is injected into the cavity 16, the air in the cavity 16 is smoothly discharged through the air vent portion, and there is no unfilled portion of the resin in the cavity 16, and the resin sealing portion 6 is good. Formed with moldability.

一方、モールドが終了した時点では、先に図９を用いて説明したように、封止樹脂部６は不要な樹脂Ｒ（ポット痕樹脂Ｒ１，ランナーゲート痕樹脂Ｒ２）に繋がった状態なので、配線基板３を樹脂Ｒに対して上方向または下方向に折り曲げることによってランナーゲート痕樹脂Ｒ２に曲げ応力を発生させ、その応力を利用して樹脂Ｒを分離させる、所謂ゲートカットを行う。   On the other hand, since the sealing resin portion 6 is connected to unnecessary resin R (pot trace resin R1, runner gate trace resin R2) as described above with reference to FIG. A bending stress is generated in the runner gate mark resin R2 by bending the substrate 3 upward or downward with respect to the resin R, and so-called gate cutting is performed in which the resin R is separated using the stress.

その際に、上述のように、メッキ配線８の端部を、樹脂導入部６ａ（モールドライン６ｂの一部）から５０〜５００ミクロン程度の間隙６８となるように離し、且つ樹脂導入部６ａに平行な方向としているため、ゲートカットの際の曲げ応力の集中部はメッキ配線８の先端部と樹脂導入部６ａとの二ヶ所となり、従来のように曲げ応力が一箇所に集中しないことから、配線基板３のクラックの発生をなくすことができ、基板内部の金属配線２の断線を防止できる。   At that time, as described above, the end portion of the plated wiring 8 is separated from the resin introduction portion 6a (a part of the mold line 6b) so as to have a gap 68 of about 50 to 500 microns, and the resin introduction portion 6a is separated. Because it is parallel, the concentrated portion of bending stress at the time of gate cutting is two places, the tip portion of the plated wiring 8 and the resin introducing portion 6a, and the bending stress is not concentrated in one place as in the past, Generation of cracks in the wiring board 3 can be eliminated, and disconnection of the metal wiring 2 inside the board can be prevented.

結果として、図３（ａ）（ｂ）（ｃ）に示すように、樹脂導入部６ａに沿って線状の僅かな樹脂Ｒ３が残る。意識的に僅かな樹脂Ｒ３を残しながら、樹脂導入部６ａにかかる曲げ応力を緩和し、モールドライン６ｂに沿った基板クラックを回避する構造である。従来品と外観上の差は殆どないので、従来使用していた電気特性検査用治具や出荷用トレイを使用できる。   As a result, as shown in FIGS. 3A, 3B, and 3C, a slight linear resin R3 remains along the resin introducing portion 6a. In this structure, a slight resin R3 is intentionally left, the bending stress applied to the resin introduction portion 6a is relaxed, and a substrate crack along the mold line 6b is avoided. Since there is almost no difference in appearance from the conventional product, it is possible to use the electrical characteristic inspection jig and the shipping tray that have been used conventionally.

なお間隙６８を５０〜５００ミクロン程度としたのは、曲げ応力の集中箇所がメッキ配線８の先端部から若干ずれた場合を考慮してのことである。５０ミクロン未満であれば、従来と同様にモールドラインへ応力が到達する可能性があり、応力分散の効果が得られず、５００ミクロンを超えると、樹脂残りが多い外観上不良になる可能性がある（１mmの樹脂残りは外観不良と扱われるのが一般的である）。   The reason why the gap 68 is set to about 50 to 500 microns is that a case where the concentrated portion of the bending stress slightly deviates from the tip of the plated wiring 8 is taken into consideration. If it is less than 50 microns, stress may reach the mold line as in the conventional case, and the effect of stress dispersion cannot be obtained. If it exceeds 500 microns, there is a possibility that the appearance will be poor with much resin residue. Yes (1mm resin residue is generally treated as poor appearance).

図４（ａ）は本発明の実施の形態２の半導体装置を示す。配線基板３上のメッキ配線８の端部は、上記の実施の形態１の半導体装置と同様に樹脂導入部６ａから間隙６８だけ離す一方、平面視で、樹脂導入部６ａに向けてＶ形に突出した形状としている。ここで言う間隙６８は、Ｖ形の最も突出した箇所と樹脂導入部６ａとの距離であり、５０〜５００ミクロン程度である。   FIG. 4A shows a semiconductor device according to the second embodiment of the present invention. The end portion of the plated wiring 8 on the wiring board 3 is separated from the resin introduction portion 6a by a gap 68 in the same manner as the semiconductor device of the first embodiment, and is formed in a V shape toward the resin introduction portion 6a in plan view. It has a protruding shape. The gap 68 here is the distance between the most protruding portion of the V shape and the resin introducing portion 6a, and is about 50 to 500 microns.

この半導体装置では、ゲートカットの際の曲げ応力の集中部は樹脂導入部６ａとメッキ配線８の先端部とに分散し、モールドライン６ｂへの曲げ応力は線でなく点となることになり、実施の形態１の半導体装置と同様に、配線基板３のクラックの発生をなくし、基板内部の金属配線４の断線を防止できる。   In this semiconductor device, the concentrated portion of the bending stress at the time of gate cutting is dispersed in the resin introduction portion 6a and the tip end portion of the plated wiring 8, and the bending stress on the mold line 6b is not a line but a point. As in the semiconductor device of the first embodiment, the generation of cracks in the wiring board 3 can be eliminated, and disconnection of the metal wiring 4 inside the board can be prevented.

結果として、図４（ｂ）（および図３（ａ）（ｂ））に示すように、樹脂導入部６ａに沿って２つの三角柱が繋がった形状の僅かな樹脂Ｒ３が残るが、従来品と外観上の差はないので、従来使用していた電気特性検査用治具や出荷用トレイを使用できる。   As a result, as shown in FIG. 4B (and FIGS. 3A and 3B), a slight resin R3 having a shape in which two triangular prisms are connected along the resin introduction portion 6a remains. Since there is no difference in appearance, it is possible to use an electrical characteristic inspection jig and a shipping tray which have been used conventionally.

図５（ａ）は本発明の実施の形態３の半導体装置を示す。配線基板３上のメッキ配線８の端部は、上記の実施の形態１の半導体装置と同様に樹脂導入部６ａから間隙６８だけ離す一方、平面視で、樹脂導入部６ａに向けてＶ形に窪んだ形状としている。ここで言う間隙６８は、Ｖ形の最も窪んだ箇所と樹脂導入部６ａとの距離であり、５０〜５００ミクロン程度である。   FIG. 5A shows a semiconductor device according to the third embodiment of the present invention. The end portion of the plated wiring 8 on the wiring board 3 is separated from the resin introduction portion 6a by a gap 68 in the same manner as the semiconductor device of the first embodiment, and is formed in a V shape toward the resin introduction portion 6a in plan view. It has a recessed shape. The gap 68 referred to here is the distance between the most concave portion of the V shape and the resin introduction portion 6a, and is about 50 to 500 microns.

この半導体装置では、ゲートカットの際の曲げ応力の集中部は樹脂導入部６ａとメッキ配線８の先端部とに分散し、モールドライン６ｂへの曲げ応力は線でなく点となることになり、実施の形態１の半導体装置と同様に、配線基板３のクラックの発生をなくし、基板内部の金属配線４の断線を防止できる。   In this semiconductor device, the concentrated portion of the bending stress at the time of gate cutting is dispersed in the resin introduction portion 6a and the tip end portion of the plated wiring 8, and the bending stress on the mold line 6b is not a line but a point. As in the semiconductor device of the first embodiment, the generation of cracks in the wiring board 3 can be eliminated, and disconnection of the metal wiring 4 inside the board can be prevented.

結果として、図５（ｂ）（および図３（ａ）（ｂ））に示すように、樹脂導入部６ａに沿って三角柱状の僅かな樹脂Ｒ３が残るが、従来品と外観上の差はないので、従来使用していた電気特性検査用治具や出荷用トレイを使用できる。   As a result, as shown in FIG. 5B (and FIGS. 3A and 3B), a slight triangular prism-shaped resin R3 remains along the resin introduction portion 6a. Since there is no electrical jig, it is possible to use an electrical property inspection jig and a shipping tray which have been used conventionally.

以上、配線基板３にハンダボール７などのボール状の外部接続電極を設けるとして説明したが、図６（ａ）（ｂ）に示すように、ランド７ａを外部接続のために設けても構わない。   As described above, the ball-shaped external connection electrode such as the solder ball 7 is provided on the wiring board 3. However, as shown in FIGS. 6A and 6B, the land 7a may be provided for external connection. .

また、複数の配線基板３の領域を繋げた短冊状の基板を用いるとして説明したが、生産効率の点では劣るものの、独立した配線基板３を用いてもよいのは言うまでもない。   Moreover, although it demonstrated as using the strip-shaped board | substrate which connected the area | region of the some wiring board 3, although it is inferior in terms of production efficiency, it cannot be overemphasized that the independent wiring board 3 may be used.

本発明の実施の形態１の半導体装置の配線基板部分を拡大して示す平面図The top view which expands and shows the wiring board part of the semiconductor device of Embodiment 1 of this invention 図１の半導体装置の製造方法を説明する工程断面図Process sectional drawing explaining the manufacturing method of the semiconductor device of FIG. 図１の半導体装置を製造する際のゲートカットを説明する断面図および平面図Sectional drawing and top view explaining the gate cut at the time of manufacturing the semiconductor device of FIG. 本発明の実施の形態２の半導体装置の一部拡大平面図Partially enlarged plan view of the semiconductor device according to the second embodiment of the present invention 本発明の実施の形態３の半導体装置の一部拡大平面図Partially enlarged plan view of the semiconductor device according to the third embodiment of the present invention 本発明の実施の形態４の半導体装置の断面図および一部拡大断面図Sectional drawing and partial expanded sectional view of the semiconductor device of Embodiment 4 of this invention 従来よりある半導体装置の全体構成を示す断面図および平面図Sectional drawing and top view which show the whole structure of the conventional semiconductor device 図７の半導体装置の製造に用いる基板の平面図FIG. 7 is a plan view of a substrate used for manufacturing the semiconductor device of FIG. 図７の半導体装置を製造する際のゲートカットを説明する断面図Sectional drawing explaining the gate cut at the time of manufacturing the semiconductor device of FIG. 図７の半導体装置の一部を拡大して示す断面図および平面図FIG. 7 is an enlarged cross-sectional view and plan view of a part of the semiconductor device of FIG. 従来よりある他の半導体装置を製造する際のゲートカットを説明する断面図Sectional drawing explaining the gate cut at the time of manufacturing another conventional semiconductor device 図７の半導体装置を製造する際のゲートカット時の基板クラック発生を説明する断面図および平面図Sectional drawing and top view explaining the generation | occurrence | production of the substrate crack at the time of the gate cut at the time of manufacturing the semiconductor device of FIG.

符号の説明Explanation of symbols

１ 素子搭載領域
２ 金属配線
３ 配線基板
４ 半導体素子
６ 封止樹脂部
６ａ 樹脂導入部
６ｂ モールドライン
７ ハンダボール
８ メッキ配線
Ｌ 間隙
Ｒ 樹脂 DESCRIPTION OF SYMBOLS 1 Element mounting area 2 Metal wiring 3 Wiring board 4 Semiconductor element 6 Sealing resin part 6a Resin introduction part 6b Mold line 7 Solder ball 8 Plating wiring L Gap R Resin

Claims (5)

配線パターンと、半導体素子を搭載する素子搭載領域と、前記素子搭載領域を含む樹脂封止領域と、前記樹脂封止領域の周囲の非封止領域とを有した有機配線基板において、
前記樹脂封止領域の１または複数のコーナー部に、モールド金型の樹脂導入路に接続する樹脂導入部が設定され、前記樹脂導入部との間に間隙を有するように、前記非封止領域における前記モールド金型の樹脂導入路が当接する部位にメッキ部が形成されたことを特徴とする有機配線基板。 In an organic wiring board having a wiring pattern, an element mounting region for mounting a semiconductor element, a resin sealing region including the element mounting region, and a non-sealing region around the resin sealing region,
The non-sealing region is configured such that a resin introduction portion connected to a resin introduction path of a mold is set at one or a plurality of corner portions of the resin sealing region, and a gap is provided between the resin introduction portion and the resin introduction portion. An organic wiring board, wherein a plating portion is formed at a site where the resin introduction path of the mold die contacts. 樹脂封止領域の樹脂導入部に対向するメッキ部の端部が、平面視して、矩形、Ｖ形に突出した形状、あるいはＶ形に窪んだ形状であることを特徴とする請求項１記載の有機配線基板。   The end of the plated portion facing the resin introduction portion in the resin sealing region is rectangular, protruded in a V shape, or recessed in a V shape in plan view. Organic wiring board. メッキ部のメッキ材料が、Ａｕ、Ｐｄ、あるいはこれらの金属と封止樹脂に対する密着力が同等の材料であることを特徴とする請求項１記載の有機配線基板。   2. The organic wiring board according to claim 1, wherein the plating material of the plating portion is Au, Pd, or a material having an adhesion strength equivalent to these metals and the sealing resin. 半導体素子を有機配線基板の片面に搭載し、電気的に接続し、前記半導体素子およびその電気的接続部を樹脂モールドした半導体装置であって、
前記有機配線基板は、配線パターンと、半導体素子を搭載する素子搭載領域と、前記素子搭載領域を含む樹脂封止領域と、前記樹脂封止領域の周囲の非封止領域とを有しており、前記樹脂封止領域の１または複数のコーナー部に、モールド金型の樹脂導入路に接続する樹脂導入部が設定され、前記樹脂導入部との間に間隙を有するように、前記非封止領域における前記モールド金型の樹脂導入路が当接する部位にメッキ部が形成されていることを特徴とする半導体装置。 A semiconductor device in which a semiconductor element is mounted on one side of an organic wiring board and electrically connected, and the semiconductor element and its electrical connection portion are resin-molded,
The organic wiring board has a wiring pattern, an element mounting area for mounting a semiconductor element, a resin sealing area including the element mounting area, and a non-sealing area around the resin sealing area. The non-sealing is performed so that a resin introduction portion connected to a resin introduction path of a mold is set at one or a plurality of corner portions of the resin sealing region, and a gap is provided between the resin introduction portion and the resin introduction portion. A semiconductor device, wherein a plating portion is formed in a region where the resin introduction path of the mold die contacts. 半導体素子を有機配線基板の片面に搭載し、電気的に接続し、前記半導体素子およびその電気的接続部を樹脂モールドした半導体装置の製造方法であって、
配線パターンと、半導体素子を搭載する素子搭載領域と、前記素子搭載領域を含む樹脂封止領域と、前記樹脂封止領域の周囲の非封止領域と、前記樹脂封止領域の１または複数のコーナー部に設定された樹脂導入部との間に間隙を有するように前記非封止領域における前記モールド金型の樹脂導入路が当接する部位に形成されたメッキ部とを有する前記有機配線基板に、前記半導体素子を搭載し、電気的接続を行なう第１の工程と、
前記第１の工程の後に、前記有機配線基板の樹脂封止領域をモールド金型を用いて樹脂モールドする第２の工程と、
前記第２の工程の後に、前記非封止領域における前記モールド金型の樹脂導入路に残った樹脂を、前記樹脂に対して前記有機配線基板をその基板面の上下方向に相対移動させることにより分離することを特徴とする半導体装置の製造方法。 A semiconductor device is mounted on one side of an organic wiring board, electrically connected, and a method of manufacturing a semiconductor device in which the semiconductor element and its electrical connection portion are resin-molded,
One or more of a wiring pattern, an element mounting area for mounting a semiconductor element, a resin sealing area including the element mounting area, a non-sealing area around the resin sealing area, and the resin sealing area The organic wiring board having a plating portion formed at a portion where the resin introduction path of the mold die contacts in the non-sealing region so as to have a gap between the resin introduction portion set at the corner portion A first step of mounting the semiconductor element and performing electrical connection;
After the first step, a second step of resin-molding the resin sealing region of the organic wiring substrate using a mold,
After the second step, the resin remaining in the resin introduction path of the mold in the non-sealing region is moved relative to the resin in the vertical direction of the substrate surface with respect to the resin. A method for manufacturing a semiconductor device, wherein the semiconductor device is separated.
JP2007080395A 2007-03-27 2007-03-27 Semiconductor device, manufacturing method thereof, and organic wiring board therefor Pending JP2008244026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007080395A JP2008244026A (en) 2007-03-27 2007-03-27 Semiconductor device, manufacturing method thereof, and organic wiring board therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007080395A JP2008244026A (en) 2007-03-27 2007-03-27 Semiconductor device, manufacturing method thereof, and organic wiring board therefor

Publications (1)

Publication Number Publication Date
JP2008244026A true JP2008244026A (en) 2008-10-09

Family

ID=39915026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007080395A Pending JP2008244026A (en) 2007-03-27 2007-03-27 Semiconductor device, manufacturing method thereof, and organic wiring board therefor

Country Status (1)

Country Link
JP (1) JP2008244026A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012060105A (en) * 2010-08-09 2012-03-22 Renesas Electronics Corp Semiconductor device, method for manufacturing semiconductor device, metal mold, and sealing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012060105A (en) * 2010-08-09 2012-03-22 Renesas Electronics Corp Semiconductor device, method for manufacturing semiconductor device, metal mold, and sealing device

Similar Documents

Publication Publication Date Title
JP3971434B2 (en) Semiconductor integrated circuit device
US7514293B2 (en) Method of manufacturing a semiconductor device
JP3686287B2 (en) Manufacturing method of semiconductor device
US20140151865A1 (en) Semiconductor device packages providing enhanced exposed toe fillets
JP2003243600A (en) Semiconductor device and method of manufacturing the same
US20170005030A1 (en) Flat No-Leads Package With Improved Contact Pins
JP2008130701A (en) Wiring substrate, semiconductor device using the substrate, and method of manufacturing the semiconductor device
TW201626473A (en) Flat no-leads package with improved contact leads
US6642082B2 (en) Method for manufacturing a resin-sealed semiconductor device
TWI405307B (en) Chip package and process thereof
JP3660854B2 (en) Manufacturing method of semiconductor device
JP2008244026A (en) Semiconductor device, manufacturing method thereof, and organic wiring board therefor
JP4737995B2 (en) Semiconductor device
JP4994148B2 (en) Manufacturing method of semiconductor device
JP2005277434A (en) Semiconductor device
JP5512784B2 (en) Manufacturing method of semiconductor device
JP5266371B2 (en) Semiconductor device and manufacturing method thereof
JP2008227317A (en) Semiconductor device, wiring board therefor, sealing die and manufacturing method
JP5184558B2 (en) Semiconductor device
JP4840305B2 (en) Manufacturing method of semiconductor device
JP5311505B2 (en) Semiconductor device
JP2014112714A (en) Semiconductor device
KR940005712B1 (en) Jack-type ic package
JP4409528B2 (en) Semiconductor device
KR100902096B1 (en) Carrier for holding unit type board