JP2008258261A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2008258261A JP2008258261A JP2007096411A JP2007096411A JP2008258261A JP 2008258261 A JP2008258261 A JP 2008258261A JP 2007096411 A JP2007096411 A JP 2007096411A JP 2007096411 A JP2007096411 A JP 2007096411A JP 2008258261 A JP2008258261 A JP 2008258261A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 150000001875 compounds Chemical class 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 11
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- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 5
- 238000003475 lamination Methods 0.000 abstract 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 28
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 25
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- 239000010408 film Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
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- 238000000034 method Methods 0.000 description 8
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- 230000001681 protective effect Effects 0.000 description 6
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- 238000010295 mobile communication Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
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- 230000037431 insertion Effects 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
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- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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Abstract
【解決手段】 基板1上に積層された複数の化合物半導体層を含む積層体の第1領域に形成されたFET1、前記積層体の第2領域に形成されたFET2を有する半導体装置50であって、第1領域と第2領域とで同層に形成された第1導電型のチャネル層5と、チャネル層5上に形成されると共に、第1領域と第2領域とで同層に形成された中間層11と、第1領域に形成されると共に、中間層11と同層に形成された第2導電型の化合物半導体層18と、化合物半導体層18にオーミック接触されたFET1のゲート電極19と、第2領域の中間層11にショットキー接触されたFET2のゲート電極20と、を備える。
【選択図】 図1
Description
以下、第1の実施形態に係る半導体装置50について図1を用いて説明する。図1に、半導体装置50の概略的な断面構成を説明するための模式図を示す。なお、まず、半導体装置50の構成について説明する。
ΔVT=κ1 ・tGaAs+κ2・tInGaP+((φE−φD)/q) ・・・式1
ここで、κ1は中間層(GaAs層)11内の電界強度、κ2はストッパ層(InGaP層)10の電界強度、tGaAsは中間層(GaAs層)11の膜厚、tInGaPはストッパ層(InGaP層)10の膜厚、qは電荷素量である。
以下、第2の実施形態に係る半導体装置51について図2を用いて説明する。図2に、半導体装置51の概略的な断面構成を説明するための模式図を示す。
以下、第3の実施形態に係る半導体装置52について図3を用いて説明する。図3に、半導体装置52の概略的な断面構成を説明するための模式図を示す。
以下、第4の実施形態に係る半導体装置53について図4を用いて説明する。図4に、半導体装置53の概略的な断面構成を説明するための模式図を示す。
以下、第5の実施形態に係る半導体装置54について図5を用いて説明する。図5に、半導体装置54の概略的な断面構成を説明するための模式図を示す。
以下、第6の実施形態に係る半導体装置55について図6を用いて説明する。図6に、半導体装置55の概略的な断面構成を説明するための模式図を示す。
以下、第7の実施形態に係る半導体装置56について図7を用いて説明する。図7に、半導体装置56の概略的な断面構成を説明するための模式図を示す。
以下、第8の実施形態に係る半導体装置57について図8を用いて説明する。図8に、半導体装置57の概略的な断面構成を説明するための模式図を示す。
以下、第9の実施形態に係る半導体装置58について図9を用いて説明する。図9に、半導体装置58の概略的な断面構成を説明するための模式図を示す。
以下、第10の実施形態に係る半導体装置59について図10を用いて説明する。図10に、半導体装置59の概略的な断面構成を説明するための模式図を示す。
2 バッファ層
3 電子供給層
4 スペーサ層
5 チャネル層
6 スペーサ層
7 電子供給層
8 中間層
9 中間層
10 ストッパ層
11 中間層
12 ストッパ層
13 キャップ層
14 ソース電極
15 ドレイン電極
16 ソース電極
17 ドレイン電極
18 化合物半導体層
19 ゲート電極
20 ゲート電極
21 表面保護膜
22 アイソレーション領域
30 空間
40〜44 リセス
Claims (9)
- 基板上に積層された複数の化合物半導体層を含む積層体の第1領域に形成された第1電界効果トランジスタ、前記積層体の第2領域に形成された第2電界効果トランジスタを有する半導体装置であって、
前記第1領域と前記第2領域とで同層に形成された第1導電型のチャネル層と、
前記チャネル層上に形成されると共に、前記第1領域と前記第2領域とで同層に形成された上部化合物半導体層と、
前記第1領域に形成されると共に、前記上部化合物半導体層と同層に形成された第2導電型の化合物半導体領域と、
第2導電型の前記化合物半導体領域にオーミック接触された前記第1電界効果トランジスタのゲート電極と、
前記第2領域の前記上部化合物半導体層にショットキー接触された前記第2電界効果トランジスタのゲート電極と、
を備える半導体装置。 - 前記第1領域と前記第2領域とで同層に形成された電子供給層と、
前記チャネル層と前記電子供給層との間に形成されると共に、前記第1領域と前記第2領域とで同層に形成されたスペーサ層と、
をさらに備える請求項1記載の半導体装置。 - 第2導電型の前記化合物半導体領域は、前記上部化合物半導体層に設けられたリセス内に堆積された化合物半導体層に不純物が導入されて形成されることを特徴とする請求項1記載の半導体装置。
- 第2導電型の前記化合物半導体領域は、前記上部化合物半導体層に不純物が直接導入されて形成されることを特徴とする請求項1記載の半導体装置。
- 前記第2電界効果トランジスタの前記ゲート電極は、前記上部化合物半導体層に設けられたリセスに充填された部分を有することを特徴とする請求項1記載の半導体装置。
- 前記第2電界効果トランジスタの前記ゲート電極は、前記上部化合物半導体層に設けられた前記リセスの内壁に当接しないことを特徴とする請求項5記載の半導体装置。
- 前記第1領域と前記第2領域との境界部分に設けられたアイソレーション層によって、前記第1電界効果トランジスタと前記第2電界効果トランジスタとは互いに分離されることを特徴とする請求項1記載の半導体装置。
- 前記第1電界効果トランジスタは、エンハンスメント型の電界効果トランジスタであり、
前記第2電界効果トランジスタは、ディプレッション型の電界効果トランジスタであることを特徴とする請求項1記載の半導体装置。 - 前記第1電界効果トランジスタは、電流増幅回路用の電界効果トランジスタであって、
前記第2電界効果トランジスタは、スイッチ回路用の電界効果トランジスタであることを特徴とする請求項1記載の半導体装置。
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---|---|---|---|
JP2007096411A JP5431652B2 (ja) | 2007-04-02 | 2007-04-02 | 半導体装置 |
US12/061,065 US8067788B2 (en) | 2007-04-02 | 2008-04-02 | Semiconductor device |
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JP2007096411A JP5431652B2 (ja) | 2007-04-02 | 2007-04-02 | 半導体装置 |
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JP2008258261A true JP2008258261A (ja) | 2008-10-23 |
JP5431652B2 JP5431652B2 (ja) | 2014-03-05 |
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JP2007096411A Expired - Fee Related JP5431652B2 (ja) | 2007-04-02 | 2007-04-02 | 半導体装置 |
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JP (1) | JP5431652B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8253218B2 (en) | 2010-02-09 | 2012-08-28 | Renesas Electronics Corporation | Protective element and semiconductor device |
JP2015104074A (ja) * | 2013-11-27 | 2015-06-04 | セイコーエプソン株式会社 | 発振回路、発振器、電子機器および移動体 |
JP2016529712A (ja) * | 2013-07-30 | 2016-09-23 | エフィシエント パワー コンヴァーション コーポレーション | 閾値電圧がマッチングした集積回路およびこれを作製するための方法 |
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US20100072484A1 (en) * | 2008-09-23 | 2010-03-25 | Triquint Semiconductor, Inc. | Heteroepitaxial gallium nitride-based device formed on an off-cut substrate |
US8344420B1 (en) * | 2009-07-24 | 2013-01-01 | Triquint Semiconductor, Inc. | Enhancement-mode gallium nitride high electron mobility transistor |
KR101736914B1 (ko) * | 2010-12-06 | 2017-05-19 | 한국전자통신연구원 | 고주파 소자 구조물의 제조방법 |
ITTO20120675A1 (it) * | 2011-08-01 | 2013-02-02 | Selex Sistemi Integrati Spa | Dispositivo phemt ad arricchimento/svuotamento e relativo metodo di fabbricazione |
US10811407B2 (en) * | 2019-02-04 | 2020-10-20 | Win Semiconductor Corp. | Monolithic integration of enhancement mode and depletion mode field effect transistors |
US11177379B2 (en) * | 2019-06-19 | 2021-11-16 | Win Semiconductors Corp. | Gate-sinking pHEMTs having extremely uniform pinch-off/threshold voltage |
CN110634867B (zh) * | 2019-09-10 | 2023-08-18 | 英诺赛科(珠海)科技有限公司 | 半导体装置及其制造方法 |
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2007
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Patent Citations (3)
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JP2004179318A (ja) * | 2002-11-26 | 2004-06-24 | Nec Compound Semiconductor Devices Ltd | 接合型電界効果トランジスタ及びその製造方法 |
JP2004221172A (ja) * | 2003-01-10 | 2004-08-05 | Renesas Technology Corp | 半導体装置及びその製造方法 |
Cited By (3)
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US8253218B2 (en) | 2010-02-09 | 2012-08-28 | Renesas Electronics Corporation | Protective element and semiconductor device |
JP2016529712A (ja) * | 2013-07-30 | 2016-09-23 | エフィシエント パワー コンヴァーション コーポレーション | 閾値電圧がマッチングした集積回路およびこれを作製するための方法 |
JP2015104074A (ja) * | 2013-11-27 | 2015-06-04 | セイコーエプソン株式会社 | 発振回路、発振器、電子機器および移動体 |
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