JP2008251622A - Manufacturing method of wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board capable of reducing mounting failure of electronic components due to a gas generated while being heated. <P>SOLUTION: The manufacturing method of a wiring board comprises a coating process for coating a connection pad of a substrate having the connection pad with solder paste; a loading process for loading electronic components on the coated solder paste; an arrangement process for arranging a lid body on the substrate so that the electronic components are covered; and a heating process for heating the substrate where the lid body is arranged. The lid body has a communication section for allowing space, formed between the lid body and the electronic component to communicate with the external space of the lid body. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board on which electronic components are mounted.

A method of manufacturing a wiring board for mounting an electronic component on a wiring board by printing a solder paste on a connection pad of the wiring board, placing an electronic component such as a chip capacitor on the solder paste, and reflowing is disclosed. (For example, refer to Patent Document 1 and Patent Document 2).
JP 2001-203445 A JP 2004-335507 A

However, in the above method, as shown in FIG. 10, a so-called chip standing phenomenon (also referred to as a Manhattan phenomenon) in which one electrode 1 a of the chip-shaped electronic component 1 is separated from the connection pad 3 of the wiring substrate 2 in the height direction. ). The solder paste is melted by heating in a reflow furnace. When the solder paste on one connection pad 3 melts earlier than the solder paste on the other connection pad 3, the surface tension of the molten solder paste causes a rotational force in the height direction with the end of the electronic component 1 as a fulcrum. Produce. Due to this rotational force, the electronic component 1 is attracted to the connection pad 3 side of the solder paste that has been melted earlier, and the chip stands. When the chip standing phenomenon occurs, the soldering is finished in this state. Therefore, the entire wiring board 2 is caused by an open defect in which the electrode 1a of the electronic component 1 on the slow melting side is separated from the connection pad 3 to be connected. It was handled as a defective product and had a problem that the manufacturing yield was reduced.
Recently, in order to improve the mounting density of wiring boards, chip-shaped electronic components have been reduced in size and weight, and as electronic components become smaller and lighter, chip standing phenomenon is more likely to occur. Therefore, there is a need for a technique that effectively prevents the chip standing phenomenon.
Therefore, in order to solve such problems, the present inventor limits the rising of the electronic component during reflow and prevents the chip from standing by arranging a lid on the substrate so as to cover the electronic component. I found out that I can do it.
However, in this method, since the electronic component is covered by the lid, the space for mounting the electronic component (in other words, the space formed between the lid and the electronic component) is sealed. For this reason, the gas generated by the vaporization of the flux in the solder paste during reflow accumulates in the space where the electronic components are mounted, and this gas expands due to heat, increasing the pressure, causing the electronic components to float or slip off the connection pads. As a result, it has been found that there is a possibility that mounting defects of electronic components may occur. Moreover, the evaporated flux may adhere to the lid or the electronic component.

  In view of the above, an object of the present invention is to provide a method for manufacturing a wiring board that can reduce mounting defects of electronic components due to gas generated during heating.

  A method for manufacturing a wiring board according to an aspect of the present invention includes a coating step of applying a solder paste on the connection pad of a substrate including a connection pad, and a mounting step of mounting an electronic component on the applied solder paste. And an arranging step of arranging a lid on the substrate so as to cover the electronic component, and a heating step of heating the substrate on which the lid is arranged, wherein the lid is the lid And a communication part that communicates the space formed between the electronic component and the external space of the lid.

  According to the method for manufacturing a wiring board according to an aspect of the present invention, the space in which the electronic component is mounted by using the communication portion formed in the lid body to generate the gas generated by the evaporation of the flux in the solder paste during heating. Therefore, it is possible to reduce mounting defects of electronic components due to gas generated during heating.

  Hereinafter, a method for manufacturing a wiring board 11 according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view schematically showing the configuration of the wiring board 11 of the present embodiment.

The wiring board 11 to which the present invention is applied has a substantially rectangular shape in plan view of, for example, about 35 mm × about 35 mm.
As shown in FIG. 1, the wiring board 11 includes a board 12 as a core material. Examples of the substrate 12 include a resin substrate, a ceramic substrate, and a metal substrate, and are appropriately selected in consideration of cost, ease of hole processing, conductivity, and the like. Specific examples of the resin substrate include a plate material made of EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), and PPE resin (polyphenylene ether resin). Specific examples of the ceramic substrate include a plate made of low-temperature firing material such as alumina, beryllia, aluminum nitride, boron nitride, silicon carbide, glass ceramic, crystallized glass, and the like. Specific examples of the metal substrate include a copper plate, a copper alloy plate, a single metal other than copper, and a plate material made of an alloy (for example, an Fe—Ni alloy). In the present embodiment, as the substrate 12, a glass cloth cloth impregnated with an epoxy resin is used.

  In FIG. 1, a buildup layer formed by alternately laminating resin insulating layers 31 and 51 and conductor layers 21 and 41 is formed on the first main surface 13 (upper surface) side of the substrate 12. On the second main surface 14 (lower surface) side of the substrate 12, a buildup layer formed by alternately laminating the resin insulating layers 32 and 52 and the conductor layers 22 and 42 is formed.

The resin insulating layers 31, 32, 51, and 52 are preferably formed using a thermosetting resin. Specific examples of suitable thermosetting resins include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), phenol resin, xylene resin, polyester resin, silicon resin, etc. There is. Among these, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin) and the like are particularly preferable.
The conductor layers 21, 22, 41, 42 are made of a conductive metal such as copper, and are formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. The conductor layers 21, 22, 41, 42 are formed by etching after forming a thin film by a technique such as sputtering or CVD, or the conductor layers 21, 22, 41, 42 are printed by printing a conductive paste or the like. It can also be formed.

  In the present embodiment, the resin insulating layers 31, 32, 51, 52 and the conductor layers 21, 22, 41, 42 are configured as follows. The first conductor layers 21 and 22 are made of copper, and are formed on the surfaces of the first main surface 13 (upper surface) and the second main surface 14 (lower surface) of the substrate 12, respectively. The first resin insulation layers 31 and 32 are made of a photosensitive epoxy resin and are formed so as to cover the first conductor layers 21 and 22. The second conductor layers 41 and 42 are made of copper, and are formed on the surfaces of the first resin insulation layers 31 and 32, respectively. The second resin insulation layers 51 and 52 are made of a photosensitive epoxy resin and are formed so as to cover the second conductor layers 41 and 42. The second resin insulation layers 51 and 52 serve as so-called solder resists for protecting portions of the conductor layers 41 and 42 other than the die pad 43 and the connection pads 44 and 45.

  In addition, through-hole conductors 15 for connecting and conducting the buildup layer on the first main surface 13 side and the buildup layer on the second main surface 14 side are formed at a plurality of locations on the substrate 12. The cavity in the through-hole conductor 15 is filled with a resin filler 23 made of an epoxy resin containing an inorganic filler.

  Blind via-hole conductors 33 and 34 are provided on the first resin insulation layers 31 and 32 by electroless copper plating, respectively. The blind via-hole conductor 33 on the first main surface 13 side is connected between the conductor layers 21 and 41, and the blind via-hole conductor 34 on the second main surface 14 side is connected and connected between the conductor layers 22 and 42.

  As shown in FIG. 1, a rectangular semiconductor integrated circuit chip 16, which is a kind of electronic component, is mounted on a die area set at a substantially central portion on the first main surface 13 (upper surface) side. . A gap formed on the lower surface side of the semiconductor integrated circuit chip 16 is filled with an underfill material 62. A large number of die pads 43 for electrical connection with the semiconductor integrated circuit chip 16 are formed in the die area. The die pad 43 is disposed in an opening provided in the second insulating resin layer 51 which is a solder resist.

On the other hand, on the second main surface 14 (lower surface) side, electronic components 17a and 17b, which are chip capacitors having different heights, are mounted on the connection pads 45 at the substantially central portion thereof. A plurality of electronic components 17a and electronic components 17b are arranged along the direction perpendicular to the cross section (paper surface) of FIG. The connection pad 45 is disposed in the opening of the second insulating resin layer 52. A large number of connection pads 44 are formed as connection terminals to be connected to the terminals on the mother board side in a region outside the mounting area of the electronic components 17a and 17b, and a mother board (not shown) can be connected. The connection pads 44 and the terminals on the motherboard side can be easily connected by providing, for example, a rectangular parallelepiped-shaped electronic component relief recess for housing the electronic components 17a and 17b in the motherboard.
A nickel-gold plating layer 46 is formed on the surfaces of the die pad 43 and the connection pads 44 and 45.

  In this specification, an electronic component refers to a chip-shaped electronic component, which may be an active component or a passive component. In addition to the chip capacitor used in the present embodiment, for example, a chip inductor, a chip resistor It may be. In the present embodiment, the electronic components 17a and 17b are arranged on the second main surface 14 side, but may be arranged only on the first main surface 13 side, or the first main surface 13 and It may be arranged on both of the second main surfaces 14.

  On the die pad 43 on which nickel-gold plating has been applied, a first solder bump 47 is formed using eutectic solder (37Pb: 63Sn, melting point 183 ° C.). The first solder bump 47 protrudes from the surface of the second insulating resin layer 51. On the connection pad 45 on which the nickel-gold plating is applied, a Pb—Sn—Bi—Sb (Pb is 70 wt%) alloy solder having a melting point higher than that of the solder for forming the first solder bump 47 is used. A second solder bump 48 is formed. The upper surface of the second solder bump 48 protrudes from the surface of the second insulating resin layer 52.

Next, a procedure for manufacturing the wiring board 11 will be described.
2A to 2D are cross-sectional views illustrating the manufacturing process of the wiring board 11. 2A to 2D correspond to the wiring substrate 11 of FIG. 1 arranged upside down.

  First, a double-sided copper clad laminate with copper foil attached to both sides of the substrate 12 is used as a starting material, and laser processing is performed using a YAG laser or a carbon dioxide gas laser to form a through-hole penetrating the double-sided copper clad laminate. To do. Next, after the through-hole conductor 15 is formed by electroless copper plating on the inner surface of the through hole, the first conductor layers 21 and 22 are patterned by etching the copper foil. Here, after the through-hole conductor 15 is filled with the resin filler 23, first resin insulation layers 31 and 32 are formed on the first main surface 13 and the second main surface 14 of the substrate 12. Next, the resin insulating layers 31 and 32 are drilled by laser processing to form blind holes for forming the blind via-hole conductors 33 and 34. Furthermore, by performing electroless copper plating without forming a mask, copper plating is deposited inside the blind hole to form blind via-hole conductors 33 and 34. At this time, electroless copper plating is deposited on the entire outer surface of the resin insulation layers 31 and 32. Thereafter, exposure and development are performed to form a predetermined pattern of plating resist. In this state, after electrolytic copper plating is performed using the electroless copper plating layer as a common electrode, first, the resist is dissolved and removed, and further unnecessary electroless copper plating layer is removed by etching. Thereby, the conductor layer 41 including the die pad 43 is formed on the surface of the upper resin insulating layer 31, and the conductor layer 42 including the connection pads 44 and 45 is formed on the surface of the lower resin insulating layer 32.

  Then, by applying and curing a photosensitive epoxy resin on the surfaces of the first main surface 13 and the second main surface 14 of the substrate 12, the second resin insulating layers 51 and 52 (solder resist) are formed. Form. Next, exposure and development are performed in a state where a predetermined mask is disposed, and openings are formed in the second resin insulating layers 51 and 52. Next, a surface roughening treatment is performed using a roughening solution containing potassium permanganate, and the surfaces of the second resin insulating layers 51 and 52 are changed to rough surfaces.

  Next, the surface of the die pad 43 and the connection pads 44 and 45 are subjected to electroless nickel plating and electroless gold plating in order, thereby forming a nickel-gold plating layer 46.

  Subsequently, solder bumps 47 are formed on the nickel-gold plating layer 46 on the die pad 43 on the first main surface 13 side. Specifically, a mask having a predetermined pattern is placed on the second resin insulating layer 51 and then a solder paste is printed on the die pad 43. In this embodiment, a solder paste containing alloy solder (37Pb: 63Sn, melting point 183 ° C.) is used.

  Subsequently, solder bumps 48 are formed on the nickel-gold plating layer 46 on the connection pads 45 on the second main surface 14 side (see FIG. 2A). Specifically, a mask having a predetermined pattern is placed on the second resin insulation layer 52, and then a solder paste is printed on the connection pads 45. In the present embodiment, a solder containing a quaternary alloy solder having a composition (Pb—Sn—Bi—Sb) having a higher melting point than the alloy solder in the solder bump 47 and having no eutectic composition (Pb is 70 wt%). Selected paste. Then, the electronic components 17a and 17b, which are chip capacitors having different heights, are arranged at predetermined positions on the respective solder bumps 48, and the plurality of electronic components 17a and the plurality of electronic components 17b are mounted on the wiring board 11 ( (See FIG. 2B).

  A reflow soldering jig 70 that accommodates the wiring board 11 when soldering in a reflow furnace is prepared. FIG. 3 is an exploded perspective view showing a state where the reflow soldering jig 70 is disassembled. The reflow soldering jig 70 includes a lower jig 80 and a lid 90. FIG. 4 is a top view of the lower jig 80. FIG. 5 is a bottom view of the lid 90.

The lower jig 80 is a jig for receiving and mounting the wiring board 11. The outer shape of the lower jig 80 is a substantially rectangular parallelepiped shape. On the upper surface of the lower jig 80, a plurality of concave parts 81 having a substantially rectangular parallelepiped shape for placing the wiring board 11 are arranged in the Y direction (in FIG. 4). The number of the concave portions 81 is three). One wiring board 11 can be accommodated in each of the recesses 81, and the same number of wiring boards 11 as the recesses 81 can be placed on one lower jig 80. The inner circumference of the recess 81 is substantially the same as the dimension of the wiring board 11.
A substantially rectangular parallelepiped escape recess 82 is further provided in the approximate center of each recess 81 to avoid the solder bump 47 from coming into contact with the lower jig 80. The relief recess 82 is formed in a size larger than the formation area of the solder bump 47 and the height at which the solder bump 47 protrudes from the surface of the insulating resin layer 51 so that the solder bump 47 can be accommodated without contacting.

  The lower jig 80 is formed with a pair of U-shaped projections 83 facing each other at a position near the corner in the negative X direction on the opening end side of the recess 81. The protrusion 83 is used to combine the lid 90 and the lower jig 80 without making a mistake in orientation by being housed in a notch (depression) 95 (described later) formed in the lid 90. The protruding portion 83 is formed in a shape corresponding to the notched portion 95 so that the protruding portion 83 can be accommodated in the notched portion (recessed portion) 95.

  The lower jig 80 is made of carbon because it is difficult for solder to adhere and has good thermal conductivity and good workability. The lower jig 80 may be made of aluminum.

  The lid 90 restricts the rise of the electronic components 17a and 17b during reflow, so that one electrode of the electronic component is separated from the connection pad 45 of the wiring board in the height direction during reflow. This is to prevent (also called the Manhattan phenomenon). The outer shape of the lid 90 is a substrate (substantially rectangular parallelepiped) shape, and the outer circumference of the lid 90 is substantially the same as the outer dimension of the wiring board 11, and one side is approximately longer than the inner circumference of the recess 81 of the lower jig 80. 0.5 mm smaller.

On the lower surface of the lid 90, a recess 91 for accommodating the electronic components 17a and 17b is formed in a substantially central portion. In the present embodiment, one recess 91 is provided corresponding to the plurality of electronic components 17a and 17b. A step 92 is formed in the recess 91 at a position along the X direction and substantially halving the bottom surface of the recess 91. The recess 91 has a bottom surface 93a disposed to face the top surfaces of the plurality of electronic components 17a and a bottom surface 93b disposed to face the top surfaces of the plurality of electronic components 17b. The depth of the bottom surface 93a of the recess 91 is about 1.45 mm, and the depth of the bottom surface 93b is about 0.55 mm. The depths of the bottom surfaces 93a and 93b of the recess 91 are each formed to be larger than the height of the plurality of electronic components 17a and 17b within a range of 0.05 mm or more and 0.20 mm or less.
Moreover, the recessed part 91 is formed in the dimension larger than the mounting area of electronic components 17a and 17b so that the side surface of electronic components 17a and 17b can be accommodated without contacting.

Further, on the lower surface of the lid 90, a communication portion having a width that is approximately half of one side arranged in the Y direction of the lid 90 and a height of about 1/120 of one side arranged in the Y direction of the lid 90. 94 is formed.
In the present specification, the communication portion communicates a space formed between the lid and the electronic component (in this embodiment, a space in the recess 91) and an external space of the lid. The communication part can function as a degassing part or a convection heat transfer path.

The communicating portion 94 is a gas passage for degassing the gas in which the flux in the solder paste is evaporated during reflow from the recess 91 of the lid 90 to the outside of the reflow soldering jig 70 (lid 90). Functions as a (gas vent). The communication portions 94 are respectively arranged from the four sides of the opening end of the recess 91 and the vicinity of both ends of the sides to the lower and substantially central portions of the four outer surfaces of the lid 90. It is formed so as to penetrate in four directions (X positive / negative direction, Y positive / negative direction). As described above, the recess 91 communicates with the outside of the reflow soldering jig 70 through the communication portion 94 and the gap between the lid 90 and the lower jig 80, so that the gas in the recess 91 is reflowed. Gas can be vented to the outside of the soldering jig 70.
Moreover, the communication part 94 also functions as a convection heat transfer path.

The number of communicating portions of the lid 90 is not particularly limited as long as it is 1 or more, but it is preferable to provide a plurality of communicating portions in order to improve convective heat transfer efficiency during solder reflow and gas escape properties. A plurality of communicating portions may be connected around the open end of the recess 91 as in the present embodiment.
The shape of the communication part 94 is not particularly limited as long as the recess 91 and the outer space of the lid 94 communicate with each other. The communication portion 94 is not limited to the groove shape like the communication portion 94 shown in the present embodiment, and may be a hole shape.

In addition, on the lower surface of the lid 90, convex portions 100 (100a to 100d) having a rectangular shape in a plan view are arranged at each of the four corner portions.
The lid 90 is formed with a pair of U-shaped notch portions (recessed portions) 95 facing the outer peripheral portion near the X negative direction. The notch portion 95 is for combining the lid 90 and the lower jig 80 without wrong orientation by accommodating the projection 83 formed on the lower jig 80. The notch 95 is formed in a shape corresponding to the protrusion 83 so that the protrusion 83 can be accommodated.

  The lid 90 is made of carbon because it is difficult for solder to adhere and has good thermal conductivity and good workability. The lid 90 may be made of aluminum.

  Next, the wiring board 11 is accommodated in the reflow soldering jig 70.

  First, the plurality of wiring boards 11 are placed in the plurality of recesses 81 of the lower jig 80 so that the solder bumps 47 escape and are accommodated in the recesses 82 with the first main surface 13 side of the wiring board 11 facing down. Each one is accommodated and placed. At this time, the chip non-mounting area of the wiring substrate 11 directly contacts the bottom surface of the recess 81, but the solder bump 47 is accommodated so as not to contact the escape recess 82.

  Subsequently, a plurality of lids 90 are arranged on the respective wiring boards so that the protrusions 83 of the lid 90 fit within the notches 95, and the lid 90 and the lower jig 80 are combined (see FIG. 2C, FIG. 2C shows a cross section of the reflow soldering jig 70 containing the wiring board 11 taken along the line AA in FIG. At this time, the lid 90 is placed on the wiring board 12 in a state where the electronic components 17 a and 17 b are accommodated in the recess 91. The chip non-mounting surface on the second main surface 14 side (the upper side of the wiring substrate 11 in FIG. 5) of the wiring substrate 11 is four convex portions 100 (100a to 100d) formed at the corner portions on the lower surface of the lid 90, respectively. Abut directly. On the other hand, none of the electronic components 17a and 17b are in contact with the recess 91, and the upper surfaces of the electronic components 17a and 17b and the bottom surfaces 93a and 93b of the recess 91 are arranged to face each other at a predetermined distance or less. .

Here, the separation distance (predetermined interval) between the upper surface and the bottom surface 93a of the electronic component 17a and the separation distance (predetermined interval) between the upper surface and the bottom surface 93b of the electronic component 17b are both 0.05 mm or more and 0.20 mm or less. It is preferable that
When the separation distance is less than 0.05 mm, the upper surface and the bottom surface 93a, 93b of the electronic components 17a, 17b come into contact with each other during reflow, so that the solder paste on the pressed connection pad 45 spreads around and adjoins. Solder paste may come into contact with each other or may reach the adjacent connection pad 45 to cause poor soldering. In addition, the electronic components 17a and 17b may be damaged by the contact between the top surfaces and the bottom surfaces 93a and 93b of the electronic components 17a and 17b during reflow.
When the separation distance exceeds 0.20 mm, when the chip standing phenomenon occurs, the electronic components 17a and 17b are mounted obliquely even if they are not upright, and one of the electrodes of the electronic components 17a and 17b is There is a possibility that an open defect may occur due to separation from the connection pad 45 to be connected in the height direction.
In the present embodiment, the distance between the upper surface and the bottom surface 93a of the electronic component 17a is 0.20 mm, and the distance between the upper surface and the bottom surface 93b of the electronic component 17b is 0.05 mm.

  The wiring board 11 accommodated in the reflow soldering jig 70 is reflowed by heating in a reflow furnace with the lid 90 facing up (see FIG. 2D, FIG. 2D is the same as FIG. 2C). The cross section of the reflow soldering jig 70 containing the wiring board 11 taken along the line AA in FIG. 3 is displayed.) After reflowing, the reflow soldering jig 70 was cooled to room temperature. As a result, the electrodes of the electronic components 17a and 17b and the solder bumps 48 are joined, and the wiring board 11 and the electronic components 17a and 17b are electrically connected.

  Next, the semiconductor integrated circuit chip 16 is mounted on the die area of the wiring board 11. At this time, the solder bumps 47 on the wiring board 11 side and the bumps 61 on the semiconductor integrated circuit chip 16 side are aligned. In this state, after reflowing by heating to a predetermined temperature using a reflow furnace, the wiring board 11 is cooled. As a result, the solder bumps 47 and the chip-side bumps 61 are joined to each other, and the wiring board 11 side and the semiconductor integrated circuit chip 16 side are electrically connected.

  Then, the gap between the wiring substrate 11 and the semiconductor integrated circuit chip 16 is filled with an underfill material 62 and subjected to a curing process (165 ° C. × 30 seconds), and the gap is sealed with resin. As a result, a desired semiconductor package (so-called organic package) is completed.

  According to the method for manufacturing the wiring substrate 11 of the present embodiment, the following advantages (effects) can be obtained.

In the manufacturing method according to the present embodiment, when the electronic components 17a and 17b are soldered by reflow, the communication portion 94 is provided on the lid 90 that constitutes the reflow soldering jig 70 that houses the wiring board 11. ing. Therefore, the gas in which the flux in the solder paste is vaporized during reflow is degassed from the recess 91 of the lid 90 to the outside of the reflow soldering jig 70 by the communication portion 94.
As a result, the communication portion 94 can prevent the gas generated by vaporization of the flux from being accumulated in the recess 91 and the gas from expanding due to heat to increase the pressure. For this reason, it is possible to prevent mounting defects in which the electrodes of the electronic components 17a and 17b are displaced from the connection pad 45 or floated away due to an increase in gas pressure.

  Further, the degassing by the communication portion 94 can prevent the lid 90 from being lifted due to an increase in the gas pressure in the recess 91. As a result, the electronic components 17a and 17b may rise due to the floating of the lid 90, and the electronic components 17a and 17b are displaced from the connection pad 45 when the lid 90 is in contact with the electronic components 17a and 17b. Mounting failure can be prevented.

  Further, since the gas generated by vaporization of the flux can be vented out of the recess 91 by the communication portion 94, it is possible to suppress the gas from remaining as a void in the solder joint portion of the electronic components 17a and 17b. . As a result, it is possible to suppress a decrease in mechanical strength due to the generation of voids, a deterioration in the passage of electricity, a decrease in bonding strength due to the generation of cracks due to voids, and poor bonding.

Further, by degassing the gas in the concave portion 91 by the communication portion 94, it is possible to suppress adhesion of dirt due to the flux to the bottom surfaces 93a and 93b of the concave portion 91 of the lid 90. Thereby, the burden which wash | cleans the dirt which adhered to the bottom face 93a, 93b of the recessed part 91 can be reduced. In addition, it may not always be easy to remove contaminants that have been left for a considerable period of time after reflow soldering and the initial deposits have deteriorated. By suppressing the adhesion, the durability of the reflow soldering jig 70 can be improved.
Further, since it is difficult to clean the dirt, it is possible to suppress the distance between the bottom surfaces 93a and 93b of the recess 91 and the top surfaces of the electronic components 17a and 17b from being narrower than the original design by degassing by the communication portion 94. As a result, it is possible to reduce the occurrence of poor soldering, which will be described later, due to the contact between the top and bottom surfaces 93a, 93b of the electronic components 17a, 17b during reflow and the spread of the solder paste. Further, it is possible to reduce the damage of the electronic components 17a and 17b due to the contact between the top surfaces and the bottom surfaces 93a and 93b of the electronic components 17a and 17b during reflow.

  Moreover, the communication part 94 functions also as a convection heat transfer path, and can suppress that heat is locally stored in the reflow soldering jig 70. Thereby, the melting management of the solder material such as setting of reflow conditions that can prevent soldering failure is facilitated, and the soldered state of the electronic components 17a and 17b can be improved.

Further, in the manufacturing method of the present embodiment, since the communication portions 94 that respectively communicate with the four outer surfaces of the lid body 90 are formed from the recess 91 and a plurality of communication portions are provided, the convection transfer during the above-described solder reflow is performed. Thermal efficiency and outgassing properties can be improved.
In the manufacturing method of the present embodiment, the communication portion 94 is formed on the lower surface of the lid 90. Therefore, when the wiring board 11 is accommodated in the reflow soldering jig 70 and the electronic components 17a and 17b are reflow soldered, the communication portion 94 is disposed on the wiring board 11 on the second main surface 14 side. . Since the communication portion 94 is disposed on the wiring substrate 11 on the second main surface 14 side, and the communication portion 94 also functions as a convection heat transfer path, the first portion of the wiring substrate 11 to which the electronic components 17a and 17b are soldered. 2 It is possible to suppress heat from being locally accumulated on the main surface 14 side. As described above, since the communication portion 94 is formed on the lower surface of the lid 90, the melting management of the solder material such as setting of reflow conditions capable of preventing the soldering failure of the electronic components 17a and 17b is further facilitated. The soldering state of the electronic components 17a and 17b can be further improved.

  Further, in the manufacturing method of the present embodiment, when the plurality of electronic components 17a and 17b having different heights are reflow-soldered to the wiring board 11, the lid 90 including the recesses 91 having the plurality of bottom surfaces 93a and 93b is provided. The electronic parts 17a and 17b are arranged on the wiring board 11 so as to cover them. At this time, the plurality of bottom surfaces 93a and 93b have a depth corresponding to the height of each of the plurality of electronic components 17a and 17b, the distance between the bottom surface 93a and the top surface of the electronic component 17a, and the bottom surface 93b and the electronic components. The distance from the upper surface of the component 17b is less than or equal to a predetermined distance. For this reason, the bottom surfaces 93a and 93b limit the rising of the electronic components 17a and 17b during reflow. As a result, even when a plurality of electronic components having different heights, such as a plurality of electronic components 17a and a plurality of electronic components 17b, are mounted, the so-called chip standing phenomenon at the time of reflow is reduced. The electronic components 17a and 17b can be effectively prevented. By preventing the chip standing phenomenon, the manufacturing yield and reliability of the wiring substrate 11 can be improved.

  In this embodiment, when the wiring board 11 is accommodated in the reflow soldering jig 70, the bottom surfaces 93a and 93b of the recess 91 and the top surfaces of the electronic components 17a and 17b facing the bottom surfaces 93a and 93b, respectively. A predetermined interval is provided between them. Therefore, when the top surfaces and bottom surfaces 93a and 93b of the electronic components 17a and 17b come into contact with each other during reflow, the pressed solder paste spreads around and the adjacent solder pastes come into contact with each other or up to the adjacent connection pad 45. It is possible to prevent soldering defects from occurring. As a result, it is possible to avoid a decrease in manufacturing yield and reliability of the wiring substrate 11 due to mounting defects, an increase in manufacturing cost, and a decrease in productivity. In addition, the electronic components 17a and 17b can be prevented from being damaged by the contact between the top surfaces and the bottom surfaces 93a and 93b of the electronic components 17a and 17b during reflow.

  In this embodiment, when the electronic components 17a and 17b are reflow soldered, the wiring board 11 is accommodated in the reflow soldering jig 70, and the wiring board 11 is placed in the lid 90 and the lower jig 80. It is pinched with. Therefore, it is possible to prevent the wiring substrate 11 from warping due to heat during soldering.

  In the present embodiment, when the electronic components 17a and 17b are soldered by reflow, the wiring board 11 is accommodated in the reflow soldering jig 70, and the wiring board 11 is placed in the lid 90 and the lower jig. It is sandwiched and covered by 80. Therefore, it can suppress that the flux residue etc. which solid components, such as a pine resin and an activator in organic flux deposited after soldering, adhere to a wiring board and are contaminated. Thereby, it is possible to suppress the flux residue having corrosiveness with respect to the wiring board 11 from deteriorating the insulation between the circuits formed on the wiring board 11, and the flux residue has a finished appearance of the wiring board 11. It can also be suppressed.

(First modification)
In the manufacturing method of the present embodiment described above, the communication part 94 penetrating each side surface of the cover 90 is provided in the cover 90 used in the reflow process for mounting the electronic components 17a and 17b on the wiring board 11. Yes.
On the other hand, it replaces with the communication part 94 and a cover body may be provided with the communication part which penetrates between the bottom surfaces 93a and 93b of the recessed part 91, and the upper surface of a cover body. FIG. 6 is a longitudinal sectional view showing a main part of a reflow soldering jig according to a first modification accommodating the wiring board 11. FIG. 7 is a bottom view showing the lid 110 according to the first modification. The lid body 110 is formed with four communicating portions 111 each having a hole shape penetrating between the four corner portions of the bottom surfaces 93 a and 93 b of the recess 91 and the upper surface of the lid body 110. From the standpoint of preventing the chip from standing up, the communication part 111 is provided with a bottom surface 93a, which is unlikely to come into contact with the raised electronic components 17a, 17b even when the electronic components 17a, 17b rise during reflow, as in this modification. It is preferable to form the region 93b.

The number of communicating portions 111 formed on the lid 110 is not particularly limited as long as it is 1 or more, but it is preferable to provide a plurality of communicating portions 111 in order to improve the convective heat transfer efficiency during solder flow and gas escape properties.
Further, a communication portion that penetrates the side surface of the lid, such as the communication portion 94, may be formed together with a communication portion that penetrates the upper portion of the lid, like the communication portion 111.
The shape of the communication portion 111 is not particularly limited as long as it penetrates the bottom surfaces 93 a and 93 b of the recess 91 and the top surface of the lid 110.

(Second modification)
In the manufacturing method of the present embodiment described above, one recess 91 having a plurality of bottom surfaces 93a, 93b having a depth corresponding to the height of each of the plurality of electronic components 17a, 17b is formed in the lid 90. .
On the other hand, the lid body may include a plurality of recesses having bottom surfaces with depths corresponding to the respective heights of the plurality of electronic components 17a and 17b. FIG. 8 is a longitudinal sectional view showing main parts of a reflow soldering jig according to a second modified example in which the wiring board 11 is accommodated. FIG. 9 is a bottom view showing a lid body 96 according to a second modification. The lid 96 has a recess 97a having a bottom surface 98a having a depth corresponding to the height of the plurality of electronic components 17a, and a recess 97b having a bottom surface 98b having a depth corresponding to the height of the plurality of electronic components 17b. Is formed.
8 and 9, a recess connection space 99 for connecting the recess 97a and the recess 97b is provided. However, the recess 97a and the recess 97b communicate with the external space of the lid 96 through the communication portion 94, respectively. The recess connection space 99 may not be provided.

  This modification is essentially not different from the method for manufacturing the wiring substrate 11 of the present embodiment except that the lid 96 used in the reflow process (heating process) has a plurality of recesses 97a and 97b. Therefore, also in the manufacturing method of the wiring board 11 which concerns on this modification, the effect similar to the manufacturing method of the wiring board 11 of this embodiment can be acquired.

(Other embodiments)
Embodiments of the present invention are not limited to the above-described embodiments, and can be expanded and modified. The expanded and modified embodiments are also included in the technical scope of the present invention.
For example, in the method of manufacturing the wiring substrate 11, the lid used in the reflow process is connected to the communication portion 94 that penetrates the side surfaces of the lids 90 and 96, or between the bottom surfaces 93 a and 93 b of the recess 91 and the top surface of the lid 110. The case where the communicating part 111 that penetrates is provided has been described as an example. Instead of the communication portions 94 and 111 (may be together with the communication portion 94 or the communication portion 111), a communication portion penetrating between the bottom surface 93a, 93b of the recess 91 and the side surface of the lid body may be provided. You may provide the communication part which penetrates the inner surface of 91, and the upper surface of a cover body.
Further, in the method of manufacturing the wiring board 11, the case where a plurality of electronic components having different heights, such as the plurality of electronic components 17 a and the plurality of electronic components 17 b, is mounted as an example is described. A plurality of electronic components may be mounted, or only one electronic component may be mounted. Also in these cases, as in the case of mounting a plurality of electronic components 17a and 17b, the lid is provided with a communication portion, and the top surface of the plurality of electronic components or the top surface of one electronic component having the same height; It is preferable to arrange the lid on the substrate so that the bottom surface of the lid is opposed to a predetermined distance or less.

1 is a cross-sectional view schematically illustrating a configuration of a wiring board according to an embodiment of the present invention. It is sectional drawing showing the manufacturing process of the wiring board which concerns on one Embodiment of this invention. It is sectional drawing showing the manufacturing process of the wiring board which concerns on one Embodiment of this invention. It is sectional drawing showing the manufacturing process of the wiring board which concerns on one Embodiment of this invention. It is sectional drawing showing the manufacturing process of the wiring board which concerns on one Embodiment of this invention. It is a disassembled perspective view showing the state which decomposed | disassembled the reflow soldering jig | tool used by one Embodiment of this invention. It is a top view of the lower jig | tool used by one Embodiment of this invention. It is a bottom view of the lid used in one embodiment of the present invention. It is a longitudinal cross-sectional view showing the principal part of the jig | tool for the reflow soldering which concerns on the 1st modification which accommodated the wiring board. It is a bottom view showing the lid concerning a 1st modification. It is a longitudinal cross-sectional view showing the principal part of the jig | tool for the reflow soldering which concerns on the 2nd modification which accommodated the wiring board. It is a bottom view showing the cover concerning a 2nd modification. It is explanatory drawing which shows a chip | tip standing phenomenon.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Wiring board, 12 ... Board | substrate, 16 ... Semiconductor integrated circuit chip, 17a, 17b ... Electronic component, 70 ... Reflow soldering jig, 80 ... Lower jig, 81 ... Recessed part, 82 ... Escape recessed part, 83 ... Projection , 90 ... lid, 91 ... recess, 92 ... step, 93a, 93b ... bottom, 94 ... communication part, 95 ... notch, 96 ... lid, 97a, 97b ... recess, 98a, 98b ... bottom, 99 ... Concave connecting space, 100 ... convex part, 110 ... lid, 111 ... communicating part.

Claims (5)

An application step of applying a solder paste on the connection pads of the substrate including the connection pads;
A mounting step of mounting electronic components on the applied solder paste;
An arrangement step of arranging a lid on the substrate so as to cover the electronic component;
A heating step of heating the substrate on which the lid is disposed;
Comprising
The method for manufacturing a wiring board, wherein the lid includes a communication portion that communicates a space formed between the lid and the electronic component and an external space of the lid.   The method for manufacturing a wiring board according to claim 1, wherein a plurality of the communication portions are formed on the lid.   In the arranging step, the lid body having a bottom surface having a depth corresponding to the height of the electronic component is arranged so that the bottom surface and the upper surface of the electronic component face each other at a predetermined interval or less. The manufacturing method of the wiring board of Claim 1 or 2. In the mounting step, mounting a plurality of the electronic components,
In the arranging step, the lid having a plurality of bottom surfaces each having a depth corresponding to the height of each of the plurality of electronic components, wherein the plurality of bottom surfaces and the top surfaces of the plurality of electronic components are all equal to or less than a predetermined interval. The method of manufacturing a wiring board according to claim 1, wherein the wiring boards are arranged so as to face each other.   5. The method for manufacturing a wiring board according to claim 3, wherein the predetermined interval is 0.2 mm.

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