JP2008243943A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing on-resistance at collapsing and reducing a gate leakage current. <P>SOLUTION: The semiconductor device has: a gate electrode 7 in Schottky-contact with nitride-based compound semiconductor layers (3, 4) on the nitride-based compound semiconductor layers (3, 4); a first insulation film 18 formed on the gate electrode 7; a source electrode 5 in low-resistance contact with the nitride-based compound semiconductor layers (3, 4) on the nitride-based compound semiconductor layers 3, 4 separated from the gate electrode 7; a source FP electrode 9 that is formed via the gate electrode 7 and the first insulation film 18, connected to the source electrode 5 electrically, and extended while straddling over the gate electrode 7 when viewed in a plan view, and a second insulation film 10 formed on the source FP electrode 9. In the semiconductor device, the source FP electrode 9 is formed to be thicker than the source electrode 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device characterized by a stress relaxation mechanism using a thick source field plate (FP) electrode and a manufacturing method thereof.

  In recent years, semiconductor elements using nitride-based compound semiconductors have attracted attention because of their high frequency and high breakdown voltage characteristics. However, a semiconductor device using a nitride-based compound semiconductor has not been put into practical use as a power device such as a switching device because of a problem of a decrease in drain current (so-called current collapse phenomenon) during high voltage operation and a gate leakage current.

  As one of the solutions, a nitride in which a field plate (FP) electrode portion (hereinafter referred to as FP electrode) extending from a main portion (hereinafter referred to as gate electrode) of the gate electrode is provided between the drain electrode and the gate electrode. A semiconductor device made of a compound semiconductor is disclosed. (For example, refer to Patent Document 1).

In Patent Document 1, a source FP structure in which a source FP electrode electrically connected to a source electrode is extended to the drain electrode side through a gate electrode and an insulating film so as to straddle the gate electrode. However, with the source FP electrode structure alone, the electric field concentration occurring near the gate electrode end cannot be sufficiently relaxed, and a high breakdown voltage may not be obtained. As a technique for solving this problem, Patent Document 1 discloses a structure in which a gate FP structure extending under the source FP electrode to the drain electrode side between the drain electrode and the gate electrode is provided.
Japanese Patent Laying-Open No. 2005-93864 (page 8, FIG. 2)

  In order to provide the semiconductor device with good moisture resistance, a silicon nitride film is used as a protective film rather than a silicon oxide film. Furthermore, a passivation film made of a polyimide resin film or the like on the silicon nitride film and protecting the surface of the semiconductor device is further formed. When formed in this manner, a semiconductor device having high moisture resistance and high external insulation can be obtained.

  However, since a tensile stress is generated when the silicon nitride film or the polyimide resin is formed, there is a problem that the height of the Schottky barrier is lowered due to the tensile stress and the gate leakage current is increased.

  An object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which the on-resistance at the time of coplus is reduced and the gate leakage current is reduced.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a first electrode in Schottky contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer, and the first electrode. A first insulating film formed on the electrode, and a first electrode of a second electrode in low resistance contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer spaced from the first electrode Part, the first electrode and the first insulating film, and electrically connected to the first part of the second electrode, and in plan view, the first electrode A semiconductor device comprising: a second portion of the second electrode extending so as to straddle the upper portion; and a second insulating film formed on the second portion of the second electrode, The thickness of the second portion of the second electrode is greater than the thickness of the first portion of the second electrode. The features.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the thickness of the second portion of the second electrode is not less than five times the thickness of the second insulating film. It is characterized by.

  According to a third aspect of the present invention, there is provided a semiconductor device comprising: a gate electrode provided with a MIS structure on the nitride compound semiconductor layer via a Schottky contact or an insulating film with the nitride compound semiconductor layer; A first insulating film formed on the gate electrode, a first portion of a source electrode in low resistance contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer spaced from the gate electrode, and the gate electrode The source electrode is formed through the first insulating film, is electrically connected to the first portion of the source electrode, and extends over the gate electrode when viewed in plan And a second insulating film formed on the second part of the source electrode, wherein the thickness of the second part of the source electrode is the same as that of the source electrode. Than the thickness of the first part Characterized in that it is Ku formed.

  According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the thickness of the second portion of the source electrode is not less than five times the thickness of the second insulating film. And

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the first insulating film is formed of a silicon oxide film.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the second insulating film is formed by laminating one or both of a silicon nitride film and a polyimide resin film. It is characterized by being formed.

  A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the nitride compound semiconductor layer has a heterojunction and is two-dimensionally adjacent to the heterojunction plane. A carrier gas layer is formed.

  The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to any one of the third to sixth aspects, wherein the gate electrode is connected to the nitride-based compound semiconductor layer via a Schottky contact or an insulating film. A first portion of the gate electrode having a MIS structure; and a second portion of the gate electrode provided on the nitride-based compound semiconductor layer via a third insulating film. As seen, the second part of the second electrode is formed so as to straddle the first part and the second part of the first electrode.

  The method of manufacturing a semiconductor device according to claim 9 of the present invention includes the step of forming the first portion of the second electrode in low resistance contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer. And forming a first electrode in Schottky contact with the nitride-based compound semiconductor layer on the nitride-based compound semiconductor layer, and forming a first insulating film formed almost over the entire surface as viewed from above. And electrically connecting the first electrode and the first insulating film so as to straddle over the first electrode when viewed from the upper surface side. And forming a second portion of the second electrode that is thicker than the first portion of the second electrode, and a second portion that is formed almost over the entire surface as viewed from above. And a step of forming an insulating film.

  The method for manufacturing a semiconductor device according to claim 10 of the present invention is the method for manufacturing a semiconductor device according to claim 9, wherein the nitride-based compound semiconductor layer has a heterojunction, and 2 near the heterointerface. It has a two-dimensional electron gas layer.

  The method for manufacturing a semiconductor device according to claim 11 of the present invention is the method for manufacturing a semiconductor device according to claim 9 or 10, wherein the first insulating film is formed of a silicon oxide film, and the second insulating film is formed. The film is formed of a silicon nitride film.

  According to the semiconductor device and the method of manufacturing the same of the present invention, the on-resistance at the time of coplus can be reduced and the gate leakage current can be reduced.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

[First embodiment]
FIG. 1 is a schematic sectional view of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has a Schottky contact with a nitride compound semiconductor layer (3,4) on a nitride compound semiconductor layer (3,4). The first electrode 7, the first insulating film 18 formed on the first electrode 7, and the nitride-based compound semiconductor layer (3, 4) spaced from the first electrode 7. Formed through the first portion (5) of the second electrode (5, 9) in low resistance contact with the compound semiconductor layer (3,4), the first electrode 7 and the first insulating film 18, The second electrode (5, 9) extending from the first part (5) side of the second electrode (5, 9) so as to straddle over the first electrode 7 in plan view. The second portion (9) and the second insulating film 10 formed on the second portion (9) of the second electrode (5, 9).

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, the thickness of the second portion (9) of the second electrode (5, 9) is the second electrode (5, 9). ) Is formed to be thicker than the thickness of the first portion (5).

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, the thickness of the second portion (9) of the second electrode (5, 9) is the second insulating film. It is characterized by being about 5 times the thickness of 10 or more.

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, the first insulating film 18 is formed of a silicon oxide film.

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, the second insulating film 10 is formed by laminating one or both of a silicon nitride film and a polyimide resin film. It is characterized by.

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, the nitride-based compound semiconductor layers (3, 4) have a heterojunction, and 2 in the vicinity of the heterojunction surface. A dimensional carrier gas layer is formed.

  As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an electron transit layer described later on a substrate 1 made of single crystal silicon (Si), silicon carbide (SiC), ceramic, or the like. 3 has a known buffer layer (buffer layer) 2 for relaxing the lattice constant difference between the substrate 3 and the substrate 1 and improving the crystallinity of the electron transit layer 3.

  On the buffer layer 2, an electron transit layer 3 made of a first nitride compound semiconductor and an electron supply layer 4 made of a second nitride compound semiconductor are sequentially laminated. A two-dimensional electron gas layer 12 is formed on the electron transit layer 3 side of the interface between the electron transit layer 3 and the electron supply layer 4. A source electrode 5, a drain electrode 6, and a gate electrode 7 are provided on the electron supply layer 4.

  For the source electrode 5 and the drain electrode 6 disposed on the electron supply layer 4, for example, a laminated electrode structure Ti / Al composed of a Ti layer having a thickness of about 25 nm and an Al layer having a thickness of about 500 nm is sputtered. Alternatively, it is formed by annealing after vacuum deposition.

  The gate electrode 7 is obtained, for example, by obtaining a desired pattern shape by a photolithography technique, and after forming a desired resist pattern, a Ni layer having a thickness of about 25 nm, an Al layer having a thickness of about 500 nm, A laminated electrode structure made of a Ti layer having a thickness of about 25 nm is formed by lift-off after a laminated structure made of Ni / Al / Ti is sputtered or vacuum deposited.

  The current collapse phenomenon is caused when a high voltage is applied between the gate and the drain of the semiconductor device, and electrons are injected from the gate electrode 7 into the surface between the gate and the drain, thereby causing a nitride compound semiconductor layer (electron supply layer) having crystal defects. 4) Even when a voltage at which the device is turned on is applied to the gate electrode 7 because the electron concentration of the two-dimensional electron gas layer 12 is reduced by being trapped and accumulated in the surface level of 4), the electron emission from the surface level is not caused. This is considered to be a phenomenon in which the steady drain-source current Ids decreases due to the slowness.

  FIG. 2 shows a structure of the semiconductor device according to the first embodiment of the present invention, in which Ni (7) / AlGaN (4) when the silicon oxide film 18 is disposed on the gate electrode 7 as shown in FIG. ) / Band diagram structure diagram in the vicinity of GaN (3), showing a schematic diagram of an example having a barrier height Vb1. FIG. 3 shows Ni (7) / when a silicon nitride film is directly disposed on the gate electrode 7 instead of the silicon oxide film 18 in the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a band diagram structure diagram in the vicinity of AlGaN (4) / GaN (3), showing a schematic diagram of an example having a barrier height of Vb2. As apparent from the comparison between FIG. 2 and FIG. 3, Vb1> Vb2 and the example of FIG. 2 in which the silicon oxide film 18 is arranged on the gate electrode 7 instead of the silicon nitride film has a Schottky barrier. The leakage current of the gate electrode 7 is reduced. In the semiconductor device according to the first embodiment of the present invention, the insulating film disposed on the exposed portion of the nitride-based compound semiconductor layer (3,4) on which no electrode is formed is a silicon nitride film. In comparison, a silicon oxide film is preferable.

  Since the silicon nitride film gives a tensile stress to the electron supply layer 4 in the same manner as the electron transit layer 3, the piezoelectric polarization of the electron transit layer 3 with the electron supply layer 4 is weakened, and the electron concentration is lowered to reduce the semiconductor device. This is because the on-resistance of the is increased.

  As shown in FIG. 1, in the semiconductor device according to the first embodiment of the present invention, the source electrode 5 is electrically connected to the gate electrode 7 so as to cover the gate electrode 7 through the silicon oxide film 18 so as to straddle the gate electrode 7. Connected source field plate (FP) electrodes 9 are formed from the source electrode 5 side to the drain electrode 6 side.

The thickness of the silicon oxide film 18 functioning as an interlayer insulating film between the source electrode 5 and the source FP electrode 9 and the gate electrode 7 is, for example, about 300 to 700 nm, and preferably about 500 nm, for example. When the silicon oxide film 18 is formed, a compressive stress (4.00 × 10 ⁹ dyn / cm ² ) is generated unlike a silicon nitride film (tensile stress, −6.14 × 10 ⁸ dyn / cm ² ).

  Therefore, as shown in FIG. 2, in the semiconductor device according to the first embodiment of the present invention, a silicon nitride film is used as an interlayer insulating film between the source electrode 5 and the source FP electrode 9 on the gate electrode 7. In this case, the tensile stress of the silicon nitride film is transmitted to the gate electrode 7 and the electron supply layer 4 exposed around the gate electrode 7, and accordingly, the height of the Schottky barrier of the gate electrode 7 is lowered and the gate leakage current is increased. It is possible to suppress the problem of end. The source FP electrode 9 is formed by electrolytic plating of Au or Cu or sputtering of Al, and is preferably about 1/10 or more of the thickness of the polyimide resin 11 described later, and has a thickness of 3 to 8 μm, for example.

  A silicon nitride film 10 having higher moisture resistance than the silicon oxide film so as to cover the upper surface and side surfaces of the silicon oxide film 18 and the source FP electrode 9 has a thickness of, for example, about 400 to 800 nm, preferably about 500 nm. Is formed.

  Further, a polyimide resin 11 having a thickness of, for example, about 5 to 20 μm, preferably about 10 μm is formed on the silicon nitride film 10 so as to cover the silicon nitride film 10.

  FIG. 4 shows the drain-source current Ids (A) when the source FP electrode 9 is provided (D2) and when the source FP electrode 9 is not provided (D1) in the semiconductor device according to the first embodiment of the present invention. / Mm) and a comparison diagram of the relationship between the drain-source voltage Vds (V). As is apparent from FIG. 4, in the case where the source FP electrode 9 is provided (D2), the leakage current is larger due to the characteristics of the drain-source current Ids (A / mm) and the drain-source voltage Vds (V). It is suppressed.

  In the semiconductor device according to the first embodiment of the present invention, as shown in FIG. 1, a silicon nitride film that causes tensile stress to the nitride semiconductor layer (electron supply layer 4) to cause a reduction in the Schottky barrier is used. However, the silicon oxide film 18 is disposed, and the silicon nitride film 10 having higher moisture resistance than the silicon oxide film 18 is provided on the silicon oxide film 18.

  However, in the region where the thick source FP electrode 9 is provided, the interlayer insulating film between the thick source FP electrode 9 and the gate electrode 7 becomes the silicon oxide film 18, and the silicon nitride film 10 is formed on the source FP electrode 9. ing. Therefore, the source FP electrode 9 can relieve the tensile stress of the silicon nitride film 10 (including the polyimide resin 11 on the silicon nitride film 10), and the influence on the gate electrode 7 and its vicinity can be suppressed.

  In addition, since the interlayer insulating film between the gate electrode 7 and the source FP electrode 9 is the silicon oxide film 18 that generates a compressive stress, even if a tensile stress is generated in the vicinity of the gate electrode 7 and its end, it can be mitigated. To work.

  Therefore, as shown in FIG. 2, the height of the Schottky barrier is lowered by the tensile stress generated in the gate electrode 7, and the leakage current between the gate / drain or between the gate / source is increased by one digit or more. Can be suppressed. Further, since the silicon nitride film 10 and the polyimide resin 11 are formed on the silicon oxide film 18, the moisture resistance is higher than that of the silicon oxide film 18 alone.

  In the semiconductor device according to the first embodiment of the present invention, either the silicon nitride film 10 or the polyimide resin 11 may be omitted, but both are formed in order to further secure moisture resistance and insulation. It is desirable.

  Furthermore, in the semiconductor device according to the first embodiment of the present invention, the buffer layer 2 can be omitted.

  Furthermore, in the semiconductor device according to the first embodiment of the present invention, when the substrate 1 is a conductive substrate, a back electrode is provided on the back side of the substrate 1 and the source electrode 5 and the back electrode are electrically connected by wiring. By doing so, the electric field concentration in the vicinity of the drain electrode 6 can be relaxed.

  Furthermore, in the semiconductor device according to the first embodiment of the present invention, a barrier layer such as an AlN barrier layer may be provided between the electron supply layer 4 and the electron transit layer 3.

  According to the semiconductor device of the first embodiment of the present invention, the on-resistance at the time of coplus can be reduced and the gate leakage current can be reduced.

[Second Embodiment]
FIG. 5 is a schematic sectional view of a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 5, the semiconductor device according to the second embodiment of the present invention has a gate field plate (FP) electrode in the gate electrode 7 in addition to the structure in which the source FP electrode 9 is arranged in the source electrode 5. 17 is provided to alleviate the electric field concentration, reduce the current collapse phenomenon, and reduce the gate leakage current.

  Furthermore, in the semiconductor device according to the second embodiment of the present invention, the drain electrode 6 is also provided with a drain field plate (FP) electrode structure, the electric field concentration is reduced, the current collapse phenomenon is reduced, and the gate leakage Current can be reduced. For example, in FIG. 6, by further extending the drain plating electrode 60 toward the gate electrode 7 or the gate FP electrode 9, the drain electrode 6 can also be provided with a drain field plate (FP) electrode structure.

  When the gate electrode 7 has a field plate (FP) structure, at least the gate electrode 7 is covered with the source FP electrode 9. Desirably, it is desirable that the source FP electrode 9 extends to the drain electrode 6 side from the end of the gate FP structure.

  The source FP electrode 9 may be integrated with the source electrode 5, but as shown in FIG. 8, the source FP electrode 9 may be formed separately from each other and electrically connected.

  As shown in FIG. 5, the semiconductor device according to the second embodiment of the present invention has a Schottky contact with the nitride compound semiconductor layer (3,4) on the nitride compound semiconductor layer (3,4). First electrode (7, 17), first insulating film (18) formed on first electrode 7, and nitride-based compound semiconductor layer spaced from first electrode (7, 17) A first portion (5) of the second electrode (5, 50, 9) in low-resistance contact with the nitride-based compound semiconductor layer (3,4) on the (3,4), and the first electrode (7 , 17) and the first insulating film (18), and the first electrode from the first portion (5) of the second electrode (5, 50, 9) in plan view A second portion (9) of the second electrode (5, 50, 9) extending across (7, 17) and a second portion of the second electrode (5, 50, 9). Second part formed on part (9) of A semiconductor device having an insulating film (10), wherein the thickness (9) of the second portion of the second electrode (5, 50, 9) is the first of the second electrode (5, 50, 9). It is characterized by being formed thicker than the thickness of the part (5).

  In the semiconductor device according to the second embodiment of the present invention, the thickness of the second portion (9) of the second electrode (5, 50, 9) is equal to the thickness of the second insulating film (10). For example, it is characterized by being about 5 times or more.

  The semiconductor device according to the second embodiment of the present invention is characterized in that the first insulating film is formed of a silicon oxide film 18 as shown in FIG.

  In the semiconductor device according to the second embodiment of the present invention, as shown in FIG. 5, the second insulating film is formed by laminating one or both of the silicon nitride film 10 and the polyimide resin film (11). It is formed.

  Further, in the semiconductor device according to the second embodiment of the present invention, as shown in FIG. 5, the nitride-based compound semiconductor layers (3,4) have a heterojunction and are two-dimensionally in the vicinity of the heterojunction plane. A carrier gas layer is formed.

  In the semiconductor device according to the second embodiment of the present invention, as shown in FIG. 5, the first electrode (7, 17) is in Schottky contact with the nitride-based compound semiconductor layer (3,4). A first portion (7) of the first electrode (7, 17) and a first insulating layer (8) provided on the nitride-based compound semiconductor layer (3,4) via a third insulating film (8). The second part (17) of the electrode (7, 17) and the second part (9) of the second electrode (5, 50, 9) is the first electrode ( 7, 17) is formed so as to straddle the first portion (7) and the second portion (17).

  As shown in FIG. 5, the semiconductor device according to the second embodiment of the present invention includes an electron transit layer described later on a substrate 1 made of single crystal silicon (Si), silicon carbide (SiC), ceramic, or the like. 3 has a known buffer layer (buffer layer) 2 for relaxing the lattice constant difference between the substrate 3 and the substrate 1 and improving the crystallinity of the electron transit layer 3.

  On the buffer layer 2, an electron transit layer 3 made of a first nitride compound semiconductor, and an electron supply layer 4 made of a second nitride compound semiconductor having a lattice constant smaller than that of the first nitride compound semiconductor. Are sequentially stacked. A two-dimensional electron gas layer 12 is formed on the electron transit layer 3 side of the interface between the electron transit layer 3 and the electron supply layer 4. A source electrode 5, a drain electrode 6, and a gate electrode 7 are provided on the electron supply layer 4.

  For the source electrode 5 and the drain electrode 6 disposed on the electron supply layer 4, for example, a laminated electrode structure Ti / Al composed of a Ti layer having a thickness of about 25 nm and an Al layer having a thickness of about 500 nm is sputtered. Alternatively, it is formed by annealing after vacuum deposition.

  After obtaining a desired pattern shape by photolithography, a source plating electrode 50 is formed on the source electrode 5 and a drain plating electrode 60 is formed on the drain electrode 6 by, for example, Au plating. The source FP electrode 9 can also be formed by Au plating simultaneously with the source plating electrode 50.

  In addition, the gate electrode 7 is formed by forming a desired resist pattern and, for example, a laminated electrode structure including a Ni layer having a thickness of about 25 nm, an Al layer having a thickness of about 500 nm, and a Ti layer having a thickness of about 25 nm. A laminated structure made of Ni / Al / Ti is formed by lift-off after sputtering or vacuum deposition. Alternatively, the gate electrode 7 may be formed of a Ni / Au laminated structure.

  The current collapse phenomenon is caused when a high voltage is applied between the gate and the drain of the semiconductor device, and electrons are injected from the gate electrode 7 into the surface between the gate and the drain, thereby causing a nitride compound semiconductor layer (electron supply layer) having crystal defects. 4) Even when a voltage is applied to the gate electrode 7 so that the electron concentration of the two-dimensional electron gas layer 12 is reduced by being trapped and accumulated at the surface level and the device is turned on, the electron emission from the surface level is not caused. This is considered to be a phenomenon in which the steady drain-source current Ids decreases due to the slowness.

  Also in the configuration of the semiconductor device according to the second embodiment of the present invention, the same effect as that of the semiconductor device according to the first embodiment of the present invention can be obtained. That is, as apparent from the comparison between FIG. 2 and FIG. 3, Vb1> Vb2, and the example of FIG. 2 in which the silicon oxide film 18 is arranged on the gate electrode 7 instead of the silicon nitride film is more Schottky. The barrier is high and the leakage current of the gate electrode 7 is reduced. In the semiconductor device according to the first embodiment of the present invention, the insulating film disposed on the exposed portion of the nitride-based compound semiconductor layer (3,4) on which no electrode is formed is a silicon nitride film. In comparison, a silicon oxide film is preferable.

  Since the silicon nitride film gives a tensile stress to the electron supply layer 4 in the same manner as the electron transit layer 3, the piezoelectric polarization of the electron transit layer 3 with the electron supply layer 4 is weakened, and the electron concentration is lowered to reduce the semiconductor device. This is because the on-resistance of the is increased.

  As shown in FIG. 5, in the semiconductor device according to the second embodiment of the present invention, the source electrode 5 is electrically connected to the gate electrode 7 so as to cover the gate electrode 7 through the silicon oxide film 18 so as to straddle the gate electrode 7. Connected source field plate (FP) electrodes 9 are formed from the source electrode 5 side to the drain electrode 6 side.

The thickness of the silicon oxide film 18 functioning as an interlayer insulating film between the source electrode 5 and the source FP electrode 9 and the gate electrode 7 is, for example, about 300 to 700 nm, and preferably about 500 nm, for example. When the silicon oxide film 18 is formed, a compressive stress (4.00 × 10 ⁹ dyn / cm ² ) is generated unlike a silicon nitride film (tensile stress, −6.14 × 10 ⁸ dyn / cm ² ).

  Therefore, as shown in FIG. 5, in the semiconductor device according to the second embodiment of the present invention, a silicon nitride film is used as an interlayer insulating film between the source electrode 5 and the source FP electrode 9 on the gate electrode 7. In this case, the tensile stress of the silicon nitride film is transmitted to the gate electrode 7 and the electron supply layer 4 exposed around the gate electrode 7, and accordingly, the height of the Schottky barrier of the gate electrode 7 is lowered and the gate leakage current is increased. It is possible to suppress the problem of end.

  As shown in FIG. 5, in the semiconductor device according to the second embodiment of the present invention, the drain FP electrode structure is formed by the drain plating electrode 60 through the silicon oxide film 18 so as to straddle the drain electrode 6. It may also be formed on the side. The drain electrode 6 can also be provided with a drain field plate (FP) electrode structure to alleviate electric field concentration, reduce the current collapse phenomenon, and reduce the gate leakage current. As described above, for example, in FIG. 5, the drain plating electrode 60 is further extended to the gate electrode 7 or the gate FP electrode 9 side, so that the drain electrode 6 can also be provided with a drain field plate (FP) electrode structure.

  Also with the drain FP electrode structure, the electric field concentration in the vicinity of the drain electrode 6 is alleviated, and the structure in which the silicon oxide film 18 is disposed between the drain plating electrode 60 and the nitride-based compound semiconductor layer (3, 4) allows compression stress. Is added, the number of electrons in the two-dimensional electron gas layer 12 is increased, and the on-resistance can be reduced.

The thickness of the silicon oxide film 18 functioning as an interlayer insulating film with the gate electrode 7 is, for example, about 300 to 700 nm, and preferably about 500 nm, for example. When the silicon oxide film 18 is formed, a compressive stress (4.00 × 10 ⁹ dyn / cm ² ) is generated unlike a silicon nitride film (tensile stress, −6.14 × 10 ⁸ dyn / cm ² ).

  Therefore, similarly to the first embodiment, the semiconductor device according to the second embodiment of the present invention has a problem that the height of the Schottky barrier decreases and the gate leakage current increases. Can be suppressed. The source FP electrode 9 is formed by electrolytic plating of Au or Cu or sputtering of Al, and is preferably about 1/10 or more of the thickness of the polyimide resin 11 described later, and has a thickness of 3 to 8 μm, for example.

  A silicon nitride film 10 having higher moisture resistance than the silicon oxide film is formed to cover the source FP electrode 9 to a thickness of, for example, about 400 to 800 nm, preferably about 500 nm.

  Further, a polyimide resin 11 having a thickness of, for example, about 5 to 20 μm, preferably about 10 μm is formed on the silicon nitride film 10 so as to cover the silicon nitride film 10 (not shown).

  Also in the semiconductor device according to the second embodiment of the present invention, the drain-source current Ids (A / mm) when the source FP electrode 9 is provided (D2) and when the source FP electrode 9 is not provided (D1). And the drain-source voltage Vds (V) are compared in the same manner as in FIG. When the source FP electrode 9 is provided (D2), the leakage current is suppressed due to the characteristics of the drain-source current Ids (A / mm) and the drain-source voltage Vds (V).

  In the semiconductor device according to the second embodiment of the present invention, as shown in FIG. 5, a silicon nitride film that causes tensile stress to the nitride semiconductor layer (electron supply layer 4) to cause a reduction in the Schottky barrier. However, the silicon oxide film 18 is disposed, and the silicon nitride film 10 having higher moisture resistance than the silicon oxide film 18 is provided on the silicon oxide film 18.

  However, in the region where the thick source FP electrode 9 is provided, the interlayer insulating film between the thick source FP electrode 9 and the gate electrode 7 becomes the silicon oxide film 18, and the silicon nitride film 10 is formed on the source FP electrode 9. ing. Therefore, the source FP electrode 9 can relieve the tensile stress of the silicon nitride film 10 (including the polyimide resin 11 on the silicon nitride film 10), and the influence on the gate electrode 7 and its vicinity can be suppressed.

  In addition, since the interlayer insulating film between the gate electrode 7 and the source FP electrode 9 is the silicon oxide film 18 that generates a compressive stress, even if a tensile stress is generated in the vicinity of the gate electrode 7 and its end, it can be mitigated. To work.

  Therefore, the height of the Schottky barrier is reduced due to the tensile stress generated in the gate electrode 7, and the problem that the leakage current between the gate and drain or between the drain and source or between the gate and source is increased by one digit or more is suppressed. can do. Further, since the silicon nitride film 10 and the polyimide resin 11 are formed on the silicon oxide film 18, the moisture resistance is higher than that of the silicon oxide film 18 alone.

  In the semiconductor device according to the second embodiment of the present invention, either the silicon nitride film 10 or the polyimide resin 11 may be omitted, but both are formed in order to further secure moisture resistance and insulation. It is desirable.

  Furthermore, in the semiconductor device according to the second embodiment of the present invention, the buffer layer 2 can be omitted.

  Furthermore, in the semiconductor device according to the second embodiment of the present invention, when the substrate 1 is a conductive substrate, a back electrode is provided on the back side of the substrate 1, and the source electrode 5 and the back electrode are electrically connected by wiring. By doing so, the electric field concentration in the vicinity of the drain electrode 6 can be relaxed.

  Furthermore, in the semiconductor device according to the second embodiment of the present invention, a barrier layer such as an AlN barrier layer may be provided between the electron supply layer 4 and the electron transit layer 3.

When the gate-drain distance L _GD shown in FIG. 5 is constant due to the characteristics of the semiconductor device according to the second embodiment of the present invention, in the single FP structure in which the source FP electrode 9 is not formed, the gate FP electrode The on-resistance at the time of coplus and the withstand voltage at the time of pulse application were in a trade-off relationship with respect to the distance L _GF-D between (17) and the drain electrode (6). On the other hand, in the double FP structure in which the length of the gate FP electrode 17 (gate FP length) is constant and the source FP electrode 9 is also formed, if the distance L _SF-D between the source FP electrode 9 and the drain electrode 6 is shortened, Reduced on-resistance during co-plus. On the other hand, the withstand voltage at the time of applying the pulse only slightly decreased.

(Modification 1)
FIG. 6 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 1 of the second embodiment of the present invention. In the semiconductor device according to the first modification of the second embodiment of the present invention, the source FP electrode 9 is connected to the gate electrode 7 via the silicon oxide film 18 disposed on the gate electrode 7 as shown in FIG. Characterized by the structure placed above. The other configuration is basically the same as that of the semiconductor device according to the second embodiment shown in FIG.

  Since the source FP electrode 9 does not extend up to the gate FP electrode 17 in terms of characteristics, the effect of mitigating the electric field concentration between the gate electrode (7, 17) and the drain electrode 6 is the second embodiment of the present invention. Therefore, the effect of reducing the on-resistance during coplus is low. However, the effect of suppressing the gate leakage current between the gate and drain or between the drain and source or between the gate and source is high as in the semiconductor device according to the second embodiment of the present invention.

On the other hand, in the structure of FIG. 6, when the length of the gate FP electrode 17 is increased, the distance L _GF-D between the gate FP electrode (17) and the drain electrode (6) is substantially reduced. There is an effect of reducing the on-resistance at the time of coplus between the gate and the drain.

(Modification 2)
7A and 7B show a semiconductor device according to Modification 2 of the second embodiment of the present invention. FIG. 7A is a schematic cross-sectional structure diagram, and FIG. A corresponding schematic plane pattern diagram is shown. As shown in FIG. 7, the semiconductor device according to the second modification of the second embodiment of the present invention includes a gate FP electrode 17 that is longer than the gate electrode 7, and is provided on the gate electrode 7 and the gate FP electrode 17. The structure is characterized in that the source FP electrode 9 is disposed on the gate electrode 7 and the gate FP electrode 17 through the disposed silicon oxide film 18. The other configuration is basically the same as that of the semiconductor device according to the second embodiment shown in FIG.

  In terms of characteristics, since the source FP electrode 9 extends to above the gate FP electrode 17, the effect of mitigating the electric field concentration between the gate electrode (7, 17) and the drain electrode 6 is reduced according to the second embodiment of the present invention. Compared with the semiconductor device according to the embodiment, the gate FP electrode 17 is higher by the length. For this reason, the effect of reducing the on-resistance at the time of coplus is high, and the leakage current near the gate electrode is also low. Further, the effect of suppressing the gate leakage current between the gate and the source is high as in the semiconductor device according to the second embodiment of the present invention.

(Modification 3)
FIG. 8 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 3 of the second embodiment of the present invention.

  As shown in FIG. 8, the semiconductor device according to the third modification of the second embodiment of the present invention includes a gate FP electrode 17 that is as long as the gate electrode 7 as in FIG. The structure is characterized in that the source FP electrode 9 is disposed on the source electrode 5, the source plating electrode 50, the gate electrode 7, and the gate FP electrode 17 through the silicon oxide film 18 disposed on the gate FP electrode 17. In addition, the source FP electrode 9 is characterized in that it is separated from the source electrode 5 and the source plating electrode 50 in terms of structure, as shown in FIG. Here, the source FP electrode 9 may be in a floating state. Alternatively, the source FP electrode 9 may be given a constant potential. Alternatively, the source electrode 5 may be connected via a wiring or other contact.

  The other configuration is basically the same as that of the semiconductor device according to the second embodiment shown in FIG.

  In terms of characteristics, since the source FP electrode 9 extends to above the gate FP electrode 17, the effect of mitigating the electric field concentration between the gate electrode (7, 17) and the drain electrode 6 is reduced according to the second embodiment of the present invention. Compared with the semiconductor device according to the embodiment, the gate FP electrode 17 is higher by the length. For this reason, the effect of reducing the on-resistance at the time of coplus is high, and the leakage current near the gate electrode is also low. Further, the effect of suppressing the gate leakage current between the gate and the source is high as in the semiconductor device according to the second embodiment of the present invention.

  When the source FP electrode 9 is separated from the source electrode 5 so as to be in an electrically floating state, the pulse breakdown voltage between the drain and the source is reduced in the semiconductor device according to the second embodiment shown in FIG. It can be made higher than that. This is because the voltage at the time of pulse application is divided between the drain electrode 6 and the source electrode 5 via the gate FP electrode 9.

(Production method)
FIG. 9 to FIG. 14 respectively show schematic cross-sectional structure diagrams of one step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

  As shown in FIGS. 9 to 14, the method of manufacturing a semiconductor device according to the second embodiment of the present invention has a nitride compound semiconductor layer (3) on a nitride compound semiconductor layer (3,4). , 4) forming the first portion (5) of the second electrode (5, 9) and the drain electrode (6) in low resistance contact (FIG. 9), and the nitride-based compound semiconductor layer (3, 4) forming a first electrode (7) in Schottky contact with the nitride-based compound semiconductor layer (3,4) on top of FIG. 10 and FIG. Forming a silicon oxide film (18) (FIG. 12) and the first electrode (5) electrically connected to the first part (5) of the second electrode (5, 9), as viewed from the upper surface side (7) The second electrode (5, 9) of the second electrode (5, 9) which is disposed so as to straddle over the second electrode (5, 9) and is thicker than the first portion (5). A step of forming a portion (9) (Fig. 13), characterized by a step of forming a silicon nitride film 10, or even the polyimide resin 11 is formed over substantially the entire surface as viewed from the top (Figure 14).

  Further, in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, as shown in FIGS. 9 to 14, the nitride-based compound semiconductor layers (3,4) have a heterojunction, A two-dimensional electron gas layer 12 is provided in the vicinity of the heterointerface.

  A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.

(A) First, as shown in FIG. 9, after an electron transit layer 3 made of a GaAlN layer or the like and an electron supply layer 4 made of a GaN layer or the like are formed on a substrate 1 made of silicon, for example, via a buffer layer 2, The source electrode 5 and the drain electrode 6 are formed by patterning.

(B) Next, as shown in FIG. 10, a silicon oxide film 8 is formed on the entire surface of the semiconductor wafer, and a window is opened to a portion where a gate electrode is to be formed by patterning.

(C) Next, as shown in FIG. 11, the gate electrode 7 is formed by patterning.

(D) Next, as shown in FIG. 12, a silicon oxide film 18 is formed on the entire surface of the semiconductor wafer, and windows are opened for the source electrode 5 and the drain electrode 6 by patterning.

(E) Next, as shown in FIG. 13, the source plating electrode 50 and the drain plating electrode 60 are formed on the source electrode 5 and the drain electrode 6 respectively, and at the same time, the silicon so as to cover the gate electrode 7 and the gate FP electrode. A source FP electrode 9 is formed through the oxide film 18. The structure shown in FIG. 13 corresponds to the structure shown in FIG. 7 in which the gate FP electrode 17 is formed short in the semiconductor device according to the second modification of the second embodiment of the present invention.

(F) Next, as shown in FIG. 14, a silicon nitride film 10 is formed on the entire surface of the semiconductor wafer, and a polyimide resin 11 is further formed.

(Cascode circuit)
FIG. 15 shows a circuit configuration diagram in which a high breakdown voltage GaNFET which is a semiconductor device according to an embodiment of the present invention is cascode-connected to a low breakdown voltage SiMOSFET.

(Example of characteristics)
FIG. 16 is a comparison diagram of transfer characteristics of the drain-source current Ids (A) and the gate-source voltage Vgs (V) in the circuit configuration in which the high breakdown voltage GaNFET shown in FIG. 15 is cascode-connected to the low breakdown voltage SiMOSFET. . A single high-voltage GaNFET can provide a normally-off characteristic by cascode connection with a low-voltage SiMOSFET even if it has a normally-on characteristic.

  FIG. 17 shows a comparison diagram of the drain-source voltage Vds (V) characteristics of the input capacitance Ciss (pF). Although the input capacitance Ciss (pF) is larger than that of a single GaNFET, the input capacitance Ciss (pF) can be reduced by cascode-connecting the GaNFET to the SiMOSFET as compared to the case of a single SiMOSFET. For this reason, high-speed switching performance can be obtained.

  FIG. 18 is an example of switching waveforms when a circuit in which a high breakdown voltage GaNFET which is a semiconductor device according to an embodiment of the present invention is cascode-connected to a low breakdown voltage SiMOSFET is applied to a PFC (Power Factor Correction) circuit. ) Vds = 440 (V), Ids = 6.2 (A) continuous switching waveform, (b) Enlarged view of turn-off waveform, (c) Enlarged view of turn-on waveform.

  Compared with the case of using only the SiMOSFET alone, the turn-off time in the rising waveform of Vds is improved by about 40% and speeded up. In addition, the peak current value in the rising waveform of Ids was reduced by about 30% compared with the case of only the SiMOSFET alone, and the noise was reduced. The power conversion efficiency when the PFC circuit is mounted increases as compared with the case of using only the SiMOSFET alone and is low in noise, so that it is possible to reduce the noise suppression circuit, increase the frequency, and reduce the size.

  According to the semiconductor device of the second embodiment of the present invention, the on-resistance at the time of coplus can be reduced and the gate leakage current can be reduced.

[Other embodiments]
As described above, the present invention has been described according to the first to second embodiments. However, it should be understood that the description and drawings constituting a part of this disclosure do not limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

For example, the semiconductor device according to the embodiment of the present invention is not limited to the high electron mobility transistor (HEMT) shown in the first embodiment, and is a composite semiconductor device in which a plurality of elements are formed. It may be.

Further, by changing the structure of the device formation layer, the semiconductor substrate according to the embodiment of the present invention can be obtained by using a light emitting element such as a light emitting diode or a semiconductor laser, a metal semiconductor field effect transistor (MESFET). Metal-oxide-semiconductor field effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), heterojunction bipolar transistors (HBTs) Junction Bipolar Transistor) is also applicable.

As described above, the present invention naturally includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a band diagram structure diagram in the vicinity of Ni / AlGaN / GaN when a silicon oxide film is applied to the semiconductor device according to the first embodiment of the present invention, and shows an example having a barrier height Vb1. FIG. 4 is a band diagram structure diagram in the vicinity of Ni / AlGaN / GaN when a silicon nitride film is applied to the semiconductor device according to the first embodiment of the present invention, and an example having a barrier height of Vb2 (> Vb1). In the semiconductor device according to the first embodiment of the present invention, the drain-source current Ids (A / mm) and the drain-source current when the source FP electrode is provided (D2) and when the source FP electrode is not provided (D1). Comparison of relationship between source voltages Vds (V). The typical cross-section figure of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical cross-section figure of the semiconductor device which concerns on the modification 1 of the 2nd Embodiment of this invention. The typical cross-section figure of the semiconductor device which concerns on the modification 2 of the 2nd Embodiment of this invention. FIG. 15 is a schematic cross-sectional structure diagram of a semiconductor device according to Modification 3 of the second embodiment of the present invention. The typical cross-section figure of one process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical cross-section figure of one process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical cross-section figure of one process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical cross-section figure of one process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical cross-section figure of one process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical cross-section figure of one process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 1 is a circuit configuration diagram in which a high breakdown voltage GaNFET, which is a semiconductor device according to an embodiment of the present invention, is cascode-connected to a low breakdown voltage SiMOSFET. The comparison figure of the transfer characteristics of drain-source current Ids (A) and gate-source voltage Vgs (V). The comparison figure of the drain-source voltage Vds (V) characteristic of the input capacitance Ciss (pF). FIG. 5 is an example of a switching waveform when a circuit configuration example in which a high voltage GaNFET, which is a semiconductor device according to an embodiment of the present invention, is cascode-connected to a low voltage SiMOSFET is applied to a PFC (Power Factor Correction) circuit, and (a) Vds = 440 (V), Ids = 6.2 (A) continuous switching waveform, (b) enlarged view of turn-off waveform, (c) enlarged view of turn-on waveform.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Buffer layer 3 ... Electron transit layer 4 ... Electron supply layer 5 ... Source electrode 6 ... Drain electrode 7 ... Gate electrodes 8, 18 ... Silicon oxide film 9 ... Source field plate (source FP) electrode 10 ... Silicon nitride Film 11 ... Polyimide resin 12 ... Two-dimensional electron gas (2DEG) layer 17 ... Gate field plate (gate FP) electrode 50 ... Source plating electrode 60 ... Drain plating electrode

Claims (11)

A first electrode in Schottky contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer;
A first insulating film formed on the first electrode;
A first portion of a second electrode in low resistance contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer spaced from the first electrode;
Formed via the first electrode and the first insulating film, electrically connected to the first portion of the second electrode and straddling the first electrode when viewed in plan A second portion of the second electrode extending in such a way that
A second insulating film formed on the second portion of the second electrode, and a semiconductor device comprising:
The thickness of the 2nd part of the said 2nd electrode is formed thicker than the thickness of the 1st part of a 2nd electrode, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
The thickness of the 2nd part of the said 2nd electrode is 5 times or more of the thickness of a 2nd insulating film, The semiconductor device characterized by the above-mentioned. A gate electrode having a MIS structure on the nitride compound semiconductor layer via a Schottky contact or an insulating film with the nitride compound semiconductor layer;
A first insulating film formed on the gate electrode;
A first portion of a source electrode in low resistance contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer spaced from the gate electrode;
Formed through the gate electrode and the first insulating film, electrically connected to the first portion of the source electrode, and extended across the gate electrode in plan view. A second portion of the source electrode;
A semiconductor device having a second insulating film formed on the second portion of the source electrode,
The thickness of the 2nd part of the said source electrode is formed thicker than the thickness of the 1st part of the said source electrode, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the thickness of the second portion of the source electrode is at least five times the thickness of the second insulating film. The semiconductor device according to claim 1,
The semiconductor device, wherein the first insulating film is formed of a silicon oxide film. The semiconductor device according to claim 1,
The semiconductor device, wherein the second insulating film is formed by laminating one or both of a silicon nitride film and a polyimide resin film. The semiconductor device according to claim 1,
The nitride compound semiconductor layer has a heterojunction, and a two-dimensional carrier gas layer is generated in the vicinity of the heterojunction surface. The semiconductor device according to claim 3,
The gate electrode is
A first portion of the gate electrode having a MIS structure via a Schottky contact or an insulating film with the nitride-based compound semiconductor layer;
A second portion of the gate electrode provided on the nitride-based compound semiconductor layer via a third insulating film,
The semiconductor device, wherein the second portion of the second electrode is formed so as to straddle the first portion and the second portion of the first electrode when viewed in a plan view. Forming a first portion of a second electrode in low resistance contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer;
Forming a first electrode in Schottky contact with the nitride compound semiconductor layer on the nitride compound semiconductor layer;
Forming a first insulating film formed on substantially the entire surface as viewed from above;
It is electrically connected to the first portion of the second electrode, and is disposed via the first electrode and the first insulating film so as to straddle over the first electrode when viewed from the upper surface side. Forming a second portion of the second electrode formed thicker than the first portion of the second electrode;
Forming a second insulating film formed on substantially the entire surface as viewed from above. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 9,
The nitride compound semiconductor layer has a heterojunction, and has a two-dimensional electron gas layer in the vicinity of the heterointerface. In the manufacturing method of the semiconductor device according to claim 9 or 10,
The method of manufacturing a semiconductor device, wherein the first insulating film is formed of a silicon oxide film, and the second insulating film is formed of a silicon nitride film.

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