JP2013062494A - Nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device with suppressed influence on a current collapse phenomenon due to a drain wiring electrode and with improved withstand voltage.SOLUTION: A nitride semiconductor device includes: a device layer that is composed of a nitride semiconductor; a source electrode and a drain electrode that are disposed spaced apart from each other on the device layer; a gate electrode that is disposed between the source electrode and the drain electrode on the device layer; an interlayer insulating film that is disposed on the device layer; a drain wiring electrode that is disposed facing the device layer via the interlayer insulating film, between the drain electrode and the gate electrode and is electrically connected to the drain electrode; and a field plate that is disposed facing the device layer via the interlayer insulating film on the device layer, between the gate electrode and the drain electrode and is located closer to a low-voltage side than to the drain electrode. The film thickness of the interlayer insulating film at a lower portion of the drain wiring electrode is thicker than that of the interlayer insulating film at a lower portion of the field plate.

Description

  The present invention relates to a nitride semiconductor device having a drain wiring electrode.

A nitride semiconductor device using a nitride semiconductor is used for a high voltage power device or the like. A typical nitride semiconductor is represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), and includes gallium nitride (GaN) and aluminum nitride (AlN). ), Indium nitride (InN), and the like.

  A bias electric field generated when a voltage is applied between the drain electrode and the source electrode of the nitride semiconductor device is concentrated at the end of the gate electrode on the drain electrode side (hereinafter referred to as “drain side end”). By reducing the concentration of the bias electric field at the drain-side end of the gate electrode, the breakdown voltage of the nitride semiconductor device can be improved. For example, there has been proposed a method of reducing electric field concentration at the drain side end of the gate electrode by arranging a field plate (see, for example, Patent Document 1).

JP 2010-278137 A

  The field plate is disposed to face a device layer made of a nitride semiconductor with an interlayer insulating film interposed therebetween, and is electrically connected to, for example, a source electrode, a gate electrode, or a drain electrode. However, since a large current flows through the drain wiring electrode that supplies current to the drain electrode, it is necessary to make the drain wiring electrode wider or thicker. However, considering the drain electrode-gate electrode tolerance, the drain electrode cannot be formed as wide as the drain wiring electrode. For this reason, the drain wiring electrode protrudes outside the drain electrode when viewed in cross section or in plan view. Until now, the current collapse phenomenon in the case where the drain wiring electrode protrudes from the drain electrode has not been sufficiently studied.

  An object of the present invention is to provide a nitride semiconductor device in which the influence on the current collapse phenomenon caused by the drain wiring electrode is suppressed and the breakdown voltage is improved.

  According to one aspect of the present invention, (b) a device layer made of a nitride semiconductor, (b) a source electrode and a drain electrode that are spaced apart from each other on the device layer, and (c) a source electrode and a drain electrode. A gate electrode disposed on the device layer, (d) an interlayer insulating film disposed on the device layer, and (e) a device layer facing the device layer through the interlayer insulating film between the drain electrode and the gate electrode. A drain wiring electrode disposed and electrically connected to the drain electrode; and (f) a drain electrode disposed between the gate electrode and the drain electrode on the device layer with an interlayer insulating film facing the device layer. A nitride semiconductor device having a field plate on the lower potential side and having a thickness of an interlayer insulating film below the drain wiring electrode larger than that of the interlayer insulating film below the field plate is provided. It is.

  ADVANTAGE OF THE INVENTION According to this invention, the influence on the current collapse phenomenon resulting from a drain wiring electrode can be suppressed, and the nitride semiconductor device with improved withstand voltage can be provided.

1 is a schematic cross-sectional view showing the structure of a nitride semiconductor device according to a first embodiment of the present invention. 1 is a schematic plan view showing the structure of a nitride semiconductor device according to a first embodiment of the present invention. It is a graph which shows the relationship between the film thickness of the interlayer insulation film under a drain wiring electrode, and a current collapse phenomenon. It is a graph which shows the relationship between the film thickness of the interlayer insulation film under a field plate, and gate leakage current. FIG. 5 is a schematic cross-sectional view showing the structure of a nitride semiconductor device according to a second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing the structure of a nitride semiconductor device according to a third embodiment of the present invention.

  Next, first to third embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following first to third embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the shape of a component. The structure, arrangement, etc. are not specified below. The embodiment of the present invention can be variously modified within the scope of the claims.

(First embodiment)
As shown in FIG. 1, a nitride semiconductor device 1 according to the first embodiment of the present invention includes a device layer 20 made of a nitride semiconductor, a source electrode 3 disposed on the device layer 20 so as to be separated from each other, and Between the drain electrode 4, the gate electrode 5 disposed on the device layer 20 between the source electrode 3 and the drain electrode 4, the interlayer insulating film 70 disposed on the device layer 20, and between the drain electrode 4 and the gate electrode 5 A drain wiring electrode 8 disposed opposite to the device layer 20 via the interlayer insulating film 70 and electrically connected to the drain electrode 4, and an interlayer insulating film on the device layer 20 between the gate electrode 5 and the drain electrode 4 A field plate 9 on the lower potential side than the drain electrode 4 is provided opposite to the device layer 20 via 70. In the nitride semiconductor device 1, the film thickness T 1 of the interlayer insulating film below the drain wiring electrode 8 is thicker than the film thickness T 2 of the interlayer insulating film below the field plate 9.

  Further, the nitride semiconductor device 1 includes an auxiliary electrode 6 disposed on the device layer 20 between the drain electrode 4 and the gate electrode 5. The field plate 9 is connected to the drain side end portion of the upper portion of the auxiliary electrode 6. The auxiliary electrode 6 is electrically connected to the source electrode 3 by the connection wiring 100.

  The auxiliary electrode 6 controls the curvature of the depletion layer at the drain side end of the gate electrode 5, and the concentration of the bias electric field concentrated at the drain side end of the gate electrode 5 is alleviated. Further, the curvature of the depletion layer at the drain side end of the auxiliary electrode 6 is controlled by the field plate 9, and the concentration of the bias electric field concentrated at the drain side end of the auxiliary electrode 6 is reduced. The drain wiring electrode 8 disposed above the drain electrode 4 is a portion that protrudes more to the gate electrode 5 side than the drain electrode 4 in plan view and directly faces the device layer 20 via the interlayer insulating film 70. Have However, the film thickness T 1 of the interlayer insulating film 70 between the drain wiring electrode 8 and the device layer 20 is larger than the film thickness T 2 of the first interlayer insulating film 71 that is the interlayer insulating film 70 between the field plate 9 and the device layer 20. Also thick enough. For this reason, the drain wiring electrode 8 does not function as a field plate, and does not cause a current collapse phenomenon in the vicinity of the drain electrode 4.

  As shown in FIG. 1, the connection wiring 100 that electrically connects the auxiliary electrode 6 and the source electrode 3 is on the interlayer insulating film 70 and extends to the drain electrode 4 side after passing over the field plate 9. May be. The extending portion 101 of the connection wiring 100 toward the drain electrode 4 side in plan view is opposed to the device layer 20 through the interlayer insulating film 70, but the film thickness T 1 of the interlayer insulating film 70 is below the field plate 9. Since it is sufficiently thicker than the film thickness T2 of the first interlayer insulating film 71, this facing portion does not function as a field plate. Note that a part of the connection wiring 100 may also serve as a part of the source wiring electrode that supplies current to the source electrode 3.

  The auxiliary electrode 6 can also be configured to function as a diode when the potential of the source electrode 3 is higher than the potential of the drain electrode 4, so that a current flows from the source electrode 3 to the drain electrode 4. For example, a Schottky junction is formed between the auxiliary electrode 6 and the device layer 20.

  Further, by electrically connecting the auxiliary electrode 6 to the source electrode 3, the mirror capacitance of the nitride semiconductor device 1 can be reduced. This is because the FET having the auxiliary electrode 6 as the gate electrode and the FET having the gate electrode 5 as the gate electrode are cascode-connected in an equivalent manner. That is, since the auxiliary electrode 6 is disposed between the gate electrode 5 and the drain electrode 4, the capacitance between the gate electrode 5 and the drain electrode 4 is reduced. Thereby, high-frequency operation of the nitride semiconductor device 1 becomes possible.

  In the nitride semiconductor device 1 shown in FIG. 1, the buffer layer 11 is disposed on the substrate 10, and the device layer 20 is disposed on the buffer layer 11. That is, the device layer 20 has a structure in which the carrier supply layer 22 and the carrier traveling layer 21 that forms a heterojunction with the carrier supply layer 22 are stacked. That is, the nitride semiconductor device 1 is a high electron mobility transistor (HEMT) using a nitride semiconductor. A heterojunction surface is formed at the interface between the carrier traveling layer 21 and the carrier supply layer 22 made of nitride semiconductors having different band gap energies, and the carrier traveling layer 21 in the vicinity of the heterojunction surface has a two-dimensional current path (channel). A carrier gas layer 23 is formed.

  FIG. 2 shows a schematic plan view of the drain wiring electrode 8 and the connection wiring 100 of the nitride semiconductor device 1. The drain electrode 4 disposed below the drain wiring electrode 8 is indicated by a broken line. FIG. 1 is a cross-sectional view taken along the II direction of FIG.

  Hereinafter, the influence of the film thickness T1 of the interlayer insulating film 70 below the drain wiring electrode 8 on the current collapse phenomenon will be described with reference to FIG. FIG. 3 shows the relationship between the drain-source voltage Vds and the on-resistance ratio when the film thickness T1 of the interlayer insulating film 70 is changed. The on-resistance ratio is a ratio of the on-resistance RPon to the on-resistance RPon_0 at Vds = 0V. In FIG. 3, characteristics A1 and A2 are characteristics when the film thickness T1 is 0.5 μm and 1.0 μm, respectively.

  FIG. 3 shows that the thicker the film thickness T1, the smaller the on-resistance. That is, in order to alleviate the current collapse phenomenon, it is effective to increase the thickness T1 of the interlayer insulating film 70 below the drain wiring electrode 8.

  Next, the influence of the film thickness T2 of the first interlayer insulating film 71 below the field plate 9 on the breakdown voltage will be described with reference to FIG. FIG. 4 shows the relationship between the drain-source voltage Vds and the gate leakage current ratio when the film thickness T2 of the first interlayer insulating film 71 is changed. The gate leakage current ratio is a ratio of the gate leakage current Ig to the gate leakage current Ig_0 at Vds = 0V. In FIG. 4, characteristics B1, B2, and B3 are characteristics when the film thickness T2 is 700 nm, 500 nm, and 350 nm, respectively.

  FIG. 4 shows that the smaller the film thickness T2, the smaller the gate leakage current. In other words, in order to improve the breakdown voltage of the nitride semiconductor device 1, the first interlayer insulating film 71 below the field plate 9 on the lower potential side than the film thickness T 1 of the interlayer insulating film 70 below the drain wiring electrode 8. It is effective to reduce the film thickness T2.

  As described above, when the film thickness T1 of the interlayer insulating film 70 is reduced, the current collapse phenomenon is deteriorated, leading to an increase in on-resistance. On the other hand, when the film thickness T2 of the first interlayer insulating film 71 is increased, the effect of the field plate is lowered and the breakdown voltage is lowered.

  However, in the nitride semiconductor device 1 shown in FIG. 1, there is no field plate connected to the drain electrode 4, and the film thickness T 1 of the interlayer insulating film below the drain wiring electrode 8 is the same as that of the interlayer insulating film below the field plate 9. Thicker than film thickness T2. That is, the thickness T1 of the interlayer insulating film 70 is increased so that the field plate is not provided on the high potential side and the field plate is provided on the low potential side between the drain electrode 4 and the gate electrode 5, and the first interlayer insulating film is formed. The film thickness T2 of 71 is reduced. As a result, by increasing the thickness T1 of the interlayer insulating film 70, the deterioration of the current collapse phenomenon caused by the drain wiring electrode 8 is suppressed, while reducing the thickness T2 of the first interlayer insulating film 71. It is suppressed that the effect of relaxing the electric field concentration by the field plate 9 is lowered.

  In order to suppress the deterioration of the current collapse phenomenon, the film thickness T1 of the interlayer insulating film 70 below the drain wiring electrode 8 is preferably, for example, about 500 nm to 1 μm, and more preferably 1 μm or more. However, if the film thickness T1 is excessively increased, the through electrode connecting the drain wiring electrode 8 and the drain electrode 4 cannot be formed well so as not to have a void. For this reason, the film thickness T1 is preferably 2 μm or less.

  On the other hand, in order to suppress a reduction in the effect of relaxing the electric field concentration by the field plate 9 on the lower potential side compared to the drain electrode 4, the film thickness T2 of the first interlayer insulating film 71 below the field plate 9 is: For example, it is preferably 500 nm or less, more preferably about 100 nm to 300 nm.

  As described above, in the nitride semiconductor device 1 according to the first embodiment of the present invention, the film thickness T1 of the interlayer insulating film below the drain wiring electrode 8 is set to the film thickness of the interlayer insulating film below the field plate 9. By making it thicker than T2, even if the drain wiring electrode 8 is made relatively wide or thick, the concentration of the bias electric field at the drain side end of the gate electrode 5 is alleviated and an increase in on-resistance during operation is suppressed. The That is, according to the nitride semiconductor device 1 shown in FIG. 1, even if the drain wiring electrode 8 is made relatively wide or thick, deterioration of the current collapse phenomenon caused by the field plate is suppressed and the breakdown voltage is improved. A nitride semiconductor device can be provided.

  A specific configuration example of the nitride semiconductor device 1 is shown below.

  As the substrate 10, a semiconductor substrate such as a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a GaN substrate, or an insulator substrate such as a sapphire substrate or a ceramic substrate can be employed. For example, the manufacturing cost of the nitride semiconductor device 1 can be reduced by adopting a silicon substrate that can be easily increased in diameter as the substrate 10.

  The buffer layer 11 can be formed by an epitaxial growth method such as a metal organic chemical vapor deposition (MOCVD) method. Although the buffer layer 11 is illustrated as one layer in FIG. 1, the buffer layer 11 may be formed of a plurality of layers. For example, a multilayer buffer in which the buffer layer 11 is formed by alternately stacking first sublayers (first sublayers) made of aluminum nitride (AlN) and second sublayers (second sublayers) made of GaN. It is good. Since the buffer layer 11 is not directly related to the operation of the HEMT, the buffer layer 11 may be omitted.

  The carrier traveling layer 21 disposed on the buffer layer 11 is formed by, for example, epitaxially growing non-doped GaN to which no impurity is added by the MOCVD method or the like. Here, non-doped means that no impurity is intentionally added.

The carrier supply layer 22 disposed on the carrier traveling layer 21 is made of a nitride semiconductor having a band gap larger than that of the carrier traveling layer 21 and a lattice constant smaller than that of the carrier traveling layer 21. Undoped Al _x Ga _1-x N can be adopted as the carrier supply layer 22.

  The carrier supply layer 22 is formed on the carrier traveling layer 21 by epitaxial growth using MOCVD or the like. Since the carrier supply layer 22 and the carrier traveling layer 21 have different lattice constants, piezoelectric polarization due to lattice distortion occurs. Due to the piezoelectric polarization and the spontaneous polarization of the crystal of the carrier supply layer 22, high-density carriers are generated in the carrier traveling layer 21 near the heterojunction, and a two-dimensional carrier gas layer 23 as a current path (channel) is formed.

  A source electrode 3 and a drain electrode 4 are formed on the device layer 20. The source electrode 3 and the drain electrode 4 are formed of a metal capable of low resistance contact (ohmic contact) with the device layer 20. For example, aluminum (Al), titanium (Ti), or the like can be used for the source electrode 3 and the drain electrode 4. Alternatively, the source electrode 3 and the drain electrode 4 are formed as a laminate of Ti and Al.

  After the source electrode 3 and the drain electrode 4 are formed, a first interlayer insulating film 71 is formed on the device layer 20. The first interlayer insulating film 71 is, for example, a silicon nitride (SiN) film having a thickness of about 100 nm to 500 nm. The film thickness of the first interlayer insulating film 71 is the film thickness T1.

  An opening is formed in the first interlayer insulating film 71, and the gate electrode 5 and the auxiliary electrode 6 are formed so as to fill the opening. At this time, the drain side end connected to the gate electrode 5 is patterned by patterning the metal film constituting the gate electrode 5 and the auxiliary electrode 6 so as to be larger than the area of the opening formed in the first interlayer insulating film 71. The field plate 9 connected to the portion 51 and the auxiliary electrode 6 can be formed. For the gate electrode 5 and the auxiliary electrode 6, for example, nickel gold (NiAu) can be used. Thus, the auxiliary electrode 6 can employ the same structure as the gate electrode 5. Note that the gate electrode 5 and the auxiliary electrode 6 may be formed in different steps.

A second interlayer insulating film 72 is formed on the first interlayer insulating film 71 so as to fill the gate electrode 5, the auxiliary electrode 6, and the field plate 9. The second interlayer insulating film 72 is made of a silicon oxide (SiOx) film, SiN film, aluminum oxide (Al ₂ O ₃ ) film, etc., which is thicker than the first interlayer insulating film 71 and has a film thickness of about 500 nm to 1500 nm. Is possible. Note that the total thickness of the first interlayer insulating film 71 and the second interlayer insulating film 72 is the film thickness T2.

  A predetermined position of the interlayer insulating film 70 where the first interlayer insulating film 71 and the second interlayer insulating film 72 are stacked, that is, the source electrode 3, the drain electrode 4, and the auxiliary electrode 6 are formed by using a photolithography technique or the like. Openings are selectively formed at the respective positions. A connection wiring 100 that connects the source electrode 3 and the auxiliary electrode 6 is formed so as to embed an opening formed above the source electrode 3 and the auxiliary electrode 6. Further, the drain wiring electrode 8 connected to the drain electrode 4 is formed so as to fill the opening formed above the drain electrode 4. For the connection wiring 100 and the drain wiring electrode 8, Au plating, Al, or the like can be adopted.

  For example, the nitride semiconductor device 1 according to the first embodiment can be manufactured as described above. However, the manufacturing method described above is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification.

(Second Embodiment)
The nitride semiconductor device 1 according to the second embodiment of the present invention is different from FIG. 1 in that the auxiliary electrode 6 is not provided as shown in FIG. In the nitride semiconductor device 1 shown in FIG. 5, the field plate 9 is connected to the drain side end portion of the upper portion of the gate electrode 5. That is, the field plate 9 is electrically connected to the gate electrode 5. Other configurations are the same as those of the first embodiment shown in FIG.

  Also in the nitride semiconductor device 1 according to the second embodiment, the film thickness T2 of the interlayer insulating film below the field plate 9 connected to the gate electrode 5 is made larger than the film thickness T1 of the interlayer insulating film below the drain wiring electrode 8. By reducing the thickness, the current collapse phenomenon is suppressed and the breakdown voltage is improved even if the drain wiring electrode 8 is wide as in the first embodiment. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

(Third embodiment)
As shown in FIG. 6, the nitride semiconductor device 1 according to the third embodiment of the present invention does not include the auxiliary electrode 6, and the field plate 9 electrically connected to the source electrode 3 includes the gate electrode 5 and the drain. It is different from FIG. 1 that it is arranged between the electrodes 4. Other configurations are the same as those of the first embodiment shown in FIG.

  The field plate 9 on the lower potential side than the drain electrode 4 of the nitride semiconductor device 1 shown in FIG. 6 is disposed to face the device layer 20 via the first interlayer insulating film 71 having a film thickness T2. Unlike the auxiliary electrode 6, it is not in contact with the device layer 20. The source electrode 3 and the field plate 9 are connected by a connection wiring 100 disposed on the interlayer insulating film 70. The field plate 9 shown in FIG. 6 is formed on the first interlayer insulating film 71 in the step of forming the gate electrode 5, for example, in the same manner as the drain-side end portion 51 that functions as the gate field plate.

  Also in the nitride semiconductor device 1 according to the third embodiment, by making the film thickness T1 of the interlayer insulating film below the drain wiring electrode 8 thicker than the film thickness T2 of the interlayer insulating film below the field plate 9, current The collapse phenomenon is suppressed and the breakdown voltage is improved.

  Note that the mirror capacitance of nitride semiconductor device 1 is reduced by electrically connecting field plate 9 to source electrode 3. That is, the capacitance between the gate electrode 5 and the drain electrode 4 is reduced by disposing the field plate 9 having the same potential as that of the source electrode 3 between the gate electrode 5 and the drain electrode 4. Thereby, high-frequency operation of the nitride semiconductor device 1 becomes possible.

  Others are substantially the same as those in the first embodiment, and redundant description is omitted.

(Other embodiments)
As described above, the present invention has been described according to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the first to third embodiments, the nitride semiconductor device 1 is an HEMT. However, the nitride semiconductor device 1 has another structure such as a field effect transistor (FET) using a nitride semiconductor. It may be a transistor.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... Nitride semiconductor device 3 ... Source electrode 4 ... Drain electrode 5 ... Gate electrode 6 ... Auxiliary electrode 8 ... Drain wiring electrode 9 ... Field plate 10 ... Substrate 11 ... Buffer layer 20 ... Device layer 21 ... Carrier running layer 22 ... Carrier Supply layer 23 ... Two-dimensional carrier gas layer 70 ... Interlayer insulating film 71 ... First interlayer insulating film 72 ... Second interlayer insulating film 100 ... Connection wiring

Claims (5)

A device layer made of a nitride semiconductor;
A source electrode and a drain electrode that are spaced apart from each other on the device layer;
A gate electrode disposed on the device layer between the source electrode and the drain electrode;
An interlayer insulating film disposed on the device layer;
A drain wiring electrode disposed between the drain electrode and the gate electrode so as to face the device layer via the interlayer insulating film, and electrically connected to the drain electrode;
A field plate on the lower potential side compared to the drain electrode, disposed on the device layer between the gate electrode and the drain electrode with the interlayer insulating film interposed therebetween, and having a lower potential side than the drain electrode; The nitride semiconductor device, wherein a film thickness of the interlayer insulating film below the wiring electrode is larger than a film thickness of the interlayer insulating film below the field plate.   The nitride semiconductor device according to claim 1, wherein the drain wiring electrode is wider than the drain electrode in plan view. An auxiliary electrode disposed on the device layer between the drain electrode and the gate electrode;
3. The nitride semiconductor device according to claim 1, wherein the field plate is connected to a drain side end portion of the upper portion of the auxiliary electrode.   The nitride semiconductor device according to claim 3, wherein the auxiliary electrode is electrically connected to the source electrode.   The nitride semiconductor device according to claim 1, wherein the field plate is electrically connected to the source electrode or the gate electrode.

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