JP2008235963A - Operational amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the slew rate of an operational amplifier, using few additional circuits. <P>SOLUTION: In the double differential type operational amplifier provided with a first differential input circuit comprising transistors Q1 and Q2 and a current source I1, a second differential input circuit comprising of transistors Q2 and Q4 and a current source I2, a first current mirror circuit comprising transistors Q5-Q7, a second current mirror circuit composed of transistors Q8-Q10, and a capacitor Cc, transistors QA1-QA4 are additionally connected; and when an input differential voltage ΔVIN in between a normal input terminal IN+ and an inversion input terminal IN- becomes 2V<SB>BE</SB>, the transistors QA1 and QA4 or QA2 and QA3 are turned on, and a current for charging or discharging the capacitor Cc is increased. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an operational amplifier that realizes a high slew rate when a high-level pulse signal is input.

  FIG. 6 shows a configuration of a conventional dual differential input type operational amplifier 20. Q1, Q2, Q8, Q9, Q10 are NPN transistors, Q3, Q4, Q5, Q6, Q7 are PNP transistors, R1, R2, R3, R4 are resistors, Cc is a capacitor, I1, I2 are current sources (current value I1 = I2), D1, D2, D3, D4 are diodes, and X1 is a buffer. V + and V− are a first power supply and a second power supply, IN + is a normal input terminal, IN− is an inverting input terminal, and OUT is an output terminal.

  As shown in FIG. 2, the operational amplifier 20 is connected to the inverting input terminal IN− to the output terminal OUT to form a voltage follower circuit, and between the low voltage VL and the high voltage VH is connected to the normal input terminal IN +. The operation when the pulse signal S1 that changes in (1) is input will be described.

  Initially, when the pulse signal S1 is at a low voltage VL, both input terminals IN + and IN- are at the same voltage (= VL). Next, when the high voltage VH is applied to the normal input terminal IN + with an arbitrary slope, the transistors Q2 and Q3 are turned on, the transistors Q1 and Q4 are turned off, and the current I1 of the current source I1 is changed to that of the transistor Q2. The current I2 of the current source I2 flows to the collector of the transistor Q3. Therefore, since the current I1 flows through the transistors Q5 to Q7 constituting the current mirror circuit and no current flows through the transistors Q8 to Q10 constituting the current mirror circuit, the current I1 is charged in the capacitor Cc, and the voltage Vp is The voltage VOUT (= −VIN) at the output terminal OUT also rises. When VIN + = VIN− = VH, charging is completed. FIG. 3 shows the waveforms of the voltages VIN + and VOUT (= −VIN) at this time, and FIG. 4 shows the waveform of the current I1.

  When the pulse signal S1 changes from the high voltage VH to the low voltage VL, a current I2 flows through the transistors Q8 to Q10, and this current I2 becomes a discharge current of the capacitor Cc, the voltage Vp decreases, and the output terminal The voltage VOUT (= −VIN) of OUT also decreases.

During the above transition, the change in the output voltage VOUT (= −VIN) has a slope, and the slew rate SR is defined by the following equation in which the current I1 charges the capacitor Cc or the current I2 discharges the charge in the capacitor Cc. Is done.
SR = I1 / Cc
= I2 / Cc (1)

  That is, in the circuit of the operational amplifier 20 of the conventional example shown in FIG. 6, there is a problem that the pulse response speed is limited by the slew rate defined by the current I1, as shown by the equation (1).

On the other hand, Patent Document 1 proposes a slew rate increasing circuit. This slew rate increasing circuit increases the operating current of the operational amplifier when the differential input voltage becomes greater than a certain value.
JP-A-6-112737

  However, the circuit described in Patent Document 1 has a problem in that the slew rate increasing circuit is configured as another circuit for the original operational amplifier, requiring a large number of circuit elements and complicating the circuit configuration. .

  An object of the present invention is to provide an operational amplifier capable of increasing the slew rate with a small number of additional circuits.

To achieve the above object, according to a first aspect of the present invention, there is provided a first and a first polarity having a first polarity in which a base is connected to the normal input terminal and the inverting input terminal, respectively, and an emitter is connected to the first current source. A first differential input circuit composed of two transistors; a third polarity and a second polarity; a base connected to the normal input terminal and the inverting input terminal; and an emitter connected to a second current source. A second differential input circuit comprising four transistors, and a collector current of the second transistor connected to the normal input terminal of the first differential input circuit, or the second differential input circuit. A first current mirror circuit that mirrors and outputs the collector current of the third transistor connected to the inverting input terminal, and the non-inverting input terminal of the second differential input circuit. 4th tiger A second current mirror circuit that mirrors and outputs a collector current of a transistor or a collector current of the first transistor connected to the inverting input terminal of the first differential input circuit; and the first current The output current of the mirror circuit is supplied as the discharge current, the output current of the second current mirror circuit is supplied as the sink current, and the voltage of the normal input terminal is higher than the voltage of the inverting input terminal by a predetermined amount or more. The discharge current adding circuit for increasing the output current of the first current mirror circuit, and the second current mirror circuit when the voltage of the non-inverting input terminal is lower than the voltage of the inverting input terminal by a predetermined value or more. And a sink current adding circuit for increasing the output current of the circuit.
According to a second aspect of the present invention, in the first aspect of the present invention, the discharge current adding circuit includes a fifth transistor of a first polarity having a base commonly connected to the second transistor, and the third transistor. And a sixth transistor having a second polarity, the emitter of which is connected to the emitter of the fifth transistor, and the collector current of the fifth or sixth transistor is the first transistor. The sink current adding circuit is added as a reference side current of a current mirror circuit, and the sink current adding circuit has a common base to the fourth transistor and a seventh transistor of the first polarity whose base is commonly connected to the first transistor. And an eighth transistor having a second polarity and having an emitter connected to the emitter of the seventh transistor. The collector current is added as a reference side current of the second current mirror circuit, characterized in that.
The invention according to claim 3 is the invention according to claim 1 or 2, wherein each of the transistors is replaced with a field effect transistor, the base is replaced with a gate, the collector is replaced with a drain, and the emitter is replaced with a source. Features.

According to the present invention, a simple circuit, for example, only four transistors are added to a dual differential input type operational amplifier, and when the input differential voltage becomes higher than a predetermined value, for example, 2V _BE, Since the rate increases, an increase in the slew rate can be realized with respect to an input of a predetermined level or more with a few additional circuits, and a high-speed operation can be achieved. When the input differential voltage is less than a predetermined value, the operation is the same as in the prior art, and the current consumption does not increase.

  FIG. 1 is a circuit diagram showing the configuration of a dual differential input operational amplifier 10 according to an embodiment of the present invention. Q1, Q2, Q8, Q9, Q10, QA1, QA2 are NPN transistors, Q3, Q4, Q5, Q6, Q7, QA3, QA4 are PNP transistors, R1, R2, R3, R4 are resistors, Cc is a capacitor, I1, I2 is a current source (current value I1 = I2), D1, D2, D3, and D4 are diodes, and X1 is a buffer. V + and V− are a first power supply and a second power supply, IN + is a normal input terminal, IN− is an inverting input terminal, and OUT is an output terminal.

  In relation to the claims, the transistors Q1 and Q2 and the current source I1 constitute a first differential input circuit, and the transistors Q3 and Q4 and the current source I2 constitute a second differential input circuit. The transistors Q5 to Q7 constitute a Wilson-type first current mirror circuit (mirror ratio = 1), and the transistors Q8 to Q10 constitute a Wilson-type second current mirror circuit (mirror ratio = 1). Transistors QA2, QA3, QA1, and QA4 constitute fifth, sixth, seventh, and eighth transistors, respectively.

  In the operational amplifier 10 of this embodiment, transistors QA1 to QA4 are additionally connected to the operational amplifier 20 of FIG. The emitters of the transistors QA1 and QA4 are commonly connected, and the emitters of the transistors QA2 and QA3 are commonly connected. The bases of the transistors QA1 and QA3 are connected to the inverting input terminal IN−, and the bases of the transistors QA2 and QA4 are connected to the normal input terminal IN +. The collector of the transistor QA1 is connected to the power supply V +, the collector of the transistor QA2 is connected to the collector of the transistor Q2, the collector of the transistor QA3 is connected to the power supply V-, and the collector of the transistor QA4 is connected to the collector of the transistor Q4.

  As shown in FIG. 2, the operational amplifier 10 has a voltage follower circuit by connecting the inverting input terminal IN− to the output terminal OUT, and the low voltage VL and the high voltage VH are connected to the non-inverting input terminal IN +. The operation when the pulse signal S1 changing between the two is input will be described.

  Initially, when the pulse signal S1 is at a low voltage VL, both input terminals IN + and IN- are at the same voltage (= VL). Next, when the high voltage VH is applied to the normal input terminal IN + with an arbitrary slope, the transistors Q2 and Q3 are turned on, the transistors Q1 and Q4 are turned off, and the current I1 of the current source I1 is the collector of the transistor Q2. The current I2 of the current source I2 flows to the collector of the transistor Q3. Therefore, a current I1 flows through the transistors Q5 to Q7 of the first current mirror circuit, and this current I1 becomes a discharge current and is supplied to the capacitor Cc, so that the voltage Vp rises and the voltage VOUT (= −VIN) of the output terminal OUT. ) Will also rise.

The input differential voltage ΔVIN between the input terminal IN + and the input terminal IN− is
ΔVIN ≧ V _BEQA2 + V _BEQA3 = 2V _BE (2)
Then, the transistors QA2 and QA3 are turned on. V _BEQA2 and V _BEQA3 are base-emitter voltages of the transistors QA2 and QA3. At this time, the current I _CQA2 flowing through the collector of the transistor QA2 is
I _CQA2 = I _SQA2 exp (ΔVIN / 2) / V _T (3)
It is. I _SQA2 is a saturation current of the transistor QA2, and V _T is a thermal voltage (= kT / q). The same current also flows through the collector of transistor QA3.

From the above, since I _CQA2 is added as the reference-side current to the first current mirror circuit (transistors Q5 to Q7), the collector current of the transistor Q7 becomes “I1 + I _CQA2 ” and increases by the current I _CQA2 . Therefore, the slew rate at this time is
SR = (I1 + I _CQA2 ) / Cc (4)
_Therefore , it is higher by I _CQA2 / Cc than the slew rate of the above-described equation (1). The input differential voltage ΔVIN between the input terminal IN + and the input terminal IN− is
ΔVIN <V _BEQA2 + V _BEQA3 = 2V _BE (5)
Then, the transistor transistors QA2 and QA3 are turned off, the slew rate SR returns to the value shown in the equation (1), and when VIN + = VIN− = VH, the charging is completed.

As described above, the operational amplifier 10 of this embodiment performs high-speed operation because the charging current of the capacitor Cc increases when the input differential voltage ΔVIN becomes 2V _BE or more. The total amount of current flowing during normal operation when the transistors QA2 and QA3 are not turned on is exactly the same as the total amount of current flowing during operation of the operational amplifier 20 shown in FIG. That is, when performing a pulse operation or an analog operation of a small amplitude signal, it operates stably in exactly the same way as the operational amplifier 20 shown in FIG.

  FIG. 3 shows the response waveforms of the input and output voltages of the operational amplifiers 10 and 20 in FIGS. 1 and 6 when the pulse signal S1 changes from the low voltage VL to the high voltage VH, and FIG. 4 shows the current supplied to the capacitor Cc. Showed changes. 3, the input voltage VIN + is indicated by a dotted line, the output voltage VOUT of the operational amplifier 10 in FIG. 1 is indicated by a solid line, and the output voltage VOUT of the operational amplifier 20 in FIG. 6 is indicated by a broken line. 4, the current supplied to the capacitor Cc of the operational amplifier 10 in FIG. 1 is indicated by a solid line, and the current supplied to the capacitor Cc of the operational amplifier 20 in FIG. 6 is indicated by a broken line.

In the operational amplifier 10 of this embodiment, the charging current of the capacitor Cc is zero when the input voltage VIN + is the low voltage VL, but starts to increase when the input voltage VIN + rises toward the high voltage VH at time t1. Current I1. Further, at time t2, when the input differential voltage ΔVIN reaches 2V _BE , the transistors QA2 and QA3 are turned on, the charging current of the capacitor Cc increases to “I1 + I _CQA2 ”, and the output voltage VOUT becomes the high voltage VH. When the input differential voltage ΔVIN becomes less than 2V _{BE at} time t3, the transistors QA2 and QA3 are turned off and returned to the current I1. At time t4 thereafter, the input differential voltage ΔVIN becomes zero. The charging current returns to zero. Note that when the input voltage VIN + falls toward the low voltage VL, this time, the operation is the reverse of the above, and the charge of the capacitor Cc is discharged. At this time, the transistors QA1 and QA4 are temporarily turned on halfway, increasing the sink current and temporarily increasing the discharge current of the capacitor Cc.

  FIG. 5 shows a simulation result of response characteristics of the operational amplifiers 10 and 20 when the voltage follower connection is made as shown in FIG. (a) is about the operational amplifier 10 of this embodiment of FIG. 1, and (b) is about the conventional operational amplifier 20 of FIG. In either case, the operational amplifiers 10 and 20 have the voltage amplification degree Gv = 1, the resistance RT = 50Ω, the resistance RL = 150Ω, and the capacitor CL = 10 pF. It can be confirmed that the response characteristic of (a) shows a higher speed response than that of (b).

  The operational amplifier 10 of the embodiment described above is an example of the present invention, and various modifications can be made. For example, in FIG. 1, the reference side current of the first current mirror circuit (transistors Q5 to Q7) that supplies the discharge current is the collector current of the transistor Q2, but the collector current of the transistor Q3 may be the reference side current. In FIG. 1, the reference current of the second current mirror circuit (transistors Q8 to Q10) that supplies the sink current is the collector current of the transistor Q4, but the collector current of the transistor Q1 may be the reference current. Further, in FIG. 1, the collector current of the transistor QA2 is used as the additional reference side current of the first current mirror circuit (transistors Q5 to Q7), but the collector current of the transistor QA3 may be used as the additional reference side current. Further, in FIG. 1, the collector current of the transistor QA4 is used as the additional reference side current of the second current mirror circuit (transistors Q8 to Q10), but the collector current of the transistor QA1 may be used as the additional reference side current. Furthermore, it is needless to say that the polarities (PNP, NPN) of the bipolar transistor shown in FIG. 1 can be reversed. Further, a field effect transistor can be used instead of the bipolar transistor.

1 is a circuit diagram of an operational amplifier according to one embodiment of the present invention. It is the circuit diagram which comprised the operational amplifier of a present Example and the prior art example as a voltage follower. FIG. 3 is a response characteristic diagram when the operational amplifiers of the present example and the conventional example are operated by the voltage follower of FIG. 2. FIG. 3 is a characteristic diagram of current flowing in a capacitor Cc when the operational amplifiers of the present example and the conventional example are operated by the voltage follower of FIG. 2. It is a response characteristic figure of the simulation result of the operational amplifier of a present Example and a prior art example. It is a circuit diagram of an operational amplifier of a conventional example.

Explanation of symbols

  10, 20: operational amplifier

Claims (3)

A first differential input circuit comprising first and second transistors having a first polarity, each having a base connected to a normal input terminal and an inverting input terminal and an emitter connected to a first current source;
A second differential input circuit comprising third and fourth transistors of second polarity, each having a base connected to the normal input terminal and the inverting input terminal and an emitter connected to a second current source;
The collector current of the second transistor connected to the normal input terminal of the first differential input circuit, or the third transistor connected to the inverted input terminal of the second differential input circuit A first current mirror circuit that mirrors and outputs the collector current of
The collector current of the fourth transistor connected to the normal input terminal of the second differential input circuit, or the first transistor connected to the inverted input terminal of the first differential input circuit A second current mirror circuit that mirrors and outputs the collector current of
A capacitor in which an output current of the first current mirror circuit is supplied as a discharge current, and an output current of the second current mirror circuit is supplied as a sink current;
A discharge current adding circuit for increasing the output current of the first current mirror circuit when the voltage of the normal input terminal is higher than the voltage of the inverting input terminal by a predetermined value or more;
A sink current adding circuit for increasing the output current of the second current mirror circuit when the voltage of the normal input terminal is lower than the voltage of the inverting input terminal by a predetermined value or more;
An operational amplifier comprising: The discharge current adding circuit includes a fifth transistor having a first polarity whose base is commonly connected to the second transistor, and a base commonly connected to the third transistor and an emitter being an emitter of the fifth transistor. And a collector current of the fifth or sixth transistor is added as a reference side current of the first current mirror circuit,
The sink current adding circuit includes a first polarity seventh transistor having a base commonly connected to the first transistor, and a base commonly connected to the fourth transistor and an emitter being an emitter of the seventh transistor. And the seventh or eighth collector current is added as a reference side current of the second current mirror circuit.
The operational amplifier according to claim 1.   3. The operational amplifier according to claim 1, wherein each of the transistors is replaced with a field effect transistor, the base is replaced with a gate, the collector is replaced with a drain, and the emitter is replaced with a source.

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