JP2008235543A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology which enables stable normally-off operation in a semiconductor device employing hetero-junction surface for a channel. <P>SOLUTION: The semiconductor device is equipped with a nitride semiconductor crystal and a gate electrode opposed to the upper side surface of the nitride semiconductor crystal through an insulating layer. The semiconductor crystal is provided with a first layer constituted of a first kind of a nitride semiconductor and a second layer, laminated on the first layer and constituted of a second kind of a nitride semiconductor. The hetero-junction surface, formed on a boundary between the first layer and the second layer, is positioned on a crystalline plane orthogonal to a (0001) crystalline plane. In the first layer, p-type semiconductor region, containing p-type impurities, is formed at a position opposed to at least one part of the gate electrode through the hetero-junction surface. In this case, the side boundary surface of the p-type semiconductor region is formed on a crystalline plane, orthogonal to the hetero-junction surface and forming an angle between the (0001) crystalline plane. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a nitride semiconductor crystal.

  Patent Document 1 discloses a semiconductor device using a nitride semiconductor crystal. This semiconductor device has a nitride semiconductor crystal and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer. The nitride semiconductor crystal includes a first layer composed of a first type nitride semiconductor (gallium nitride) and a second type nitride semiconductor (gallium nitride / aluminum) laminated on the upper side of the first layer. It has the 2nd layer comprised by these. Since the first layer and the second layer have different band gaps, the interface between them is a heterojunction surface. A gate electrode is opposed to a part of the heterojunction surface between the first layer and the second layer from one side. The semiconductor device of Patent Document 1 is a lateral field effect transistor that uses a heterojunction plane as a channel, and is called a so-called heterojunction field effect transistor.

In a heterojunction field effect transistor, when a heterojunction plane serving as a channel is formed on a (0001) crystal plane, a high-density two-dimensional electron gas layer is formed on the heterojunction plane due to the generation of an internal electric field due to spontaneous polarization and piezoelectric polarization. Is formed. When a high-density two-dimensional electron gas layer is formed on the heterojunction surface, even when no voltage is applied to the gate electrode, the heterojunction surface is in a state where a large number of electrons can travel. Therefore, a semiconductor device in which a heterojunction plane serving as a channel is formed on a (0001) crystal plane exhibits normally-on behavior.
On the other hand, in the semiconductor device of Patent Document 1, a heterojunction surface to be a channel is formed on the (11-20) crystal plane. The (11-20) crystal plane is a nonpolar plane whose polarity does not change in the thickness direction. Therefore, spontaneous polarization and piezo polarization perpendicular to the heterojunction surface formed on the (11-20) crystal plane do not occur, and the density of the two-dimensional electron gas layer is relatively low. As a result, in the state where no voltage is applied to the gate electrode, the traveling of electrons on the heterojunction surface is suppressed. According to Patent Document 1, the threshold voltage rises to −0.4 V, and almost normally-off operation characteristics can be obtained.

  Here, “-” added before “2” in the notation of (11-20) generally indicates “bar” to be added to the upper part of “2”. In the specification and claims of the present application, the crystal plane and the crystal axis are indicated in the same manner. Unless otherwise specified, for example, the notation (10-10) crystal plane includes a (10-10) crystal plane and an equivalent crystal plane. Similarly, for example, the expression <10-10> crystal axis includes a <10-10> crystal axis and an equivalent crystal axis.

JP 2006-324465 A

The semiconductor device of Patent Document 1 still has a negative threshold voltage, which is insufficient for realizing a stable normally-off operation. In order to realize a stable normally-off operation, it is necessary to more strongly inhibit the traveling of electrons on the heterojunction surface without applying a voltage to the gate electrode.
The present invention solves the above problems. The present invention provides a technique that enables a stable normally-off operation in a semiconductor device using a heterojunction plane as a channel.

A semiconductor device embodied by the present invention includes a nitride semiconductor crystal and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer. The nitride semiconductor crystal includes a first layer composed of a first type of nitride semiconductor and a second layer composed of a second type of nitride semiconductor and stacked above the first layer. I have. The heterojunction plane formed at the boundary between the first layer and the second layer is located on a crystal plane perpendicular to the (0001) crystal plane. In the first layer, a p-type semiconductor region containing a p-type impurity is formed at a position facing at least a part of the gate electrode through the heterojunction surface. The lateral boundary surface of the p-type semiconductor region is formed on a crystal plane that is perpendicular to the heterojunction plane and forms an angle with the (0001) crystal plane.
Here, the upper surface of the nitride semiconductor crystal is not intended to be a surface positioned vertically upward, but is defined for the sake of convenience in order to clarify the positional relationship of each component of the semiconductor device. In the present specification and claims, of the plurality of surfaces of the nitride semiconductor crystal, the surface on which the gate electrode is disposed is defined as the upper surface, and the surface facing the upper surface is defined as the lower surface. A direction from the lower surface to the upper surface is expressed as upward, a direction from the upper surface to the lower surface is expressed as downward, and a direction parallel to the upper surface and the lower surface is expressed as side.

In this semiconductor device, a heterojunction plane that becomes a channel is formed on a crystal plane perpendicular to the (0001) crystal plane. The crystal plane perpendicular to the (0001) crystal plane is a nonpolar plane whose polarity does not change in the thickness direction. Therefore, in the heterojunction plane formed on the crystal plane perpendicular to the (0001) crystal plane, spontaneous polarization and piezopolarization do not occur in the direction perpendicular to the heterojunction plane, and the density of the two-dimensional electron gas layer is Relatively low.
In addition to the above, in this semiconductor device, a p-type semiconductor region containing a p-type impurity is opposed to a heterojunction surface serving as a channel. Thereby, in the state where no voltage is applied to the gate electrode, the formation of the two-dimensional electron gas layer at the heterojunction surface is suppressed by the depletion layer extending from the p-type semiconductor region.
As described above, in the state where no voltage is applied to the gate electrode, the formation of the two-dimensional electron gas layer on the heterojunction surface is sufficiently suppressed, and the traveling of electrons on the heterojunction surface can be prohibited. This semiconductor device can perform a stable normally-off operation.

  The semiconductor device described above requires a nitride semiconductor crystal including a p-type semiconductor region. Such a nitride semiconductor crystal can be manufactured by utilizing crystal growth. When growing a nitride semiconductor crystal, it is difficult to grow a homogeneous crystal if the surface on which the crystal is grown contains a (0001) crystal plane. In contrast, in the semiconductor device described above, the lateral boundary surface of the p-type semiconductor region is formed on a crystal plane that is perpendicular to the heterojunction plane and forms an angle with the (0001) crystal plane. Thereby, when manufacturing using crystal growth, crystal growth from the (0001) crystal plane is not required, and a more uniform crystal can be easily grown. Since it has a structure in which homogeneous crystals can be easily obtained, there is little production quality fluctuation, and stable normally-off operation can be expected.

In the above semiconductor device, the heterojunction plane is preferably located on the (1-210) crystal plane. In this case, the lateral boundary surface of the p-type semiconductor region is preferably formed on the (10-10) crystal plane or the (10-12) crystal plane.
The (1-210) crystal plane is a crystal plane perpendicular to the (0001) crystal plane. The (10-10) crystal plane and the (10-12) crystal plane are crystal planes that are perpendicular to the (1-210) crystal plane and form an angle with the (0001) crystal plane. Since the heterojunction plane and the lateral boundary surface of the p-type semiconductor region are located on these crystal planes, the semiconductor device can realize a stable normally-off operation.

In the above semiconductor device, the p-type semiconductor region is preferably a hexagonal column-shaped region. In this case, it is preferable that the six side boundary surfaces are formed on the (10-10) crystal plane or the (10-12) crystal plane.
When the p-type semiconductor region is a hexagonal column-shaped region, the p-type semiconductor region can be effectively arranged in the nitride semiconductor crystal. When the p-type semiconductor region is a hexagonal column-shaped region, the six lateral boundary surfaces are formed on the (10-10) crystal plane or the (10-12) crystal plane, thereby stabilizing the semiconductor device. The normally-off operation can be realized.

Alternatively, in the above semiconductor device, it is also preferable that the heterojunction plane is located on a (10-10) crystal plane. In this case, the lateral boundary surface of the p-type semiconductor region is preferably formed on the (1-210) crystal plane or the (1-212) crystal plane.
The (10-10) crystal plane is a crystal plane perpendicular to the (0001) crystal plane. The (1-210) crystal plane and the (1-212) crystal plane are crystal planes that are perpendicular to the (10-10) crystal plane and form an angle with the (0001) crystal plane. Since the heterojunction plane and the lateral boundary surface of the p-type semiconductor region are located on these crystal planes, the semiconductor device can realize a stable normally-off operation.
Also in this semiconductor device, the p-type semiconductor region can be a hexagonal column-shaped region. In this case, it is preferable to form the six side boundary surfaces on the (1-210) crystal plane or the (1-212) crystal plane.

In the above-described nitride semiconductor device, it is preferable that the first type nitride semiconductor is gallium nitride and the second type nitride semiconductor is gallium nitride / aluminum.
With a combination of these materials, a heterojunction surface suitable for the channel is formed due to an appropriate band gap difference.

  The technology of the present invention provides a novel and useful method for manufacturing a semiconductor device. In this manufacturing method, a nitride semiconductor crystal having a p-type semiconductor layer containing a p-type impurity, the main material being a first type nitride semiconductor, the surface being a crystal plane perpendicular to the (0001) crystal plane, Preparing, removing a part of the nitride semiconductor crystal, and removing another part of the p-type semiconductor layer so that the side surface forms an angle with the (0001) crystal plane, A first crystal growth step of growing a first type of nitride semiconductor in the region where the p-type semiconductor layer has been removed in the removal step, and a second type of nitride semiconductor crystal on the surface of the nitride semiconductor crystal after the first crystal growth step. A second crystal growth step for crystal growth of the nitride semiconductor; and a gate electrode facing at least a part of the p-type semiconductor layer on the surface of the nitride semiconductor crystal after the second crystal growth step, with a gate insulating film interposed And forming a process .

This manufacturing method can preferably manufacture the semiconductor device described above. In this manufacturing method, crystal growth from the (0001) crystal plane is prohibited when the nitride semiconductor crystal is grown. Thereby, the crystal growth is prevented from proceeding non-uniformly, and a homogeneous crystal can be obtained.
According to this manufacturing method, the semiconductor device according to the present invention can be manufactured satisfactorily.

In the manufacturing method described above, in the removing step, a part of the p-type semiconductor layer is projected in a hexagonal column shape in which six side surfaces are located on the (10-10) crystal plane or the (10-12) crystal plane. Is preferred.
According to this manufacturing method, it is possible to effectively form the p-type semiconductor region in the nitride semiconductor crystal.

  According to the present invention, a stable normally-off operation can be realized in a semiconductor device using a heterojunction surface for a channel. A normally-off semiconductor device having a high off breakdown voltage and a low on-resistance can be realized.

First, the main features of the embodiments described below are listed.
(Feature 1) The upper surface of the nitride semiconductor crystal is a crystal plane perpendicular to the (0001) crystal plane, for example, a (1-210) crystal plane or a (10-10) crystal plane.
(Feature 2) The nitride semiconductor crystal includes a first low-concentration semiconductor region. The first low concentration semiconductor region is an n ⁻ type semiconductor region containing an n type impurity at a relatively low concentration. The first low-concentration semiconductor region is located in the uppermost layer portion of the first layer made of the first type nitride semiconductor, and is interposed between the heterojunction plane and the p-type semiconductor region.
(Feature 3) The nitride semiconductor crystal includes a drain region. The drain region is an n ⁺ type semiconductor region containing an n type impurity at a relatively high concentration. The drain region is formed in the lowermost layer portion of the first layer made of the first type nitride semiconductor, and is exposed on the lower surface of the nitride semiconductor crystal. A drain electrode is in ohmic contact with the drain region.
(Feature 4) A nitride semiconductor crystal includes a source region. The source region is an n ⁺ type semiconductor region containing an n type impurity at a relatively high concentration. The source region is formed over both the first layer composed of the first type nitride semiconductor and the second layer composed of the second type nitride semiconductor, and at the boundary surface between the two layers. A heterojunction plane passes through. The source region is exposed on the upper surface of the nitride semiconductor crystal, and the source electrode is in ohmic contact.

(Example 1)
FIG. 1 schematically shows a structure of the semiconductor device 10 according to the first embodiment when viewed from above. FIG. 2 shows a cross-sectional view taken along line II-II in FIG. FIG. 1 schematically shows a characteristic structure of the semiconductor device 10. In fact, many similar structures are formed vertically and horizontally in the drawing.
The semiconductor device 10 includes a nitride semiconductor crystal 20, a source electrode 28, a drain electrode 30, and a gate electrode 32. The source electrode 28 is formed on the upper surface 20 a of the nitride semiconductor crystal 20. The drain electrode 30 is formed on the lower surface 20 b of the nitride semiconductor crystal 20. The gate electrode 32 is formed on the upper surface 20 a of the nitride semiconductor crystal 20 via a gate insulating film 34. As shown in FIG. 1, the source electrode 28 has a substantially regular hexagonal shape when viewed from above. The gate electrode 32 has a honeycomb network shape in plan view from above.
The material which comprises the source electrode 28, the drain electrode 30, and the gate electrode 32 is not specifically limited, For example, it can comprise using a metal. In this embodiment, the source electrode 28 and the drain electrode 30 are constituted by a laminate in which titanium (Ti) and aluminum (Al) are laminated. The gate electrode 32 is mainly composed of titanium (Ti). The gate insulating film 34 is configured using silicon oxide (SiO ₂ ). The source electrode 28 and the drain electrode 30 are ohmic electrodes, and are in ohmic contact with the upper and lower surfaces 20a and 20b of the nitride semiconductor crystal 20, respectively.

The nitride semiconductor crystal 20 is a crystal body having a hexagonal crystal structure. The upper surface 20a of the nitride semiconductor crystal 20 is a (1-210) crystal plane perpendicular to the (0001) crystal plane. The nitride semiconductor crystal 20 includes a GaN layer 22 (first layer) composed of gallium nitride (GaN) and an AlGaN layer 24 (first layer) composed of gallium nitride / aluminum (Al _0.3 Ga _0.7 N). 2 layers). The AlGaN layer 24 is stacked on the upper side of the GaN layer 22. Since the band gaps of gallium nitride and gallium nitride / aluminum are different from each other, a heterojunction surface 26 is formed at the boundary between the GaN layer 22 and the AlGaN layer 24. The band gap of gallium nitride is narrower than that of gallium nitride / aluminum. The heterojunction surface 26 is parallel to the upper surface 20a of the nitride semiconductor crystal 20 and is located on the (1-210) crystal plane perpendicular to the (0001) crystal plane. A gate electrode 32 faces a part of the heterojunction surface 26 with the gate insulating film 34 and the AlGaN layer 24 therebetween.

  The GaN layer 22 can be divided into a drain region 42, low-concentration semiconductor regions 44, 48, 50, a p-type semiconductor region 46, and a source region 54 according to the type and concentration of the introduced impurity. Similarly, the AlGaN layer 24 can be divided into an i-type semiconductor region 52 and a source region 54. The source region 54 is formed across the GaN layer 22 and the AlGaN layer 24, and 26 heterojunction surfaces pass through the source region 54. The low-concentration semiconductor regions 44, 48, and 50 are the first low-concentration semiconductor region 50 located above the p-type semiconductor region 46 and the p-type semiconductor in the vertical direction (thickness direction) of the nitride semiconductor crystal 20. The region can be divided into a second low-concentration semiconductor region 48 located on the side of the region 46 (upper and lower positions are equal) and a third low-concentration semiconductor region 44 located below the p-type semiconductor region 46.

The drain region 42 is a region mainly composed of gallium nitride, and is an n ⁺ type semiconductor region containing an n-type impurity at a relatively high concentration. Silicon (Si) is used as the n-type impurity, and its concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ . The drain region 42 is formed in the lowermost layer portion of the GaN layer 22. The drain electrode 30 is in ohmic contact with the drain region 42.
The low-concentration semiconductor regions 44, 48, and 50 are regions containing gallium nitride as a main material, and are n ⁻ -type semiconductor regions containing an n-type impurity at a relatively low concentration. Silicon (Si) is used as the n-type impurity, and its concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ .
The first low-concentration semiconductor region 50 is formed below the heterojunction surface 26, and a part of the first low-concentration semiconductor region 50 is interposed between the heterojunction surface 26 and the p-type semiconductor region 46.
The second low concentration semiconductor region 48 is formed between the first low concentration semiconductor region 50 and the third low concentration semiconductor region 44. The second low concentration semiconductor region 48 is formed below the middle portion of the gate electrode 32.
The third low-concentration semiconductor region 44 is formed above the drain region 42, and a part thereof is interposed between the drain region 42 and the p-type semiconductor region 46. The low concentration semiconductor regions 44, 48, 50 form a series of n ⁻ regions extending from the heterojunction surface 26 to the drain region 42 below the intermediate portion of the gate electrode 32.

The p-type semiconductor region 46 is a region mainly composed of gallium nitride, and is a p-type semiconductor region containing p-type impurities. Magnesium (Mg) is used as the p-type impurity, and its concentration is adjusted to about 5 × 10 ¹⁹ cm ⁻³ .
FIG. 3 is a plan view of the arrangement of the p-type semiconductor regions 46 from the same viewpoint as FIG. As shown in FIGS. 2 and 3, each p-type semiconductor region 46 is a hexagonal column-shaped region extending in the vertical direction, and is located below each source electrode 28. The p-type semiconductor region 46 is formed in a wider area than the source electrode 28 when viewed from above, and the peripheral edge of the p-type semiconductor region 46 extends to below the gate electrode 32.
The six side surfaces 46a and 46b of the p-type semiconductor region 46 are perpendicular to the upper surface 20a of the nitride semiconductor crystal 20 and are located on a crystal plane that forms an angle with the (0001) crystal plane (not parallel). . Specifically, the two side surfaces 46a facing in the left-right direction in the drawing are located on the (10-10) crystal plane perpendicular to the (0001) crystal plane. The other four side surfaces 46b are located on the (10-12) crystal plane that forms an angle of approximately 30 degrees with the (0001) crystal plane.

  As shown in FIG. 2, the p-type semiconductor region 46 is not formed under the intermediate portion of the gate electrode 32, and the second low-concentration semiconductor region 48 is formed. As shown in FIGS. 2 and 3, the second low-concentration semiconductor region 48 is located in the gap between the plurality of p-type semiconductor regions 46 having a hexagonal column shape, and is a honeycomb-like region. Below the central portion of the gate electrode 32, the lightly doped semiconductor regions 44, 48, 50 and the drain region 42 pass through the side of the p-type semiconductor region 46 from the heterojunction surface 26 and below the nitride semiconductor crystal 20. A series of n-type semiconductor regions reaching the side surface 20b are formed. The series of n-type semiconductor regions 42, 44, 48, and 50 constitute a part of a channel through which electrons travel when a voltage is applied to the gate electrode 32.

The source region 54 is formed across the GaN layer 22 and the AlGaN layer 24, and is exposed on the upper surface 20 a of the nitride semiconductor crystal 20. The source region 54 is an n ⁺ type region containing an n type impurity at a relatively high concentration. Silicon (Si) is used as the n-type impurity, and its concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ . The source region 54 is formed under the source electrode 28 and extends to a position facing the end of the gate electrode 32.

  The i-type semiconductor region 52 is a region mainly composed of gallium nitride / aluminum, and is an i-type semiconductor region into which no impurity is introduced. The i-type semiconductor region 52 is located between the central portion of the gate electrode 32 and the first low-concentration semiconductor region 50. A part of the heterojunction surface 26 formed at the boundary between the i-type semiconductor region 52 and the upper low-concentration semiconductor region 50 is opposed to the gate electrode 32 from above, and the p-type semiconductor region 46 is opposed from below. ing. Note that the i-type semiconductor region 52 may be an n-type semiconductor region by introducing an n-type impurity.

  Next, the operation of the semiconductor device 10 will be described. In the semiconductor device 10, the heterojunction surface 26 is formed on the (1-210) crystal plane. The (1-210) crystal plane is a nonpolar plane whose polarity does not change in the vertical direction. Therefore, spontaneous polarization and piezo polarization do not occur in the direction perpendicular to the heterojunction plane 26. Further, a p-type semiconductor region 46 is opposed to a part of the heterojunction surface 26 with the second low-concentration semiconductor region 50 interposed therebetween. As a result, when no voltage is applied to the gate electrode 32, a depletion layer is formed in the low concentration semiconductor regions 44, 48, and 50, and the depletion layer extends to the heterojunction surface 26. As a result, in a state where no voltage is applied to the gate electrode 32, the low concentration semiconductor regions 44, 48 and 50 are depleted and the formation of the two-dimensional electron gas layer on the heterojunction surface 26 is prohibited. In the semiconductor device 10, energization between the source electrode 28 and the drain electrode 30 is prohibited while no voltage is applied to the gate electrode 32.

  On the other hand, when a positive voltage is applied to the gate electrode 32, the depletion layer formed in the low concentration semiconductor regions 44, 48, 50 is reduced and a two-dimensional electron gas layer is formed on the heterojunction surface 26. . In other words, in order to reduce the depletion layer formed in the low-concentration semiconductor regions 44, 48, 50 and form a two-dimensional electron gas layer on the heterojunction surface 26, a relatively large positive electrode is formed on the gate electrode 32. Must be applied. When a positive voltage is applied to the gate electrode 32, the heterojunction surface 26 and the low-concentration semiconductor regions 44, 48, and 50 are in a state in which a large number of electrons can travel, and the source electrode 28 and the drain electrode 30 can be energized. It becomes. Thus, the semiconductor device 10 can realize a stable normally-off operation.

  The threshold voltage (gate voltage required for turning on) of the semiconductor device 10 is such that the impurity concentration of the low concentration semiconductor regions 44, 48 and 50, the impurity concentration of the p-type semiconductor region 48, and the thickness of the first low concentration semiconductor region 50. It varies depending on t (see FIG. 2) and the like. Alternatively, it is changed by introducing an n-type impurity into the i-type semiconductor region 52, for example. Therefore, the semiconductor device 10 having a desired threshold voltage can be realized by appropriately changing these settings.

The heterojunction plane 26 is not limited to a specific (1-210) crystal plane, and can be formed on a crystal plane equivalent to the (1-210) crystal plane. Alternatively, the heterojunction surface 26 may be formed on another crystal plane perpendicular to the (0001) crystal plane, such as a (10-10) crystal plane. The crystal plane perpendicular to the (0001) crystal plane is a nonpolar plane whose polarity does not change in the vertical direction. Therefore, by forming the heterojunction plane 26 on a crystal plane perpendicular to the (0001) crystal plane, avoiding the (0001) crystal plane, spontaneous polarization and piezoelectric polarization in the direction perpendicular to the heterojunction plane 26 are achieved. Can be suppressed. Thereby, the density of the two-dimensional electron gas generated on the heterojunction surface 26 can be moderately suppressed.
When the heterojunction plane 26 is formed on the (10-10) crystal plane, the six lateral boundary surfaces of the p-type semiconductor region 46 are on the (1-210) crystal plane or the (1-212) crystal plane. It is preferable to form.

(Manufacturing method of the semiconductor device 10)
Next, a method for manufacturing the semiconductor device 10 will be described.
First, as shown in FIG. 4, a semiconductor substrate 42 (which will later become a drain region 42) whose main surface is n ⁺ -type gallium nitride and whose main surface is a (1-210) crystal plane is prepared. Next, using an MOCVD (Metal Organic Chemical Vapor Deposition) method, an n ⁻ -type gallium nitride layer 44 (which later becomes the third low-concentration semiconductor region 44) is crystal-grown on the semiconductor substrate 42. Next, a p-type gallium nitride layer 46 (which will later become a p-type semiconductor region 46) is grown on the n ⁻ -type gallium nitride layer 44 by MOCVD.
Next, as shown in FIG. 5, a groove 47 that penetrates the p-type gallium nitride layer 46 and reaches the n ⁻ -type gallium nitride layer 44 is formed using the lithography technique and the RIE technique. The shape of the groove 47 is equal to the shape of the region in which the second low-concentration semiconductor region 48 is crystal-grown in a later step, that is, the shape in plan view is formed in a honeycomb shape (see FIG. 3). As a result, the p-type gallium nitride layer 46 is divided into a plurality of regions protruding in a hexagonal column shape, and the side surface 47a is located on the (10-10) crystal plane or the (10-12) crystal plane.

Next, as shown in FIG. 6, by utilizing the MOCVD method, n ^- on the type gallium nitride layer 44 and p-type gallium nitride layer 46, n ^- first the type gallium nitride layer 48, 50 (after (2) a low-concentration semiconductor region 48 and a first low-concentration semiconductor region 50) are grown. At this time, crystal growth proceeds from each of the side surfaces 47 a of the p-type gallium nitride layer 46 inside the groove 47. As described above, the side surface 47a of the p-type gallium nitride layer 46 is a (10-10) crystal plane or a (10-12) crystal plane perpendicular to the (0001) crystal plane. Therefore, crystal growth proceeds from each side surface 47a at a substantially equal speed. Crystal growth proceeds from each side surface 47 a at a substantially equal speed, so that the n ⁻ -type gallium nitride layer 48 can be formed uniformly in the groove 47.

On the other hand, when the (0001) crystal plane is included in the six side surfaces 47a of the p-type gallium nitride layer 46, only one of the side surface 47a and the side surface 47a opposite to the side surface 47a across the groove 47 exists. (0001) crystal plane, and the other side surface 47a is a (0001) crystal plane in which only nitrogen atoms exist. Crystal growth from a (0001) crystal plane in which only gallium atoms are present has a significantly slower progression rate than crystal growth from a (0001) crystal plane in which only nitrogen atoms are present. Therefore, when the (0001) crystal plane is included in the side surface 47 a of the p-type gallium nitride layer 46, crystal asymmetry occurs in the groove 47, and the n ⁻ -type gallium nitride layer is formed in the groove 47. 48 cannot be formed uniformly.

Next, as shown in FIG. 7, an i-type gallium nitride / aluminum layer 52 (which later becomes an i-type semiconductor region 52) is crystallized on the n ⁻ -type gallium nitride layer 50 using MOCVD. Grow.
Next, as shown in FIG. 8, ion implantation is performed to form a source region 54. At the time of this ion implantation, a mask (not shown) having an opening in the formation region of the source region 54 is formed on the upper surface of the i-type gallium nitride / aluminum layer 52.
Through the above steps, the formation of the nitride semiconductor crystal 20 of the semiconductor device 10 is completed. The nitride semiconductor crystal 20 that has been formed is annealed after forming a protective layer on the surface as necessary.

Next, as shown in FIG. 9, a silicon oxide layer 34 (which will later become the gate insulating film 34) is formed on the i-type gallium nitride / aluminum layer 52 using the CVD method.
Next, as shown in FIG. 10, a part of the silicon oxide layer 34 is removed and a part of the source region 54 is exposed using a lithography technique and an etching technique.
Next, the source electrode 28, the drain electrode 30, and the gate electrode 32 are formed. The source electrode 28 is formed on the drain region 54, the drain electrode 30 is formed on the drain region 42, and the gate electrode 32 is formed on the gate insulating film 34. Through the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.
The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and achieving one of the objects itself has technical utility.

The schematic diagram which shows the structure which planarly viewed the semiconductor device. II-II sectional view taken on the line in FIG. The figure which shows the arrangement | sequence of a p-type semiconductor region in planar view. The figure which shows the 1st manufacturing process of a semiconductor device. The figure which shows the 2nd manufacturing process of a semiconductor device. The figure which shows the 3rd manufacturing process of a semiconductor device. The figure which shows the 4th manufacturing process of a semiconductor device. The figure which shows the 5th manufacturing process of a semiconductor device. The figure which shows the 6th manufacturing process of a semiconductor device. The figure which shows the 7th manufacturing process of a semiconductor device.

Explanation of symbols

10: Semiconductor device 20: Nitride semiconductor crystal 22: GaN layer (first layer)
24: AlGaN layer (second layer)
26: Heterojunction surface 28: Source electrode 30: Drain electrode 32: Gate electrode 34: Gate insulating film 42: Drain region 44, 48, 50: Low concentration semiconductor region 46: P-type semiconductor region 52: i-type semiconductor region 54: Source region

Claims (8)

A nitride semiconductor crystal, and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer,
The nitride semiconductor crystal includes a first layer composed of a first type of nitride semiconductor and a second layer composed of a second type of nitride semiconductor and stacked above the first layer. Has
The heterojunction plane formed at the boundary between the first layer and the second layer is located on a crystal plane perpendicular to the (0001) crystal plane,
In the first layer, a p-type semiconductor region containing a p-type impurity is formed at a position facing at least a part of the gate electrode through the heterojunction surface,
A side boundary surface of the p-type semiconductor region is formed on a crystal plane that is perpendicular to the heterojunction plane and forms an angle with the (0001) crystal plane. The heterojunction plane is located on a (1-210) crystal plane;
2. The semiconductor device according to claim 1, wherein a lateral boundary surface of the p-type semiconductor region is formed on a (10-10) crystal plane or a (10-12) crystal plane.   The p-type semiconductor region is a hexagonal column-shaped region, and six side boundary surfaces thereof are formed on a (10-10) crystal plane or a (10-12) crystal plane. Item 3. The semiconductor device according to Item 2. The heterojunction plane is located on a (10-10) crystal plane;
2. The semiconductor device according to claim 1, wherein a lateral boundary surface of the p-type semiconductor region is formed on a (1-210) crystal plane or a (1-212) crystal plane.   The p-type semiconductor region is a hexagonal column-shaped region, and six side boundary surfaces thereof are formed on a (1-210) crystal plane or a (1-212) crystal plane. Item 5. The semiconductor device according to Item 4.   4. The semiconductor device according to claim 1, wherein the first type nitride semiconductor is gallium nitride, and the second type nitride semiconductor is gallium nitride / aluminum. 5. A method for manufacturing a semiconductor device, comprising:
Providing a nitride semiconductor crystal having a p-type semiconductor layer whose main material is a first type nitride semiconductor, a surface is a crystal plane perpendicular to the (0001) crystal plane, and includes a p-type impurity;
Removing a part of the nitride semiconductor crystal and causing another part of the p-type semiconductor layer to protrude so that the side surface forms an angle with the (0001) crystal plane;
A first crystal growth step in which a first type nitride semiconductor is crystal-grown at least in a region where the p-type semiconductor layer has been removed in the removal step;
A second crystal growth step of growing a second type of nitride semiconductor on the surface of the nitride semiconductor crystal after the first crystal growth step;
Forming a gate electrode facing at least a part of the p-type semiconductor layer on the surface of the nitride semiconductor crystal after the second crystal growth step with a gate insulating film interposed therebetween;
A method for manufacturing a semiconductor device comprising:   In the removing step, a part of the p-type semiconductor layer is protruded in a hexagonal column shape having six side surfaces located on a (10-10) crystal plane or a (10-12) crystal plane. 6. A method for manufacturing a semiconductor device according to 5.

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