JP2008233141A - Electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of an electro-optical device wherein current consumption will not increase, even when an electrostatic protecting circuit is installed, and to provide the electro-optical device. <P>SOLUTION: In an electro-optical device 100, an upper light-shielding material 510 and a lower light-shielding material 520 are formed in areas overlapping an electrostatic protecting circuit 190. Consequently, the electrostatic protecting circuit 190 is not irradiated with UV light, when UV-curing resin compositions 410a and 420a applied over an element substrate 310 and a flexible printed circuit board 400 are irradiated with UV light, to form an upper face-side UV-curing mold material 410 and a lower face-side UV-curing mold material 420. As a result, leakage current is prevented from being produced due to the change in the current-voltage characteristics, which is caused by irradiation with UV light, in a diode device formed in the electrostatic protecting circuit 190. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device in which a flexible wiring board is connected to a terminal of an element substrate.

  Among various electro-optical devices, for example, in a liquid crystal device, an element substrate on which a plurality of pixels each including a pixel electrode are arranged and a counter substrate are bonded together by a sealing material, and the region is surrounded by the sealing material. Liquid crystal as an electro-optical material is held. Further, a terminal is formed on the upper surface side of the element substrate on which the pixel electrode is formed, and a flexible wiring substrate is connected to the terminal. In order to protect the connection part between the element substrate and flexible wiring board from external stress, UV (Ultra-Violet / UV) extends across the element substrate and flexible wiring board on the upper surface side of the element substrate. In many cases, a curable molding material is formed, and a UV curable molding material is formed on the lower surface side of the element substrate so as to straddle the element substrate and the flexible wiring board.

  Such a liquid crystal device is required to have low power consumption when mounted as a display device in a portable electronic device such as a cellular phone. However, since the liquid crystal device performs a refresh operation for rewriting the state of each pixel for each frame regardless of the display content, power is consumed by a drive circuit for driving each pixel, its control circuit, or the like.

In view of this, a technique has been proposed in which a static memory circuit that stores 1 bit for each pixel is incorporated, and a pixel is turned on or off according to the bit stored in the memory circuit. If the display is performed, refreshing is unnecessary, so that it is not necessary to operate the drive circuit or the like, and accordingly, power consumption can be reduced (see, for example, Patent Documents 1, 2, 3, and 4).
Pamphlet of international application WO00 / 8625 JP-A-8-286170 JP 2002-278498 A JP 2003-122331 A

  In a liquid crystal device, there is a possibility that an element used in a driving circuit formed in an outer region of a pixel region in an element substrate may be damaged by intrusion of static electricity during or after the manufacturing. Therefore, an electrostatic protection circuit may be provided for a signal line or the like extending from the terminal at a position adjacent to the terminal formation region. The electrostatic protection circuit may connect the constant potential line and the signal line to a diode element. It has the structure electrically connected via. For this reason, even when an electrostatic protection circuit is provided, the constant potential line and the signal line are insulated by the diode element, so that a problem such as an increase in current consumption in the liquid crystal device should not occur.

  However, the inventors of the present application have obtained a result that when the electrostatic protection circuit is provided in the liquid crystal device, the current consumption increases as compared with the case where the electrostatic protection circuit is not provided.

  In view of the above problems, an object of the present invention is to provide an electro-optical device in which an increase in current consumption does not occur even when an electrostatic protection circuit is provided.

  The inventor of the present application has studied the various causes of the increase in current consumption when the electrostatic protection circuit is provided as compared with the case where the electrostatic protection circuit is not provided, and has obtained the following new knowledge. First, in order to reinforce the connection portion between the element substrate and the flexible wiring substrate with the UV curable molding material, after the UV curable resin composition is disposed, the UV curable resin composition is irradiated with UV light and cured. In this case, when UV light is incident on the diode element of the electrostatic protection circuit, the current-voltage characteristic of the diode element changes. As a result, a minute current leaks between the constant potential line and the signal line via the diode element, and the current consumption increases. Such a leakage current is difficult to be manifested as an increase in current consumption in a conventional liquid crystal device in which a memory element is not provided in each of a plurality of pixels. However, in a liquid crystal device in which a memory element is provided in each of a plurality of pixels, Since the current consumption is small, a minute current flowing through the diode element tends to surface as an increase in current consumption.

  The present invention has been achieved based on such new knowledge, and includes an element substrate in which a plurality of pixels each including a pixel electrode are arranged, and on the upper surface side where the pixel electrode is formed on the element substrate, In the electro-optical device in which the terminal to which the flexible wiring substrate is connected is formed, an electrostatic protection circuit including a diode element is formed on the upper surface side of the element substrate in a region adjacent to the terminal formation region. On the upper surface side of the element substrate, an upper surface side UV curable molding material is formed so as to straddle the element substrate and the flexible wiring substrate, and an upper light shielding material is provided in a region overlapping above the electrostatic protection circuit. Is arranged. Such a configuration is employed regardless of whether the base material of the element substrate is a translucent substrate. Note that “upper” and “lower” in the present invention mean the direction in which the element substrate is located, and when the electro-optical device is used, a pixel electrode is formed on the element substrate. You may face down.

  In the present invention, since the upper light-shielding material is disposed in a region overlapping above the electrostatic protection circuit, when the upper surface side UV curable mold material is cured, the electrostatic protection circuit is not irradiated with UV light. In the electrostatic protection circuit, the current-voltage characteristic of the diode element does not change. Therefore, current can be prevented from leaking through the diode element, so that even when an electrostatic protection circuit is provided, increase in current consumption does not occur.

  In another embodiment of the present invention, an element substrate having a plurality of pixels each including a pixel electrode is provided, and the terminal to which the flexible wiring substrate is connected is provided on the upper surface side of the element substrate on which the pixel electrode is formed. In the formed electro-optical device, an electrostatic protection circuit including a diode element is formed in a region adjacent to the terminal formation region on the upper surface side of the element substrate, and the base material is transparent to the element substrate. A region that is an optical substrate and has a lower surface side UV curable molding material formed on the lower surface side of the element substrate so as to straddle the element substrate and the flexible wiring substrate, and overlaps the electrostatic protection circuit below. Is characterized in that a lower light shielding material is disposed.

  In the present invention, since the lower light shielding material is disposed in a region overlapping with the electrostatic protection circuit below, when the lower surface side UV curable molding material is cured, the UV light is transmitted through the element substrate and electrostatic protection is performed. Since the circuit is not irradiated, the current-voltage characteristic of the diode element does not change in the electrostatic protection circuit. Therefore, current can be prevented from leaking through the diode element, so that even when an electrostatic protection circuit is provided, increase in current consumption does not occur.

  In still another embodiment of the present invention, the device includes an element substrate on which a plurality of pixels each including a pixel electrode are arranged, and the terminal to which a flexible wiring substrate is connected on the upper surface side where the pixel electrode is formed on the element substrate. In the electro-optical device in which is formed, an electrostatic protection circuit including a diode element is formed in a region adjacent to the terminal formation region on the upper surface side of the element substrate. It is a translucent substrate, and on the upper surface side of the element substrate, an upper surface side UV curable molding material is formed so as to straddle the element substrate and the flexible wiring substrate, and on the lower surface side of the element substrate, A lower surface side UV curable molding material is formed so as to straddle the element substrate and the flexible wiring substrate, and an upper light shielding material is disposed in a region overlapping with the electrostatic protection circuit. Together and, characterized in that it is arranged beneath the light-shielding material in a region overlapping with lower relative to the electrostatic protection circuit.

  In the present invention, since the upper light shielding material is disposed in a region overlapping above the electrostatic protection circuit, when forming the upper surface side UV curable mold material, the electrostatic protection circuit is not irradiated with UV light. In addition, since the lower light shielding material is disposed in a region overlapping with the electrostatic protection circuit below, when the lower surface side UV curable molding material is cured, the UV light is transmitted through the element substrate to the electrostatic protection circuit. There is no irradiation. For this reason, the current-voltage characteristic of the diode element does not change in the electrostatic protection circuit. Therefore, current can be prevented from leaking through the diode element, so that even when an electrostatic protection circuit is provided, increase in current consumption does not occur.

  In the present invention, the upper light shielding material may employ a configuration in which the upper light shielding material is laminated on an upper layer of the electrostatic protection circuit in the element substrate, for example.

  In the present invention, a configuration may be adopted in which a counter substrate that is oriented with respect to the element substrate is provided, and the upper light shielding material is formed in a region overlapping the electrostatic protection circuit in the counter substrate. In this case, a stripe-shaped or lattice-shaped light shielding pattern may be formed in a region overlapping the pixel region on the lower surface of the counter substrate facing the element substrate. It is preferable that the lower substrate is formed of the same material as the light shielding pattern on the lower surface of the counter substrate. If comprised in this way, it is not necessary to add a process in forming an upper light shielding material.

  In the present invention, for example, a configuration in which the lower light shielding material is disposed on the lower surface side of the element substrate can be employed.

  In the present invention, the lower light shielding material may adopt a configuration formed on the lower layer side of the electrostatic protection circuit on the upper surface side of the element substrate.

In the present invention, the upper light shielding material and the lower light shielding material include metals such as Mo (molybdenum), W (tungsten), Ti (titanium), and Cr (chromium), TiN (titanium nitride), and MnO _n (manganese oxide). ), An organic material such as a metal compound such as ceramics, carbon, or a black resin. Further, as the upper light shielding material and the lower light shielding material, a black ink containing a metal compound, carbon, or an organic material can be used.

  The present invention is particularly effective when a storage element is formed in each of the plurality of pixels in the element substrate. In a liquid crystal device in which a storage element is not provided for each of a plurality of pixels, leakage current resulting from irradiation of UV light onto a diode element does not surface much as an increase in current consumption. Since the original current consumption is small in the liquid crystal device provided with, a minute current flowing through the diode element appears as an increase in current consumption. Therefore, when the present invention is applied when a memory element is formed in each of the plurality of pixels, the original purpose of reducing power consumption can be sufficiently achieved by providing the memory element in each of the plurality of pixels. It will be.

  The present invention can be applied to, for example, a liquid crystal device. In this case, a liquid crystal layer is provided on the upper surface side of the element substrate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the present invention is applied to a liquid crystal device as a typical electro-optical device. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing.

[Embodiment 1]
(Overall configuration of electro-optical device)
1A, 1B, and 1C are respectively a plan view of an electro-optical device to which the present invention is applied as viewed from the counter substrate side together with each component, a bottom view viewed from the element substrate side, and H It is -H 'sectional drawing. In FIG. 1B, the positional relationship between the left and right is made to match that in FIG. 1A so that the correspondence with FIG.

  As shown in FIGS. 1A, 1B, and 1C, the electro-optical device 100 includes an element substrate 310 (first substrate) and a counter substrate 320 (second substrate) through a predetermined gap. Includes a liquid crystal panel 300 bonded with a sealing material 107 made of a thermosetting resin or a UV curable resin through a predetermined gap, and a region surrounded by the sealing material 107 has a twisted nematic (TN). A liquid crystal layer 50a made of a type liquid crystal is held. The sealing material 107 is disposed along the edge of the counter substrate 320. A liquid crystal injection port 107a is formed in the sealing material 107 by the interrupted portion, and the liquid crystal injection port 107a is closed by the sealing material 106 after the liquid crystal is injected. The sealing material 107 may be mixed with a gap material such as glass fiber or glass beads for setting the distance between the two substrates to a predetermined value.

As will be described in detail later, the central region of the element substrate 310 is a pixel region 310a in which a plurality of pixels 100b including the pixel electrodes 118 are formed in a matrix. In the counter substrate 320, a light shielding layer 308 called a frame is formed in an inner region of the sealant 107, and the inner side is a display region 100a. On the counter substrate 320, a light shielding film 323 (lattice or stripe light shielding pattern) called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrode 118 of the element substrate 310. The light shielding films 323 and 308 are made of Mo (molybdenum), W (tungsten), Ti (titanium), Cr (chromium), MnO _n (manganese oxide), or the like.

  In this embodiment, since the electro-optical device 100 is a transmissive liquid crystal device, both the pixel electrode 118 and the common electrode 108 are made of a light-transmitting conductive film such as ITO (Indium Tin Oxide). Further, translucent substrates 310d and 320d such as glass or quartz are used as the base material of the element substrate 310 and the counter substrate 320.

  The element substrate 310 is larger than the counter substrate 320. In the element substrate 310, a plurality of terminals 102 are formed along the substrate edge in an extended region 320 b that protrudes from the edge of the counter substrate 320. In addition, a flexible wiring substrate 400 is connected to the element substrate 310 with respect to the terminal 102 by an anisotropic conductive material or the like.

  In this embodiment, for the purpose of reinforcing the connecting portion between the element substrate 310 and the flexible wiring substrate 400, the upper surface 310e side (opposite the counter substrate 320) on which the pixel electrode 118 is formed, of both surfaces of the element substrate 310. On the inner surface side), an upper surface side UV curable mold material 410 such as an acrylic resin is formed so as to straddle the element substrate 310 and the flexible wiring substrate 400. Further, the element substrate 310 and the flexible wiring substrate 400 are also provided on the element substrate 310 on the lower surface 310f side opposite to the side where the pixel electrode 118 is formed (the outer surface side opposite to the side facing the counter substrate 320). A lower surface side UV curable mold material 420 such as an acrylic resin is formed so as to extend over the surface.

  In addition, as will be described in detail later, in this embodiment, as indicated by a slanting region with a lower right side, an upper light shielding material is provided on the upper surface 310e side of the element substrate 310 in a region overlapping with an electrostatic protection circuit 190 described later. 510 is disposed, and a lower light shielding member 520 is disposed on the lower surface 310 f side of the element substrate 310 in a region overlapping with the electrostatic protection circuit 190.

(Electrical configuration of electro-optical device)
2A and 2B are a block diagram illustrating an electrical configuration of the electro-optical device 100 according to the present embodiment, and a circuit diagram of a pixel circuit. FIGS. 3A and 3B are a partially enlarged view of the electro-optical device 100 according to the present embodiment and an explanatory diagram illustrating a writing operation with respect to the memory circuit.

  In the electro-optical device 100 according to the present embodiment, there is proposed a system technique in which a static memory circuit that stores one bit for each pixel is incorporated, and the pixel is turned on or off according to the bit stored in the memory circuit. For this reason, the electro-optical device 100 has the following configuration.

  As shown in FIG. 2A, in the display region 100a (pixel region 310a) of the electro-optical device 100 of the present embodiment, for example, 320 Y selection lines 311 each extend in the row (X) direction. , 240 columns of X selection lines 211 are provided so as to extend in the column (Y) direction. The pixel block 10 is provided corresponding to the intersection of 320 rows of Y selection lines 311 and 240 columns of X selection lines 211. For this reason, in this embodiment, the pixel blocks 10 are arranged in 320 vertical rows × 240 horizontal columns. For the sake of convenience, the pixel block 10 corresponding to the X selection lines 211 in the first, second, third,..., 240th columns from the left in the display area 100 will be generally described without particularly specifying the columns. Sometimes, the expression of the j-th column (j is an integer satisfying 1 ≦ j ≦ 240) may be used.

  In the present embodiment, one pixel block 10 further includes four pixel circuits 20 (pixels 100b) arranged along the X direction. For this reason, in this embodiment, four pixel circuits 20 are provided corresponding to the intersection of the Y selection line 311 and the X selection line 211. As a result, the pixel circuit 20 is arranged in a matrix of 320 vertical rows × 960 horizontal rows (= 240 × 4) columns. Will be arranged. Each pixel block 10 is structurally identical to each other, and the configuration of the four pixel circuits 20 in one pixel block 10 is also identical to each other. Therefore, the pixel block 10 will be described as a representative corresponding to the intersection of the Y selection line 311 in the first row and the X selection line 211 in the first column, and further, the leftmost end included in the pixel block 10. The pixel circuit 20 will be described with reference to FIG.

  Although not shown in FIG. 2A, in the pixel circuit 20 arranged in a matrix, as shown in FIG. 2B, the bit line 215 and the complementary bit line 216 extend in the column (Y) direction. As described above, the pixel circuit 20 is provided corresponding to each column. As described above, since the pixel circuit 20 has 960 rows in this embodiment, 960 sets of bit lines 215 and complementary bit lines 216 are also provided. For convenience, the data bits supplied to the bit lines 215 in the first, second, third,..., 960th columns from the left in the display area 100 are denoted as D1, D2, D3,. The inverted data bits supplied to the complementary bit lines 216 in the first, second, third,..., 960 columns are denoted as / D1, / D2, / D3,. For the pixel block 10 in the j-th column, the bit line 215 and the complementary bit line 216 in the (4j-3) th column, the (4j-2) th column, the (4j-1) th column and the (4j) th column. These four sets correspond.

  In this embodiment, the pixel circuit 20 includes a static memory circuit 30, a selection circuit 40, and a liquid crystal element 50. The memory circuit 30 includes n-channel TFTs (Thin Film Transistors / hereinafter referred to simply as “TFTs”) 22, 24, 26, and 28 that function as switching elements, and NOT (inverter) circuits 32 and 34. Prepare. As for the TFT 22, its source is connected to the bit line 215, its drain is connected to the source of the TFT 24, and its gate is connected to the Y selection line 311. The TFT 24 has its drain connected to the input terminal of the NOT circuit 32 and its gate connected to the X selection line 211. The output terminal of the NOT circuit 32 is connected to the input terminal of the NOT circuit 34, and the output terminal of the NOT circuit 34 is fed back to the input terminal of the NOT circuit 32. Here, the input terminal of the NOT circuit 32 (the output terminal of the NOT circuit 34) is the (forward rotation) terminal Q of the memory circuit 30, and the input terminal of the NOT circuit 34 (the output terminal of the NOT circuit 32) is ( Inverted terminal / Q. Since the memory circuit 30 is complementary, the TFT 26 has its source connected to the complementary bit line 216, its drain connected to the source of the TFT 28, and its gate connected to the Y selection line 311. The drain of the TFT 28 is connected to the input terminal of the NOT circuit 34, and the gate thereof is connected to the X selection line 211.

  In such a memory circuit 30, when the logic level of the Y selection line 311 becomes H level and the logic level of the X selection line 211 becomes H level, the TFTs 22, 24, 26 and 28 are simultaneously turned on. Thus, the data bit supplied to the bit line 215 is held at the terminal Q, while the inverted data bit supplied to the complementary bit line 216 is held at the terminal / Q.

  The selection circuit 40 includes transmission gates 42 and 44. A signal Von is supplied to the input terminal of the transmission gate 42, while a signal Voff having a logical inversion relationship with the signal Voff is supplied to the input terminal of the transmission gate 44, and the output terminals of the transmission gates 42 and 44 are output. Are commonly connected to pixel electrodes 118 formed individually for each pixel. The normal control gate of the transmission gate 42 and the inversion control gate of the transmission gate 44 are connected to the terminal Q of the memory circuit 30, and the inversion control gate of the transmission gate 42 and the normal control gate of the transmission gate 44 are the memory circuit. It is connected to 30 terminals / Q. The signals Von and Voff are signals for turning the liquid crystal element 50 on and off, respectively, and are commonly supplied from the upper control circuit (not shown) over the pixel circuits 20. The transmission gates 42 and 44 are turned on (conductive state) between the input end and the output end when the normal rotation control gate is at the H level (the reverse control level is the L level). Accordingly, when the logic level at the terminal Q of the memory circuit 30 is H level, the transmission gates 42 and 44 are turned on and off, respectively, and the signal Von is applied to the pixel electrode 118, while the logic level at the terminal Q is In the case of the L level, the transmission gates 42 and 44 are turned off and on, respectively, and the signal Voff is applied to the pixel electrode 118.

  The liquid crystal element 50 has a configuration in which a TN liquid crystal 105 is sandwiched between an individual pixel electrode 118 for each pixel 100b and a common electrode 108 common to all the pixels. In this embodiment, as shown in FIG. 3B, a signal LCcom that is logically inverted every frame (1F: about 16.7 milliseconds) is applied to the common electrode 108. The signal LCcom is supplied in common to the pixel circuits 20 from the upper control circuit, similarly to the signals Von and Voff. The logic level of the signal LCcom has an inversion relationship with the signal Von and the same relationship with the signal Voff. Further, when the logic levels of the signals Von, Voff and LCcom are H level, the power supply voltage Vdd is taken, and when the signals Von, Voff and LCcom are L level, the ground potential Gnd is taken.

  In the liquid crystal element 50, the amount of transmitted light in unit time changes according to the held voltage effective value. Specifically, the liquid crystal element 50 is set to a normally black mode in which the amount of transmitted light decreases as the held voltage decreases. However, in this embodiment, since only one of the voltages corresponding to ON or OFF is held in the liquid crystal element 50, only a binary display in a bright state (white) or a dark state (black) is possible. It has become.

  Referring again to FIG. 2A, the timing control circuit 110 combines the three functions of the X control circuit 112, the data bit supply circuit 114, and the Y control circuit 116 into one block. Among these, the X control circuit 112 outputs, as an X address Adx, address data specifying the X direction among address data supplied in synchronization with the timing signal from a host control circuit (not shown). The circuit 116 outputs the address data specifying the Y direction as the Y address Ady among the address data supplied in synchronization with the timing signal. The data bit supply circuit 114 is configured to synchronize four bits of data bits supplied from the upper control circuit and four bits of data bits obtained by inverting the logic with the X address Adx and the Y address Ady, respectively. The signal line 60 is supplied.

  The X address decoder 120 applies an H level logic signal indicating selection of the column to the X selection line 211 of the column designated by the X address Adx, and an L level logic signal to the X selection lines of other columns. Are supplied as column selection signals. For convenience, column selection signals supplied to the X selection lines 211 in the first, second, third,..., 240th columns from the left in the display area 100 are X1, X2, X3,. It is written.

  The sample and hold circuit (sampling circuit) 130 samples the 4-bit data bits supplied to the signal line 60 onto the four columns of bit lines 215 corresponding to the X selection lines 211 selected by the X address decoder 120, respectively. The four inverted data bits supplied to the signal line 60 are sampled and supplied to four columns of complementary bit lines 216 corresponding to the selected X selection line 211, respectively. The sample and hold circuit 130 may also have a function of holding sampled data bits.

  The Y address decoder 140 selects, for each row designated by the Y address Ady, an H level logic signal indicating the selection of the row, and an L level logic signal for the Y selection line of the other column. It is output as a signal.

  The buffer group 150 is an aggregate of buffer circuits provided corresponding to each row, and increases the drive capability of the row selection signal and supplies the row selection signal to the X selection line 211. For convenience, the row selection signals supplied to the Y selection lines 311 of the first, second, third,..., 320th rows counted from the top in the display area 100 are Y1, Y2, Y3,. It is written.

  In this embodiment, the timing control circuit 110, the X address decoder 120, the sample and hold circuit 130, the Y address decoder 140, and the buffer group 150 are all formed on the element substrate 310 by the polysilicon process together with the constituent elements in the pixel block 10. The

(Operation)
The operation of the electro-optical device 1 according to this embodiment will be described. First, since the electro-optical device 1 is based on the premise that data bits are stored in the memory circuit 30 of each pixel circuit 20, an operation of storing data bits in the memory circuit 30 will be described. In the present embodiment, the data bit storage operation for the memory circuit 30 is executed in units of the pixel block 10. Here, for example, when data bits are stored in the eight pixel circuits 20 in the pixel block 10 in the i row and j column, the upper control circuit outputs an address designating the i row and the j column, 4 bits of data bits to be stored in the pixel circuit 20 belonging to the pixel block 10, that is, the pixel circuit 20 in the i-th row from the (4j-3) th column to the (4j) th column, and those A total of 8 bits for 4 inverted data bits are output.

  The X control circuit 112 receiving the address supplies the X address Adx of the address to the X address decoder 120, while the Y control circuit 116 receiving the address supplies the Y address Ady of the address. Is supplied to the Y address decoder 140. Further, the data bit supply circuit 114 matches the supply timing of the supplied data bits and the inverted data bits to the X address Adx and the Y address Ady to the signal line 60 via the wiring 76. Supply.

  The X address decoder 120 sets the column selection signal Xj to the H level by the X address Adx. As a result, the sample and hold circuit 130 samples the 4 bits of the data bits to be stored on the four bit lines 215 corresponding to the jth column, while the 4 bits of the inverted data bits also have the jth column. Sampling is performed on four complementary bit lines 216 corresponding to the eyes. More specifically, the sample and hold circuit 130 outputs 4 bits of data bits to be stored in the pixel circuit 20 in the i-th row and from the (4j-3) th column to the (4j) th column, respectively (4j− 3) The bit lines 215 from the column to the column (4j) are sampled as D (4j-3), D (4j-2), D (4j-1), and D4j, and 4 bits of the inverted data bits are sampled. , And / D (4j-3), / D (4j-2), / D (4j-1), / D4j to the complementary bit lines 216 from the (4j-3) th column to the (4j) th column, respectively. Sampling. Therefore, no data bit is supplied to the other bit lines 215 and complementary bit lines 216.

  On the other hand, the Y address decoder 140 sets only the row selection signal Yi to the H level by the Y address Ady designating the i-th row. In the four pixel circuits 20 belonging to the pixel block 10 in the i row and j column, since the row selection signal Yi is at the H level, the TFTs 22 and 26 are turned on, and further, since the column selection signal Xj is at the H level, the TFT 24, Since 28 is turned on, the bit supplied to the bit line 215 is written to the terminal Q, and the bit supplied to the complementary bit line 216 is written to the terminal / Q.

  In this state, when one or both of the row selection signal Yi and the column selection signal Xj become L level, the four pixel circuits 20 belonging to the pixel block 10 in the i row and j column each have TFTs 22, 26 or 24, 28 is turned off or both are turned off. For this reason, in the memory circuit 30, the terminal Q is electrically disconnected from the bit line 215 and the terminal / Q is electrically disconnected from the complementary bit line 216, but the memory circuit 30 continues to hold the written bit.

  When the column selection signal Xj is at the H level and the row selection signal Yi is at the H level, the pixel circuit 20 other than the pixel block 10 in the i row and j column receives either the row selection signal or the column selection signal. Alternatively, both the row selection signal and the column selection signal are at the L level. Therefore, in these pixel circuits 20, one or both of the TFTs 22, 24 (26, 28) are turned off, so that the terminal Q of the memory circuit 30 is electrically disconnected from the bit line 215, and similarly, the terminal / Q Are electrically disconnected from the complementary bit line 216. Therefore, the memory circuit 30 in the pixel circuit 20 other than the pixel block 10 in the i row and j column is not affected by the voltage change of the bit line 215 and the complementary bit line 216 at all. That is, in the memory circuit 30 of these pixel circuits 20, if a data bit has already been written, the data bit is continuously held regardless of the voltage state of the bit line 215 and the complementary bit line 216.

  Immediately after the power is turned on, such a writing operation is executed for all the pixel blocks 10, and accordingly, in each of the memory circuits 30 in all the pixel circuits 20, either H or L level data bits are used. Is retained. In addition, when the display contents are changed, a total of 8 bits of data bits that define the display contents after the change and their inverted data bits are supplied from the upper control circuit together with the address and specified by the address. The data bits held in the four memory circuits 30 in the pixel block 10 are each rewritten.

  Next, a description will be given from the viewpoint of what happens to the liquid crystal element 50 when each data bit is held in each pixel circuit 20 in this way. First, in the memory circuit 30 of the pixel circuit 20, when the terminal Q is held at the L level (that is, when the H level is held at the terminal / Q), the transmission gates 42 and 44 are turned off and on, respectively. A signal Voff having the same logical relationship as that of the common electrode 108 is applied to the pixel electrode 118 of the pixel. For this reason, as shown in FIG. 3B, the voltage VLC applied to the liquid crystal element 50, here, the potential of the pixel electrode 118 with reference to the potential of the common electrode 108 becomes zero. In the black mode, the pixel is turned off.

  On the other hand, in the memory circuit 30 of the pixel circuit 20, when the terminal Q is held at the H level (that is, when the L level is held at the terminal / Q), the transmission gates 42 and 44 are turned on and off, respectively. A signal Von having a logic inversion relationship with the common electrode 108 is applied to the pixel electrode 118 of the pixel. For this reason, as shown in FIG. 3B, the voltage VLC applied to the liquid crystal element 50 is + Vdd or −Vdd. Therefore, in the normally black mode, the pixel is turned on. .

  Such ON or OFF display is executed in each pixel circuit 20 in accordance with the holding state of the memory circuit 30, and a predetermined image is displayed. In addition, since data bits are stored in the memory circuit 30 during a period in which data is not rewritten, refreshing is not necessary if a still image is displayed, so that the drive circuit and the like need not be operated. , Low power consumption can be achieved.

  Further, the data bit in the memory circuit 30 is rewritten in units of the pixel block 10 corresponding to the intersection of the X selection line 211 and the Y selection line 311. Further, except for the pixel block 10 designated by the address, the terminals Q and / Q of the memory circuit 30 are electrically disconnected from the bit line 215 and the complementary bit line 216, respectively, so that the content held in the memory circuit 30 is the bit line. 215 and the complementary bit line 216 can be prevented from being affected by noise. Furthermore, in this embodiment, the X control circuit 112, the data supply circuit 114, and the Y control circuit 116 are combined as a timing control circuit 110 that is one functional block, so the size of the element substrate 310 in the X direction is reduced. It is possible.

  In the present embodiment, the number of the pixel circuits 20 included in the pixel block 10 is four, but a plurality of other pixel circuits or a single one may be used. The timing control circuit 110, the X address decoder 120, the sample and hold circuit 130, the Y address decoder 140, and the buffer group 150 are all formed on the element substrate by the polysilicon process together with the constituent elements in the pixel block 10. The present invention is also applicable when these are mounted on an element substrate as an IC chip. The level of the signal LCcom is inverted at a period of one frame. The reason for the level inversion of the signal LCcom is only to drive the liquid crystal element 50 with an alternating current. Therefore, for example, the level of the signal LCcom may be inverted at a period of 2 frames or more. The upper control circuit is configured to supply the inverted data bit together with the data bit, but may be configured to separately provide a NOT circuit that logically inverts the data bit while supplying only the data bit. Although the liquid crystal element 50 is in the normally black mode, it may be in a normally white mode that is dark when no voltage is applied. For the sake of simplification of description, the binary display of on / off is used. However, each pixel circuit 20 corresponds to, for example, the three primary colors RGB, RGB,. It may be configured to display eight colors that are turned on and off. Further, a dynamic type may be adopted for the memory circuit.

(Configuration of element substrate 310)
FIG. 4 is a plan view showing a circuit arrangement on the element substrate 310 used in the electro-optical device 100 of the present embodiment. As shown in FIGS. 1A, 1B, 1C, and 4, the central region of the element substrate 310 is a pixel region 310a in which a plurality of pixels 100a including pixel electrodes 118 are formed in a matrix. It has become. In the pixel area 310a, a dummy pixel may be formed in an area overlapping with the light shielding film 108 as a frame. In this case, an area excluding the dummy pixel in the pixel area 310a is used as the display area 100a. It will be.

  The element substrate 310 has a rectangular shape whose longitudinal direction is the X direction, and a plurality of connection terminals 102 are provided along the X direction on one side in the longitudinal direction. On one side, the electrostatic protection circuit 190 and the first circuit region 101 are arranged along the X direction in order from the direction close to the terminal 102, and further, the first circuit region 101 with the pixel region 310a interposed therebetween. An inspection circuit 160 is arranged on the opposite side to the above. In the first circuit region 101, a timing control circuit 110, an X address decoder 120, and a sample and hold circuit 130 are formed in order from a direction close to the electrostatic protection circuit 190.

  In the element substrate 310, the second circuit region 104 is disposed along the Y direction on one side in the short direction, and the inspection circuit 170 is disposed on the opposite side of the second circuit region 104 across the pixel region 310a. Is arranged. In the second circuit region 104, a Y address decoder 140 and a buffer group 150 are formed in order from the outside.

  In this manner, the terminal 102, the electrostatic protection circuit 190, the first circuit region 101 (the timing control circuit 110, the X address decoder 120, the sample and hold circuit 130), and the second circuit are provided outside the pixel region 310a. A region 104 (Y address decoder 140, buffer group 150) and inspection circuits 160, 170 are formed. The terminal 102, the electrostatic protection circuit 190, the first circuit area 101 (timing control circuit 110, the X address decoder 120, the sample and hold circuit 130), and the second circuit area 104 (Y address decoder 140, buffer group 150). ) And the inspection circuits 160 and 170 are formed in the outer region of the sealing material 107.

  Wirings 72, 74, 76, 78, 80, 82, 84 are formed on the element substrate 20. The wiring 72 transmits data bits and various timing signals supplied from the upper control circuit to the terminal 102 via the flexible wiring board 400 to the timing control circuit 110. The wiring 74 transmits the X address Adx, the clock signal, and the like by the timing control circuit 110 to the X address decoder 120. The wiring 76 extends in the X direction between the X address decoder 120 and the sample and hold circuit 130 by passing the data bit whose timing is adjusted by the timing control circuit 110 through the region where the X address decoder 120 is formed. Connected to the eight signal lines 60. Specifically, the wiring 76 is 8 bits corresponding to 4 bits of the data bits corresponding to the 4 pixel circuits 20 constituting one pixel block 10 and 4 bits of the inverted data bits thereof, The signal lines 60 are connected to the eight wirings 76 in a one-to-one correspondence. As shown in FIG. 3A, the eight signal lines 60 include a bit line 215 and complementary bit lines 216 for the first, second, third, and fourth pixel circuits 20 in each pixel block 10 from the left. Respectively. Then, the data bits and the inverted data bits supplied to the eight signal lines 60 are transferred to the bit line 215 and the complementary bit line 216 of the pixel block 10 corresponding to the column selection signal by the column selection signal that has become H level. Sampled. 3A shows only a partial region of the timing control circuit 110, the X address decoder 120, and the sample and hold circuit 130. Therefore, only four wirings 76 are shown, and four signals are shown. Although only connected to the line 60, in reality, there are eight wirings 76 as described above, and each of the eight signal lines 60 is individually connected. The wiring 78 feeds the power supply voltage supplied to the terminal 102 to the Y address decoder 140, and the wiring 80 transmits the Y address Ady, the clock signal, and the like by the timing control circuit 110 to the Y address decoder 140.

  The inspection circuits 160 and 170 are connected to the timing control circuit 110, the X address decoder 120, the sample and hold circuit 130, the Y address decoder 140, the buffer group 150, and the pixels in the display area 100 before the element substrate 310 and the counter substrate 320 are bonded to each other. The block 10 is a circuit for checking whether or not the function is electrically normal. Therefore, the inspection circuit 160 is connected to the X selection line 211, the bit line, and the complementary bit line, respectively, while the inspection circuit 170 is connected to the other end of the Y selection line 311 to output the inspection output signal. Is output from the terminal 102 via the wiring 82.

  An inter-substrate conduction electrode 182 is formed outside the display region 100 a and at a diagonal position on the element substrate 310. The inter-substrate conduction electrode 182 is for applying the signal LCcom to the common electrode 108 formed on the counter substrate 320. Specifically, the element substrate 310 is bonded to the counter substrate 320 by the sealing material 107. At this time, the element substrate 310 is interposed between the substrates through the conductive material provided in the region corresponding to the inter-substrate conductive electrode 182. Electrical connection between the conducting electrode 182 and the common electrode 108 is achieved. Since the inter-substrate conduction electrode 182 is connected to the terminal 102 via the wiring 84, the signal LCcom is applied to the common electrode 108 via the terminal 102 provided on the element substrate 310. .

(Configuration of electrostatic protection circuit 190)
5A, 5B, 5C, and 5D are each a circuit diagram of an electrostatic protection circuit 190 used in the electro-optical device 100 to which the present invention is applied, a circuit diagram illustrating an example thereof, 2 is a cross-sectional view of a protection circuit 190 and a cross-sectional view of a pixel 100b.

  In this embodiment, when electrostatic discharge occurs during assembly of the liquid crystal panel 300, non-operation such as transportation, or operation in which power is supplied, each circuit may be destroyed or deteriorated. Therefore, an electrostatic protection circuit 190 is formed on the element substrate 310 for the wiring 72 that connects the terminal 102 and the timing control circuit 110.

  As shown in FIG. 5A, a high potential line 6s and a low potential line 6t are routed through the electrostatic protection circuit 190, and a diode element 41 is provided between the wiring 72 and the high potential line 6s. The diode element 42 is inserted between the wiring 72 and the low potential line 6t. Of the two diode elements 41 and 42, the diode element 41 has an anode side electrically connected to the wiring 72 and a cathode side electrically connected to the high potential line 6s. On the other hand, the diode element 42 has a cathode side electrically connected to the wiring 72 and an anode side electrically connected to the low potential line 6t. In addition, it is preferable that a resistor (not shown) for suppressing an inrush current value to the diode elements 41 and 42 is interposed in a wiring portion located between the diode elements 41 and 42.

  The diode elements 41 and 42 can be constituted by PIN junction type diodes or MOS type diodes in which TFTs are diode-connected. FIGS. 5B and 5C show MOS type in which N-type TFTs are diode-connected. An example using a diode is shown. Such a MOS type diode has substantially the same structure as the complementary TFT formed in each pixel 100b, and the MOS type diode and the complementary TFT are formed at the same time using the mutual process. Therefore, the configuration of the electrostatic protection circuit 190 will be described below, and the configuration of complementary TFTs (P-channel TFT 80 and N-channel TFT 90) formed in each pixel 100b will be described.

  As shown in FIGS. 5C and 5D, the element substrate 310 is provided with a base protective film 12 made of a silicon oxide film or the like on the surface of the translucent substrate 310d, and a diode element on the surface side thereof. Semiconductor layers 1a and 1b for forming 41 and 42, and semiconductor layers 1h and 1m for forming complementary TFTs (P-channel TFT 80 and N-channel TFT 90) are formed in an island shape, respectively. Yes. A gate insulating film 2 is formed on the surface side of the semiconductor layers 1a, 1b, 1h, and 1m. Gate electrodes 3a, 3b, and 3e are formed on the surface of the gate insulating film 2, and interlayer insulating films 4 and 7 are formed on the upper layer side of the gate electrodes 3a, 3b, and 3e.

  The semiconductor layers 1a, 1b, 1h, and 1m are polysilicon films that are polycrystallized by laser annealing or lamp annealing after an amorphous silicon film is formed on the element substrate 310, for example. Therefore, a glass transparent substrate 310d can be used as the base material of the element substrate 310. Note that a quartz substrate can be used as a base material of the element substrate 310. Further, as the semiconductor layers 1a, 1b, 1h, and 1m, single crystal silicon layers can be used. Such a structure has an SOI (Silicon) in which a quartz substrate and a single crystal silicon substrate are bonded to each other through an insulating layer. On Insulator) substrate can be used. Such an SOI substrate is formed by, for example, a method in which a silicon oxide film is formed on a single crystal silicon substrate and bonded to a quartz substrate, or a silicon oxide film is formed on both a quartz substrate and a single crystal silicon substrate and then silicon. A method in which the oxide films are brought into contact with each other and bonded can be employed. When such a substrate is used, the gate insulating layer 2 can be formed by a thermal oxide film for the semiconductor layer.

  The semiconductor layers 1a, 1d, 1h and 1m are provided with semiconductor regions 1a ', 1d', 1h 'and 1m' at positions facing the gate electrodes 3a, 3b and 3e with the gate insulating film 2 interposed therebetween. Reference numerals 1a ′, 1d ′, 1h ′, and 1m ′ correspond to channel regions. The semiconductor layers 1a, 1d, and 1m are provided with N-type impurity introduction regions 1b, 1c, 1e, 1f, 1n, and 1p on both sides of the semiconductor regions 1a ′, 1d ′, and 1m ′. P-type impurity introduction regions 1i and 1j are provided on both sides of the region 1h '. When complementary TFTs (P-channel TFT 80 and N-channel TFT 90) have an LDD (Lightly Doped Drain) structure, a low concentration impurity introduction region and a high concentration impurity are introduced into the semiconductor layers 1h and 1m as impurity introduction regions. An introduction region is formed.

  As shown in FIG. 5C, in the formation region of the diode elements 41 and 42, the high potential line 6s, the low potential line 6t, and the wiring 72 are formed in the upper layer of the interlayer insulating film 4, and these wirings are respectively These are electrically connected to the impurity introduction regions 1c, 1e, 1b (1f) through contact holes that penetrate the interlayer insulating film 4 and the gate insulating film 2. Further, the high potential line 6s and the low potential line 6t are also electrically connected to the gate electrodes 3a and 3b through contact holes that penetrate the interlayer insulating film 4 in different regions. In this way, the diode elements 41 and 42 (MOS type diodes) are configured.

  As shown in FIG. 5D, in the complementary TFT formation region, the high potential line 6e, the low potential line 6g, and the output wiring 6f are formed in the upper layer of the interlayer insulating film 4, and the high potential line 6e and the low potential line 6f are formed. The potential lines 6g are electrically connected to the source regions (impurity introduction regions 1i and 1p) of the semiconductor layers 1h and 1m through contact holes that penetrate the interlayer insulating film 4 and the gate insulating film 2, respectively. The output wiring 6f is electrically connected to the drain regions (impurity introduction regions 1j, 1n) of the semiconductor layers 1h, 1m through contact holes that penetrate the interlayer insulating film 4 and the gate insulating film 2. Although not shown, the input wiring is connected to the common gate electrode 3 e through a contact hole that penetrates the interlayer insulating film 4. In this manner, complementary TFTs (P-channel TFT 80 and N-channel TFT 90) are formed. In addition, when the formation process of complementary TFTs (P-channel TFT 80 and N-channel TFT 90) is used, the diode elements 41 and 42 can be formed by PIN junction diodes. In each pixel 100b, a pixel electrode 118 is formed on the interlayer insulating film 7, and an alignment film 316 is formed on the surface side thereof. In contrast, the counter substrate 320 includes a light-shielding film 328 (black matrix), a color filter 324, and a planarization film 325 (protective film) on the surface of the light-transmitting substrate 310b that faces the element substrate 310. The common electrode 108 and the alignment film are formed.

(Configuration and manufacturing method of light shielding material of electro-optical device 100)
6A, 6 </ b> B, and 6 </ b> C are process cross-sectional views illustrating a molding material forming process in the electro-optical device manufacturing process to which the present invention is applied. To manufacture the electro-optical device 100 of this embodiment, after forming the liquid crystal panel 300 shown in FIGS. 1A, 1B, and 1C, as shown in FIG. Then, the flexible wiring board 400 is connected by an anisotropic conductive material or the like.

  Next, as shown in FIG. 6B, on the upper surface 310 e side (the inner surface side facing the counter substrate 320) of the element substrate 310, an acrylic resin or the like is straddled across the element substrate 310 and the flexible wiring substrate 400. A UV curable resin composition 410a is applied. In addition, a UV curable resin composition 420a such as an acrylic resin is straddled across the element substrate 310 and the flexible wiring substrate 400 on the lower surface 310f side (the side opposite to the side facing the counter substrate 320) of the element substrate 310. Apply.

  Here, the upper light shielding material 510 is laminated on the upper surface 310 e side of the element substrate 310 in a region overlapping with the electrostatic protection circuit 190, and the electrostatic protection is provided on the lower surface 310 f side of the element substrate 310. A lower light shielding material 520 is stacked in a region overlapping with the circuit 190 at the lower side. In this embodiment, the upper light-shielding material 510 and the lower light-shielding material 520 are arranged in a strip shape in a wide region that also overlaps the first circuit region 101 in addition to the electrostatic protection circuit 190.

As shown in FIG. 5C, the upper light shielding material 510 is formed on the upper layer of the interlayer insulating film 7 that covers the diode elements 41 and 42 of the electrostatic protection circuit 190, such as metal such as Mo, W, Ti, and Cr, TiN, It is laminated as a light shielding film made of a metal compound such as MnO _n , ceramics, or an organic material such as carbon or black resin. Such an upper light shielding material 510 can be formed by a mask sputtering method, a mask vapor deposition method, a printing method, or the like, and can be formed without using a photolithography technique. The lower light shielding material 520 is formed on the lower surface of the element substrate 310 as a light shielding film made of a metal compound such as Mo, W, Ti, or Cr, a metal compound such as TiN, MnO _n , or ceramics, an organic material such as carbon, or a black resin. Are stacked. The lower light shielding material 520 can be formed by a mask sputtering method, a mask vapor deposition method, a printing method, or the like, and can be formed without using a photolithography technique. The lower light shielding material 520 may be formed by applying black ink to the lower surface of the element substrate 310.

  Therefore, according to this embodiment, as indicated by the arrow UV1 in FIG. 6C, the UV curable resin composition 410a is cured by irradiating the UV light on the upper surface 310e side of the element substrate 310, and the upper surface side. When the UV curable molding material 410 is formed, the electrostatic protection circuit 190 is not irradiated with UV light. Further, as indicated by an arrow UV2 in FIG. 6C, the UV curable resin composition 420a is cured by irradiating UV light on the lower surface 310f side of the element substrate 310, thereby lowering the UV curable molding material 420 on the lower surface side. When forming the electrostatic protection circuit 190, UV light is not irradiated.

(Main effects of this form)
As described above, in this embodiment, when forming the upper surface side UV curable mold material 410 and the lower surface side UV curable mold material 420, the resin composition 410a without irradiating the electrostatic protection circuit 190 with UV light, Since 420a is cured, the current-voltage characteristics of the diode elements 41 and 42 provided in the electrostatic protection circuit 190 do not change. Therefore, since it is possible to prevent a wasteful current from flowing through the diode elements 41 and 42, even when the electrostatic protection circuit 190 is provided, an increase in current consumption does not occur.

  In particular, in this embodiment, since the memory circuit 30 is provided in each of the plurality of pixels 100b, the original current consumption is small. Therefore, if the current-voltage characteristics of the diode elements 41 and 42 change due to UV irradiation and the current consumption increases even slightly, the purpose of providing the memory circuit 30 in each of the plurality of pixels 100b is impaired. According to the embodiment, the original purpose of reducing power consumption can be sufficiently achieved by providing the memory circuit 30 in each of the plurality of pixels 100b.

[Modification of Upper Shading Material 510]
FIGS. 7A, 7 </ b> B, 7 </ b> C, and 7 </ b> D are explanatory diagrams illustrating modifications of the upper light shielding material used in the electro-optical device to which the present invention is applied. In the above embodiment, when forming the upper light shielding material 510, as shown in FIG. 5C, the light shielding film is laminated on the upper layer of the interlayer insulating film 7, but for example, as shown in FIG. The substrate 320 is extended to a position where it overlaps the electrostatic protection circuit 190, and a metal such as Mo, W, Ti, Cr, TiN, MnO _n , ceramics on the outer surface side (the surface opposite to the side facing the element substrate 310). You may laminate | stack the light shielding film which consists of organic materials, such as metal compounds, such as carbon, or black resin. Such an upper light shielding material 510 can be formed by a mask sputtering method, a mask vapor deposition method, a printing method, or the like, and can be formed without using a photolithography technique. The upper light shielding material 510 may be formed by applying black ink to the outer surface of the counter substrate 320.

Further, as shown in FIG. 7B, the counter substrate 320 is extended to a position where it overlaps with the electrostatic protection circuit 190, and an upper light shielding material 510 is formed on the inner surface side (the surface facing the element substrate 310). Also good. In this case, as the upper light shielding material 510, a light shielding film made of a metal such as Mo, W, Ti, or Cr, a metal compound such as TiN, MnO _n , or ceramics, an organic material such as carbon or black resin, or the like is used. it can. At this time, if the upper light shielding material 510 is formed simultaneously with the light shielding layers 308 and 323, the upper light shielding material 510 can be formed without adding a new process.

  As shown in FIGS. 7A and 7B, when the counter substrate 320 is extended to a position where it overlaps the electrostatic protection circuit 190, as shown in FIGS. 7C and 7D, the electrostatic protection is performed. The sealing material 107 may be formed at a position overlapping with the circuit 190.

[Modification of Lower Shading Material 520]
FIGS. 8A and 8B are explanatory views showing modifications of the lower light shielding material used in the electro-optical device to which the present invention is applied. In the above embodiment, when forming the lower light shielding material 520, the light shielding film is laminated on the lower surface 310f of the element substrate 310 as shown in FIG. 5C. However, as shown in FIG. On the upper surface 310e, a light shielding film may be formed on the lower layer side of the electrostatic protection circuit 190. For example, as shown in FIG. 8B, among the lower layers of the diode elements 41 and 42 of the electrostatic protection circuit 190, Mo, W, Ti, Cr, etc. are provided between the base protective film 12 and the translucent substrate 310b. A light shielding film made of a metal compound such as TiN, MnO _n , a ceramic compound such as ceramics, an organic material such as carbon or black resin, or the like may be formed as the lower light shielding material 520. The lower light shielding material 520 can be formed by a mask sputtering method, a mask vapor deposition method, a printing method, or the like, and can be formed without using a photolithography technique.

(Modification of reinforcement structure)
In the above embodiment, the upper surface side UV curable mold material 410 and the lower surface side UV curable mold material 420 are formed on both surfaces of the element substrate 310, but only the upper surface side UV curable mold material 410 may be formed. In this case, only the upper light shielding material 510 may be formed. When such a configuration is adopted, on the lower surface side, a mold material other than the UV curable mold material (room temperature curable mold material, heat curable mold material, visible light curable mold material, etc.), other Either a reinforcing means is taken or a configuration without reinforcing is adopted. Such a configuration is a configuration that should be adopted regardless of whether or not the base material of the element substrate 310 has translucency.

  Further, only the lower surface side UV curable molding material 420 may be formed. In this case, only the lower light shielding material 520 may be formed. In addition, when such a configuration is adopted, the upper surface side is made of a mold material other than the UV curable mold material (room temperature curable mold material, heat curable mold material, visible light curable mold material, etc.), other Either a reinforcing means is taken or a configuration without reinforcing is adopted. Such a configuration is a configuration that should be adopted when the base material of the element substrate 310 has translucency.

[Other embodiments]
In the above embodiment, the present invention is applied to the electro-optical device 100 having the circuit configuration described with reference to FIGS. 2 to 4. However, the electro-optical device includes other memory circuits in each pixel 100 b. The present invention may be applied to 100. Even in the electro-optical device 100 that does not include the memory circuit in each pixel 100b, the power consumption can be reduced by applying the present invention.

  In the above embodiment, the transmissive electro-optical device 100 has been described as an example. However, the present invention may be applied to a reflective or transflective electro-optical device 100. When such a configuration is employed, a light reflecting layer is formed on the element substrate 310 or the counter substrate 320. Therefore, by forming the light reflection layer in a region overlapping with the electrostatic protection circuit 190, the electrostatic protection circuit 190 may be prevented from being irradiated with UV light when the sealing material 107 is formed. In the case of a reflective liquid crystal device, a single crystal silicon substrate may be used as the base material of the element substrate 310. Furthermore, as a base material of the element substrate 310 or the counter substrate 320, a rigid substrate such as a glass substrate, a quartz substrate, or a single crystal silicon substrate, a substrate that has been made thin to give flexibility, a plastic substrate, or the like Alternatively, a flexible substrate may be used.

  In the above embodiment, a TN type liquid crystal is used. However, a dye (guest) having anisotropy in absorption of visible light in a major axis direction and a minor axis direction of a molecule such as an STN type liquid crystal having a certain molecular arrangement ( Alternatively, a guest-host type liquid crystal in which dye molecules are aligned in parallel with liquid crystal molecules may be used. In addition, a vertical alignment (homeotropic alignment) configuration is adopted in which liquid crystal molecules are aligned vertically to both substrates when no voltage is applied, while liquid crystal molecules are aligned horizontally to both substrates when voltage is applied. May be. Further, the present invention may be applied to a liquid crystal device (electro-optical device) in an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. In this case, the common electrode 108 is similar to the pixel electrode 118 in the same manner. It is formed on the element substrate 310.

  In the above embodiment, the liquid crystal device has been described as the electro-optical device 100. However, the present invention is applied to an electro-optical device using an organic EL (electroluminescence) element, an electrophoretic element, an electron-emitting element, a plasma display element, or the like. Also good.

[Example of mounting on electronic devices]
Next, an electronic apparatus to which the electro-optical device 100 according to the above-described embodiment is applied will be described. FIG. 9A shows a configuration of a mobile personal computer including the electro-optical device 100. The personal computer 2000 includes an electro-optical device 100 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. FIG. 9B shows a configuration of a mobile phone provided with the electro-optical device 100. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled. FIG. 9C shows the configuration of a personal digital assistant (PDA) to which the electro-optical device 100 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 as a display unit. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 100.

  As an electronic apparatus to which the electro-optical device 100 is applied, in addition to those shown in FIG. 9, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, Examples include calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. The electro-optical device 100 described above can be applied as a display unit of these various electronic devices. In the projection display device, the electro-optical device 100 (liquid crystal device) may be used as a light valve.

(A), (b), and (c) are each a plan view of the electro-optical device to which the present invention is applied as viewed from the side of the counter substrate together with each component, a bottom view as viewed from the element substrate side, and HH thereof. It is a cross-sectional view. FIGS. 2A and 2B are a block diagram illustrating an electrical configuration of the electro-optical device illustrated in FIG. 1 and a circuit diagram of a pixel circuit. (A), (b) is the elements on larger scale of the electro-optical apparatus shown in FIG. 1, and explanatory drawing which shows the write-in operation | movement with respect to a memory circuit. It is a top view which shows the circuit arrangement | positioning in the element substrate shown in FIG. (A), (b), (b), (d) is a circuit diagram of an electrostatic protection circuit used in the electro-optical device shown in FIG. 1, a circuit diagram showing an example thereof, and a sectional view of the electrostatic protection circuit. FIG. 3 is a cross-sectional view of a pixel. (A), (b), (c) is process sectional drawing which shows a mold material formation process among the manufacturing processes of the electro-optical apparatus to which this invention is applied, respectively. It is explanatory drawing which shows the modification of the upper light shielding material used for the electro-optical apparatus to which this invention is applied. It is explanatory drawing which shows the modification of the downward light shielding material used for the electro-optical apparatus to which this invention is applied. It is explanatory drawing of the electronic device using the electro-optical apparatus which concerns on this invention.

Explanation of symbols

10..Pixel block, 20..Pixel circuit, 30..Memory circuit, 41, 42..Diode element for electrostatic protection, 50..Liquid crystal element, 100..Electro-optical device, 100a..Image display area 100b..Pixel, 102..Terminal, 190..Static protection circuit, 300..Panel, 310..Element substrate, 310a..Pixel region, 310e..Top surface of element substrate, 310f..Element substrate Lower surface, 320, .. counter substrate, 410, upper surface side UV curable mold material, 420, upper surface side UV curable mold material, 410a, 420a, UV curable resin composition, 510, upper light shielding material, 520 ..Lower light shielding material,

Claims (12)

In an electro-optical device including an element substrate in which a plurality of pixels each including a pixel electrode are arranged, and on the upper surface side where the pixel electrode is formed on the element substrate, the terminal to which a flexible wiring substrate is connected is formed.
On the upper surface side of the element substrate, an electrostatic protection circuit including a diode element is formed in an area adjacent to the terminal formation area,
On the upper surface side of the element substrate, an upper surface side UV curable mold material is formed so as to straddle the element substrate and the flexible wiring substrate,
An electro-optical device, wherein an upper light shielding material is disposed in a region overlapping above the electrostatic protection circuit. In an electro-optical device including an element substrate in which a plurality of pixels each including a pixel electrode are arranged, and on the upper surface side where the pixel electrode is formed on the element substrate, the terminal to which a flexible wiring substrate is connected is formed.
On the upper surface side of the element substrate, an electrostatic protection circuit including a diode element is formed in an area adjacent to the terminal formation area,
In the element substrate, the base material is a translucent substrate,
On the lower surface side of the element substrate, a lower surface side UV curable mold material is formed so as to straddle the element substrate and the flexible wiring substrate,
An electro-optical device, wherein a lower light shielding material is disposed in a region overlapping with the electrostatic protection circuit below. In an electro-optical device including an element substrate in which a plurality of pixels each including a pixel electrode are arranged, and on the upper surface side where the pixel electrode is formed on the element substrate, the terminal to which a flexible wiring substrate is connected is formed.
On the upper surface side of the element substrate, an electrostatic protection circuit including a diode element is formed in an area adjacent to the terminal formation area,
In the element substrate, the base material is a translucent substrate,
On the upper surface side of the element substrate, an upper surface side UV curable molding material is formed so as to straddle the element substrate and the flexible wiring substrate, and on the lower surface side of the element substrate, the element substrate and the flexible wiring are formed. A lower surface side UV curable molding material is formed so as to straddle the substrate,
An upper light shielding material is disposed in a region overlapping above the electrostatic protection circuit, and a lower light shielding material is disposed in a region overlapping below the electrostatic protection circuit. An electro-optical device.   4. The electro-optical device according to claim 1, wherein the upper light shielding member is laminated on an upper layer of the electrostatic protection circuit in the element substrate. Comprising a counter substrate oriented with respect to the element substrate;
The electro-optical device according to claim 1, wherein the upper light shielding material is formed in a region overlapping the electrostatic protection circuit in the counter substrate. On the lower surface of the counter substrate facing the element substrate, a stripe-shaped or lattice-shaped light shielding pattern is formed in a region overlapping the pixel region,
The electro-optical device according to claim 5, wherein the upper light shielding material is formed of the same material as the light shielding pattern on a lower surface of the counter substrate.   The electro-optical device according to claim 2, wherein the lower light-shielding material is disposed on a lower surface side of the element substrate.   The electro-optical device according to claim 2, wherein the lower light shielding material is formed on a lower layer side of the electrostatic protection circuit on an upper surface side of the element substrate.   The electro-optical device according to claim 1, wherein the upper light shielding material includes at least one of a metal, a metal compound, carbon, and an organic material.   The electro-optical device according to claim 2, 3, 7, or 8, wherein the lower light shielding material includes at least one of a metal, a metal compound, carbon, and an organic material.   11. The electro-optical device according to claim 1, wherein a storage element is formed in each of the plurality of pixels in the element substrate.   The electro-optical device according to claim 1, further comprising a liquid crystal layer on an upper surface side of the element substrate.

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