JP2008227537A - Method for fabricating wiring board, and the same - Google Patents

Method for fabricating wiring board, and the same Download PDF

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JP2008227537A
JP2008227537A JP2008126083A JP2008126083A JP2008227537A JP 2008227537 A JP2008227537 A JP 2008227537A JP 2008126083 A JP2008126083 A JP 2008126083A JP 2008126083 A JP2008126083 A JP 2008126083A JP 2008227537 A JP2008227537 A JP 2008227537A
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metal foil
wiring
dielectric sheet
conductor
wiring board
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JP4203536B2 (en
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Tatsuya Ito
達也 伊藤
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for easily fabricating wiring board that is formed by alternately laminating a dielectric material layer formed of a polymer material and a conductive layer without use of a core board and also to provide a wiring board obtained with the same method. <P>SOLUTION: On the principal front surface of a lower dielectric material layer 21 formed on a supporting board 20 for reinforcement in the fabrication process, a laminated sheet 10 is formed with inclusion of a metal foil contact body 5 formed of a pair of metal foils 5a, 5b provided in close contact state, a first dielectric material sheet 11 sealing the metal foil contact body 5 through close contact with a lower dielectric material layer 21 at the peripheral region 21c of the metal foil contact body 5, a first conductor layer 31, and a first via conductor 41 formed through the first dielectric material sheet 11. A region on the metal foil contact body 5 of the laminated sheet 10 is defined as a wiring lamination part 100 to become the wiring board and the peripheral part of such region is removed and the wiring lamination part 100 is separated at the interface of a pair of metal foils 5a, 5b under the condition that only one metal foil 5b is adhered thereto. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、コア基板を有さない配線基板、及びその製造方法に関する。 The present invention relates to a wiring board that does not have a core substrate, and a method for manufacturing the wiring board.

近年、電子機器における高機能化並びに軽薄短小化の要求により、ＩＣチップやＬＳＩ等の電子部品では高密度集積化が急速に進んでおり、これに伴い、電子部品を搭載するパッケージ基板には、従来にも増して高密度配線化及び多端子化が求められている。 In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

このようなパッケージ基板としては、現状において、ビルドアップ多層配線基板が採用されている。ビルドアップ多層配線基板とは、補強繊維に樹脂を含浸させた絶縁性のコア基板（ＦＲ−４等のガラスエポキシ基板）のリジッド性を利用し、その両主表面上に、高分子材料からなる誘電体層と導体層とが交互に配されたビルドアップ層を形成したものである。このようなビルドアップ多層配線基板では、ビルドアップ層において高密度配線化が実現されており、一方、コア基板は補強の役割を果たす。そのため、コア基板は、ビルドアップ層と比べて非常に厚く構成され、またその内部にはそれぞれの主表面に配されたビルドアップ層間の導通を図るための配線（例えば、スルーホール導体と呼ばれる）が厚さ方向に貫通形成されている。ところが、使用する信号周波数が１ＧＨｚを超える高周波帯域となってきた現在では、そのような厚いコア基板を貫通する配線は、大きなインダクタンスとして寄与してしまうという問題があった。 As such a package substrate, a build-up multilayer wiring substrate is currently used. The build-up multilayer wiring board uses a rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and is made of a polymer material on both main surfaces thereof. A build-up layer in which dielectric layers and conductor layers are alternately arranged is formed. In such a build-up multilayer wiring board, high-density wiring is realized in the build-up layer, while the core board plays a reinforcing role. For this reason, the core substrate is configured to be very thick compared to the buildup layer, and the wiring inside it (for example, referred to as a through-hole conductor) for establishing conduction between the buildup layers disposed on the respective main surfaces Are formed penetrating in the thickness direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring penetrating such a thick core substrate contributes as a large inductance.

そこで、そのような問題を解決するため、特許文献１に示されるような、コア基板を有さず、高密度配線化が可能なビルドアップ層を主体とした配線基板が提案されている。このような配線基板では、コア基板が省略されているため、全体の配線長が短く構成され、高周波用途に供するのに好適である。このような配線基板を製造するためには、段落００１２〜００２９及び図１〜４に記載されているように、金属板上にビルドアップ層を形成した後、該金属板をエッチングすることにより薄膜のビルドアップ層のみを得る。そして、このビルドアップ層が配線基板とされる。 Therefore, in order to solve such a problem, there has been proposed a wiring board mainly composed of a build-up layer that does not have a core board and can be formed with high density wiring, as shown in Patent Document 1. In such a wiring board, since the core board is omitted, the entire wiring length is short, which is suitable for high-frequency applications. In order to manufacture such a wiring board, as described in paragraphs 0012 to 0029 and FIGS. 1 to 4, a thin film is formed by forming a buildup layer on a metal plate and then etching the metal plate. Only get the build-up layer. This build-up layer is used as a wiring board.

特開２００２−２６１７１号公報JP 2002-26171 A

しかし、特許文献１に記載された製造方法の場合、ビルドアップ層が形成される金属板は、製造時における補強の役割を担うことが可能な程度の厚さ（例えば、銅板にして０．８ｍｍ程度）に設定されるが、ビルドアップ層を形成後にそれを全てエッチングすることは、時間が掛かり過ぎる（例えば、銅板０．８ｍｍに対して３０分程度）など工程上の無駄が多いという問題があった。 However, in the case of the manufacturing method described in Patent Document 1, the metal plate on which the build-up layer is formed has a thickness that can play a reinforcing role at the time of manufacturing (for example, 0.8 mm in the case of a copper plate). However, it takes too much time (for example, about 30 minutes for a copper plate of 0.8 mm) to etch all of the build-up layer after forming it. there were.

そこで、本発明では、コア基板を有さず、高分子材料からなる誘電体層と導体層とが交互に積層された配線基板を容易に得ることが可能な製造方法と、それにより得られる信頼性の高い配線基板を提供することを課題とする。 Therefore, in the present invention, a manufacturing method capable of easily obtaining a wiring board in which dielectric layers and conductor layers made of a polymer material are alternately laminated without having a core substrate, and the reliability obtained thereby. It is an object to provide a wiring board with high performance.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

上記課題を解決するため、本発明の配線基板の製造方法では、コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層された配線基板を製造するために、製造時における補強のための支持基板上に形成された下地誘電体シートの主表面上に、該主表面に包含されるよう配された、分離可能な２つの金属箔が密着してなる金属箔密着体と、該金属箔密着体を包むよう形成され、かつ該金属箔密着体の周囲領域にて下地誘電体シートと密着して該金属箔密着体を封止する第一誘電体シートと、該第一誘電体シート上に形成された第一導体層と、該第一導体層と金属箔密着体とを接続する第一誘電体シートに貫通形成された第一ビア導体と、を有する積層シート体を形成するとともに、積層シート体のうち、金属箔密着体上の領域を配線基板となるべき配線積層部として、その周囲部を除去し、該配線積層部の端面を露出させた後、配線積層部を支持基板から、片方の金属箔が付着した状態で、金属箔密着体における２つの金属箔の界面にて剥離することを特徴とする。 In order to solve the above-mentioned problems, in the method for manufacturing a wiring board according to the present invention, a dielectric layer and a conductor layer made of a polymer material so as not to have a core substrate and both main surfaces are composed of dielectric layers. In order to manufacture a wiring board in which and are alternately laminated, on the main surface of a base dielectric sheet formed on a support substrate for reinforcement at the time of manufacture, it is arranged to be included in the main surface A metal foil adhesion body in which two separable metal foils are in close contact with each other, and a metal foil adhesion body formed so as to wrap around the metal foil adhesion body, and in close contact with the underlying dielectric sheet in the peripheral region of the metal foil adhesion body A first dielectric sheet for sealing the metal foil adhesion body, a first conductor layer formed on the first dielectric sheet, and a first dielectric for connecting the first conductor layer and the metal foil adhesion body And forming a laminated sheet body having a first via conductor formed through the sheet Of the laminated sheet body, a region on the metal foil adhesion body is used as a wiring laminated portion to be a wiring substrate, and the peripheral portion is removed and the end surface of the wiring laminated portion is exposed, and then the wiring laminated portion is removed from the support substrate. The metal foil is peeled off at the interface between the two metal foils in the metal foil adhesion body with one metal foil attached.

上記本発明によると、本発明の配線基板の製造方法は、図１を参照して簡略に説明すると、（ａ）支持基板２０（特許文献１における金属板に該当する）上に形成された下地誘電体シート２１上に、配線基板となるべき配線積層部１００（図２参照）を含有する積層シート体１０を形成し、（ｂ）積層シート体１０のうち配線積層部１００の周囲部（図中の破線部）を除去することにより、配線積層部１００の端面１０３を露出させて、（ｃ）配線積層部１００を支持基板２０（及び下地誘電体シート２１）から剥離する。このように、配線積層部と支持基板との分離を剥離により行うことで、容易に配線基板を得ることが可能となっている。また、配線積層部と支持基板との分離をエッチングにより行わないため、支持基板の両主表面に積層シート体を形成することもでき、ひいては配線基板の量産が可能となる。 According to the present invention, the method for manufacturing a wiring board according to the present invention will be briefly described with reference to FIG. 1. (a) A base formed on a support substrate 20 (corresponding to a metal plate in Patent Document 1). On the dielectric sheet 21, a laminated sheet body 10 containing a wiring laminated portion 100 (see FIG. 2) to be a wiring substrate is formed, and (b) a peripheral portion of the wiring laminated portion 100 (see FIG. 2). The end surface 103 of the wiring laminated portion 100 is exposed by removing the inner broken line portion), and (c) the wiring laminated portion 100 is peeled from the support substrate 20 (and the underlying dielectric sheet 21). As described above, the wiring substrate can be easily obtained by separating the wiring laminated portion and the supporting substrate by peeling. In addition, since the wiring laminated portion and the support substrate are not separated by etching, a laminated sheet body can be formed on both main surfaces of the support substrate, which enables mass production of the wiring substrate.

以下、図１のそれぞれの工程に関して詳細な説明を行う。図１（ａ）では、支持基板２０上に形成された下地誘電体シート２１上に、配線基板となるべき配線積層部１００（図２参照：詳細は後述）を含有する積層シート体１０が形成されている。積層シート体１０では、下地誘電体シート２１の主表面に包含されるように、分離可能な２つの金属箔５ａ、５ｂが密着してなる金属箔密着体５が配され、該金属箔密着体５を包むように第一誘電体シート１１が配されている。なお、積層シート体１０は、この他に、第一誘電体シート１１上に形成された第一導体層３１と、該第一導体層３１と金属箔密着体５とを接続する第一誘電体シート１１に貫通形成された第一ビア導体４１と、も有するが、これらに関しては後述する。そして、該金属箔密着体５を包むよう形成された第一誘電体シート１１は、金属箔密着体５（上側金属箔５ｂ）に密着するとともに、金属箔密着体５の周囲領域２１ｃにて下地誘電体シート２１と密着しており、これによって、金属箔密着体５は第一誘電体シート１１に封止された状態とされている。 Hereinafter, detailed description will be given with respect to each step of FIG. In FIG. 1A, a laminated sheet body 10 containing a wiring laminated portion 100 (see FIG. 2; details will be described later) to be a wiring board is formed on a base dielectric sheet 21 formed on a support substrate 20. Has been. In the laminated sheet body 10, a metal foil adhesion body 5 formed by adhering two separable metal foils 5 a and 5 b is disposed so as to be included in the main surface of the base dielectric sheet 21, and the metal foil adhesion body First dielectric sheet 11 is arranged so as to wrap 5. In addition, the laminated sheet body 10 includes, in addition, a first conductor layer 31 formed on the first dielectric sheet 11, and a first dielectric body that connects the first conductor layer 31 and the metal foil adhesion body 5. The first via conductor 41 is formed through the sheet 11 and will be described later. The first dielectric sheet 11 formed so as to wrap the metal foil adhesion body 5 is in close contact with the metal foil adhesion body 5 (upper metal foil 5b) and is grounded in the peripheral region 21c of the metal foil adhesion body 5. It is in close contact with the dielectric sheet 21, whereby the metal foil contact body 5 is sealed with the first dielectric sheet 11.

このように金属箔密着体５が第一誘電体シート１１に封止されていることにより、金属箔密着体５（下側金属箔５ａ）と下地誘電体シート２１との界面に膨れや剥れが生じることなく、積層シート体１０を形成することができる。そしてその後、図１（ｂ）において、第一誘電体シート１１と下地誘電体シート２１とが密着している周囲領域２１ｃが除去されるので、図１（ｃ）において、金属箔密着体５の界面で配線積層部１００の剥離を容易に行うことが可能となる。つまり、このように構成することにより、密着性が要求される積層シート体の形成（図１（ａ））と、剥離容易性が要求される配線積層部の剥離（図１（ｃ））とを、どちらも良好に行うことが可能となる。 Thus, the metal foil adhesion body 5 is sealed by the first dielectric sheet 11, so that the interface between the metal foil adhesion body 5 (lower metal foil 5 a) and the base dielectric sheet 21 swells or peels off. The laminated sheet body 10 can be formed without the occurrence of. Then, in FIG. 1B, since the peripheral region 21c where the first dielectric sheet 11 and the base dielectric sheet 21 are in close contact with each other is removed, in FIG. It becomes possible to easily peel off the wiring laminated portion 100 at the interface. That is, with this configuration, formation of a laminated sheet body that requires adhesion (FIG. 1 (a)) and separation of a wiring laminate portion that requires ease of peeling (FIG. 1 (c)). Both can be performed satisfactorily.

なお、図２に示すように、積層シート体１０のうち、金属箔密着体５上の領域は、配線積層部１００とされている。配線積層部１００は、図１（ｃ）の剥離により上側金属箔５ｂが付着した状態で得られ、その後配線基板となるべきものである。すなわち、コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層された構造を有する（詳細な構造については後述する）。 As shown in FIG. 2, a region on the metal foil adhesion body 5 in the laminated sheet body 10 is a wiring laminated portion 100. The wiring laminated portion 100 is obtained in a state where the upper metal foil 5b is adhered by the peeling of FIG. In other words, it has a structure in which dielectric layers and conductor layers made of a polymer material are alternately laminated so as not to have a core substrate and both main surfaces are composed of dielectric layers (detailed structure) Will be described later).

また、積層シート体１０の形態は、配線積層部１００（金属箔密着体５上の領域）を有していればよく、図１（ａ）の形態に限定されない。例えば、図３（ａ）のように、金属箔密着体５上に誘電体シート１１１、１１２が配され、それらをまとめて第一誘電体シート１１が封止する形態であってもよい。なお、この場合、最下層の誘電体シート１１に形成され、金属箔密着体５に接続されるビア導体を第一ビア導体４１とし、第一誘電体シート１１上に形成された導体層を第一導体層３１として、その間には導体層及びビア導体が配される。また、図３（ｂ）のように、第一誘電体シート１１上に形成される他の誘電体シートが、配線積層部１００となる部分のみにより構成されていてもよい。 Moreover, the form of the lamination sheet body 10 should just have the wiring lamination | stacking part 100 (area | region on the metal foil contact | adherence body 5), and is not limited to the form of Fig.1 (a). For example, as shown in FIG. 3A, a configuration in which the dielectric sheets 111 and 112 are arranged on the metal foil adhesion body 5 and the first dielectric sheet 11 is sealed together may be employed. In this case, the via conductor formed on the lowermost dielectric sheet 11 and connected to the metal foil adhesion body 5 is a first via conductor 41, and the conductor layer formed on the first dielectric sheet 11 is a first conductor layer. As one conductor layer 31, a conductor layer and a via conductor are disposed therebetween. Further, as shown in FIG. 3B, another dielectric sheet formed on the first dielectric sheet 11 may be configured only by a portion that becomes the wiring laminated portion 100.

次に、図１（ｂ）では、積層シート体１０のうち、配線積層部１００の周囲部（図中の破線部）を除去し、該配線積層部１００の端面１０３を露出させる。つまり、第一誘電体シート１１と下地誘電体シート２１とが密着している周囲領域２１ｃが取り除かれ、金属箔密着体５の端面が露出することになる。これにより、図１（ｃ）のように、配線積層部１００を支持基板２０から、金属箔密着体５の界面（すなわち、下側金属箔５ａと上側金属箔５ｂとの界面）にて容易に剥離することができる。なお、積層シート体１０において配線積層部１００の周囲部（図中の破線部）を除去する際、該周囲部とともに、支持基板２０及び下地誘電体シート２１の該周囲部下にあたる領域も除去するようにすれば、配線積層部１００の端面１０３の露出が容易に行うことができる。 Next, in FIG.1 (b), the surrounding part (dashed line part in a figure) of the wiring lamination | stacking part 100 is removed among the lamination sheet bodies 10, and the end surface 103 of this wiring lamination | stacking part 100 is exposed. That is, the peripheral region 21c where the first dielectric sheet 11 and the base dielectric sheet 21 are in close contact with each other is removed, and the end face of the metal foil adhesive body 5 is exposed. As a result, as shown in FIG. 1C, the wiring laminated portion 100 can be easily removed from the support substrate 20 at the interface of the metal foil adhesion body 5 (that is, the interface between the lower metal foil 5a and the upper metal foil 5b). Can be peeled off. When removing the peripheral portion (broken line portion in the drawing) of the wiring laminated portion 100 in the laminated sheet body 10, the region under the peripheral portion of the support substrate 20 and the base dielectric sheet 21 is also removed together with the peripheral portion. By doing so, the end surface 103 of the wiring laminated portion 100 can be easily exposed.

また、図１（ｂ）では配線積層部１００の周囲部を除去する際に、第一誘電体シート１１と下地誘電体シート２１とが密着している周囲領域２１ｃを取り除き、金属箔密着体５の端部を露出させることで配線積層部１００の剥離が可能となるが、金属箔密着体５の端部をより確実に露出させるため、図４（ａ）及び（ｂ）に示すように、配線積層部１００を、金属箔密着体５のうち外縁端付近を除いた部分及び該部分上の領域によって構成し、その周囲領域を除去、すなわち金属箔密着体５の外縁端付近も除去するようにすることができる。 Further, in FIG. 1B, when the peripheral portion of the wiring laminated portion 100 is removed, the peripheral region 21c where the first dielectric sheet 11 and the base dielectric sheet 21 are in close contact is removed, and the metal foil adhesive body 5 is removed. As shown in FIGS. 4 (a) and 4 (b), it is possible to peel the wiring laminated portion 100 by exposing the end portion of the metal foil. The wiring laminated portion 100 is constituted by a portion excluding the vicinity of the outer edge of the metal foil adhesion body 5 and a region on the portion, and the peripheral area is removed, that is, the vicinity of the outer edge of the metal foil adhesion body 5 is also removed. Can be.

次に、積層シート体１０は、その他、第一誘電体シート１１上に形成された第一導体層３１と、該第一導体層３１と金属箔密着体５とを接続する第一誘電体シート１１に貫通形成された第一ビア導体４１と、を有する。そのため、図１（ｃ）に示す金属箔５ｂが付着した配線積層体１００は、例えば図１０に示すように、金属端子８を形成するために金属箔５ｂを除去すると、その面に第一導体層３１と接続された第一ビア導体４１を有する開口１１ａが現れ、そこに金属端子８を直接形成することができる。これにより、剥離後の薄く軟らかい配線積層部１００に対して、第一誘電体シート１１´の穿孔したり、その孔を導体（例えば、予備ハンダ）で充填する等の作業を行うことなく金属端子８を形成することが可能となる。 Next, the laminated sheet body 10 includes, in addition, a first dielectric layer 31 formed on the first dielectric sheet 11 and a first dielectric sheet that connects the first conductor layer 31 and the metal foil adhesion body 5. 11 and a first via conductor 41 penetratingly formed. Therefore, in the wiring laminated body 100 to which the metal foil 5b shown in FIG. 1C is attached, for example, as shown in FIG. 10, when the metal foil 5b is removed to form the metal terminal 8, the first conductor is formed on the surface. An opening 11a having a first via conductor 41 connected to the layer 31 appears, and the metal terminal 8 can be directly formed there. As a result, the metal terminals can be formed without performing operations such as perforating the first dielectric sheet 11 ′ and filling the holes with a conductor (for example, spare solder) in the thin and soft wiring laminated portion 100 after peeling. 8 can be formed.

また、図１（ｃ）に示す金属箔５ｂが付着した配線積層体１００は、該金属箔５ｂが第一ビア導体４１を介して第一導体層３１と接続されているので、例えば図１５に示すように、該金属箔５ｂを一部とした金属端子８を形成することもできる。 Further, in the wiring laminate 100 to which the metal foil 5b shown in FIG. 1C is attached, the metal foil 5b is connected to the first conductor layer 31 through the first via conductor 41. As shown, a metal terminal 8 having part of the metal foil 5b can be formed.

また、本発明の配線基板の製造方法は、第一誘電体シートは、支持基板側の下部第一誘電体シートと、その上に形成された上部第一誘電体シートとにてなるものであり、下部第一誘電体シートの所定の位置に開口を貫通形成し、該開口の壁部および底部を含む領域を覆うように被膜導体部を形成し、該被膜導体部が封止されるように上部第一誘電体シートを下部第一誘電体シート上に形成し、前記開口の底部をなす部位と接続するように上部第一誘電体シートに第一ビア導体を貫通形成するとともに、配線積層部を支持基板から剥離し、該配線積層部の第一誘電体シートが構成する主表面に付着した金属箔を除去したのちには、当該主表面に露出した前記被膜導体部を金属端子パッドとすることを特徴とするものであってもよい。 In the method for manufacturing a wiring board according to the present invention, the first dielectric sheet comprises a lower first dielectric sheet on the support substrate side and an upper first dielectric sheet formed thereon. An opening is formed at a predetermined position of the lower first dielectric sheet, a coated conductor portion is formed so as to cover a region including a wall portion and a bottom portion of the opening, and the coated conductor portion is sealed An upper first dielectric sheet is formed on the lower first dielectric sheet, and a first via conductor is formed through the upper first dielectric sheet so as to connect to a portion forming the bottom of the opening, and a wiring laminated portion Is removed from the support substrate, and after removing the metal foil attached to the main surface of the first dielectric sheet of the wiring laminate, the coated conductor exposed on the main surface is used as a metal terminal pad. It may be characterized by that.

これにより、形成された配線基板の金属端子となるパッド導体は、密着する誘電体シートとの密着面積が広く形成される。これにより、パッド導体と誘電体シートとの界面を起点に生じる誘電体シート内のクラック等を効果的に防止することができる。強度支持部分であるコア基板を有さない薄い配線基板においては、それらの防止効果を有するパッド構造は有効である。また、本発明の配線基板の製造方法では、前記第一導体層の形成は、前記上部第一誘電体シートにおいて、前記開口及びその近傍を除く領域をマスク材により被膜し、メッキ処理により前記被膜導体部を選択的に形成することを特徴とするものであってもよい。上記被膜導体部として形成されるパッド構造は、複雑な立体構造をなすが、所定パターンのマスク材を被覆した上で、電解メッキ処理を行うことによって、本パッド構造を容易に形成することが可能となる。 Thereby, the contact area with the dielectric sheet which adhere | attaches the pad conductor used as the metal terminal of the formed wiring board is widely formed. Thereby, the crack in the dielectric sheet which originates in the interface of a pad conductor and a dielectric sheet can be prevented effectively. In a thin wiring substrate that does not have a core substrate that is a strength supporting portion, a pad structure having such a prevention effect is effective. In the method for manufacturing a wiring board according to the present invention, the first conductor layer may be formed by coating the upper first dielectric sheet with a mask material in a region excluding the opening and the vicinity thereof, and performing plating to form the film. The conductor portion may be selectively formed. The pad structure formed as the film conductor portion has a complicated three-dimensional structure, but this pad structure can be easily formed by performing an electroplating process after covering a mask material with a predetermined pattern. It becomes.

また、本発明の配線基板の製造方法は、金属箔密着体をなす２つの金属箔のうち、主表面が配線積層部の第一誘電体シートに付着する金属箔が、第一ビア導体または被膜導体部とは異なる金属材料からなることを特徴とするものであってもよい。これにより、配線積層部を支持基板から剥離した後、該配線積層部の第一誘電体シート側の主表面に付着した金属箔を除去するときに、露出する導体部（例えば、被膜導体部、ビア導体など）の端面に対して、金属箔を選択的に除去することができるため、表れる露出面（導体部と第一誘電体層からなる面）を平坦とすることができる。これらは、例えばウェットエッチングによる選択エッチングにより行うことができる。 In the method for manufacturing a wiring board according to the present invention, the metal foil whose main surface adheres to the first dielectric sheet of the wiring laminated portion is the first via conductor or the coating, out of the two metal foils forming the metal foil adhesion body. It may be characterized by comprising a metal material different from the conductor portion. Thereby, after peeling the wiring laminated part from the support substrate, when removing the metal foil attached to the main surface of the wiring laminated part on the first dielectric sheet side, the exposed conductor part (for example, the coated conductor part, Since the metal foil can be selectively removed with respect to the end surface of the via conductor or the like, the exposed surface (surface consisting of the conductor portion and the first dielectric layer) can be made flat. These can be performed by, for example, selective etching by wet etching.

また、本発明の配線基板は、ビア導体の端面が、第一誘電体層の第一主表面と同一平面をなすことを特徴とするものであってもよい。上記のように、金属箔に導体層とは異なる金属材料を用いる場合、金属箔を除去した際に現れる導体部と第一誘電体層とからなる露出面を、平坦に形成することができる。また、オーバーエッチングによる導体部表面の粗れを抑えることができる。 Further, the wiring board of the present invention may be characterized in that the end face of the via conductor is flush with the first main surface of the first dielectric layer. As described above, when a metal material different from the conductor layer is used for the metal foil, the exposed surface composed of the conductor portion and the first dielectric layer that appear when the metal foil is removed can be formed flat. Moreover, the roughness of the conductor part surface by overetching can be suppressed.

以下、本発明の実施の形態について、図面を参照して説明する。図５は、本発明の配線基板の製造方法により得られる配線基板１の断面構造の概略を表す図である。配線基板１は、高分子材料からなる誘電体層（Ｂ１〜Ｂ３、ＳＲ）と導体層（Ｍ１、Ｍ２、ＰＤ）とが交互に積層された構造を有する。その第一主表面ＭＰ１は電子部品を搭載するための搭載面とされ、主表面をなす第一誘電体層Ｂ１には、電子部品と接続するための、周知のハンダで構成された突起状の金属端子（ハンダバンプ）ＦＢが形成されている。また、第二主表面ＭＰ２は、外部基板へ接続するための接続面とされ、主表面をなす誘電体層（ソルダーレジスト層）ＳＲには開口が形成されており、該開口内には外部基板への接続を担うハンダボール（後述）を設置するための金属端子（金属パッド）ＰＤが露出している。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 is a diagram showing an outline of a cross-sectional structure of the wiring board 1 obtained by the method for manufacturing a wiring board of the present invention. The wiring substrate 1 has a structure in which dielectric layers (B1 to B3, SR) made of a polymer material and conductor layers (M1, M2, PD) are alternately stacked. The first main surface MP1 is a mounting surface for mounting an electronic component, and the first dielectric layer B1 forming the main surface has a protruding shape made of a well-known solder for connecting to the electronic component. Metal terminals (solder bumps) FB are formed. The second main surface MP2 is a connection surface for connecting to an external substrate, and an opening is formed in the dielectric layer (solder resist layer) SR forming the main surface, and the external substrate is in the opening. A metal terminal (metal pad) PD for installing a solder ball (described later) that bears the connection to is exposed.

また、金属層Ｍ１、Ｍ２において配線ＣＬが形成されており、誘電体層Ｂ１〜Ｂ３内には該配線ＣＬに接続されるビア導体ＶＡが埋設形成されている。そして、配線ＣＬ及びビア導体ＶＡにより、電気導通路（例えばハンダバンプＦＢから金属パッドＰＤへの）が形成される。なお、誘電体層Ｂ１〜Ｂ３、ＳＲは、例えばエポキシ樹脂を主成分とする材料にて構成することができ、また配線ＣＬ、ビア導体ＶＡ及び金属パッドＰＤは、例えば銅を主成分とする材料にて構成することができる。また、金属パッドＰＤは、その表面に例えばＮｉ−Ａｕメッキによる表面メッキを施すことができる。 A wiring CL is formed in the metal layers M1 and M2, and a via conductor VA connected to the wiring CL is embedded in the dielectric layers B1 to B3. An electric conduction path (for example, from the solder bump FB to the metal pad PD) is formed by the wiring CL and the via conductor VA. The dielectric layers B1 to B3, SR can be made of, for example, a material mainly containing an epoxy resin, and the wiring CL, the via conductor VA, and the metal pad PD are, for example, materials mainly made of copper. Can be configured. Further, the surface of the metal pad PD can be subjected to surface plating by Ni—Au plating, for example.

以上のような配線基板１は、図６に示すように、第二主表面ＭＰ２の金属パッドＰＤに外部基板への接続を担うハンダボールＳＢが設置され、一方、第一主表面ＭＰ１には、補強枠（スティフナー）ＳＴが設置されるとともに、電子部品ＩＣがハンダバンプＦＢにフリップチップ接続され、また電子部品ＩＣ下の隙間がアンダーフィル材ＵＦにて充填されることで、半導体装置３００となる。 As shown in FIG. 6, the wiring board 1 as described above is provided with solder balls SB that are connected to an external substrate on the metal pad PD of the second main surface MP2, while the first main surface MP1 has The reinforcing frame (stiffener) ST is installed, the electronic component IC is flip-chip connected to the solder bump FB, and the gap under the electronic component IC is filled with the underfill material UF, so that the semiconductor device 300 is obtained.

図１２は、本発明の配線基板の製造方法により得られる配線基板１の第二実施形態の断面構造の概略を表す図である。なお、ここでは、上記第一実施形態の配線基板１と異なる点についてのみ説明し、同じ点については図中に同符号を付することで説明を省略する。第二実施形態では、電子部品を搭載するための搭載面とされる第一主表面ＭＰ１上に、金属箔ＣＦにて構成される金属端子ＴＢが形成されている。金属端子ＴＢは、裏面にビア導体ＶＡが接続された金属箔ＣＦと、該金属箔ＣＦの表面に形成されたメッキ層ＮＭとにより構成されている。メッキ層ＮＭは、金属箔ＣＦの表面を保護するものであり、例えばＮｉ−Ａｕメッキ等を用いることができる。また、言い換えると、金属箔ＣＦは、ビア導体ＶＡとメッキ層ＮＭとの間に介在しており、このような構造は、ビア導体上に直接メッキ層が形成された場合と比べて、良好な接続信頼性を有する。 FIG. 12 is a diagram showing an outline of a cross-sectional structure of the second embodiment of the wiring board 1 obtained by the method for manufacturing a wiring board of the present invention. Here, only different points from the wiring substrate 1 of the first embodiment will be described, and the same points are denoted by the same reference numerals in the drawing, and the description thereof is omitted. In the second embodiment, a metal terminal TB composed of a metal foil CF is formed on a first main surface MP1 that is a mounting surface for mounting an electronic component. The metal terminal TB is composed of a metal foil CF with a via conductor VA connected to the back surface and a plating layer NM formed on the surface of the metal foil CF. The plating layer NM protects the surface of the metal foil CF, and for example, Ni—Au plating or the like can be used. In other words, the metal foil CF is interposed between the via conductor VA and the plating layer NM, and such a structure is better than the case where the plating layer is directly formed on the via conductor. Has connection reliability.

そのような金属端子８は、例えばワイヤボンディング用の端子またはＴＡＢ（Tape Automated Bonding）用の端子、チップキャパシター搭載用の端子等として形成することができる。そして、図１３に示すように、搭載面となる第一主表面ＭＰ１上に電子部品ＩＣが搭載され、かつ電子部品ＩＣと金属端子８とがボンディングワイヤＹＢ等により接続されることで半導体装置３００となる。 Such a metal terminal 8 can be formed, for example, as a wire bonding terminal, a TAB (Tape Automated Bonding) terminal, a chip capacitor mounting terminal, or the like. Then, as shown in FIG. 13, the electronic component IC is mounted on the first main surface MP1 serving as the mounting surface, and the electronic component IC and the metal terminal 8 are connected by the bonding wire YB or the like. It becomes.

以下、本発明の実施形態である配線基板の製造方法の一例を説明する。図７〜図１０は製造工程を表す図である。工程１〜５に示す支持基板２０上に積層シート体１０を形成していく工程は、周知のビルドアップ法等により行うことができる。まず、図７の工程１に示すように、製造時における補強のための支持基板２０上に下地誘電体シート２１を形成する。支持基板２０は、下地誘電体シート２１が密着するものであれば特には限定されないが、例えばＦＲ−４等のガラスエポキシ基板（上述のようにコア基板に用いられる材料である）にて構成することができる。また、下地誘電体シート２１も、特には限定されないが、例えば後述する第一誘電体シート１１と同材料、すなわちエポキシを主成分とする材料にて構成することができる。 Hereinafter, an example of the manufacturing method of the wiring board which is embodiment of this invention is demonstrated. 7-10 is a figure showing a manufacturing process. The step of forming the laminated sheet body 10 on the support substrate 20 shown in steps 1 to 5 can be performed by a known build-up method or the like. First, as shown in Step 1 of FIG. 7, a base dielectric sheet 21 is formed on a support substrate 20 for reinforcement during manufacturing. The support substrate 20 is not particularly limited as long as the underlying dielectric sheet 21 is in close contact with each other. For example, the support substrate 20 is composed of a glass epoxy substrate such as FR-4 (which is a material used for the core substrate as described above). be able to. Also, the base dielectric sheet 21 is not particularly limited, but can be made of, for example, the same material as the first dielectric sheet 11 described later, that is, a material mainly composed of epoxy.

次に、工程２に示すように、下地誘電体シート２１の主表面上に、該主表面に包含されるよう配され、分離可能な２つの金属箔５ａ、５ｂが密着してなる金属箔密着体５を配す。なお、金属箔密着体５は、半硬化状態の下地誘電体シート２１上に配すようにすることができる。これにより、以降の工程で金属箔密着体５（下側金属箔５ａ）が下地誘電体シート２１から剥れない程度の密着性が得られやすくなる。また、金属箔密着体５は、例えば２つの銅箔を金属メッキ（例えばＣｒ）を介して密着させたものを用いることができる。 Next, as shown in step 2, the metal foil adhesion formed by adhering two separable metal foils 5 a and 5 b on the main surface of the underlying dielectric sheet 21 so as to be included in the main surface. Arrange the body 5. In addition, the metal foil adhesion body 5 can be arranged on the base dielectric sheet 21 in a semi-cured state. Thereby, it becomes easy to obtain adhesiveness to such an extent that the metal foil adhesion body 5 (lower metal foil 5a) does not peel from the base dielectric sheet 21 in the subsequent steps. In addition, as the metal foil adhesion body 5, for example, two copper foils adhered through metal plating (for example, Cr) can be used.

次に、工程３に示すように、金属箔密着体５を包むように第一誘電体シート１１を形成する。そして、第一誘電体シート１１は、金属箔密着体５（上側金属箔５ｂ）とともに、金属箔密着体５の周囲領域にて下地誘電体シート２１と密着して、金属箔密着体５を封止する。なお、誘電体シートの形成は、例えば周知の真空ラミネーション法を用いることができる。 Next, as shown in step 3, the first dielectric sheet 11 is formed so as to wrap the metal foil adhesion body 5. The first dielectric sheet 11 is in close contact with the base dielectric sheet 21 in the peripheral region of the metal foil adhesion body 5 together with the metal foil adhesion body 5 (upper metal foil 5b) to seal the metal foil adhesion body 5. Stop. The dielectric sheet can be formed using, for example, a well-known vacuum lamination method.

次に、図８の工程４に示すように、第一誘電体シート１１上に第一導体層３１をパターン形成し、また第一誘電体シート１１には該第一導体層３１と金属箔密着体５とを接続する第一ビア導体４１を形成する。なお、導体層の形成は、例えば周知のセミアディティブ法により形成することができる。また、ビア導体は、例えば周知のフォトビアプロセスによりビア孔を形成し、該ビア孔を、上記セミアディティブ法における無電解メッキによって充填することにより得ることができる。ただし、第一導体層３１および第一部ビア導体４１は必ずしも本工程４において形成されなくてもよい。工程４にて第一導体層３１および第一ビア導体４１を形成しない場合は、後述する工程８において配線積層部１００を支持基板２０から剥離した後、その際に該配線積層部１００に付着して残る金属箔５ｂ側から、第一誘電体シート１１であった第一誘電体層１１´に第一ビア導体４１を形成することができる。なお、この場合、配線基板には第一導体層３１が形成されず、第一ビア導体４１の端面が露出して表れる。 Next, as shown in Step 4 of FIG. 8, the first conductor layer 31 is patterned on the first dielectric sheet 11, and the first conductor layer 31 and the metal foil are in close contact with the first dielectric sheet 11. A first via conductor 41 connecting the body 5 is formed. The conductor layer can be formed by, for example, a known semi-additive method. The via conductor can be obtained, for example, by forming a via hole by a well-known photo via process and filling the via hole by electroless plating in the semi-additive method. However, the first conductor layer 31 and the first partial via conductor 41 are not necessarily formed in the present step 4. In the case where the first conductor layer 31 and the first via conductor 41 are not formed in Step 4, after the wiring laminated portion 100 is peeled off from the support substrate 20 in Step 8 described later, it adheres to the wiring laminated portion 100 at that time. The first via conductor 41 can be formed on the first dielectric layer 11 ′ that is the first dielectric sheet 11 from the remaining metal foil 5 b side. In this case, the first conductor layer 31 is not formed on the wiring board, and the end face of the first via conductor 41 appears.

次に、第一誘電体シート１１（及び第一導体層３１）上に第二誘電体シート１２を形成し、該第二誘電体シート１２内にビア導体４２を形成するとともに、該第二誘電体シート１２上に第二導体層３２を形成する。そして、同様の工程を繰り返して、誘電体シート１３、１４、ビア導体４３、導体層３３を形成していき、工程５に示すような積層シート体１０を形成する。なお、本実施形態では、積層シート体１０は、金属箔密着体５及び４層の誘電体シート１１〜１４にて構成されているが、誘電体シートの層数はこれに限られることはない。以上により、下地誘電体シート２１の主表面上に、該主表面に包含されるよう配された金属箔密着体５と、該金属箔密着体５を包むよう形成され、かつ該金属箔密着体５の周囲領域にて下地誘電体シート２１と密着して該金属箔密着体５を封止する第一誘電体シート１１と、を有する積層シート体１０が形成される。 Next, the second dielectric sheet 12 is formed on the first dielectric sheet 11 (and the first conductor layer 31), the via conductors 42 are formed in the second dielectric sheet 12, and the second dielectric sheet 12 is formed. The second conductor layer 32 is formed on the body sheet 12. And the same process is repeated and the dielectric sheets 13 and 14, the via conductor 43, and the conductor layer 33 are formed, and the lamination sheet body 10 as shown to the process 5 is formed. In addition, in this embodiment, although the lamination sheet body 10 is comprised by the metal foil adhesion body 5 and the dielectric sheet 11-14 of 4 layers, the number of layers of a dielectric sheet is not restricted to this. . As described above, the metal foil adhesion body 5 disposed so as to be included in the main surface on the main surface of the base dielectric sheet 21, and the metal foil adhesion body formed so as to wrap around the metal foil adhesion body 5. 5, a laminated sheet body 10 having a first dielectric sheet 11 that is in close contact with the base dielectric sheet 21 and seals the metal foil adhesion body 5 is formed.

なお、誘電体シート１１〜１４は、エポキシを主成分とする材料にて構成することができる。また、導体層３１〜３３とビア導体４１〜４３は銅を主成分として構成することができる。 The dielectric sheets 11 to 14 can be made of a material mainly composed of epoxy. Further, the conductor layers 31 to 33 and the via conductors 41 to 43 can be composed mainly of copper.

本実施形態では、積層シート体１０の上側の露出した主表面が、図５及び図１２に示す配線基板１の第二主表面ＭＰ２となるように形成されている。したがって、積層シート体１０の上側主表面をなす誘電体シート１４は、図５の配線基板１のソルダーレジスト層ＳＲに該当し、またその開口１４ａ内に露出する導体層３３は、図５及び図１２の配線基板１の金属パッドＰＤに該当する。なお、これとは反対に上側主表面を、図５に示す配線基板１の第一主表面ＭＰ１とすることもできる。その場合は、上側主表面をなす誘電体シート１４に、図５に示すハンダバンプＦＢを形成する。 In the present embodiment, the exposed main surface on the upper side of the laminated sheet body 10 is formed to be the second main surface MP2 of the wiring board 1 shown in FIGS. Therefore, the dielectric sheet 14 forming the upper main surface of the laminated sheet 10 corresponds to the solder resist layer SR of the wiring board 1 of FIG. 5, and the conductor layer 33 exposed in the opening 14a is shown in FIGS. This corresponds to 12 metal pads PD of the wiring board 1. On the other hand, the upper main surface may be the first main surface MP1 of the wiring board 1 shown in FIG. In that case, the solder bump FB shown in FIG. 5 is formed on the dielectric sheet 14 forming the upper main surface.

次に、積層シート体１０は、金属箔密着体５上の領域が、配線基板１（図５参照）となるべき配線積層部１００となるよう形成されている。そこで、工程６に示すように、配線積層部１００の周囲領域を除去し、端面１０３を露出させる（図９の工程７）。その際、配線積層部１００と周囲部との境界において、その下の下地誘電体シート２１及び支持基板２０ごと、例えばブレード刃等により切断する。このようにして、配線積層部１００の周囲領域とともに、支持基板２０及び下地誘電体シート２１のうちの該周囲部下にあたる領域も除去するようにすると、端面１０３の露出が容易である。 Next, the laminated sheet body 10 is formed so that the region on the metal foil adhesion body 5 becomes the wiring laminated portion 100 to be the wiring substrate 1 (see FIG. 5). Therefore, as shown in Step 6, the peripheral region of the wiring laminated portion 100 is removed to expose the end face 103 (Step 7 in FIG. 9). At that time, at the boundary between the wiring laminated portion 100 and the peripheral portion, the underlying dielectric sheet 21 and the supporting substrate 20 thereunder are cut by, for example, a blade blade or the like. In this manner, when the region under the peripheral portion of the support substrate 20 and the base dielectric sheet 21 is removed together with the peripheral region of the wiring laminated portion 100, the end face 103 is easily exposed.

次に、工程８に示すように、配線積層部１００を支持基板２０から、片方の金属箔（上側金属箔５ｂ）が付着した状態で、金属箔密着体５における２つの金属箔５ａ、５ｂの界面にて剥離する。 Next, as shown in step 8, the two metal foils 5 a and 5 b in the metal foil adhesion body 5 are attached to the wiring laminated portion 100 from the support substrate 20 with one metal foil (upper metal foil 5 b) attached thereto. Peel at the interface.

そして、配線積層部１００を支持基板２０から剥離した後に、図１０に示すように、該配線積層部１００の第一誘電体シート１１が構成する主表面に付着した金属箔５ｂを除去し（工程９）、第一ビア導体４と接続された金属端子５（図５の配線基板１ではハンダバンプＦＢ）を形成する（工程１０）。これにより、図５に示す配線基板１が得られる。 And after peeling the wiring laminated part 100 from the support substrate 20, as shown in FIG. 10, the metal foil 5b adhering to the main surface which the 1st dielectric sheet 11 of this wiring laminated part 100 comprises is removed (process). 9) Metal terminals 5 (solder bumps FB in the wiring board 1 of FIG. 5) connected to the first via conductors 4 are formed (step 10). Thereby, the wiring board 1 shown in FIG. 5 is obtained.

工程９において、金属箔５ｂの除去は、例えばエッチングにより行うことができる。金属箔５ｂが除去された第一誘電体シート１´の主表面には、内部に第一ビア導体４１が露出したビア孔１１ａが現れる。第一ビア導体４１は、金属箔５ｂのエッチングにより多少エッチングされるので、その端面がビア孔内（例えば、開口１１ａの近傍）に位置することになる。つまり、完成した配線基板は、コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層１１´〜１４´と導体層３１〜３３とが交互に積層され、第一主表面をなす第一誘電体層１１´に貫通形成されたビア孔１１ａ内に、該第一誘電体層１１´直下の第一導体層３１´と接続されたビア導体４１が形成されてなるとともに、該ビア導体４１は、第一主表面側の端面がビア孔１１ａ内に位置してなり、当該端面には、金属端子８が接続された構成となる。このように、ビア導体４１の端面がビア孔１１ａ内に位置すれば、例えばハンダからなる金属端子（ハンダバンプ）８の形成が容易となるうえ、接続信頼性も確保できる。 In step 9, the metal foil 5b can be removed by etching, for example. A via hole 11a in which the first via conductor 41 is exposed appears on the main surface of the first dielectric sheet 1 ′ from which the metal foil 5b has been removed. Since the first via conductor 41 is slightly etched by etching the metal foil 5b, the end face thereof is located in the via hole (for example, in the vicinity of the opening 11a). That is, the completed wiring board does not have a core board, and the dielectric layers 11 ′ to 14 ′ made of a polymer material and the conductor layers 31 to 33 so that both main surfaces are constituted by dielectric layers. Are alternately stacked and connected to the first conductor layer 31 ′ directly below the first dielectric layer 11 ′ in the via hole 11 a formed through the first dielectric layer 11 ′ forming the first main surface. The via conductor 41 is formed, and the via conductor 41 is configured such that the end surface on the first main surface side is located in the via hole 11a, and the metal terminal 8 is connected to the end surface. Thus, if the end face of the via conductor 41 is located in the via hole 11a, the metal terminals (solder bumps) 8 made of, for example, solder can be easily formed, and connection reliability can be ensured.

なお、図１４に示すように、ビア導体４１の端面の、第一主表面からの深さ位置をＤ、ビア孔の最大径をＷとしたとき、比Ｄ／Ｗが０超過０．５以下となるよう設定することが好ましい。比Ｄ／Ｗが０．５を超えると、ビア導体４１と、接続される金属端子８との間にボイドが発生し、接続信頼性が多少低下する場合がある。 As shown in FIG. 14, when the depth position from the first main surface of the end face of the via conductor 41 is D and the maximum diameter of the via hole is W, the ratio D / W is greater than 0 and 0.5 or less. It is preferable to set so that. If the ratio D / W exceeds 0.5, a void may be generated between the via conductor 41 and the metal terminal 8 to be connected, and the connection reliability may be somewhat lowered.

一方、図１５の工程９´及び１０´に示すように、金属箔５ｂの一部５ｂ´を利用した金属端子８を形成することもできる。すなわち、配線積層部１００を支持基板２０から剥離した後に、該配線積層部１００の第一誘電体シート１１が形成された主表面に付着した金属箔５ｂを選択的に除去し（工程９´）、第一ビア導体４１と接続され、かつ残存した金属箔５ｂ´を一部とした金属端子８を形成する（工程１０´）。つまり、完成した配線基板では、コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層１１´〜１４´と導体層３１〜３とが交互に積層され、第一主表面に、金属箔５ｂ´にて構成される金属端子８が形成された構成となる。 On the other hand, as shown in steps 9 ′ and 10 ′ of FIG. 15, the metal terminal 8 using a part 5 b ′ of the metal foil 5 b can be formed. That is, after peeling the wiring laminated portion 100 from the support substrate 20, the metal foil 5b attached to the main surface of the wiring laminated portion 100 on which the first dielectric sheet 11 is formed is selectively removed (step 9 '). Then, the metal terminal 8 connected to the first via conductor 41 and including a part of the remaining metal foil 5b ′ is formed (step 10 ′). That is, in the completed wiring board, the dielectric layers 11 ′ to 14 ′ made of a polymer material and the conductor layers 31 to 3 do not have a core board and both main surfaces are constituted by dielectric layers. Are alternately laminated, and a metal terminal 8 composed of a metal foil 5b ′ is formed on the first main surface.

なお、以上の製造工程では、図１１に示すように、積層シート体１０に含まれる配線積層部１００は、一つの配線基板に対応する個体１００´が複数連結されたもの、つまり、配線基板１の多数個取りワーク基板として構成することができる。 In the above manufacturing process, as shown in FIG. 11, the wiring laminated portion 100 included in the laminated sheet body 10 is formed by connecting a plurality of individual 100 ′ corresponding to one wiring board, that is, the wiring board 1. It can be configured as a multi-piece work substrate.

また、上記実施形態の工程２（図７）にて形成される金属箔密着体５のうち、導体層側をなす金属箔５ｂが、該金属箔５ｂに接続されるビア導体４１と、異なる金属材料で構成することもできる。上記実施形態では導体層３１〜３３とビア導体４１〜４３とは銅を主成分として構成され、金属箔密着体５は２つの銅箔５ａ，５ｂを密着させたものを用いることが例示されているが、このときの金属箔密着体５の金属箔５ｂを、第一ビア導体４１に対して選択エッチング性を有する金属材料を用いるとしてもよい。例えば、第一ビア導体がＣｕを主成分として構成し、主表面に前記配線積層部１００側の第一誘電体シート１１が付着した前記金属箔５ｂが、Ｔｉ，Ｃｒ，Ａｌ，Ａｇ，Ｓｎのうち少なくとも１種以上からなる金属材料とすることができる。工程８（図８）において、支持基板２０側の剥離後、配線積層部１００には金属箔５ｂが付着して残るが、この金属箔５ｂはエッチングによって除去される。このとき、金属箔５ｂが上記金属材料にて構成されていれば、銅に対して選択的にエッチングすることが可能となる。したがって、第一ビア導体４１はエッチングされずにそのままの状態を保ちつつ、その端面が露出するため、このとき露出する配線基板の主表面は、第一ビア導体４１の露出面と第一誘電体層１１´の主表面とが同一平面をなし、極めてフラットな平面を形成できる。 Further, in the metal foil adhesion body 5 formed in step 2 (FIG. 7) of the above embodiment, the metal foil 5b on the conductor layer side is different from the via conductor 41 connected to the metal foil 5b. It can also consist of materials. In the above embodiment, the conductor layers 31 to 33 and the via conductors 41 to 43 are composed mainly of copper, and the metal foil contact body 5 is exemplified by using two copper foils 5a and 5b in close contact. However, a metal material having selective etching properties with respect to the first via conductor 41 may be used for the metal foil 5b of the metal foil adhesion body 5 at this time. For example, the first via conductor is composed of Cu as a main component, and the metal foil 5b with the first dielectric sheet 11 on the wiring laminate 100 side attached to the main surface is made of Ti, Cr, Al, Ag, Sn. It can be set as the metal material which consists of at least 1 or more types. In step 8 (FIG. 8), after peeling off on the support substrate 20 side, the metal foil 5b remains attached to the wiring laminated portion 100, but this metal foil 5b is removed by etching. At this time, if the metal foil 5b is made of the above metal material, it can be selectively etched with respect to copper. Therefore, the first via conductor 41 is not etched and remains as it is, and its end face is exposed. Therefore, the main surface of the wiring board exposed at this time is the exposed surface of the first via conductor 41 and the first dielectric. The main surface of the layer 11 ′ is flush with the main surface, and an extremely flat plane can be formed.

また、本発明は、上記配線基板およびその製造方法に限定されるものではなく、請求項の記載に基づく技術的範囲を逸脱しない限り、種々の変形ないし改良を付加することができる。そこで、上記実施形態を第一実施形態（図５〜図１０）と第二実施形態（図１２、図１５）とした上で、本発明に係わる他の実施形態の代表的なものを以下に説明する。 Further, the present invention is not limited to the wiring board and the manufacturing method thereof, and various modifications or improvements can be added without departing from the technical scope based on the description of the claims. Then, after making the said embodiment into 1st embodiment (FIGS. 5-10) and 2nd embodiment (FIG. 12, FIG. 15), the typical thing of other embodiment concerning this invention is shown below. explain.

上記第一実施形態の配線基板の製造方法においては、図７〜図１０に示されているように、電子部品搭載面側を支持基板２０側とし、その搭載面を金属箔密着体５と密着するように積層形成されているが、電子部品搭載面の逆側の主表面を支持基板２０側となるように積層する製造方法であってもよい。この場合、例えば図１６のような配線基板１ａを形成することが可能となる。図１６では、上記第一実施形態（図７〜図１０）の導体層１４のような広面積の導体部ＰＤ１（他の基板やマザーボード等と接続される金属端子部である）が、第一導体層Ｍ１として第一誘電体層Ｂ１に形成され、上記実施形態（図７〜図１０）の第一ビア導体４１（電子部品搭載面側のビア導体）に対応するビア導体ＶＡが、第三誘電体層Ｂ３に形成されている。また、図１６では、第三誘電体層Ｂ３に形成されるビア導体ＶＡ上には導体部ＰＤ２が形成され、該第三誘電体層上の誘電体層（ソルダーレジスト層）ＳＲの開口から露出し、その露出部にはメッキ層を介してハンダバンプＦＢが形成されている。 In the method of manufacturing the wiring board according to the first embodiment, as shown in FIGS. 7 to 10, the electronic component mounting surface side is the support substrate 20 side, and the mounting surface is in close contact with the metal foil adhesion body 5. However, it may be a manufacturing method in which the main surface opposite to the electronic component mounting surface is laminated on the support substrate 20 side. In this case, for example, a wiring board 1a as shown in FIG. 16 can be formed. In FIG. 16, the conductor portion PD1 having a large area like the conductor layer 14 in the first embodiment (FIGS. 7 to 10) (which is a metal terminal portion connected to another substrate, a motherboard, or the like) is the first. A via conductor VA formed on the first dielectric layer B1 as the conductor layer M1 and corresponding to the first via conductor 41 (via conductor on the electronic component mounting surface side) of the above-described embodiment (FIGS. 7 to 10) is the third conductor layer M1. It is formed on the dielectric layer B3. In FIG. 16, a conductor portion PD2 is formed on the via conductor VA formed in the third dielectric layer B3, and is exposed from the opening of the dielectric layer (solder resist layer) SR on the third dielectric layer. And the solder bump FB is formed in the exposed part through the plating layer.

このときの図１６に示す配線基板１ａの製造方法を、図１７〜図１９にて主要な製造工程を示しつつ、説明する。図１７に示す工程１ａ，２ａは、上記第一実施形態の工程１,２（図７）と同様である。工程３ａでは、金属箔密着体５上に第一導体層３１をパターン形成した上で、第一誘電体シート１１を金属箔密着体５と第一導体層３１とが封止されるようにラミネートする。図１８の工程４ａでは、周知のビルドアップ法に基づき配線積層部１００ａ（図１９）を含む積層シート体１０ａを形成し、工程５ａでは上記第一実施形態の工程７（図９）のように、配線積層部１００ａの端面が露出するように切断する。図１９の工程６ａでは、上記実施形態の工程８（図９）と同様に、配線積層部１００ａを支持基板２０から、片方の金属箔（上側金属箔５ｂ）が付着した状態で、金属箔密着体５における２つの金属箔５ａ、５ｂの界面にて剥離する。そして、工程７ａが示すように、配線積層部１００ａの第一誘電体シート１１が構成する主表面に付着した金属箔５ｂを除去し、第三ビア導体４３と接続された第四導体層３４の導体部に金属端子８（図１６の配線基板１ａではハンダバンプＦＢ）を形成する。これにより、図１６に示す配線基板１ａが得られる。なお、ここで述べた配線基板の製造方法および該製造方法によって形成されうる配線基板を、本発明の第三実施形態とする。 The manufacturing method of the wiring board 1a shown in FIG. 16 at this time will be described while showing main manufacturing steps in FIGS. Steps 1a and 2a shown in FIG. 17 are the same as steps 1 and 2 (FIG. 7) of the first embodiment. In step 3a, the first conductor layer 31 is patterned on the metal foil adhesion body 5, and then the first dielectric sheet 11 is laminated so that the metal foil adhesion body 5 and the first conductor layer 31 are sealed. To do. In step 4a of FIG. 18, a laminated sheet body 10a including the wiring laminated portion 100a (FIG. 19) is formed based on a known build-up method, and in step 5a, as in step 7 (FIG. 9) of the first embodiment. Then, the wiring laminate 100a is cut so that the end face is exposed. In Step 6a of FIG. 19, as in Step 8 (FIG. 9) of the above-described embodiment, the wiring laminated portion 100a is adhered to the metal foil with one metal foil (upper metal foil 5b) attached from the support substrate 20. It peels at the interface of the two metal foils 5a and 5b in the body 5. Then, as shown in step 7a, the metal foil 5b attached to the main surface of the wiring laminate 100a of the first dielectric sheet 11 is removed, and the fourth conductor layer 34 connected to the third via conductor 43 is removed. Metal terminals 8 (solder bumps FB in the wiring substrate 1a of FIG. 16) are formed on the conductor portions. Thereby, the wiring board 1a shown in FIG. 16 is obtained. The wiring board manufacturing method described here and the wiring board that can be formed by the manufacturing method are defined as a third embodiment of the present invention.

本発明の配線基板の金属端子は、図２０に示すような導体部ＰＤ１のような、上記第一、第二、および第三実施形態とは異なる導体構造であってもよく、以下、図２０に示す実施形態について説明する。この場合、第一誘電体層Ｂ１となるべき第一誘電体シート１１は、下地誘電体層側をなす下部第一誘電体シート１１ａ（後、下部第一誘電体層Ｂ１ａとなる）と配線積層部側をなす上第一誘電体シート１１ｂ（後、上部第一誘電体層Ｂ１ｂとなる）とからなる。以下、図２０に示す配線基板１ｂの製造方法を、図２１〜図２４にて主要な製造工程を示しつつ、簡単に説明する。 The metal terminal of the wiring board of the present invention may have a conductor structure different from those of the first, second, and third embodiments, such as the conductor portion PD1 as shown in FIG. The embodiment shown in FIG. In this case, the first dielectric sheet 11 to be the first dielectric layer B1 is composed of a lower first dielectric sheet 11a (to be later referred to as the lower first dielectric layer B1a) and a wiring laminate. It consists of an upper first dielectric sheet 11b (to be later referred to as an upper first dielectric layer B1b). Hereinafter, a method of manufacturing the wiring substrate 1b shown in FIG. 20 will be briefly described while showing main manufacturing steps in FIGS.

図２１に示すに示す工程１ｂ，２ｂ，３ｂは、上記第一実施形態の工程１,２，３（図７）と同様である。ただし、工程３ｂにて形成される誘電体シートは第一誘電体シート１１となるべき下部第一誘電体シート１１ａである。図２２の工程４ｂでは、下部第一誘電体シート１１ａに開口を形成して、パターニングされた下部第一誘電体シート１１ａと開口とからなる最表層の露出面全面を覆うように、無電解メッキ処理を行う。さらにその無電解メッキ層３１ｂ上にメッキレジスト６を形成し、これをパターニング処理する。次いで工程５ｂでは、パターニングされたメッキレジスト６をマスクとして電解メッキ処理を行った後、メッキレジスト６を除去し、次いで電解メッキ層（被膜導体部）をメッキレジスト（図示なし）によりマスクして、マスクされていない領域の無電解メッキ層３１ｂを除去し、メッキレジスト層（図示なし）を除去する。これにより、導体パターン３１ａ（図２０の導体部ＰＤ１）を形成することができる。このように形成された導体パターン３１ａは、下部第一誘電体シート１１ａの開口の壁部の側面側と上面側とを覆うように形成され、この壁部を覆っている壁面導体部は鉤型形状をなしている。工程６ｂでは、この導体パターン３１ａを覆うように上部第一誘電体シート１１ｂをラミネートする。該上部部第一誘電体シート１１ｂには、ビア用開口部を形成する。このビア用開口部は、開口内に形成されるビア導体４１が導体部３１ａの底部の中央と接続するように形成される。これにより、第一誘電体シート１１が、下部第一誘電体シート１１ａと上第一誘電体シート１１ｂとにより形成され、導体部３１ａが、図２０のように下部第一誘電体シート１１ａの開口の底部を覆うパッド本体ＰＤ１ａと壁部を覆う壁面導体部ＰＤ１ｂとにて構成される構造を有する。 Steps 1b, 2b, and 3b shown in FIG. 21 are the same as steps 1, 2, and 3 (FIG. 7) of the first embodiment. However, the dielectric sheet formed in the step 3b is the lower first dielectric sheet 11a to be the first dielectric sheet 11. In step 4b of FIG. 22, an opening is formed in the lower first dielectric sheet 11a, and electroless plating is performed so as to cover the entire exposed surface of the outermost layer composed of the patterned lower first dielectric sheet 11a and the opening. Process. Further, a plating resist 6 is formed on the electroless plating layer 31b and patterned. Next, in step 5b, after the electrolytic plating process is performed using the patterned plating resist 6 as a mask, the plating resist 6 is removed, and then the electrolytic plating layer (coating conductor portion) is masked with a plating resist (not shown). The electroless plating layer 31b in the unmasked region is removed, and the plating resist layer (not shown) is removed. Thereby, the conductor pattern 31a (conductor part PD1 of FIG. 20) can be formed. The thus formed conductor pattern 31a is formed so as to cover the side surface side and the upper surface side of the wall portion of the opening of the lower first dielectric sheet 11a, and the wall surface conductor portion covering this wall portion is a saddle type. It has a shape. In step 6b, the upper first dielectric sheet 11b is laminated so as to cover the conductor pattern 31a. A via opening is formed in the upper first dielectric sheet 11b. The via opening is formed so that the via conductor 41 formed in the opening is connected to the center of the bottom of the conductor 31a. Thus, the first dielectric sheet 11 is formed by the lower first dielectric sheet 11a and the upper first dielectric sheet 11b, and the conductor portion 31a is an opening of the lower first dielectric sheet 11a as shown in FIG. The pad main body PD1a that covers the bottom of the wall and the wall surface conductor portion PD1b that covers the wall portion have a structure.

工程６ｂ以降は、図２３に示すように、工程７ｂでは、周知のビルドアップ法に基づき配線積層部１００ｂを含む積層シート体１０ｂを形成し、工程８ｂでは上記第一実施形態の工程７（図９）のように、配線積層部１００ｂの端面が露出するように切断する。図２４の工程９ｂでは、上記実施形態の工程８（図９）と同様に、配線積層部１００ｂを支持基板２０から、片方の金属箔（上側金属箔５ｂ）が付着した状態で、金属箔密着体５における２つの金属箔５ａ、５ｂの界面にて剥離する。そして、工程１０ｂが示すように、配線積層部１００ｂの第一誘電体シート１１が構成する主表面に付着した金属箔５ｂを除去し、第三ビア導体４３と接続された第四導体層３４の導体部に金属端子８（図２０の配線基板１ではハンダバンプＦＢ）を形成する。これにより、図２０に示す配線基板１ｂが得られる。この配線基板１ｂは、両主表面が誘電体層にて構成されるよう、導体層と誘電体層とが積層されるとともに、少なくとも一方の主表面をなす前記誘電体層の開口に形成された金属端子パッドを有する配線基板であって、前記金属端子パッドは、前記開口に露出面を有し、かつ該露出面の裏面で前記配線基板内部の前記導体層とビア接続されるパッド本体と、該パッド本体の外縁から前記配線基板の内層方向に、前記開口の壁部に沿って形成される壁面導体部と、にて構成されることを特徴とするものである。なお、ここで述べた配線基板の製造方法およびそれによって形成されうる配線基板を本発明の第四実施形態とする。 After Step 6b, as shown in FIG. 23, in Step 7b, a laminated sheet body 10b including the wiring laminated portion 100b is formed based on a well-known buildup method, and in Step 8b, Step 7 (FIG. As in 9), cutting is performed so that the end face of the wiring laminated portion 100b is exposed. In step 9b of FIG. 24, in the same manner as in step 8 (FIG. 9) of the above embodiment, the wiring laminated portion 100b is adhered to the metal foil with one metal foil (upper metal foil 5b) attached from the support substrate 20. It peels at the interface of the two metal foils 5a and 5b in the body 5. Then, as shown in step 10b, the metal foil 5b attached to the main surface formed by the first dielectric sheet 11 of the wiring laminated portion 100b is removed, and the fourth conductor layer 34 connected to the third via conductor 43 is removed. Metal terminals 8 (solder bumps FB in the wiring board 1 of FIG. 20) are formed on the conductor portions. Thereby, the wiring board 1b shown in FIG. 20 is obtained. The wiring substrate 1b is formed in the opening of the dielectric layer which forms at least one main surface while the conductor layer and the dielectric layer are laminated so that both main surfaces are constituted by dielectric layers. A wiring board having a metal terminal pad, the metal terminal pad having an exposed surface in the opening, and a pad main body via-connected to the conductor layer in the wiring board on the back surface of the exposed surface; And a wall surface conductor portion formed along the wall portion of the opening from the outer edge of the pad main body toward the inner layer of the wiring board. Note that the wiring board manufacturing method described here and the wiring board that can be formed thereby are the fourth embodiment of the present invention.

本発明に限らず、このような薄い配線基板の製造においては、ビルドアップ層（配線積層部を含む積層シート体）の積層時、支持体（積層時の補強部）時、及びその除去後の工程において発生する外力が、支持体と密着する導体部と、その直上に形成される誘電体層との界面に集中しやすくなる。そのため、そうした界面から、クラック等の欠陥が誘起されやすい。従って、薄いビルドアップ層を有する配線基板の製造方法においては、このようなクラック発生の問題に対して、何らかの対策が必要とされる場合がある。本発明の上記第三実施形態はそうした問題を解決する一つの実施形態を示すものであり、これによれば、第一導体層Ｍ１の導体部と第一誘電体層Ｂ１（第一誘電体シート１１）との接着面積が、図５に示す第一実施形態および図１６に示す第二実施形態よりも大きく確保され、外力の集中を緩和することができる。
In the manufacture of such a thin wiring board, not limited to the present invention, a build-up layer (a laminated sheet body including a wiring laminated portion) is laminated, a support (a reinforcing portion at the time of lamination), and after its removal. The external force generated in the process tends to concentrate on the interface between the conductor portion in close contact with the support and the dielectric layer formed immediately above the conductor portion. Therefore, defects such as cracks are easily induced from such an interface. Therefore, in a method for manufacturing a wiring board having a thin build-up layer, some measures may be required for such a problem of crack generation. The third embodiment of the present invention shows one embodiment that solves such a problem, and according to this, the conductor portion of the first conductor layer M1 and the first dielectric layer B1 (first dielectric sheet). 11) is ensured larger than the first embodiment shown in FIG. 5 and the second embodiment shown in FIG. 16, and the concentration of external force can be alleviated.

本発明の配線基板の製造方法の工程を簡略的に示す図。The figure which shows simply the process of the manufacturing method of the wiring board of this invention. 積層シート体１０に含まれる配線積層シート体１００を示す図。The figure which shows the wiring lamination sheet body 100 contained in the lamination sheet body 10. FIG. 積層シート体１０の変形例を表す図。The figure showing the modification of the laminated sheet body. 積層シート体１０における配線積層部１００とする領域の変形例。The modification of the area | region used as the wiring lamination | stacking part 100 in the lamination sheet body 10. FIG. 本発明の一実施形態である配線基板の断面構造の概略を表す図。The figure showing the outline of the cross-sectional structure of the wiring board which is one Embodiment of this invention. 図５の配線基板１を用いた半導体装置。A semiconductor device using the wiring substrate 1 of FIG. 本発明の一実施形態である配線基板の製造方法の工程を表す図。The figure showing the process of the manufacturing method of the wiring board which is one Embodiment of this invention. 図７に続く図。The figure following FIG. 図８に続く図。The figure following FIG. 図９に続く図。The figure following FIG. 多数個取りワーク基板とされた配線積層部１００を上部より見た図。The figure which looked at the wiring lamination | stacking part 100 made into the multi-piece work board | substrate from the upper part. 本発明の第二実施形態である配線基板の断面構造の概略を表す図。The figure showing the outline of the cross-sectional structure of the wiring board which is 2nd embodiment of this invention. 図１２の配線基板１を用いた半導体装置。The semiconductor device using the wiring board 1 of FIG. ビア孔内に露出する第一ビア導体４１の端面位置を表す図。The figure showing the end surface position of the 1st via conductor 41 exposed in a via hole. 第二実施形態の配線基板を製造するための工程を表す図。The figure showing the process for manufacturing the wiring board of 2nd embodiment. 本発明の第三実施形態である配線基板の断面構造の概略を表す図。The figure showing the outline of the cross-sectional structure of the wiring board which is 3rd embodiment of this invention. 第三実施形態の配線基板を製造するための工程を表す図。The figure showing the process for manufacturing the wiring board of 3rd embodiment. 図１７に続く図。The figure following FIG. 図１８に続く図。The figure following FIG. 本発明の第四実施形態である配線基板の断面構造の概略を表す図。The figure showing the outline of the cross-sectional structure of the wiring board which is 4th embodiment of this invention. 第四実施形態の配線基板を製造するための工程を表す図。The figure showing the process for manufacturing the wiring board of 4th embodiment. 図２１に続く図。The figure following FIG. 図２２に続く図。The figure following FIG. 図２３に続く図。The figure following FIG.

符号の説明Explanation of symbols

１配線基板
５金属箔密着体
１０積層シート体
１１第一誘電体シート
２０支持基板
２１下地誘電体シート
１００配線積層シート体 1 wiring board 5 metal foil adhesion body 10 laminated sheet body 11 first dielectric sheet 20 support substrate 21 base dielectric sheet 100 wiring laminated sheet body

Claims (10)

コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層された配線基板を製造するために、製造時における補強のための支持基板上に形成された下地誘電体シートの主表面上に、該主表面に包含されるよう配された、分離可能な２つの金属箔が密着してなる金属箔密着体と、該金属箔密着体を包むよう形成され、かつ該金属箔密着体の周囲領域にて前記下地誘電体シートと密着して該金属箔密着体を封止する第一誘電体シートと、該第一誘電体シート上に形成された第一導体層と、該第一導体層と前記金属箔密着体とを接続する前記第一誘電体シートに貫通形成された第一ビア導体と、を有する積層シート体を形成するとともに、前記積層シート体のうち、前記金属箔密着体上の領域を前記配線基板となるべき配線積層部として、その周囲部を除去し、該配線積層部の端面を露出させた後、前記配線積層部を前記支持基板から、片方の金属箔が付着した状態で、前記金属箔密着体における２つの金属箔の界面にて剥離することを特徴とする配線基板の製造方法。 In order to manufacture a wiring board in which dielectric layers and conductor layers made of a polymer material are alternately laminated so that both main surfaces are composed of dielectric layers without having a core substrate, Metal foil adhesion body formed by adhering two separable metal foils arranged to be included in the main surface on the main surface of the base dielectric sheet formed on the support substrate for reinforcement in And a first dielectric sheet that is formed to wrap around the metal foil adhesion body and seals the metal foil adhesion body in close contact with the base dielectric sheet in a peripheral region of the metal foil adhesion body, A first conductor layer formed on the first dielectric sheet; and a first via conductor formed through the first dielectric sheet connecting the first conductor layer and the metal foil adhesion body. While forming a laminated sheet body, among the laminated sheet bodies, on the metal foil adhesion body A state where the region is the wiring laminated portion to be the wiring substrate, the peripheral portion is removed, and the end surface of the wiring laminated portion is exposed, and then the wiring laminated portion is attached to the supporting substrate from one metal foil. Then, the method for producing a wiring board, comprising peeling at an interface between two metal foils in the metal foil adhesion body. 前記第一誘電体シートは、前記支持基板側の下部第一誘電体シートと、その上に形成された上部第一誘電体シートとにてなるものであり、前記下部第一誘電体シートの所定の位置に開口を貫通形成し、該開口の壁部および底部を含む領域を覆うように被膜導体部を形成し、該被膜導体部が封止されるように前記上部第一誘電体シートを前記下部第一誘電体シート上に形成し、前記開口の底部をなす部位と接続するように前記上部第一誘電体シートに前記第一ビア導体を貫通形成するとともに、前記配線積層部を前記支持基板から剥離し、該配線積層部の前記第一誘電体シートが構成する主表面に付着した前記金属箔を除去したのちには、当該主表面に露出した前記被膜導体部を金属端子パッドとすることを特徴とする請求項１に記載の配線基板の製造方法。 The first dielectric sheet is composed of a lower first dielectric sheet on the support substrate side and an upper first dielectric sheet formed on the lower dielectric sheet. An opening is formed at a position of the film, a coated conductor portion is formed so as to cover a region including a wall portion and a bottom portion of the opening, and the upper first dielectric sheet is formed so as to seal the coated conductor portion. The first via conductor is formed through the upper first dielectric sheet so as to be connected to a portion forming the bottom of the opening and formed on the lower first dielectric sheet, and the wiring laminated portion is formed on the support substrate. After removing the metal foil attached to the main surface of the first dielectric sheet of the wiring laminate, the coated conductor exposed on the main surface is used as a metal terminal pad. The wiring board according to claim 1, wherein The method of production. 前記第一導体層の形成は、前記上部第一誘電体シートにおいて、前記開口及びその近傍を除く領域をマスク材により被膜し、メッキ処理により前記被膜導体部を選択的に形成することを特徴とする請求項２に記載の配線基板の製造方法。 The formation of the first conductor layer is characterized in that, in the upper first dielectric sheet, a region excluding the opening and the vicinity thereof is coated with a mask material, and the coated conductor portion is selectively formed by a plating process. A method for manufacturing a wiring board according to claim 2. 前記積層シート体において前記配線積層部の周囲部を除去する際、該周囲部とともに、前記支持基板及び前記下地誘電体シートの該周囲部下にあたる領域も除去することを特徴とする請求項１ないし３のいずれか１項に記載の配線基板の製造方法。 4. When removing a peripheral portion of the wiring laminated portion in the laminated sheet body, an area under the peripheral portion of the supporting substrate and the base dielectric sheet is also removed together with the peripheral portion. The manufacturing method of the wiring board of any one of these. 前記配線積層部を前記支持基板から剥離した後に、該配線積層部の前記第一誘電体シートが構成する主表面に付着した前記金属箔を除去し、前記第一ビア導体と接続された金属端子を前記主表面に形成することを特徴とする請求項１ないし４のいずれか１項に記載の配線基板の製造方法。 After peeling off the wiring laminated portion from the support substrate, the metal foil attached to the main surface of the wiring laminated portion formed by the first dielectric sheet is removed, and the metal terminal connected to the first via conductor 5. The method of manufacturing a wiring board according to claim 1, wherein: is formed on the main surface. 前記配線積層部を前記支持基板から剥離した後に、該配線積層部の前記第一誘電体シートが形成された主表面に付着した前記金属箔を選択的に除去し、前記第一ビア導体と接続され、かつ残存した前記金属箔を一部とした金属端子を形成することを特徴とする請求項１ないし４のいずれか１項に記載の配線基板の製造方法。 After peeling off the wiring laminated part from the support substrate, the metal foil attached to the main surface of the wiring laminated part on which the first dielectric sheet is formed is selectively removed and connected to the first via conductor. 5. The method of manufacturing a wiring board according to claim 1, wherein a metal terminal including a part of the remaining metal foil is formed. 6. 前記金属箔密着体及び前記第一誘電体シートは、半硬化状態の前記下地誘電体シート上に配されることを特徴とする請求項１ないし６のいずれか１項に記載の配線基板の製造方法。 The said metal foil adhesion body and said 1st dielectric sheet are distribute | arranged on the said base dielectric sheet of a semi-hardened state, The manufacturing of the wiring board of any one of Claim 1 thru | or 6 characterized by the above-mentioned. Method. コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層され、第一主表面をなす第一誘電体層に貫通形成されたビア孔内に、該第一誘電体層直下の第一導体層と接続されたビア導体が形成されてなるとともに、該ビア導体は、前記第一主表面側の端面が前記ビア孔内に位置してなり、当該端面には、金属端子が接続されてなることを特徴とする配線基板。 A first dielectric that does not have a core substrate and is composed of a dielectric layer made of a polymer material and a conductor layer alternately so that both main surfaces are composed of dielectric layers, and forms a first main surface. A via conductor connected to the first conductor layer immediately below the first dielectric layer is formed in a via hole formed through the layer, and the via conductor has an end face on the first main surface side. A wiring board, which is located in the via hole and has a metal terminal connected to the end face. 前記ビア導体の前記端面の、前記第一主表面からの深さ位置をＤ、前記ビア孔の最大径をＷとしたとき、比Ｄ／Ｗが０超過０．５以下であることを特徴とする請求項８に記載の配線基板。 When the depth position of the end face of the via conductor from the first main surface is D and the maximum diameter of the via hole is W, the ratio D / W is more than 0 and 0.5 or less. The wiring board according to claim 8. コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層され、第一主表面に、金属箔にて構成される金属端子が形成されてなることを特徴とする配線基板。 A dielectric layer made of a polymer material and a conductor layer are alternately laminated so that both main surfaces are composed of dielectric layers without having a core substrate, and the first main surface is made of metal foil. A wiring board comprising a metal terminal to be formed.
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