JP2008227290A - Part containing wiring board and part contained in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a part containing wiring board having excellent reliability by reducing variations of a clearance caused between an accommodating hole and a part. <P>SOLUTION: The wiring board 10 comprises a core board 11, a ceramic capacitor 101 and a wiring laminate part 31. An accommodating hole 90 is formed at the core board 11. A ceramic sintered body 104 constituting the ceramic capacitor 101 has a side face conductor layer 151 disposed in a partial area on a capacitor side face 106. When the ceramic sintered body 104 in which the side face conductor layer 151 is disposed is cut in a thickness direction, at a cutting face, a visible outline 109 on the side of the capacitor side face 106 is in parallel to the thickness direction of the ceramic sintered body 104, and the surface of the side face conductor layer 151 is parallel to the inner wall face 91 of the accommodating hole 90. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a component built-in wiring board having a structure in which a wiring laminated portion is formed on the surface of a core substrate, in which components such as capacitors are accommodated, and a wiring board built-in component used for the component built-in wiring substrate Is.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . As an example, a wiring board in which a chip-like capacitor is embedded in a core substrate made of a polymer material and a buildup layer is formed on the front surface and the back surface of the core substrate has been conventionally proposed (for example, see Patent Document 1). ).

One example of the conventional method for manufacturing a wiring board will be described below. First, a core substrate 204 made of a polymer material having an accommodation hole 203 that opens on both the core main surface 201 and the core back surface 202 is prepared (see FIG. 20). At the same time, a capacitor 208 (see FIGS. 21 and 22) is prepared in which a plurality of surface electrodes 207 project from the capacitor main surface 205 and the capacitor back surface 206, respectively. Next, a taping step of attaching the adhesive tape 209 to the core back surface 202 side is performed, and the opening of the housing hole 203 on the core back surface 202 side is sealed in advance. And the accommodation process which accommodates the capacitor | condenser 208 in the accommodation hole part 203 is performed, and the capacitor | condenser back surface 206 is affixed on the adhesive surface of the adhesive tape 209, and is temporarily fixed (refer FIG. 21). Next, after the gap A1 between the inner wall surface of the accommodation hole 203 and the side surface of the capacitor 208 is filled with the filler 210, a fixing step is performed to cure the capacitor A, thereby fixing the capacitor 208 (see FIG. 22). Thereafter, a buildup layer is formed by alternately forming a resin insulating layer mainly composed of a polymer material and a conductor layer on the core main surface 201 and the core back surface 202 of the core substrate 204. As a result, a desired wiring board is obtained.
Japanese Patent Laying-Open No. 2005-39243 (see FIG. 4)

  By the way, the capacitor 208 is generally formed by firing a laminated body made of a ceramic green sheet. However, warpage occurs as a whole due to the influence of firing or the like, and accordingly, the side surface 211 of the capacitor 208 may be bent or inclined (see FIGS. 23 and 24). In this state, when the capacitor 208 is accommodated in the accommodation hole 203, the width of the gap A1 generated around the capacitor 208 is partially widened or narrowed. In addition, at least a part of the side surface 211 is not parallel to the inner wall surface of the accommodation hole 203. As a result, variation occurs in the gap A1, and a portion in which the filler 210 is difficult to enter is generated. Therefore, even if the gap A1 is filled with the filler 210, an unfilled portion may occur. Therefore, when the filler 210 is deformed due to a temperature change, the stress applied to the filler 210 becomes non-uniform and the stress is locally concentrated. Therefore, the capacitor 208 cannot be fixed by the filler 210 and the reliability of the wiring board can be reduced. May decrease.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board with a built-in component that is excellent in reliability by reducing variation in a gap generated between the housing hole and the component. There is. Another object of the present invention is to provide a wiring board built-in component suitable for the above-described component built-in wiring board.

  As means for solving the above problems (means 1), a core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main surface, and a component back surface And the component main body having a component side surface, the core main surface and the component main surface facing the same side, and the inner wall surface of the housing hole and the component side surface facing each other A component housed in the hole, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface, and at least a partial region on the side surface of the component In the cut surface obtained by cutting the component main body in which the side conductor layer is arranged in the thickness direction, the outline on the side surface of the component is parallel to the thickness direction of the component main body, and the surface of the side conductor layer is the surface It is characterized by being parallel to the inner wall surface of the receiving hole There is that component built-in wiring board.

  Therefore, according to the component built-in wiring board of means 1, at least a part of the region on the side surface of the component is covered with the side conductor layer, so that the surface of the side conductor layer becomes parallel to the inner wall surface of the accommodation hole. As a result, the variation in the gap between the surface of the side conductor layer and the inner wall surface of the accommodation hole is reduced, and the filler can easily enter, so that the gap can be reliably filled with the filler. Therefore, when the filler is deformed, the stress applied to the filler becomes uniform and is not easily concentrated locally, so that the component can be reliably fixed by the filler. Therefore, a component built-in wiring board having excellent reliability can be obtained.

  The core substrate constituting the component-embedded wiring substrate is formed in a plate shape having, for example, a core main surface and a core back surface located on the opposite side, and has an accommodation hole for accommodating the component. The accommodation hole may be a non-through hole that opens only on the core main surface side, or may be a through hole that opens on both the core main surface side and the core back surface side. In addition, the component may be housed in the housing hole in a completely embedded state, or may be housed in the housing hole in a state in which a part protrudes from the opening of the housing hole.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The components constituting the component-embedded wiring board have a component main surface, a component back surface, and a component side surface. The shape of the component can be arbitrarily set. For example, it is preferable that the component has a plate shape in which the area of the component main surface is larger than the area of the component side surface. Further, the shape of the component in plan view is preferably a polygonal shape in plan view having a plurality of sides. Examples of the polygonal shape in a plan view include a substantially rectangular shape in a plan view, a substantially triangular shape in a plan view, and a substantially hexagonal shape in a plan view, and in particular, a generally rectangular shape in a plan view. It is preferable. Here, the “substantially rectangular shape in plan view” does not mean only a complete rectangular shape in plan view but also includes a shape with chamfered corners and a shape in which a part of the side is curved. .

  Suitable components include a capacitor, a semiconductor integrated circuit element (IC chip), a MEMS (Micro Electro Mechanical Systems) element manufactured by a semiconductor manufacturing process, and the like. Here, “semiconductor integrated circuit element” refers to an element mainly used as a microprocessor of a computer or the like.

  Examples of suitable capacitors include a chip capacitor, a capacitor main body, a capacitor main surface, a capacitor back surface and a capacitor side surface, and a capacitor body having a structure in which a plurality of internal electrode layers are laminated via a dielectric layer, Examples include a plurality of via conductors in a capacitor connected to a plurality of internal electrode layers, a capacitor having a plurality of surface electrodes connected to at least an end of the capacitor main surface in the plurality of via conductors in the capacitor. . The capacitor is preferably a via array type capacitor in which the plurality of capacitor via conductors are arranged in an array as a whole. With such a structure, the inductance of the capacitor can be reduced, and noise absorption and voltage stabilization can be achieved. In addition, it is easy to reduce the size of the entire capacitor, and it is also easy to reduce the size of the entire component-embedded wiring board. Moreover, a high electrostatic capacity is easily achieved for a small amount, and a more stable power supply can be achieved.

  The dielectric layer constituting the capacitor (the component main body) is located on the component main surface side closest to the first dielectric layer, and is formed thicker than the first dielectric layer. The side conductor layer may be disposed so as to be in contact with the second dielectric layer and may be disposed so as not to be in contact with the first dielectric layer. In this way, the side conductor layer is the component closer to the internal electrode layer positioned closest to the component main surface, that is, the internal electrode layer positioned between the first dielectric layer and the second dielectric layer. Since it is located on the main surface side, the side conductor layer does not contact the internal electrode layer even when the internal electrode layer is exposed on the side surface of the component. Therefore, the short circuit resulting from the contact with a side conductor layer and an internal electrode layer can be prevented.

  Examples of the dielectric layers (first dielectric layer and second dielectric layer) constituting the capacitor include a ceramic dielectric layer, a resin dielectric layer, and a dielectric layer made of a ceramic-resin composite material. As the ceramic dielectric layer, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like is preferably used, and for borosilicate glass or lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized. Further, as the resin dielectric layer, an epoxy resin, a resin such as tetrafluoroethylene resin (PTFE) containing an adhesive is preferably used. Furthermore, as the dielectric layer made of the ceramic-resin composite material, barium titanate, lead titanate, strontium titanate or the like is preferably used as the ceramic, and as the resin material, epoxy resin, phenol resin, urethane resin, Thermosetting resins such as silicone resin, polyimide resin, unsaturated polyester, thermoplastic resin such as polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, and latex such as nitrile butadiene rubber, styrene butadiene rubber, and fluoro rubber are suitable. Used for.

  The internal electrode layer, the capacitor via conductor, and the surface electrode are not particularly limited. For example, when the dielectric layer is a ceramic dielectric layer, it is preferably a metallized conductor. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, alumina), the metal powder in the metallized conductor includes nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), etc. And their alloys can be selected. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

  The component main body may have a rounded portion at least at a connection portion between the component side surface and the component main surface, or at least a connection portion between the component side surface and the component back surface. If it is such a structure, the surface of a side conductor layer will become parallel to the inner wall face of an accommodation hole part by forming a side conductor layer in a rounded part. As a result, the variation in the gap between the surface of the side conductor layer and the inner wall surface of the accommodation hole portion is reduced, and the filler can easily enter, so that the gap can be reliably filled with the filler. Further, at least a part of the line segment constituting the component side surface in the cut surface obtained by cutting the component main body in the thickness direction may be inclined with respect to the thickness direction of the component main body. If it is such a structure, the surface of a side conductor layer will become parallel to the inner wall face of an accommodation hole part by forming a side conductor layer in the inclined part of a component side. As a result, the variation in the gap between the surface of the side conductor layer and the inner wall surface of the accommodation hole is reduced, and the filler can easily enter, so that the gap can be reliably filled with the filler.

  The side conductor layer constituting the component is arranged in at least a part of the region on the side surface of the component. Note that part or all of the side conductor layers can be formed of a conductive metal material or the like. Examples of the metal material constituting the side conductor layer include copper, silver, iron, cobalt, nickel and the like. The side conductor layer is also preferably a metallized conductor when the dielectric layer is a ceramic dielectric layer, for example.

  The side conductor layer is preferably formed of the same metal material as the surface electrode. By doing so, it is not necessary to prepare a material different from the material of the surface electrode when forming the side conductor layer. Further, since the side conductor layers can be formed simultaneously in the same process as the surface electrode, the number of steps is reduced. Therefore, parts can be formed easily and at low cost.

  The thickness of the side conductor layer is not particularly limited, but is preferably set to 200 μm or more and 800 μm or less, for example. If the thickness of the side conductor layer is less than 200 μm, even if the side conductor layer is disposed, the surface of the side conductor layer may not be parallel to the inner wall surface of the accommodation hole. On the other hand, if the thickness of the side conductor layer is larger than 800 μm, the component becomes too large, and there is a possibility that the component cannot be accommodated in the accommodation hole.

  For example, when the component has a substantially rectangular shape in plan view, that is, when there are four component side surfaces, the side conductor layer may cover only one component side surface, or two or more components. The side may be covered.

  When the side conductor layer is made of, for example, a metal material, examples of the method for forming the side conductor layer include a method of forming a side conductor layer by printing a metal paste on the component side surface of the component body. However, in addition to the above method, a metal foil having the same size as the side conductor layer is applied to form a side conductor layer, or a metal foil larger than the side conductor layer is attached, and then the metal foil is etched. It is also possible to adopt a method such as forming a side conductor layer by plating or forming a side conductor layer by plating. Furthermore, as a method for forming the side conductor layer, the side conductor layer is fired simultaneously with the firing of the dielectric layers and the conductors constituting the component (the internal electrode layer, the via conductor in the capacitor, and the surface electrode). Examples include a firing method. Further, a post-firing method in which the side conductor layer is fired after the dielectric layers and the conductors constituting the above components are fired may be employed. If the side conductor layer is formed by the simultaneous firing method, the number of man-hours required for manufacturing the component is reduced, so that the component can be easily formed at low cost. On the other hand, if the side conductor layer is formed by a post-firing method, the function of the side conductor layer is equalized, and the filling amount of the filler filled in the gap between the surface of the side conductor layer and the inner wall surface of the accommodation hole is uniform. In addition, the function of the conductor constituting the component can be specialized in the function of flowing current, so that the performance of the component can be improved. Further, since the side conductor layer is formed on the dielectric layer cured by firing, the side conductor layer can be easily formed.

  Furthermore, the side conductor layer may or may not allow current to flow. The component has at least a plurality of surface electrodes on the component main surface side, and the side conductor layer is integrally formed with a surface electrode located on an outer peripheral portion of the component main surface among the plurality of surface electrodes. May be. With such a configuration, the side conductor layer can be formed simultaneously with the surface electrode. Therefore, it is not necessary to form the side conductor layer separately from the surface electrode, so that the component can be easily formed. Further, when a current is passed through the side conductor layer when the side conductor layer is connected to the ground layer, electromagnetic waves from a noise source can be shielded by the side conductor layer, and a problem that causes noise interference can be reduced.

  The wiring laminated portion constituting the component built-in wiring board has a structure in which an interlayer insulating layer mainly composed of a polymer material and a conductor layer are laminated. In addition, although the wiring laminated portion is formed only on the core main surface and the component main surface, a laminated portion having the same structure as the wiring laminated portion may be formed on the core back surface and the component back surface. Good. With this configuration, an electric circuit can be formed not only in the wiring laminated portion formed on the core main surface and the component main surface, but also in the laminated portion formed on the core back surface and the component back surface. It is possible to further increase the functionality of the substrate.

  The interlayer insulating layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the interlayer insulating layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, etc. And other thermoplastic resins. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  Further, another means (means 2) for solving the problems of the present invention is a wiring board built-in component that is used in a state of being accommodated in the accommodation hole portion of the wiring board, the component main surface, the component A component main body having a back surface and a component side surface; and a side conductor layer disposed in at least a part of the region on the component side surface; and constituting the component side surface in a cut surface obtained by cutting the component main body in a thickness direction. At least a part of the line segment is inclined with respect to the thickness direction of the component main body, and the side conductor layer is formed on at least a part of the inclined portion of the component side surface. There are built-in parts.

  Therefore, according to the means 2, the side conductor layer is formed on at least a part of the inclined portion of the side surface of the component, and the line segment constituting the surface of the side conductor layer at the cut surface is parallel to the thickness direction of the component body. When the components accommodated in the accommodation hole are fixed by, for example, a filler, the variation in the gap between the surface of the side conductor layer and the inner wall surface of the accommodation hole is reduced. Since it becomes easy to enter, the gap can be reliably filled with a filler. In addition, since the stress applied to the filler becomes uniform and does not concentrate locally when the filler is deformed, the component can be reliably fixed by the filler. Therefore, a wiring board built-in component suitable for the component built-in wiring board of the means 1 can be provided.

  Further, another means (means 3) for solving the problems of the present invention is a wiring board built-in component used in a state of being accommodated in the accommodation hole portion of the wiring board, wherein the component main surface, the component A component main body having a back surface and a component side surface, and a side conductor layer disposed in at least a part of the region on the component side surface, wherein the component main body includes at least a connection portion between the component side surface and the component main surface; Alternatively, there is a wiring board built-in component that has a rounded portion at least at a connection portion between the component side surface and the component back surface, and the side conductor layer is formed on the rounded portion.

  Therefore, according to the means 3, the side conductor layer is formed in the rounded portion, and the component in which the line segment constituting the surface of the side conductor layer is parallel to the thickness direction of the component main body in the cut surface is accommodated in the accommodation hole portion. Therefore, when the component is accommodated in the accommodation hole portion and the component accommodated in the accommodation hole portion is fixed by, for example, a filler, the variation in the gap between the surface of the side conductor layer and the inner wall surface of the accommodation hole portion is reduced, and the filling is performed. Since the agent can easily enter, the gap can be reliably filled with the filler. In addition, since the stress applied to the filler becomes uniform and does not concentrate locally when the filler is deformed, the component can be reliably fixed by the filler. Therefore, a wiring board built-in component suitable for the component built-in wiring board of the means 1 can be provided.

[First Embodiment]

  Hereinafter, a first embodiment in which a component-embedded wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, a component built-in wiring board (hereinafter referred to as “wiring board”) 10 of this embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 11, a first buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the core substrate 11, and the core substrate 11. The second buildup layer 32 is formed on the core back surface 13 (the lower surface in FIG. 1).

  The first buildup layer 31 formed on the core main surface 12 of the core substrate 11 is composed of two resin insulating layers 33 and 35 (so-called interlayer insulating layer) made of thermosetting resin (epoxy resin) and copper. The conductive layers 42 are alternately laminated. In this embodiment, the thermal expansion coefficients of the resin insulating layers 33 and 35 are about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). Here, the “thermal expansion coefficient” means a thermal expansion coefficient in a direction (XY direction) perpendicular to the thickness direction (Z direction), and TMA (thermomechanical analysis) between 0 ° C. and 100 ° C. It means the value measured by the device. “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01. In addition, the thermal expansion coefficient of the resin insulating layers 33 and 35 means an average value of measured values between 30 ° C. and the glass transition temperature (Tg).

  As shown in FIG. 1, terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin insulating layer 35. Further, the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. Note that an area including the terminal pads 44 and the solder bumps 45 is an IC chip mounting area 23 on which the IC chip 21 can be mounted. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. Further, via conductors 43 and 47 are provided in the resin insulation layers 33 and 35, respectively. These via conductors 43 and 47 electrically connect the conductor layer 42 and the terminal pad 44 to each other.

  As shown in FIG. 1, the second buildup layer 32 formed on the core back surface 13 of the core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin insulation layers 34 and 36 made of a thermosetting resin (epoxy resin) and a conductor layer 42 are alternately laminated. The thermal expansion coefficients of 34 and 36 are about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). BGA pads 48 that are electrically connected to the conductor layer 42 via via conductors 43 are formed in a lattice pattern at a plurality of locations on the lower surface of the second resin insulating layer 36. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  As shown in FIG. 1, the core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm long × 25 mm wide × 1.0 mm thick. The core substrate 11 has a thermal expansion coefficient in the plane direction (XY direction) of about 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.). In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 0 degreeC-glass transition temperature (Tg). The core substrate 11 includes a base material 161 made of glass epoxy, a sub-base material 164 formed on an upper surface and a lower surface of the base material 161 and made of an epoxy resin to which an inorganic filler such as silica filler is added, and an upper surface of the base material 161. And a conductor layer 163 made of copper and formed on the lower surface. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 163. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the core substrate 11 and is electrically connected to the conductor layer 163. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the resin insulating layer 33, and the lower end of the through-hole conductor 16 is a conductor on the lower surface of the resin insulating layer 34. A part of the layer 42 is electrically connected. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Furthermore, the core substrate 11 has one rectangular accommodation hole 90 in a plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole.

  And in the accommodation hole part 90, the ceramic capacitor 101 (component) which is a wiring board built-in component shown in FIGS. 2-5 etc. is accommodated in the embedded state. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 of the core substrate 11 and the inner wall surface 91 of the accommodation hole 90 and the capacitor side surface 106 facing each other. Yes. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view with a length of 10.0 mm × width of 10.0 mm × thickness of 0.8 mm. The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1, FIG. 2, FIG. 4, FIG. 5, etc., the ceramic capacitor 101 of this embodiment is a so-called via array type capacitor. A ceramic sintered body 104 (component main body) constituting the ceramic capacitor 101 has one capacitor main surface 102 (upper surface in FIG. 1) as a component main surface and one capacitor rear surface 103 (lower surface in FIG. 1) as a component back surface. And a plate-like object having four capacitor side surfaces 106 (left surface and right surface in FIG. 1) which are component side surfaces. In this embodiment, the thermal expansion coefficient of the ceramic sintered body 104 is less than 15 ppm / ° C., specifically about 12 to 13 ppm / ° C. The thermal expansion coefficient of the ceramic sintered body 104 refers to an average value of measured values between 30 ° C. and 250 ° C.

  As shown in FIGS. 2 and 3, the line segment 107 constituting the capacitor side surface 106 on the cut surface (front surface in FIG. 2) obtained by cutting the ceramic sintered body 104 in the thickness direction is the thickness of the ceramic sintered body 104. It is inclined with respect to the vertical direction.

  As shown in FIG. 2, the ceramic sintered body 104 has a structure in which power source internal electrode layers 141 and ground internal electrode layers 142 are alternately stacked via a ceramic dielectric layer 105 (dielectric layer). Have. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power internal electrode layer 141 and the ground internal electrode layer 142. To do. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104. The distance from the outer peripheral edge of the internal electrode layers 141 and 142 to the capacitor side surface 106 is set to 2 μm or more and 10 μm or less. Specifically, the distance from the outer peripheral edge of the internal electrode layers 141 and 142 to the capacitor side surface 106 is set to 3 μm at the minimum and 10 μm at the maximum. For this reason, the internal electrode layers 141 and 142 are not exposed to the capacitor side surface 106.

  As shown in FIGS. 1, 2, 4, and 5, a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole. In the present embodiment, for convenience of explanation, the via conductors 131 and 132 in the capacitor are illustrated in 5 columns × 5 columns, but there are actually more columns.

  2 and the like, on the capacitor main surface 102 of the ceramic sintered body 104, a plurality of main surface side power supply electrodes 111 (surface electrodes) and a plurality of main surface side ground electrodes 112 (surface electrodes) ) And protruding. Each main surface side ground electrode 112 is individually formed on the capacitor main surface 102, but may be formed integrally. The main surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground electrode 112 is connected to the plurality of ground capacitor internal electrodes. The via conductor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  Further, on the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power supply electrodes 121 (surface electrodes) and a plurality of back surface side ground electrodes 122 (surface electrodes) are projected. Each back surface side ground electrode 122 is individually formed on the capacitor back surface 103, but may be formed integrally. The back surface side power supply electrode 121 is directly connected to the end surface on the capacitor back surface 103 side of the plurality of power supply capacitor internal via conductors 131, and the back surface side ground electrode 122 is connected to the plurality of ground capacitor internal via conductors 132. Is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode layer 142. Is conducting.

  As shown in FIG. 1, the electrodes 111 and 112 on the capacitor main surface 102 side include the via conductor 47, the conductor layer 42, the via conductor 43, the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. Is electrically connected to the IC chip 21 via On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side pass through via conductors 47, conductor layers 42, via conductors 43, BGA pads 48, and solder bumps 49 with respect to electrodes (contactors) of a mother board (not shown). Are electrically connected.

  As shown in FIG. 2 and the like, the electrodes 111, 112, 121, and 122 are made of nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). These electrodes 111, 112, 121, 122 and the via conductors 131, 132 in the capacitor are disposed immediately below the substantially central portion of the IC chip 21. In the present embodiment, the diameters of the electrodes 111, 112, 121, and 122 are set to about 500 μm, and the minimum pitch length is set to about 580 μm.

  For example, when energization is performed from the motherboard side via the electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges are accumulated in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  As shown in FIGS. 1 to 5 and the like, side conductor layers 151 are formed on the inclined portions of the four capacitor side surfaces 106 of the ceramic sintered body 104, respectively. The side conductor layer 151 is a conductor layer formed so as to surround the ceramic sintered body 104 (see FIGS. 4 and 5). The side conductor layer 151 is a layer formed mainly of the same nickel as the electrodes 111, 112, 121, and 122, and the surface is covered with a copper plating layer (not shown). The thickness of the side conductor layer 151 is a maximum value (500 μm in this embodiment) at a connection portion with the capacitor main surface 102 or a connection portion with the capacitor back surface 103. Further, the thermal expansion coefficient of the side conductor layer 151 is set to a value larger than the thermal expansion coefficient of the ceramic sintered body 104, and specifically, set to about 15 ppm / ° C.

  As shown in FIGS. 2 and 3, on the cut surface (front surface in FIG. 2) obtained by cutting the ceramic sintered body 104 on which the side conductor layer 151 is disposed in the thickness direction, the outline 109 on the capacitor side surface 106 side is Further, the ceramic sintered body 104 is parallel to a virtual line L1 extending in the thickness direction. The outline 109 is constituted by a line segment that appears corresponding to the surface of the side conductor layer 151. Further, the surface of the side conductor layer 151 is parallel to the inner wall surface 91 of the accommodation hole 90.

  As shown in FIG. 1 and the like, the gap between the inner wall surface 91 of the accommodation hole 90 and the surface of the side conductor layer 151 is a filler 33a that is a part of the resin insulating layer 33 in contact with the core main surface 12. Is buried by. The filler 33 a has a function of fixing the ceramic capacitor 101 to the core substrate 11. The ceramic capacitor 101 has a substantially square shape in plan view, and has chamfered portions with chamfering dimensions of 0.55 mm or more (in this embodiment, chamfering dimensions of 0.6 mm) at the four corners. Thereby, when the filler 33a is deformed due to a temperature change, stress concentration on the corners of the ceramic capacitor 101 can be alleviated, so that the crack of the filler 33a can be prevented.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the core substrate preparation step, an intermediate product of the core substrate 11 is prepared by a conventionally known technique and prepared in advance.

  The intermediate product of the core substrate 11 is manufactured as follows. First, a copper clad laminate (see FIG. 6) in which a copper foil 162 is attached to both surfaces of a base material 161 having a length of 350 mm, a width of 375 mm, and a thickness of 0.6 mm is prepared. Next, the copper foil 162 on both sides of the copper-clad laminate is etched to pattern the conductor layer 163 by, for example, a subtractive method (see FIG. 7). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 162 are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 161 and the conductor layer 163, an epoxy resin film (thickness of 80 μm) to which an inorganic filler has been added is attached to the upper and lower surfaces of the base material 161 by thermocompression bonding. Then, the sub-base material 164 is formed (see FIG. 8).

  Next, a conductor layer 41 (for example, 50 μm) is formed on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, respectively. Specifically, after performing electroless copper plating on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 161 and the sub base material 164 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions. (See FIG. 9). The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  In the component preparation step (capacitor preparation step), the ceramic capacitor 101 is prepared by a conventionally known method and prepared in advance.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheets with the power supply internal electrode portions and the green sheets with the ground internal electrode portions are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate. Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown).

  Thereafter, the green sheet laminate is dried to solidify the green sheet laminate to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, barrel polishing is performed on the surface of the ceramic sintered body 104 (the capacitor main surface 102, the capacitor back surface 103, and the capacitor side surface 106), and then on the capacitor main surface 102 of the ceramic sintered body 104 at a predetermined position. A mask 153 having an opening 152 is stacked (see FIG. 10). The opening 152 exists at a position where the main surface side power supply electrode 111 and the main surface side ground electrode 112 are to be formed and above a position where the side conductor layer 151 is to be formed (an inclined portion of the capacitor side surface 106). Yes. Then, a paste is printed on the capacitor main surface 102 of the ceramic sintered body 104 through the mask 153. As a result, the main surface side power supply electrode 111 and the main surface side ground electrode 112 are formed on the capacitor main surface 102 of the ceramic sintered body 104 so as to cover the upper end surfaces of the via conductors 131 and 132 in each capacitor. At the same time, the side conductor layer 151 is formed on the inclined portion of the capacitor side face 106. Note that the surface of the side conductor layer 151 is parallel to the thickness direction of the ceramic sintered body 104 by polishing or embossing the side conductor layer 151 during or after the formation of the side conductor layer 151. You may shape | mold so that it may become.

  Further, after the ceramic sintered body 104 is turned upside down, a mask (not shown) having an opening at a predetermined position is laminated on the capacitor back surface 103 of the ceramic sintered body 104. The opening exists above the planned formation position of the back surface side power supply electrode 121 and the back surface side ground electrode 122 and above the planned formation position of the side conductor layer 151 (the inclined portion of the capacitor side surface 106). And a paste is printed on the capacitor | condenser back surface 103 of the ceramic sintered compact 104 through a mask. As a result, the back-side power electrode 121 and the back-side ground electrode 122 are formed so as to cover the lower end surfaces of the via conductors 131 and 132 in each capacitor on the capacitor back surface 103 of the ceramic sintered body 104, A side conductor layer 151 is formed on the inclined portion of the capacitor side face 106.

  Thereafter, the electrodes 111, 112, 121, 122 and the side conductor layer 151 are dried and solidified to some extent. Next, electroless copper plating (thickness of about 10 μm) is performed on each of the electrodes 111, 112, 121, 122 and the side conductor layer 151 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122 and the side conductor layer 151, and the ceramic capacitor 101 is completed.

  In the subsequent housing step, the ceramic capacitor 101 is housed in the housing hole 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 11). At this time, the outer shape line 109 on the capacitor side surface 106 side is made parallel to the thickness direction of the ceramic sintered body 104 and the surface of the side surface conductor layer 151 is accommodated in parallel with the inner wall surface 91 of the accommodation hole 90. The ceramic capacitor 101 is accommodated in the hole 90. The opening on the core back surface 13 side of each housing hole 90 is sealed with a peelable adhesive tape 171. The adhesive tape 171 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 171.

  Next, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, a fixing process is first performed. That is, a photosensitive epoxy resin is applied to the core main surface 12 and the capacitor main surface 102, and exposure and development are performed to form the resin insulating layer 33 (see FIG. 12). In place of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer (LCP) may be deposited. In addition, a gap between the inner wall surface 91 of the accommodation hole 90 and the surface of the side conductor layer 151 covering the capacitor side surface 106 is filled with the filler 33a which is a part of the resin insulating layer 33. Thereafter, when heat treatment is performed, the resin insulating layer 33 (filler 33a) and the side conductor layer 151 are cured, and the ceramic capacitor 101 is fixed to the core substrate 11. At this point, the adhesive tape 171 is peeled off.

  Next, a photosensitive epoxy resin is applied to the core back surface 13 and the capacitor back surface 103, and exposure and development are performed to form the resin insulating layer 34 (see FIG. 13). Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In the subsequent exposure step, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes 181 and 182 at positions where via conductors 47 are to be formed (see FIG. 14). Specifically, a via hole 181 penetrating the resin insulating layer 33 is formed to expose the main surface side power supply electrode 111 and the main surface side ground electrode 112. Similarly, a via hole 182 penetrating the resin insulating layer 34 is formed, and the back surface side power supply electrode 121 and the back surface side ground electrode 122 are exposed.

  Further, drilling is performed using a drill machine, and a through hole 191 that penetrates the core substrate 11 and the resin insulating layers 33 and 34 is formed in advance at a predetermined position (see FIG. 15). Then, after electroless copper plating is performed on the resin insulating layers 33 and 34, the inner surfaces of the via holes 181 and 182 and the inner surfaces of the through holes 191, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, the conductor layer 42 is patterned on the resin insulating layer 33 and the resin insulating layer 34 (see FIG. 16). At the same time, the through-hole conductor 16 is formed in the through hole 191, and the via conductor 47 is formed in each via hole 181, 182.

  Thereafter, a hole filling process is performed. Specifically, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form a closing body 17 (see FIG. 17).

  Next, a photosensitive epoxy resin is deposited on the resin insulating layers 33 and 34, and exposure and development are performed, whereby the resin insulating layers 35 and 184 having via holes 183 and 184 at positions where the via conductors 43 are to be formed. 36 is formed (see FIG. 17). Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In this case, via holes 183 and 184 are formed at positions where the via conductors 43 are to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 in the via holes 183 and 184, and terminal pads 44 are formed on the resin insulating layer 35. A BGA pad 48 is formed.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 10 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-cavity wiring board is divided, a large number of wiring boards 10 which are individual products can be obtained simultaneously.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the wiring substrate 10 of the present embodiment, when the side surface conductive layer 151 is formed on the inclined portion of the capacitor side surface 106, the ceramic capacitor 101 accommodated in the accommodation hole 90 is fixed by the filler 33a. The variation in the gap between the surface of the side conductor layer 151 and the inner wall surface 91 of the accommodation hole 90 is reduced, and the filler 33a can easily enter, so that the gap can be reliably filled with the filler 33a. In addition, when the filler 33a is deformed, the stress applied to the filler 33a becomes uniform and it is difficult to concentrate locally, so that the ceramic capacitor 101 can be reliably fixed by the filler 33a. Therefore, it is possible to obtain the wiring board 10 having excellent reliability.

  (2) In this embodiment, by covering the ceramic capacitor 101 with the side conductor layer 151, a gap generated between the accommodation hole 90 and the ceramic capacitor 101 is reduced. A large amount of the resin insulating layer 33 (filler 33a) need not be filled in between. As a result, the gap can be sufficiently filled with a part of the resin insulating layer 33 (filler 33a) without increasing the thickness of the resin insulating layer 33 in contact with the core main surface 12. Can be prevented. Therefore, the wiring board 10 excellent in reliability can be obtained.

  (3) In the present embodiment, the filler 33a that forms part of the resin insulating layer 33 is a filler that fills the gap between the inner wall surface 91 of the accommodation hole 90 and the surface of the side conductor layer 151 that covers the capacitor side surface 106. Therefore, it is not necessary to prepare a material different from the resin insulating layer 33 when forming the filler. Therefore, since the material necessary for manufacturing the wiring board 10 is reduced, the cost of the wiring board 10 can be reduced.

  (4) In this embodiment, since the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, the wiring connecting the ceramic capacitor 101 and the IC chip 21 is shortened, and the wiring inductance is reduced. Increase in ingredients is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

(5) In this embodiment, since the IC chip mounting area 23 is located in the area immediately above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 has high rigidity and a thermal expansion coefficient. Supported by a small ceramic capacitor 101. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.
[Second Embodiment]

  Hereinafter, a second embodiment in which the component built-in wiring board of the present invention is embodied will be described in detail with reference to the drawings. Here, the description will focus on the parts that are different from the first embodiment, and the common parts will not be described in place of the same member numbers.

  The wiring board 10 of the present embodiment is different from the ceramic capacitor 101 of the first embodiment in the configuration of the ceramic capacitor. That is, as shown in FIGS. 18 and 19, the ceramic sintered body 104 constituting the ceramic capacitor 195 of this embodiment includes a connection portion between the capacitor side surface 106 and the capacitor main surface 102, and the capacitor side surface 106 and the capacitor. Each of the connecting portions with the back surface 103 has rounded portions 108.

  Further, the distance from the outer peripheral edge of the internal electrode layers 141 and 142 to the capacitor side surface 106 is set to 2 μm or more and 10 μm or less. Specifically, the distance from the outer peripheral edge of the internal electrode layers 141 and 142 to the capacitor side surface 106 (the portion not having the rounded portion 108) is set to 10 μm. Furthermore, the distance from the outer peripheral edge of the internal electrode layers 141 and 142 to the capacitor side surface 106 (portion having the rounded portion 108) is set to 3 μm at the minimum. For this reason, the internal electrode layers 141 and 142 are not exposed to the capacitor side surface 106.

  As shown in FIGS. 18 and 19, side conductor layers 151 are formed on the four capacitor side surfaces 106 of the ceramic sintered body 104 to cover the entire region of each capacitor side surface 106. Further, the thickness of the side conductor layer 151 is the maximum value (500 μm in this embodiment) at the connection portion between the rounded portion 108 and the capacitor main surface 102 and the connection portion between the rounded portion 108 and the capacitor back surface 103. Become. In this embodiment, the entire region of each capacitor side surface 106 is covered with the side conductor layer 151, but only a part of each capacitor side surface 106 (specifically, a region having the rounded portion 108) is a side conductor. Covering with a layer 151 is preferred. In this case, the contour line 109 (see FIG. 19) on the capacitor side surface 106 side includes a line segment (a part of the line segment 107) that appears corresponding to a portion where the side conductor layer 151 is not disposed on the capacitor side surface 106, and the side surface. The line segment appears corresponding to the surface of the conductor layer 151.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (6) According to the wiring substrate 10 of the present embodiment, the ceramic capacitor 195 is accommodated in the accommodation hole 90 by forming the side conductor layer 151 at least in the rounded portion 108, and the ceramic capacitor accommodated in the accommodation hole 90. When fixing 195 with the filler 33a, the variation in the gap between the surface of the side conductor layer 151 and the inner wall surface 91 of the receiving hole 90 is reduced, and the filler 33a is also easily contained. Can be filled reliably. In addition, when the filler 33a is deformed, the stress applied to the filler 33a becomes uniform and it is difficult to concentrate locally, so that the ceramic capacitor 195 can be reliably fixed by the filler 33a. Therefore, it is possible to obtain the wiring board 10 having excellent reliability.

  (7) By the way, due to the difference in thermal expansion coefficient between the ceramic sintered body 104 and the filler 33a, stress concentrates on the corners of the ceramic capacitor 101 when the filler 33a is deformed due to temperature change, and the filler 33a and the ceramic capacitor. Adhesiveness with 101 tends to decrease. On the other hand, in the present embodiment, the side conductor layer 151 is formed at the corner portion (the round portion 108) where stress tends to concentrate. Since the difference in thermal expansion coefficient between the side conductor layer 151 and the filler 33a is smaller than the difference in thermal expansion coefficient between the ceramic sintered body 104 and the filler 33a, the stress concentration associated with the temperature change can be reduced. The filler 33a and the ceramic capacitor 101 can be reliably adhered.

  In addition, you may change embodiment of this invention as follows.

  In each of the above embodiments, the side conductor layer 151 is located on the surface electrode (main surface side power supply electrode 111 and main surface side ground electrode 112) located on the outer periphery of the capacitor main surface 102, or on the outer periphery of 103. It may be formed integrally with the surface electrodes (the back side power supply electrode 121 and the back side ground electrode 122). With such a configuration, the side conductor layer 151 can be formed simultaneously with the electrodes 111, 112, 121, 122. Therefore, it is not necessary to form the side conductor layer 151 separately from the electrodes 111, 112, 121, and 122, so that the ceramic capacitor 101 can be easily formed.

  In the second embodiment, only a part of the capacitor side surface 106 (specifically, a region having the rounded portion 108) is covered with the side conductor layer 151, and the ceramic dielectric layer 105 is covered with the first dielectric layer. You may comprise by a body layer and the 2nd dielectric material layer located in the capacitor | condenser main surface 102 side most and formed thicker than the 1st dielectric material layer. Then, the side conductor layer 151 formed at the connection portion between the capacitor side face 106 and the capacitor main face 102 is disposed so as to be in contact with the second dielectric layer, while not being in contact with the first dielectric layer. You may arrange.

  In this way, the side electrode layer 151 is the internal electrode layer located closest to the capacitor main surface 102 (that is, the internal electrode layer located between the first dielectric layer and the second dielectric layer). The power supply internal electrode layer 141 is located on the capacitor main surface 102 side. For this reason, even if the power internal electrode layer 141 and the ground internal electrode layer 142 are exposed on the capacitor side surface 106, the side conductor layer 151 does not contact the exposed portion. Therefore, it is possible to prevent a short circuit due to the contact between the side conductor layer 151 and the internal electrode layers 141 and 142.

  In order to realize the above configuration, the side conductor layer 151 extends from the capacitor main surface 102 toward the capacitor back surface 103 side, and the capacitor back surface from the end of the side conductor layer 151 on the capacitor main surface 102 side. The length to the end on the 103 side is preferably set to, for example, 50 μm or more and 150 μm or less. In this case, the side conductor layer 151 may be thinner than the electrodes 111, 112, 121, 122.

  In the above embodiments, the side conductor layer 151 is disposed on the four capacitor side surfaces 106, but may be disposed only on one capacitor side surface 106, or on two or three capacitor side surfaces 106. May be.

  In each of the above embodiments, the gap between the inner wall surface 91 of the accommodation hole 90 and the surface of the side conductor layer 151 is filled using the filler 33 a that is a part of the resin insulating layer 33. However, the gap may be filled using a filler different from the filler 33a. In this way, the function of the filler 33a can be specialized to the function of fixing the ceramic capacitor 101, so that the reliability of the wiring board 10 can be improved.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface; a component main body having a component main surface, a component back surface and a component side surface; With the main surface and the component main surface facing the same side, and with the inner wall surface of the housing hole and the component side face facing each other, the component housed in the housing hole, an interlayer insulating layer, and A wiring laminated portion having a structure in which a conductor layer is laminated on the core main surface and the component main surface, and the component main body in which the side conductor layer is disposed in at least a part of the side surface of the component. In the cut surface cut in the vertical direction, a line segment corresponding to the surface of the side conductor layer is parallel to an imaginary line extending in the thickness direction of the component body, and the surface of the side conductor layer is the receiving hole portion. Built-in component arrangement characterized by being parallel to the inner wall surface Board.

  (2) a core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface; a capacitor main surface, a capacitor back surface, and a capacitor side surface; Capacitor body having a structure in which a plurality of internal electrode layers are stacked, a plurality of via conductors in a capacitor connected to the plurality of internal electrode layers, and at least an end portion on the capacitor main surface side in the plurality of via conductors in the capacitor A plurality of surface electrodes connected to each other, with the core main surface and the capacitor main surface facing the same side, and in a state where the inner wall surface of the housing hole and the capacitor side surface face each other, It has a structure in which a capacitor housed in the housing hole, an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface, and is in contact with the core main surface A part of the interlayer insulating layer includes a wiring laminated portion that fixes the capacitor by filling a gap between the inner wall surface of the accommodation hole and the side surface of the capacitor, and a side conductor in at least a part of the capacitor side surface In the cut surface obtained by cutting the capacitor body in which the layer is disposed in the thickness direction, the outer side line of the capacitor side surface is parallel to the thickness direction of the capacitor body, and the surface of the side conductor layer is the accommodation hole portion. A capacitor-embedded wiring board, wherein the distance from the outer peripheral edge of the plurality of internal electrode layers to the side surface of the capacitor is set to 2 μm or more and 10 μm or less.

  (3) a core substrate having a core main surface and a core back surface and having a housing hole opening at least in the core main surface; a component main body having a component main surface, a component back surface and a component side surface; With the main surface and the component main surface facing the same side, and with the inner wall surface of the housing hole and the component side face facing each other, the component housed in the housing hole, an interlayer insulating layer, and A wiring laminated portion having a structure in which a conductor layer is laminated on the core main surface and the component main surface, and the component main body in which the side conductor layer is disposed in at least a part of the side surface of the component. In the cut surface cut in the vertical direction, the external line on the side surface of the component is parallel to the thickness direction of the component main body, and the surface of the side conductor layer is parallel to the inner wall surface of the receiving hole A method for manufacturing a substrate, comprising: After the substrate preparation step, the component preparation step of preparing the component in which the side conductor layer is arranged in at least a part of the side surface of the component, the core substrate preparation step, and the component preparation step, the component body In the cut surface cut in the thickness direction, the contour line on the side surface of the component is made parallel to the thickness direction of the component body, and the surface of the side conductor layer is parallel to the inner wall surface of the receiving hole portion of the core substrate. In this state, the housing step of housing the component in the housing hole, and the interlayer contacting the core main surface in the gap between the surface of the side conductor layer and the inner wall surface of the housing hole after the housing step And a fixing step of fixing the component by filling a part of the insulating layer.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. Similarly, the schematic sectional drawing which shows a ceramic capacitor. Similarly, the figure for demonstrating a ceramic capacitor. Similarly, the schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Similarly, the schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. The schematic sectional drawing which shows the ceramic capacitor in 2nd Embodiment. Similarly, the figure for demonstrating a ceramic capacitor. Explanatory drawing of the manufacturing method of the wiring board in a prior art. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing which shows the problem of a prior art. Explanatory drawing which shows the problem of a prior art.

Explanation of symbols

10 ... Component built-in wiring board (wiring board)
DESCRIPTION OF SYMBOLS 11 ... Core board | substrate 12 ... Core main surface 13 ... Core back surface 31 ... 1st buildup layers 33 and 35 as a wiring lamination | stacking part ... Resin insulating layer 42 as an interlayer insulation layer ... Conductive layer 90 ... Accommodating hole 91 ... Accommodating hole Inner wall surfaces 101, 195 of the part and ceramic capacitor 102 as the component and wiring board built-in component. Capacitor main surface 103 as the component main surface. Capacitor back surface 104 as the component back surface. Ceramic sintered body 105 as the component body. Ceramic dielectric layer 106 as a body layer ... Capacitor side surface 107 as a component side surface ... Line segment 108 constituting the component side surface ... Round portion 109 ... Outline line 111 ... Main surface side power supply electrode 112 as a surface electrode ... As a surface electrode Main-surface-side ground electrode 121... Back-surface-side power supply electrode 122 as a surface electrode... Back-surface-side ground electrode as a surface electrode 51 ... side surface conductor layer

Claims (9)

A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface;
A component main body having a component main surface, a component back surface, and a component side surface, the core main surface and the component main surface are directed to the same side, and the inner wall surface of the receiving hole and the component side surface are opposed to each other In a state where the parts are accommodated in the accommodation hole,
A wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface;
In the cut surface obtained by cutting the component main body in which the side conductor layer is disposed in at least a part of the side surface of the component in the thickness direction, the outline on the side surface of the component is parallel to the thickness direction of the component main body. A component built-in wiring board, wherein a surface of the side conductor layer is parallel to an inner wall surface of the receiving hole.   The component body has a rounded portion at least at a connection portion between the component side surface and the component main surface, or at least a connection portion between the component side surface and the component back surface. Wiring board with built-in components as described.   The line segment constituting the component side surface in the cut surface obtained by cutting the component body in the thickness direction is at least partially inclined with respect to the thickness direction of the component body. The component built-in wiring board according to 2. The component has a plurality of surface electrodes on at least the component main surface side,
The said side conductor layer is integrally formed with the surface electrode located in the outer peripheral part of the said component main surface among these surface electrodes, The one of Claims 1 thru | or 3 characterized by the above-mentioned. Component built-in wiring board. The dielectric layer constituting the component body is a first dielectric layer and a second dielectric layer that is located closest to the component main surface and is thicker than the first dielectric layer. And consist of
The side conductor layer is disposed so as to contact the second dielectric layer, and is disposed so as not to contact the first dielectric layer. The component built-in wiring board according to Item 1. A wiring board built-in component that is used in a state of being accommodated in the accommodation hole of the wiring board,
A component body having a component main surface, a component back surface and a component side surface;
A side conductor layer disposed in at least a partial region on the side surface of the component,
The line segment constituting the component side surface in the cut surface obtained by cutting the component body in the thickness direction is at least partially inclined with respect to the thickness direction of the component body.
A wiring board built-in component, wherein the side conductor layer is formed on at least a part of an inclined portion of the component side surface. A wiring board built-in component that is used in a state of being accommodated in the accommodation hole of the wiring board,
A component body having a component main surface, a component back surface and a component side surface;
A side conductor layer disposed in at least a partial region on the side surface of the component,
The component main body has a rounded portion at least at a connection portion between the component side surface and the component main surface, or at least a connection portion between the component side surface and the component back surface,
A wiring board built-in component, wherein the side conductor layer is formed in the rounded portion. The component has a plurality of surface electrodes on at least the component main surface side,
The wiring board built-in component according to claim 6, wherein the side conductor layer is integrally formed with a surface electrode located on an outer peripheral portion of the component main surface. The dielectric layer constituting the component body is a first dielectric layer and a second dielectric layer that is located closest to the component main surface and is thicker than the first dielectric layer. And consist of
The said side conductor layer is arrange | positioned so that it may contact with said 2nd dielectric material layer, and is arrange | positioned so that it may not contact with said 1st dielectric material layer. The wiring board built-in component according to Item 1.

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