JP2008218940A - Power module and method of manufacturing the same - Google Patents

Power module and method of manufacturing the same Download PDF

Info

Publication number
JP2008218940A
JP2008218940A JP2007058031A JP2007058031A JP2008218940A JP 2008218940 A JP2008218940 A JP 2008218940A JP 2007058031 A JP2007058031 A JP 2007058031A JP 2007058031 A JP2007058031 A JP 2007058031A JP 2008218940 A JP2008218940 A JP 2008218940A
Authority
JP
Japan
Prior art keywords
power module
layer
manufacturing
heat sink
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007058031A
Other languages
Japanese (ja)
Inventor
Mutsumi Ito
睦 伊藤
Masayuki Kato
雅幸 加藤
Kazuhiko Futai
和彦 二井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2007058031A priority Critical patent/JP2008218940A/en
Publication of JP2008218940A publication Critical patent/JP2008218940A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost power module with less number of components, and to provide a method of manufacturing the same. <P>SOLUTION: A process for manufacturing the power module 10 includes a step of firmly fixing a metal wiring 23 on a heat sink 21 with an insulating resin layer 26; a step of mounting an electrode terminal layer 56 and a module resin frame 53 on the heat sink 21; and a step of connecting a semiconductor chip 11 onto the metal wiring 23 by a Pb-free solder. By reducing the number of components, manufacturing cost can be reduced; and further, since a single solder layer is used, only a low-temperature melting Pb-free solder is used, and connection reliability is ensured. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体チップの発熱に対する冷却機能を有するパワーモジュールおよびその製造方法に関する。   The present invention relates to a power module having a cooling function against heat generation of a semiconductor chip and a method for manufacturing the same.

図８は、従来のＩＧＢＴチップを搭載したパワーモジュールの構造を示す断面図である。同図に示すように、ＣｕＭｏ等により構成されている放熱基板１０１の主面側には、放熱基板１０１に、半田層１０２により固定されたＡｌ板１０４と、Ａｌ板１０４の主面にＡｌろうによって固定されたＡｌＮ板１０６と、ＡｌＮ板１０６の主面にＡｌろうによって固定されたＡｌ配線１０８と、Ａｌ配線１０８の上に、半田層１０９により固定された半導体チップ１２０とを備えている。また、放熱基板１０１の裏面側には、グリース１１２によりフィン付きのヒートシンク１１３が取り付けられている。上記Ａｌ板１０４，ＡｌＮ板１０６およびＡｌ配線１０８は、ＤＢＡ基板として一体的に用いられている。   FIG. 8 is a cross-sectional view showing the structure of a power module on which a conventional IGBT chip is mounted. As shown in the figure, on the main surface side of the heat radiating substrate 101 made of CuMo or the like, an Al plate 104 fixed to the heat radiating substrate 101 by a solder layer 102 and an Al solder on the main surface of the Al plate 104. The AlN plate 106 fixed by the above, the Al wiring 108 fixed to the main surface of the AlN plate 106 by Al solder, and the semiconductor chip 120 fixed by the solder layer 109 on the Al wiring 108 are provided. Further, a heat sink 113 with fins is attached to the rear surface side of the heat dissipation substrate 101 with grease 112. The Al plate 104, AlN plate 106, and Al wiring 108 are integrally used as a DBA substrate.

このように、Ａｌ板１０４，ＡｌＮ板１０６およびＡｌ配線１０８をＤＢＡ基板（絶縁層を含む配線部材）として用いたパワーモジュールの構造は、たとえば、特許文献１に記載されている（同文献の図５参照）。
特開２００１−１６８２５６号公報 Thus, the structure of the power module using the Al plate 104, the AlN plate 106, and the Al wiring 108 as a DBA substrate (wiring member including an insulating layer) is described in, for example, Patent Document 1 (FIG. 1). 5).
JP 2001-168256 A

しかしながら、図８に示すパワーモジュールの構造では、部品数が多く必要であり、製造コストが高くなるという不具合があった。   However, the structure of the power module shown in FIG. 8 requires a large number of parts and has a disadvantage that the manufacturing cost increases.

本発明の主たる目的は、部品数が少なくて製造コストの安価なパワーモジュールを製造する方法、およびこの方法によって実現される，安価なパワーモジュールを提供することにある。   A main object of the present invention is to provide a method for manufacturing a power module with a small number of components and low manufacturing costs, and an inexpensive power module realized by this method.

また、特許文献１の図８には、チップ直下の半田層（同図の符号１２２）には、液相点が３００℃〜３３０℃の高融点半田（Ｓｎ−90%Ｐｂ）を用い、下方の半田層（同図の符号１２５）には、液相点が２１６℃程度の低融点半田（Ｓｎ−50%Ｐｂ）を用いている例が開示されている。なお、本明細書においては、組成割合を表す「％」は、重量％を示すものとする。   In FIG. 8 of Patent Document 1, a high melting point solder (Sn-90% Pb) having a liquidus point of 300 ° C. to 330 ° C. is used for the solder layer (reference numeral 122 in the figure) immediately below the chip. An example in which a low melting point solder (Sn-50% Pb) having a liquidus point of about 216 ° C. is used for the solder layer (reference numeral 125 in the figure). In the present specification, “%” representing the composition ratio represents weight%.

一般に、コストの上昇を回避したい場合には、できるだけ高融点のろう材（たとえば、特許文献１に記載されているような，融点が６００℃程度のＡｌ−11%Ｓｉ−2%Ｍｇ）の使用を避けて、リフロー炉を利用できる半田を用いる。そこで、図８に示す下方の半田層１０２には、たとえば特許文献１における低融点半田（Ｓｎ−50%Ｐｂ）や、液相点が１８３℃程度の共晶半田（Ｓｎ−37%Ｐｂ）を用い、上方の半田層１０９には、たとえば液相点が３００℃〜３３０℃の高融点半田（Ｓｎ−90%Ｐｂなど）を用いるのが一般的である。すなわち、先の半田付け工程では高融点半田を用い、後の半田付け工程では、先の工程で形成された半田層がリフロー炉内で融解しないように、低融点半田を用いるのである。   Generally, when it is desired to avoid an increase in cost, the use of a solder having a melting point as high as possible (for example, Al-11% Si-2% Mg having a melting point of about 600 ° C. as described in Patent Document 1) Use solder that can use a reflow oven. Therefore, for example, low melting point solder (Sn-50% Pb) in Patent Document 1 or eutectic solder (Sn-37% Pb) having a liquidus point of about 183 ° C. is applied to the lower solder layer 102 shown in FIG. As the upper solder layer 109, for example, a high melting point solder (Sn-90% Pb or the like) having a liquidus point of 300 ° C. to 330 ° C. is generally used. That is, high melting point solder is used in the previous soldering process, and low melting point solder is used in the subsequent soldering process so that the solder layer formed in the previous process does not melt in the reflow furnace.

近年、環境問題から各種製品として、Ｐｂ（鉛）を使わない、いわゆるＰｂフリー（鉛フリー）部品を用いることが義務づけられつつある。しかしながら、低融点半田（Ｓｎ−50%Ｐｂ）を、たとえば（Ｓｎ−3.0%Ａｇ−0.5%Ｃｕ）などの低融点のＰｂフリー半田に置き換えることは現在の技術で可能であるが、従来の高融点半田（Ｓｎ−90%Ｐｂ）に代わる，接続信頼性の高い高融点のＰｂフリー半田が存在しないのが現状である。したがって、従来のパワーモジュールの構造では、高い接続信頼性を維持しつつ、Ｐｂフリー化を図ることは困難であった。   In recent years, it has become mandatory to use so-called Pb-free (lead-free) parts that do not use Pb (lead) as various products due to environmental problems. However, although it is possible to replace the low melting point solder (Sn-50% Pb) with a low melting point Pb free solder such as (Sn-3.0% Ag-0.5% Cu), for example, At present, there is no high melting point Pb-free solder with high connection reliability, replacing the melting point solder (Sn-90% Pb). Therefore, with the conventional power module structure, it has been difficult to achieve Pb-free while maintaining high connection reliability.

そこで、本発明では、接続信頼性を維持しつつ、Ｐｂフリー化を図ることが可能なパワーモジュールの製造方法を提供することを、副次的な目的としている。   Accordingly, a secondary object of the present invention is to provide a method of manufacturing a power module that can achieve Pb-free while maintaining connection reliability.

本発明のパワーモジュールの製造方法は、ヒートシンク上に樹脂接着剤により半導体チップの配線部材を固着する工程と、ヒートシンク上にバスバーおよびその絶縁支持部材を取り付ける工程とを含んでいる。   The power module manufacturing method of the present invention includes a step of fixing a wiring member of a semiconductor chip on a heat sink with a resin adhesive and a step of attaching a bus bar and its insulating support member on the heat sink.

これにより、配線とヒートシンクとの間には、ＤＢＡ基板等の部品が不要となり、製造コストの低減を図ることができる。   As a result, parts such as a DBA substrate are not required between the wiring and the heat sink, and the manufacturing cost can be reduced.

バスバー等の取付工程を、配線部材の固着工程の後に行うことにより、接着剤の形成方法として、シート状接着剤の使用だけでなく、スクリーン印刷等を採用することが可能になり、接着剤を塗布する方法の選択範囲が拡大する。   By performing the attaching process of the bus bar after the fixing process of the wiring member, it becomes possible to adopt not only the use of sheet-like adhesive but also screen printing as an adhesive forming method. The selection range of the application method is expanded.

バスバー等の取付工程を、配線部材の固着工程の前に、樹脂によって、ヒートシンクおよびバスバーと一体成形することにより、製造コストのさらなる低減を図ることができる。   The manufacturing process of the bus bar and the like can be further reduced by manufacturing the heat sink and the bus bar integrally with the resin before the wiring member fixing process.

配線部材の固着工程では、樹脂接着剤を２層重ねて形成することにより、下層で脱泡による電気的耐圧を確保しつつ、上層で固着強度を確保して、接続信頼性の向上を図ることができる。   In the fixing process of the wiring member, by forming two layers of resin adhesives, securing the bonding strength in the upper layer while securing the electrical breakdown voltage due to defoaming in the lower layer, and improving the connection reliability Can do.

Ｐｂフリー半田により、配線部材上に半導体チップを固着する工程をさらに含むことにより、パワーモジュール全体として単一の半田層を用いるだけでよいので、比較的低融点で接続信頼性の高いＰｂフリー半田のみを用いることができる。よって、接続の信頼性を確保しつつ、Ｐｂフリー化を図ることができる。   By further including the step of fixing the semiconductor chip on the wiring member with Pb-free solder, it is only necessary to use a single solder layer for the entire power module. Therefore, Pb-free solder with a relatively low melting point and high connection reliability Only can be used. Therefore, Pb-free can be achieved while ensuring connection reliability.

本発明のパワーモジュールは、ヒートシンクの上に、半導体チップ用の配線部材を絶縁樹脂層を介在させて配線部材を設け、さらに、バスバーおよびバスバー支持用の絶縁支持部材を設けたものである。   In the power module of the present invention, a wiring member for a semiconductor chip is provided on a heat sink with an insulating resin layer interposed therebetween, and further, an insulating support member for supporting the bus bar and the bus bar is provided.

これにより、部品数の少なく、安価なパワーモジュールが得られる。   Thereby, an inexpensive power module with a small number of parts can be obtained.

本発明のパワーモジュールまたはその製造方法によると、部品数の低減により、製造コストの安価なパワーモジュールの提供を図ることができる。   According to the power module or the manufacturing method thereof of the present invention, it is possible to provide a power module with a low manufacturing cost by reducing the number of components.

（実施の形態１）
−パワーモジュールの構造−
図１は、実施の形態におけるパワーモジュールセットの構造を示す斜視図である。同図に示すように、本実施形態のパワーモジュールセットは、放熱器５０の上に、複数のパワーモジュール１０を取り付けて構成されている。放熱器５０は、天板５０ａと天板５０ａに接合された容器５０ｂとからなり、天板５０ａには、パワーモジュール１０を組み込むための多数の矩形状貫通穴が設けられている。本実施形態においては、矩形状貫通穴が多数設けられているが、１つだけでもよい。放熱器５０を構成する天板５０ａと容器５０ｂとは、アルミニウムまたはアルミニウム合金からなり、ダイキャスト，押し出し，鍛造，鋳造，機械加工等によって組み立てることができる。 (Embodiment 1)
-Power module structure-
FIG. 1 is a perspective view showing a structure of a power module set in the embodiment. As shown in the figure, the power module set of the present embodiment is configured by attaching a plurality of power modules 10 on a radiator 50. The radiator 50 includes a top plate 50a and a container 50b joined to the top plate 50a. The top plate 50a is provided with a number of rectangular through holes for incorporating the power module 10 therein. In the present embodiment, a large number of rectangular through holes are provided, but only one may be provided. The top plate 50a and the container 50b constituting the radiator 50 are made of aluminum or an aluminum alloy, and can be assembled by die casting, extrusion, forging, casting, machining, or the like.

本実施の形態では、放熱器５０は天板５０ａと容器５０ｂとを個別に形成してから両者を接合しているが、天板と容器とを一体に形成してもよい。その場合、たとえば一体型を用いたダイキャストにより放熱器を形成することができる。   In the present embodiment, the radiator 50 is formed by individually forming the top plate 50a and the container 50b and then joining the two. However, the top plate and the container may be integrally formed. In that case, the radiator can be formed, for example, by die casting using an integral type.

図２は、実施の形態に係るパワーモジュールセットのII-II線における断面図である。ただし、図２において配線構造の図示は省略されている。図３は、図２の一部を拡大して示す断面図である。本実施の形態のパワーモジュールセットにおいて、放熱器５０の天板５０ａと容器５０ｂとの間の空間５１には、熱交換媒体としての冷却水が図２の紙面に直交する方向に流れている。パワーモジュール１０は、Ｏリング２５により気密を保持しつつボルト５４により天板５０ａにネジ止めされている。また、パワーモジュール１０は、主要部材として、ＩＧＢＴなどの半導体素子が形成された半導体チップ１１と、半導体チップ１１内の半導体素子と外部部材とを電気的に接続するための金属配線２３と、金属配線２３と半導体チップ１１とを接合する，Ｐｂフリー半田を含む半田層１４と、焼結Ａｌ合金からなり半導体チップ１１で発生した熱を外方に放出するためのヒートシンク２１と、金属配線２３をヒートシンク２１に固着する絶縁樹脂層２６とを備えている。図３に示すように、半導体チップ１１の上面および下面には、それぞれ、ＩＧＢＴなどの半導体素子の活性領域に接続される上面電極１２および裏面電極１３が設けられている。そして、半導体チップ１１の裏面電極１３が、半田層１４によって、金属配線２３に導通状態で接合されている。   FIG. 2 is a cross-sectional view taken along line II-II of the power module set according to the embodiment. However, the illustration of the wiring structure is omitted in FIG. FIG. 3 is an enlarged cross-sectional view of a part of FIG. In the power module set of the present embodiment, cooling water as a heat exchange medium flows in a space 51 between the top plate 50a and the container 50b of the radiator 50 in a direction perpendicular to the paper surface of FIG. The power module 10 is screwed to the top plate 50 a by bolts 54 while being kept airtight by the O-ring 25. The power module 10 includes, as main members, a semiconductor chip 11 on which a semiconductor element such as an IGBT is formed, a metal wiring 23 for electrically connecting the semiconductor element in the semiconductor chip 11 and an external member, a metal A solder layer 14 containing Pb-free solder for joining the wiring 23 and the semiconductor chip 11, a heat sink 21 made of a sintered Al alloy for releasing heat generated in the semiconductor chip 11 to the outside, and a metal wiring 23 And an insulating resin layer 26 fixed to the heat sink 21. As shown in FIG. 3, an upper surface electrode 12 and a back surface electrode 13 connected to an active region of a semiconductor element such as an IGBT are provided on the upper surface and the lower surface of the semiconductor chip 11, respectively. The back electrode 13 of the semiconductor chip 11 is joined to the metal wiring 23 in a conductive state by the solder layer 14.

図２左上および図３に拡大詳示するように、本実施の形態では、上記絶縁樹脂層２６は、エポキシ樹脂からなる下部接着剤層２６ａと、同じくエポキシ樹脂からなる上部接着剤層２６ｂとを含んでいる。下部接着剤層２６ａは十分に脱泡されているが、上部接着剤層２６ｂには相当量の気泡が含まれており、下部接着剤層２６ａにより、金属配線２３−ヒートシンク２１間の電気的耐圧を確保しつつ、上部接着剤層２６ｂにより、金属配線２３とヒートシンク２１との接続を確保するように構成されている。   As shown in enlarged detail in the upper left of FIG. 2 and FIG. 3, in the present embodiment, the insulating resin layer 26 includes a lower adhesive layer 26a made of an epoxy resin and an upper adhesive layer 26b also made of an epoxy resin. Contains. The lower adhesive layer 26a is sufficiently defoamed, but the upper adhesive layer 26b contains a considerable amount of bubbles, and the lower adhesive layer 26a causes an electrical withstand voltage between the metal wiring 23 and the heat sink 21. The upper adhesive layer 26b secures the connection between the metal wiring 23 and the heat sink 21.

ヒートシンク２１は、平板部２１ａと、平板部２１ａの裏面側から突出するフィン部２１ｂとからなり、平板部２１ａは、金属配線２３を支持する支持部材として機能している。そして、フィン部２１ｂは、熱交換媒体である冷却水にさらされて、熱交換効率を高めるように構成されている。ただし、フィン部２１ｂは必ずしも必要ではなく、また、フィン部２１ｂに代えて、他の放熱構造体を備えていてもよい。   The heat sink 21 includes a flat plate portion 21 a and fin portions 21 b protruding from the back surface side of the flat plate portion 21 a, and the flat plate portion 21 a functions as a support member that supports the metal wiring 23. And the fin part 21b is exposed to the cooling water which is a heat exchange medium, and is comprised so that heat exchange efficiency may be improved. However, the fin part 21b is not necessarily required, and may be provided with another heat dissipation structure instead of the fin part 21b.

また、放熱器５０の天板５０ａ上に、半導体チップ１１等を囲むモジュール樹脂枠５３が設けられていて、モジュール樹脂枠５３がボルト５４によって天板５０ａに固定されている。モジュール樹脂枠５３の内部および外表面には、一体成形により、電極端子層５６（バスバー）が設けられている。モジュール樹脂枠５３は、電極端子層５６（バスバー）を支持するための絶縁支持部材として機能する。この電極端子層５６と金属配線２３とは、大電力用配線１８によって接続されており、電極端子層５６と半導体チップ１１の上面電極１２の一部とは、信号配線１７によって接続されている。これによって、パワーモジュール１０と外部機器との電気的な接続が可能になっている。また、モジュール樹脂枠５３の内方には、シリコンゲルからなるゲル層４０が設けられていて、ヒートシンク２１の上面側で半導体チップ１１，信号配線１７，大電力用配線１８，金属配線２３，半田層１４，絶縁樹脂層２６などの部材がゲル層４０内に埋設されている。   A module resin frame 53 surrounding the semiconductor chip 11 and the like is provided on the top plate 50 a of the radiator 50, and the module resin frame 53 is fixed to the top plate 50 a by bolts 54. An electrode terminal layer 56 (bus bar) is provided on the inner and outer surfaces of the module resin frame 53 by integral molding. The module resin frame 53 functions as an insulating support member for supporting the electrode terminal layer 56 (bus bar). The electrode terminal layer 56 and the metal wiring 23 are connected by the high power wiring 18, and the electrode terminal layer 56 and a part of the upper surface electrode 12 of the semiconductor chip 11 are connected by the signal wiring 17. As a result, the power module 10 and the external device can be electrically connected. Further, a gel layer 40 made of silicon gel is provided on the inner side of the module resin frame 53, and the semiconductor chip 11, the signal wiring 17, the high power wiring 18, the metal wiring 23, the solder on the upper surface side of the heat sink 21. Members such as the layer 14 and the insulating resin layer 26 are embedded in the gel layer 40.

また、本実施の形態では、Ｐｂフリー半田からなる半田層１４と、絶縁樹脂層２６とを備えている。一般に、Ｐｂフリー半田には、以下のものがある。たとえば、Ｓｎ（液相点２３２℃），Ｓｎ−3.5%Ａｇ（液相点２２１℃），Ｓｎ−3.0%Ａｇ（液相点２２２℃），Ｓｎ−3.5%Ａｇ−0.55%Ｃｕ（液相点２２０℃），Ｓｎ−3.0%Ａｇ−0.5%Ｃｕ（液相点２２０℃），Ｓｎ−1.5%Ａｇ−0.85%Ｃｕ−2.0Ｂｉ（液相点２２３℃），Ｓｎ−2.5%Ａｇ−0.5%Ｃｕ−1.0Ｂｉ（液相点２１９℃），Ｓｎ−5.8Ｂｉ（液相点１３８℃），Ｓｎ−0.55%Ｃｕ（液相点２２６℃），Ｓｎ−0.55%Ｃｕ−その他（液相点２２６℃），Ｓｎ−0.55%Ｃｕ−0.3%Ａｇ（液相点２２６℃），Ｓｎ−5.0%Ｃｕ（液相点３５８℃），Ｓｎ−3.0%Ｃｕ−0.3%Ａｇ（液相点３１２℃），Ｓｎ−3.5%Ａｇ−0.5%Ｂｉ−3.0Ｉｎ（液相点２１６℃），Ｓｎ−3.5%Ａｇ−0.5%Ｂｉ−4.0Ｉｎ（液相点２１１℃），Ｓｎ−3.5%Ａｇ−0.5%Ｂｉ−8.0Ｉｎ（液相点２０８℃），Ｓｎ−8.0%Ｚｎ−3.0%Ｂｉ（液相点１９７℃）等がある。本実施の形態では、液相点が２５０℃以下の低融点のＰｂフリー半田、たとえば、Ｓｎ−3.0%Ａｇ−0.5%Ｃｕ（液相点２２０℃）を用いているが、これに限定されるものではない。ただし、Ｓｎ−5.0%Ｃｕ（液相点３５８℃），Ｓｎ−3.0%Ｃｕ−0.3%Ａｇ（液相点３１２℃）等の高融点のＰｂフリー半田（液相点が２５０℃を超えるもの）は除くものとする。   In this embodiment, the solder layer 14 made of Pb-free solder and the insulating resin layer 26 are provided. In general, Pb-free solder includes the following. For example, Sn (liquid phase point 232 ° C.), Sn-3.5% Ag (liquid phase point 221 ° C.), Sn-3.0% Ag (liquid phase point 222 ° C.), Sn-3.5% Ag−0.55% Cu (liquid phase point) 220 ° C.), Sn-3.0% Ag-0.5% Cu (liquid phase point 220 ° C.), Sn-1.5% Ag-0.85% Cu-2.0 Bi (liquid phase point 223 ° C.), Sn-2.5% Ag-0.5% Cu -1.0Bi (liquid phase point 219 ° C), Sn-5.8Bi (liquid phase point 138 ° C), Sn-0.55% Cu (liquid phase point 226 ° C), Sn-0.55% Cu-others (liquid phase point 226 ° C) , Sn-0.55% Cu-0.3% Ag (liquid phase point 226 ° C), Sn-5.0% Cu (liquid phase point 358 ° C), Sn-3.0% Cu-0.3% Ag (liquid phase point 312 ° C), Sn- 3.5% Ag-0.5% Bi-3.0In (liquid phase point 216 ° C), Sn-3.5% Ag-0.5% Bi-4.0In (liquid phase point 211 ° C), Sn-3.5% Ag-0.5% Bi-8.0In (Liquid phase point 208 ° C), Sn-8.0% Zn 3.0% Bi (liquidus point 197 ° C.), and the like. In this embodiment, a low-melting point Pb-free solder having a liquidus point of 250 ° C. or lower, for example, Sn-3.0% Ag-0.5% Cu (liquidus point 220 ° C.) is used. It is not a thing. However, high melting point Pb-free solder such as Sn-5.0% Cu (liquid phase point 358 ° C), Sn-3.0% Cu-0.3% Ag (liquid phase point 312 ° C) (liquid phase point exceeding 250 ° C) Shall be excluded.

絶縁樹脂層２６には、本実施の形態では、金属やセラミクスの充填剤を含むエポキシ樹脂が用いられている。エポキシ樹脂の使用可能温度は、種類によって異なるが、２５０℃を超えるものを選択することは容易であり、本実施の形態では、Ｐｂフリー半田の液相点よりも高いものを用いている。したがって、後述するパワーモジュールの組み立て工程において、絶縁樹脂層２６を形成した後で、Ｐｂフリー半田のリフロー工程を行うことが可能になる。たとえば、エポキシ樹脂に、アルミナ，シリカ，アルミニウム，窒化アルミニウムなどを充填したものを用いることができ、熱伝導率が３．０（Ｗ／ｍ・Ｋ）以上であることが好ましく、５．０（Ｗ／ｍ・Ｋ）以上であることがより好ましい。   In the present embodiment, an epoxy resin containing a metal or ceramic filler is used for the insulating resin layer 26. Although the usable temperature of the epoxy resin varies depending on the type, it is easy to select a temperature exceeding 250 ° C. In this embodiment, a temperature higher than the liquid phase point of Pb-free solder is used. Therefore, it becomes possible to perform a Pb-free solder reflow process after the insulating resin layer 26 is formed in the power module assembly process described later. For example, an epoxy resin filled with alumina, silica, aluminum, aluminum nitride, or the like can be used, and the thermal conductivity is preferably 3.0 (W / m · K) or more, and 5.0 ( W / m · K) or more is more preferable.

絶縁樹脂層２６の厚みは、０．４ｍｍ以下であることが好ましく、０．２ｍｍ以下であることがより好ましい。絶縁樹脂層２６の熱抵抗は、熱伝導率と厚みに依存して定まるが、厚みが薄いほど熱抵抗が小さくなる。したがって、厚みが０．４ｍｍ以下であることにより、放熱機能が高くなることになる。   The thickness of the insulating resin layer 26 is preferably 0.4 mm or less, and more preferably 0.2 mm or less. The thermal resistance of the insulating resin layer 26 is determined depending on the thermal conductivity and thickness, but the thermal resistance decreases as the thickness decreases. Therefore, when the thickness is 0.4 mm or less, the heat dissipation function is enhanced.

本実施の形態では、ヒートシンク２１の材料として、焼結アルミニウム（焼結Ａｌ）を用いているが、これに限定されるものではない。たとえば、ＡｌＮ，ＳｉＮ，ＢＮ，ＳｉＣ，ＷＣなどのセラミックス、或いは、Ａｌ−ＳｉＣ，Ｃｕ−Ｗ，Ｃｕ−Ｍｏなどの複合材料を用いてもよい。   In the present embodiment, sintered aluminum (sintered Al) is used as the material of the heat sink 21, but the material is not limited to this. For example, ceramics such as AlN, SiN, BN, SiC, and WC, or composite materials such as Al—SiC, Cu—W, and Cu—Mo may be used.

本実施の形態では、金属配線２３の材料として、ＣｕまたはＣｕ合金を用いているが、これに限定されるものではない。たとえば、Ａｌ，Ａｌ合金，ＤＢＡ基板，ＤＢＣ基板や、Ａｌ−ＳｉＣ，Ｃｕ−Ｗ，Ｃｕ−Ｍｏなどの複合材料を用いてもよい。ただし、ＤＢＡ基板やＤＢＣ基板を用いると、製造コストが高くつく。本発明では、ＤＢＡ基板やＤＢＣ基板を用いなくても接合の信頼性を維持することができるので、金属配線２３をＣｕやＣｕ合金などの金属板単体構造とすることにより、製造コストの削減を図ることができる。   In the present embodiment, Cu or Cu alloy is used as the material of the metal wiring 23, but the material is not limited to this. For example, a composite material such as Al, Al alloy, DBA substrate, DBC substrate, Al—SiC, Cu—W, or Cu—Mo may be used. However, using a DBA substrate or a DBC substrate increases the manufacturing cost. In the present invention, since the reliability of bonding can be maintained without using a DBA substrate or a DBC substrate, manufacturing costs can be reduced by making the metal wiring 23 a single metal plate structure such as Cu or Cu alloy. Can be planned.

−パワーモジュールの製造工程−
次に、図４（ａ）〜（ｄ），図５（ａ）〜（ｄ）および図６（ａ）〜（ｃ）を参照しながら、本実施の形態のパワーモジュールの製造方法について説明する。図４（ａ）〜（ｄ）は、本実施の形態の製造工程における，樹脂接着剤の塗布からモジュール樹脂枠の取付までの工程を示す断面図である。図５（ａ）〜（ｄ）は、本実施の形態の製造工程における，チップマウントからポッティングまでの工程を示す断面図である。図６（ａ）〜（ｃ）は、本実施の形態の製造工程における，Ｏリングの設置からボルトの締結までの工程を示す断面図である。 -Power module manufacturing process-
Next, a method for manufacturing the power module of the present embodiment will be described with reference to FIGS. 4 (a) to (d), FIGS. 5 (a) to (d) and FIGS. 6 (a) to (c). . FIGS. 4A to 4D are cross-sectional views showing steps from application of a resin adhesive to attachment of a module resin frame in the manufacturing process of the present embodiment. 5A to 5D are cross-sectional views showing steps from chip mounting to potting in the manufacturing process of the present embodiment. FIGS. 6A to 6C are cross-sectional views showing steps from installation of an O-ring to fastening of a bolt in the manufacturing process of the present embodiment.

まず、図４（ａ）に示す工程で、焼結Ａｌからなり、平板部２１ａとフィン部２１ｂとを有するヒートシンク２１を準備する。そして、ヒートシンク２１の平板部２１ａの上面上に、高熱伝導率を有する絶縁性エポキシ樹脂をスクリーン印刷等により塗布し、硬化させて、下部接着剤層２６ａを形成する。このとき、金属配線は下部接着剤層２６ａの上に設置せず、硬化前に、真空引きによって下部接着剤層２６ａの気泡を十分に抜く（脱泡処理）。下部接着剤層２６ａの硬化後の厚みは、設計耐圧によって定まる。   First, in the step shown in FIG. 4A, a heat sink 21 made of sintered Al and having a flat plate portion 21a and fin portions 21b is prepared. Then, on the upper surface of the flat plate portion 21a of the heat sink 21, an insulating epoxy resin having high thermal conductivity is applied by screen printing or the like and cured to form the lower adhesive layer 26a. At this time, the metal wiring is not placed on the lower adhesive layer 26a, and before curing, air bubbles in the lower adhesive layer 26a are sufficiently removed by vacuuming (defoaming process). The thickness of the lower adhesive layer 26a after curing is determined by the design pressure resistance.

次に、図４（ｂ）に示す工程で、下部接着剤層２６ａの上に重ねて、上部接着剤層２６ｂを塗布した後、所定形状にパターニングされた金属配線２３を上部接着剤層２６ｂの上にマウントする。   Next, in the step shown in FIG. 4B, after the upper adhesive layer 26b is applied over the lower adhesive layer 26a, the metal wiring 23 patterned into a predetermined shape is formed on the upper adhesive layer 26b. Mount on top.

そして、図４（ｃ）に示す工程で、上部接着剤層２６ｂを硬化させる。上部接着剤層２６ｂの硬化後の厚みは、必要な接着強度に応じて定まる。このように、下部接着剤層２６ａおよび上部接着剤層２６ｂからなる絶縁樹脂層２６により、金属配線２３をヒートシンク２１の平板部２１の上面に固着する。ただし、単一の接着剤層からなる絶縁樹脂層２６によって、金属配線２３をヒートシンク２１に固着してもよい。   Then, in the step shown in FIG. 4C, the upper adhesive layer 26b is cured. The thickness of the upper adhesive layer 26b after curing is determined according to the required adhesive strength. Thus, the metal wiring 23 is fixed to the upper surface of the flat plate portion 21 of the heat sink 21 by the insulating resin layer 26 including the lower adhesive layer 26 a and the upper adhesive layer 26 b. However, the metal wiring 23 may be fixed to the heat sink 21 by the insulating resin layer 26 made of a single adhesive layer.

次に、図４（ｄ）に示す工程で、ヒートシンク２１の平板部２１ａの上に、モジュール樹脂枠５３を取り付ける。モジュール樹脂枠５３の内部および外表面には、電極端子層５６が一体成形により形成されている。そして、モジュール樹脂枠５３の内側には、電極端子層５６の一部が露出している。   Next, in the step shown in FIG. 4D, the module resin frame 53 is attached on the flat plate portion 21 a of the heat sink 21. Electrode terminal layers 56 are integrally formed on the inner and outer surfaces of the module resin frame 53. A part of the electrode terminal layer 56 is exposed inside the module resin frame 53.

次に、図５（ａ）に示す工程で、金属配線２３の上に、Ｐｂフリー半田を吐出または印刷し、Ｐｂフリー半田の上に、半導体チップ１１をマウントする。半導体チップ１１には、パワーデバイスとして機能するＩＧＢＴと、ダイオードとが形成されている。さらに、図５（ｂ）に示す工程で、パワーモジュールをリフロー炉に投入し、半導体チップ１１と金属配線２３とを接合する半田層１４を形成する。このときのリフロー炉の雰囲気は不活性ガス雰囲気または還元性雰囲気で、炉内の最高温度は２６０℃である。その後、フラックス洗浄を行なって、フラックス残渣を除去する。なお、この工程は、金属配線２３を絶縁樹脂層２６によってヒートシンク２１に固着する前に行なってもよい。   Next, in a step shown in FIG. 5A, Pb-free solder is discharged or printed on the metal wiring 23, and the semiconductor chip 11 is mounted on the Pb-free solder. The semiconductor chip 11 is formed with an IGBT functioning as a power device and a diode. Further, in the step shown in FIG. 5B, the power module is put into a reflow furnace, and the solder layer 14 for joining the semiconductor chip 11 and the metal wiring 23 is formed. The atmosphere of the reflow furnace at this time is an inert gas atmosphere or a reducing atmosphere, and the maximum temperature in the furnace is 260 ° C. Thereafter, flux cleaning is performed to remove the flux residue. This step may be performed before the metal wiring 23 is fixed to the heat sink 21 by the insulating resin layer 26.

次に、図５（ｃ）に示す工程で、比較的大径（たとえば４００μｍ径）のＡｌワイヤを用いたワイヤボンディングを行う。そして、半導体チップ１１の上面電極１２（図３参照）同士や、上面電極１２と金属配線２３との間、金属配線２３と電極端子層５６との間を接続する大電力用配線１８を形成する。その後、小径（たとえば１２５μｍ径）のＡｌワイヤを用いたワイヤボンディングを行なって、半導体チップ１１の上面電極１２と電極端子層５６との間を接続する信号配線１７を形成する。   Next, in the step shown in FIG. 5C, wire bonding using a relatively large diameter (for example, 400 μm diameter) Al wire is performed. Then, the high-power wirings 18 that connect the top surface electrodes 12 (see FIG. 3) of the semiconductor chip 11, between the top surface electrode 12 and the metal wiring 23, and between the metal wiring 23 and the electrode terminal layer 56 are formed. . Thereafter, wire bonding using an Al wire having a small diameter (for example, 125 μm diameter) is performed to form the signal wiring 17 that connects the upper surface electrode 12 of the semiconductor chip 11 and the electrode terminal layer 56.

次に、図５（ｄ）に示す工程で、シリコンゲルを用いたポッティングにより、モジュール樹脂枠５３の内方を埋めるゲル層４０を形成する。これにより、ヒートシンク２１の上面に設けられている、半導体チップ１１，信号配線１７，大電力用配線１８，金属配線２３，半田層１４，絶縁樹脂層２６などの部材が、ゲル層４０内に埋め込まれる。   Next, in the step shown in FIG. 5D, the gel layer 40 that fills the inside of the module resin frame 53 is formed by potting using silicon gel. Thereby, members such as the semiconductor chip 11, the signal wiring 17, the high power wiring 18, the metal wiring 23, the solder layer 14, and the insulating resin layer 26 provided on the upper surface of the heat sink 21 are embedded in the gel layer 40. It is.

次に、図６（ａ）に示す工程で、準備されている天板５０ａの矩形状貫通穴の周縁部に設けられた環状溝にＯリング２５を設置する。   Next, in the step shown in FIG. 6A, an O-ring 25 is installed in an annular groove provided at the peripheral edge of the rectangular through hole of the prepared top plate 50a.

次に、図６（ｂ）に示す工程で、天板５０ａの矩形状貫通穴にヒートシンク２１のフィン部２１ｂを挿通させて、パワーモジュール１０を放熱器５０にマウントし、図６（ｃ）に示す工程で、ボルト５４により、パワーモジュール１０を天板５０ａに固定する。同様にして、複数のパワーモジュールを、放熱器５０の複数の矩形状貫通穴に、それぞれ取り付ける。   Next, in the step shown in FIG. 6B, the fin portion 21b of the heat sink 21 is inserted into the rectangular through hole of the top plate 50a, and the power module 10 is mounted on the radiator 50. In the illustrated process, the power module 10 is fixed to the top board 50a by the bolt 54. Similarly, the plurality of power modules are respectively attached to the plurality of rectangular through holes of the radiator 50.

上述の工程により、放熱器５０の天板５０ａにパワーモジュール１０が実装された後、天板５０ａが容器５０ｂに接合される（図１および図２参照）。この接合は、機械かしめ等によって行なってもよい。これより、パワーモジュールセットが形成される。なお、先に天板５０ａと容器５０ｂとを接合してから、天板５０ａに各パワーモジュール１０を取り付けてもよい。   After the power module 10 is mounted on the top plate 50a of the radiator 50 by the above-described steps, the top plate 50a is joined to the container 50b (see FIGS. 1 and 2). This joining may be performed by mechanical caulking or the like. Thus, a power module set is formed. In addition, after joining the top plate 50a and the container 50b previously, you may attach each power module 10 to the top plate 50a.

本実施の形態によると、図８に示される放熱基板１０１やＤＢＡ基板などの部材を用いることなく、金属配線２３を、絶縁樹脂層２６を挟んでヒートシンク２１に接続する構造としているので、部品数の低減により、製造コストの低減を図ることができる。   According to the present embodiment, the metal wiring 23 is connected to the heat sink 21 with the insulating resin layer 26 interposed therebetween without using members such as the heat dissipation substrate 101 and the DBA substrate shown in FIG. By reducing the manufacturing cost, the manufacturing cost can be reduced.

また、従来用いられていた２つの半田層に代えて、１つの半田層１４と、樹脂接着剤からなる絶縁樹脂層２６とを用いているので、工程の先後に応じて低融点のＰｂフリー半田と高融点のＰｂフリー半田とを用いる必要はなく、低融点のＰｂフリー半田だけで済むことになる。現在、Ｐｂフリー半田として、比較的Ｃｕ組成比の高いＰｂフリー半田（たとえば液相点が３００℃以上のＳｎ−5.0%Ｃｕ，Ｓｎ−3.0%Ｃｕ−0.3%Ａｇ）も開発されているが、銅喰われ問題，酸化物問題はじめ多くの問題が重なって、確実な接続信頼性を有する高融点のＰｂフリー半田を得ることは困難である。一方、低融点のＰｂフリー半田としては、たとえば液相点が２２０℃のＳｎ−3.0%Ａｇ−0.5%Ｃｕ（ＪＥＩＴＡ推奨合金）などの接続信頼性の高いものが得られている。また、樹脂接着剤としては、使用可能温度が３００℃を超えるエポキシ樹脂など、低融点のＰｂフリー半田の液相点よりも高温に耐えうるものは容易に得られる。したがって、本実施の形態により、半田層１４を低融点のＰｂフリー半田を用いて、接続信頼性を確保しつつ、Ｐｂフリー化を図ることができるのである。   In addition, since one solder layer 14 and an insulating resin layer 26 made of a resin adhesive are used in place of the two solder layers conventionally used, a low-melting point Pb-free solder is used depending on the process before and after the process. It is not necessary to use high melting point Pb-free solder, and only low melting point Pb-free solder is required. Currently, Pb-free solder having a relatively high Cu composition ratio (for example, Sn-5.0% Cu, Sn-3.0% Cu-0.3% Ag having a liquidus point of 300 ° C. or higher) has been developed as a Pb-free solder. It is difficult to obtain high melting point Pb-free solder having reliable connection reliability due to many problems such as copper erosion problem and oxide problem. On the other hand, as the low melting point Pb-free solder, for example, a solder having high connection reliability such as Sn-3.0% Ag-0.5% Cu (JEITA recommended alloy) having a liquidus point of 220 ° C. has been obtained. Moreover, as the resin adhesive, an epoxy resin having a usable temperature exceeding 300 ° C. can easily be obtained that can withstand a higher temperature than the liquid phase point of the low melting point Pb-free solder. Therefore, according to the present embodiment, the solder layer 14 can be made Pb-free while using Pb-free solder having a low melting point while ensuring connection reliability.

また、本実施の形態のパワーモジュールの製造方法では、先に、樹脂接着剤を用いて絶縁樹脂層２６を形成してから、Ｐｂフリー半田を用いて半田層１４を形成しているので、下方の部材の固着から上方の部材の固着までを、順次、効率よく行うことができる。すなわち、絶縁樹脂層２６の形成時には、金属配線２３のみを把持して樹脂接着剤の上に載置すればよく、半田層１４の形成時には、半導体チップ１１のみを把持してＰｂフリー半田の上に載置すればよいので、先に半田層１４を形成して半導体チップ１１および金属配線２３をヒートシンク２１上に載置するのに比べ、組立作業のための装置が簡素化され、作業能率も高くなる。よって、製造コストの低減を図ることができる。   In the power module manufacturing method of the present embodiment, the insulating resin layer 26 is first formed using a resin adhesive, and then the solder layer 14 is formed using Pb-free solder. From the fixing of the member to the fixing of the upper member can be performed sequentially and efficiently. That is, when the insulating resin layer 26 is formed, only the metal wiring 23 is gripped and placed on the resin adhesive, and when the solder layer 14 is formed, only the semiconductor chip 11 is gripped and placed on the Pb-free solder. Therefore, compared with the case where the solder layer 14 is first formed and the semiconductor chip 11 and the metal wiring 23 are placed on the heat sink 21, the assembly apparatus is simplified and the work efficiency is also improved. Get higher. Therefore, the manufacturing cost can be reduced.

さらに、本実施の形態の製造方法では、図４（ｂ）〜（ｄ）に示すように、ヒートシンク２１上に、絶縁樹脂層２６により金属配線２３を固着してから、電極端子層５６およびモジュール樹脂枠５３を、ヒートシンク２１上に取り付けているので、絶縁樹脂層２６（下部接着剤層２６ａおよび上部接着剤層２６ｂ）を形成する際には、スクリーン印刷を用いることができる。ただし、シート状のエポキシ樹脂を用いる場合には、電極端子層５６およびモジュール樹脂枠５３の取付と、金属配線２３の固着とのいずれを先に行なってもよい。つまり、本実施の形態のように、電極端子層５６およびモジュール樹脂枠５３の取付を、金属配線２３の固着の後に行うことにより、接着剤を塗布する方法の選択範囲が拡大することになる。   Furthermore, in the manufacturing method of the present embodiment, as shown in FIGS. 4B to 4D, after the metal wiring 23 is fixed on the heat sink 21 by the insulating resin layer 26, the electrode terminal layer 56 and the module are fixed. Since the resin frame 53 is mounted on the heat sink 21, screen printing can be used when forming the insulating resin layer 26 (the lower adhesive layer 26a and the upper adhesive layer 26b). However, when a sheet-like epoxy resin is used, either the attachment of the electrode terminal layer 56 and the module resin frame 53 or the fixing of the metal wiring 23 may be performed first. That is, the selection range of the method for applying the adhesive is expanded by attaching the electrode terminal layer 56 and the module resin frame 53 after the metal wiring 23 is fixed as in the present embodiment.

また、絶縁樹脂層２６を下部接着剤層２６ａと、上部接着剤層２６ｂとに分けて、２回塗りを行っているので、以下の効果を発揮することができる。エポキシ樹脂を塗布して、その上に金属配線２３を設置すると、硬化前に真空引きなどによっても気泡を十分に抜くことは困難である。そこで、下部接着剤層２６ａを塗布した後、金属配線２３を設置せずに、真空引きを行うことにより、硬化前に下部接着剤層２６ａ中の気泡を十分抜くことができる。空気の耐圧は、約１ｋＶ／ｍｍであるが、エポキシ樹脂の耐圧は１０ｋＶ／ｍｍ以上である。したがって、パワーモジュールが配置される機器において、種々のサージが印加されることを想定すると、接着剤層の気泡を十分に抜いておくことが好ましい。よって、本実施の形態のごとく、２層塗りの接着剤層からなる絶縁樹脂層２６を形成することにより、下部接着剤層２６ａにより耐圧を確保しつつ、上部接着剤層２６ｂにより金属配線２３とヒートシンク２１との固着強度を確保することができる。   Moreover, since the insulating resin layer 26 is divided into the lower adhesive layer 26a and the upper adhesive layer 26b and applied twice, the following effects can be exhibited. When an epoxy resin is applied and the metal wiring 23 is placed thereon, it is difficult to sufficiently remove bubbles even by evacuation before curing. Therefore, after applying the lower adhesive layer 26a, by performing evacuation without installing the metal wiring 23, bubbles in the lower adhesive layer 26a can be sufficiently removed before curing. The pressure resistance of air is about 1 kV / mm, but the pressure resistance of epoxy resin is 10 kV / mm or more. Therefore, assuming that various surges are applied to the device in which the power module is disposed, it is preferable to sufficiently remove bubbles from the adhesive layer. Therefore, as in the present embodiment, by forming the insulating resin layer 26 composed of the two-layered adhesive layer, the lower adhesive layer 26a ensures the withstand voltage, and the upper adhesive layer 26b and the metal wiring 23 The fixing strength with the heat sink 21 can be ensured.

（実施の形態２）
次に、図７（ａ）〜（ｃ）を参照しながら、実施の形態２のパワーモジュールの製造方法について説明する。図７（ａ）〜（ｃ）は、本実施の形態の製造工程における，樹脂接着剤の塗布からモジュール樹脂枠の取付までの工程を示す断面図である。なお、本実施の形態においても、チップマウントからポッティングまでの工程、およびＯリングの設置からボルトの締結までの工程は、実施の形態１における図５（ａ）〜（ｄ）および図６（ａ）〜（ｃ）と同様であるので、図示を省略する。 (Embodiment 2)
Next, the manufacturing method of the power module of Embodiment 2 is demonstrated, referring FIG. 7 (a)-(c). FIGS. 7A to 7C are cross-sectional views showing steps from application of the resin adhesive to attachment of the module resin frame in the manufacturing process of the present embodiment. Also in the present embodiment, the steps from tip mounting to potting and the steps from O-ring installation to bolt fastening are shown in FIGS. 5A to 5D and FIG. ) To (c), the illustration is omitted.

まず、図７（ａ）に示す工程で、焼結Ａｌからなり、平板部２１ａとフィン部２１ｂとを有するヒートシンク２１を準備する。また、電極端子層５６を形成しておく。そして、ヒートシンク２１および電極端子層５６を、モジュール樹脂枠５３用の成型用金型にセットして、ＰＰＳなどの樹脂を流し込むことにより、ヒートシンク２１，電極端子層５６およびモジュール樹脂枠５３を一体的に成形する（アウトサート成形）。   First, in the step shown in FIG. 7A, a heat sink 21 made of sintered Al and having a flat plate portion 21a and fin portions 21b is prepared. Moreover, the electrode terminal layer 56 is formed. The heat sink 21 and the electrode terminal layer 56 are set in a molding die for the module resin frame 53, and a resin such as PPS is poured into the heat sink 21, the electrode terminal layer 56, and the module resin frame 53. (Outsert molding).

次に、図７（ｂ）に示す工程で、ヒートシンク２１の平板部２１ａの上面上に、高熱伝導率を有する，シート状の絶縁性エポキシ樹脂を設置し、硬化させて、下部接着剤層２６ａを形成する。このとき、金属配線は下部接着剤層２６ａの上に設置せず、硬化前に、真空引きによって下部接着剤層２６ａの気泡を十分に抜く（脱泡処理）。下部接着剤層２６ａの硬化後の厚みは、設計耐圧によって定まる。   Next, in the step shown in FIG. 7B, a sheet-like insulating epoxy resin having high thermal conductivity is placed on the upper surface of the flat plate portion 21a of the heat sink 21, and cured, and the lower adhesive layer 26a. Form. At this time, the metal wiring is not placed on the lower adhesive layer 26a, and before curing, air bubbles in the lower adhesive layer 26a are sufficiently removed by vacuuming (defoaming process). The thickness of the lower adhesive layer 26a after curing is determined by the design pressure resistance.

さらに、下部接着剤層２６ａの上に重ねて、上部接着剤層２６ｂを塗布した後、所定形状にパターニングされた金属配線２３を上部接着剤層２６ｂの上にマウントする。   Further, after applying the upper adhesive layer 26b so as to overlap the lower adhesive layer 26a, the metal wiring 23 patterned in a predetermined shape is mounted on the upper adhesive layer 26b.

そして、図７（ｃ）に示す工程で、上部接着剤層２６ｂを硬化させる。上部接着剤層２６ｂの硬化後の厚みは、必要な接着強度に応じて定まる。このように、下部接着剤層２６ａおよび上部接着剤層２６ｂからなる絶縁樹脂層２６により、金属配線２３をヒートシンク２１の平板部２１の上面に固着する。ただし、１層の接着剤層からなる絶縁樹脂層２６によって、金属配線２３をヒートシンク２１に固着してもよい。   Then, in the step shown in FIG. 7C, the upper adhesive layer 26b is cured. The thickness of the upper adhesive layer 26b after curing is determined according to the required adhesive strength. Thus, the metal wiring 23 is fixed to the upper surface of the flat plate portion 21 of the heat sink 21 by the insulating resin layer 26 including the lower adhesive layer 26 a and the upper adhesive layer 26 b. However, the metal wiring 23 may be fixed to the heat sink 21 by the insulating resin layer 26 made of one adhesive layer.

その後の工程は、実施の形態１における図５（ａ）〜〜（ｄ）および図６（ａ）〜（ｃ）に示すとおりである。   Subsequent steps are as shown in FIGS. 5A to 5D and FIGS. 6A to 6C in the first embodiment.

本実施の形態のパワーモジュールの製造方法によると、ヒートシンク２１，電極端子層５６およびモジュール樹脂枠５３を一体的に成形しているので、製造工程が簡素化され、製造コストの低減を図ることができる。   According to the power module manufacturing method of the present embodiment, since the heat sink 21, the electrode terminal layer 56, and the module resin frame 53 are integrally formed, the manufacturing process can be simplified and the manufacturing cost can be reduced. it can.

（他の実施の形態）
本発明のパワーモジュールに配置される半導体素子は、ワイドバンドギャップ半導体（ＳｉＣ，ＧａＮなど）を用いたパワーデバイスでもよいし、Ｓｉを用いたパワーデバイスでもよい。 (Other embodiments)
The semiconductor element disposed in the power module of the present invention may be a power device using a wide band gap semiconductor (SiC, GaN, etc.) or a power device using Si.

上記実施の形態では、半導体チップ１１に、ＩＧＢＴが形成されているが、ＭＯＳＦＥＴ，ダイオード，ＪＦＥＴなどが形成された半導体チップを用いてもよい。   In the above embodiment, the IGBT is formed on the semiconductor chip 11, but a semiconductor chip on which a MOSFET, a diode, a JFET, or the like is formed may be used.

上記実施の形態では、天板５０ａに多数のパワーモジュール１０を取り付ける構造を採ったが、天板を兼ねる単一のヒートシンク上に多数の半導体チップを搭載してもよい。   In the above embodiment, a structure in which a large number of power modules 10 are attached to the top plate 50a is adopted. However, a large number of semiconductor chips may be mounted on a single heat sink that also serves as the top plate.

ヒートシンク２１との熱交換を行う熱交換媒体は、冷却能やコストを考慮すると、フロリナートや水などの液体であることが好ましい。ただし、ヘリウム，アルゴン，窒素，空気などの気体であってもよい。   The heat exchange medium for exchanging heat with the heat sink 21 is preferably a liquid such as fluorinate or water in consideration of cooling ability and cost. However, it may be a gas such as helium, argon, nitrogen or air.

上記各実施の形態では、絶縁樹脂層２６を熱硬化樹脂であるエポキシ樹脂によって構成したが、ＰＰＳなどの熱可塑性樹脂によって構成してもよい。その場合には、絶縁樹脂層２６の上に金属配線２３を設置した状態でも、気泡を抜くことが容易であるので、接着剤層の１回塗りで済み、製造コストがより安価になる。   In each of the above embodiments, the insulating resin layer 26 is made of an epoxy resin that is a thermosetting resin, but may be made of a thermoplastic resin such as PPS. In that case, even when the metal wiring 23 is placed on the insulating resin layer 26, it is easy to remove the bubbles, so that the adhesive layer only needs to be applied once and the manufacturing cost becomes lower.

上記開示された本発明の実施の形態の構造は、あくまで例示であって、本発明の範囲はこれらの記載の範囲に限定されるものではない。本発明の範囲は、特許請求の範囲の記載によって示され、さらに特許請求の範囲の記載と均等の意味及び範囲内でのすべての変更を含むものである。   The structure of the embodiment of the present invention disclosed above is merely an example, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

本発明のパワーモジュールは、ＭＯＳＦＥＴ，ＩＧＢＴ，ダイオード，ＪＦＥＴ等を搭載した各種機器に利用することができる。   The power module of the present invention can be used for various devices equipped with MOSFET, IGBT, diode, JFET and the like.

実施の形態におけるパワーモジュールセットの構造を示す斜視図である。It is a perspective view which shows the structure of the power module set in embodiment. 実施の形態に係るパワーモジュールセットのII-II線における断面図である。It is sectional drawing in the II-II line of the power module set which concerns on embodiment. 図２の一部を拡大して示す断面図である。It is sectional drawing which expands and shows a part of FIG. （ａ）〜（ｄ）は、実施の形態１の製造工程における，樹脂接着剤の塗布からモジュール樹脂枠の取付までの工程を示す断面図である。(A)-(d) is sectional drawing which shows the process from application | coating of a resin adhesive to attachment of a module resin frame in the manufacturing process of Embodiment 1. FIG. （ａ）〜（ｄ）は、実施の形態１の製造工程における，チップマウントからポッティングまでの工程を示す断面図である。(A)-(d) is sectional drawing which shows the process from the chip mounting to potting in the manufacturing process of Embodiment 1. FIG. （ａ）〜（ｃ）は、実施の形態１の製造工程における，Ｏリングの設置からボルトの締結までの工程を示す断面図である。(A)-(c) is sectional drawing which shows the process from installation of an O ring in the manufacturing process of Embodiment 1 to the fastening of a volt | bolt. （ａ）〜（ｃ）は、実施の形態２の製造工程における，樹脂接着剤の塗布からモジュール樹脂枠の取付までの工程を示す断面図である。(A)-(c) is sectional drawing which shows the process from application | coating of a resin adhesive to attachment of a module resin frame in the manufacturing process of Embodiment 2. FIG. 従来のＩＧＢＴチップを搭載したパワーモジュールの構造を示す断面図である。It is sectional drawing which shows the structure of the power module carrying the conventional IGBT chip | tip.

符号の説明Explanation of symbols

１０ パワーモジュール
１１ 半導体チップ
１２ 上面電極
１３ 裏面電極
１４ 半田層
１７ 信号配線
１８ 大電力用配線
２１ ヒートシンク
２１ａ 平板部
２１ｂ フィン部
２３ 金属配線
２５ Ｏリング
２６ 絶縁樹脂層
２６ａ 下部接着剤層
２６ｂ 上部接着剤層
４０ ゲル層
５０ 放熱器
５０ａ 天板
５０ｂ 容器
５１ 空間
５３ モジュール樹脂枠
５６ 電極端子層 DESCRIPTION OF SYMBOLS 10 Power module 11 Semiconductor chip 12 Upper surface electrode 13 Back surface electrode 14 Solder layer 17 Signal wiring 18 High power wiring 21 Heat sink 21a Flat plate part 21b Fin part 23 Metal wiring 25 O-ring 26 Insulating resin layer 26a Lower adhesive layer 26b Upper adhesive Layer 40 Gel layer 50 Radiator 50a Top plate 50b Container 51 Space 53 Module resin frame 56 Electrode terminal layer

Claims (6)

ヒートシンク上に、樹脂接着剤により半導体チップの配線部材を固着する工程（ａ）と、
前記工程（ａ）の後または前に、前記ヒートシンク上に、バスバーおよび該バスバー支持用の絶縁支持部材を取り付ける工程（ｂ）と、
を含むパワーモジュールの製造方法。 A step (a) of fixing a wiring member of a semiconductor chip on a heat sink by a resin adhesive;
A step (b) of attaching a bus bar and an insulating support member for supporting the bus bar on the heat sink after or before the step (a);
The manufacturing method of the power module containing. 請求項１記載のパワーモジュールの製造方法において、
前記工程（ｂ）は、前記工程（ａ）の後で行われる、パワーモジュールの製造方法。 In the manufacturing method of the power module of Claim 1,
The said process (b) is a manufacturing method of the power module performed after the said process (a). 請求項１記載のパワーモジュールの製造方法において、
前記工程（ｂ）は、前記工程（ａ）の前に、前記絶縁支持部材を、樹脂によって、前記ヒートシンクおよびバスバーと一体成形することにより行われる、パワーモジュールの製造方法。 In the manufacturing method of the power module of Claim 1,
The step (b) is a method for manufacturing a power module, which is performed by integrally forming the insulating support member with the heat sink and the bus bar with a resin before the step (a). 請求項１〜３のいずれかに記載のパワーモジュールの製造方法において、
前記工程（ａ）では、前記樹脂接着剤を２層重ねて形成する、パワーモジュールの製造方法。 In the manufacturing method of the power module in any one of Claims 1-3,
In the step (a), a method for manufacturing a power module, wherein two layers of the resin adhesive are stacked. 請求項１〜４のいずれかに記載のパワーモジュールの製造方法において、
Ｐｂフリー半田により、前記配線部材上に半導体チップを固着する工程（ｃ）をさらに含むパワーモジュールの製造方法。 In the manufacturing method of the power module in any one of Claims 1-4,
A method for manufacturing a power module, further comprising a step (c) of fixing a semiconductor chip on the wiring member with Pb-free solder. ヒートシンクと、
半導体チップ用の配線部材と、
前記配線部材と前記ヒートシンクとの間に介在する絶縁樹脂層と、
バスバーおよび該バスバー支持用の絶縁支持部材と、
を備えている、パワーモジュール。 A heat sink,
A wiring member for a semiconductor chip;
An insulating resin layer interposed between the wiring member and the heat sink;
A bus bar and an insulating support member for supporting the bus bar;
Power module equipped with.
JP2007058031A 2007-03-08 2007-03-08 Power module and method of manufacturing the same Pending JP2008218940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007058031A JP2008218940A (en) 2007-03-08 2007-03-08 Power module and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007058031A JP2008218940A (en) 2007-03-08 2007-03-08 Power module and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2008218940A true JP2008218940A (en) 2008-09-18

Family

ID=39838574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007058031A Pending JP2008218940A (en) 2007-03-08 2007-03-08 Power module and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2008218940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017201545A1 (en) 2016-03-15 2017-09-21 Fuji Electric Co., Ltd. SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A SEMICONDUCTOR MODULE

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017201545A1 (en) 2016-03-15 2017-09-21 Fuji Electric Co., Ltd. SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A SEMICONDUCTOR MODULE
US10128167B2 (en) 2016-03-15 2018-11-13 Fuji Electric Co., Ltd. Semiconductor module and manufacturing method of semiconductor module

Similar Documents

Publication Publication Date Title
CN103035601B (en) Include the semiconductor devices of Diffusion Welding layer on sintering silver layer
JP2009021530A (en) Insulating resin film and power module
JP4438489B2 (en) Semiconductor device
US10510640B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2007305962A (en) Power semiconductor module
US9887338B2 (en) Light emitting diode device
JP2007251076A (en) Power semiconductor module
JP2008300476A (en) Power module
JP5957862B2 (en) Power module substrate
JP2009044156A (en) Circuit support structure having improved radiation property
JP4610414B2 (en) Electronic component storage package, electronic device, and electronic device mounting structure
JP2008300379A (en) Power module
JP2006100640A (en) Ceramic circuit board and power semiconductor module using same
JPWO2016079881A1 (en) Semiconductor power module, method for manufacturing the same, and moving body
US20050258550A1 (en) Circuit board and semiconductor device using the same
JP5141061B2 (en) Power module
US20230075200A1 (en) Power module and method for manufacturing same
JP2009019182A (en) Surface-coated filler, composite adhesive and power module
JP2007088030A (en) Semiconductor device
JP2008218814A (en) Power module
JP2008218940A (en) Power module and method of manufacturing the same
JP2004336046A (en) Application specific heat sink element
JP2003258150A (en) Insulated type semiconductor device
JP2005353867A (en) Semiconductor apparatus
JP2001007281A (en) Power semiconductor module

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091221