JP2008211188A - Semiconductor device and portable equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which enhances a radiation property of a semiconductor device having laminated semiconductor devices, and improves its reliability. <P>SOLUTION: The semiconductor device includes a wiring substrate 40, a first semiconductor device 10 mounted on the wiring substrate 40, a second semiconductor device 20 which is laminated on the first semiconductor device 10, and in which a projected portion 20b projects from an outer edge of the first semiconductor device 10, and a sealed resin layer 50 which seals each of the semiconductor devices. The second semiconductor device 20 includes a first analog cell 21a and a second analog cell 21b on its upper face, wherein the second analog cell is easy to generate heat at higher temperature than the first analog cell 21a, and the second analog cell 21b is arranged so that it may include the projected portion 20b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of semiconductor elements are stacked.

  In recent years, a multi-stage stack structure (multi-chip package structure) in which a plurality of semiconductor elements (for example, semiconductor chips) are mixed and stacked is known as a package technology that realizes miniaturization and high functionality of a semiconductor device used in an electronic device. (See Patent Document 1).

  FIG. 4 is a schematic cross-sectional view showing a stack structure semiconductor device described in Patent Document 1. In FIG. In this semiconductor device, a first semiconductor chip 1110 having a relatively large area is fixed on a wiring board (interposer) 1140 by a die bond material 1112 so that it does not interfere with the electrode pads 1113 of the first semiconductor chip 1110. In addition, the second semiconductor chip 1120 is fixed on the first semiconductor chip 1110 by the die bond material 1122.

  The electrode pad 1113 formed on the upper surface of the first semiconductor chip 1110 is electrically connected to the pad electrode 1143 formed on the wiring substrate 1140 by a bonding wire 1114 made of a gold wire or the like. The pad electrode 1123 on the upper surface of the second semiconductor chip 1120 is electrically connected to the pad electrode 1143 by a bonding wire 1124.

  The first semiconductor chip 1110 and the second semiconductor chip 1120 stacked on the wiring substrate 1140 are sealed with a sealing resin layer 1150. An external connection terminal 1145 electrically connected to the pad electrode 1143 is formed on the back surface (lower surface) of the semiconductor chip mounting surface of the wiring substrate 1140.

Since the semiconductor device of the stack structure can be used by being mounted on a printed wiring board or the like, compared to the case where a plurality of semiconductor elements (semiconductor chips) are arranged in a plane, the mounting area in the planar direction can be reduced. It can meet the demand for downsizing and high integration of electronic equipment.
JP-A-11-204720

  However, in such a semiconductor device adopting a stack structure for miniaturization and high integration, particularly when a semiconductor element having a circuit region (heat generating circuit region) with high power consumption is incorporated, If the heat dissipation to the outside is not sufficiently performed when the temperature of the circuit region rises rapidly, there is a concern that it may cause a malfunction or be destroyed.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a technique capable of improving the heat dissipation and improving the reliability of a semiconductor device having stacked semiconductor elements. .

  In order to solve the above-described problem, a semiconductor device according to the present invention includes a first semiconductor element, and a second layer that is stacked on the first semiconductor element and has a protruding portion that protrudes from the outer edge of the first semiconductor element. The second semiconductor element has a first circuit region on its upper surface and a second circuit region that easily generates heat at a temperature higher than that of the first circuit region. The circuit region is arranged so as to include a protruding portion.

  In the above structure, the first semiconductor element and the second semiconductor element are disposed on the substrate and are sealed by a resin layer formed on the substrate, and the resin layer is the second semiconductor element of the second semiconductor element. It is preferable that the distance between the end including the second circuit region and the corresponding side wall of the resin layer is shorter than the distance at the other end.

  In the above configuration, the amount of current flowing through the first wiring connecting the electrode part included in the first circuit region and the terminal provided in the substrate is provided in the electrode part and substrate included in the second circuit region. It is preferable that the amount of current is smaller than the amount of current flowing through the second wiring connecting the connected terminals.

  In the above configuration, the terminal of the substrate to which the second wiring is connected is provided in a region different from the region between the end including the second circuit region and the side wall surface of the resin layer corresponding thereto. It is preferable.

  In the above configuration, the resin layer is formed such that the interval between the end portion and the side wall surface of the resin layer corresponding thereto is shorter than the interval between the upper surface of the second semiconductor element and the upper surface of the resin layer. It is preferable.

  In the above structure, the second semiconductor element is preferably stacked on the first semiconductor element such that a plurality of sides of the second semiconductor element protrude from the outer edge of the first semiconductor element. More preferably, the second semiconductor element is stacked on the first semiconductor element such that the four sides of the second semiconductor element protrude from the outer edge of the first semiconductor element.

  In the above structure, the first semiconductor element preferably has a plurality of protruding electrode terminals connected to the substrate on a surface opposite to the side where the second semiconductor element is stacked.

  In the above structure, the second circuit region preferably includes an electrode portion, and the electrode portion is preferably disposed in a region where the first semiconductor element and the second semiconductor element overlap.

  In the above configuration, it is preferable that the second circuit region includes an electrode portion, and the electrode portion is disposed on the protruding portion.

  Another embodiment of the present invention is a portable device. This portable device may be mounted with any of the semiconductor devices described above.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which makes it possible to improve the heat dissipation of the semiconductor device which has the laminated semiconductor element and to improve the reliability is provided.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of a semiconductor device having stacked semiconductor elements according to the first embodiment, and FIG. 2 is a plan view (top view) of the semiconductor device.

  The semiconductor device according to the present embodiment is stacked on the wiring substrate 40, the first semiconductor element 10 mounted on the wiring substrate 40, and the first semiconductor element 10, and the protruding portion 20 b is the first semiconductor element 10. The 2nd semiconductor element 20 which protrudes from the outer edge of this, and the sealing resin layer 50 which seals each semiconductor element are provided. The second semiconductor element 20 has a first analog cell 21a and a second analog cell 21b that easily generates heat at a temperature higher than that of the first analog cell 21a on the upper surface thereof. The cell 21 b is disposed so as to include the protruding portion 20 b of the second semiconductor element 20. The first analog cell 21a and the second analog cell 21b are not limited to the upper surface of the second semiconductor element 20, and may be on the lower surface or the peripheral edge.

  The wiring board 40 is a base board having a multilayer wiring structure in which a plurality of wiring layers and insulating layers are alternately formed. A plurality of pad electrodes 43 made of copper (Cu), nickel (Ni), and gold (Au) are formed on the upper surface (semiconductor element mounting surface) of the wiring substrate 40, and the lower surface (semiconductor element mounting surface) of the wiring substrate 40. An external connection terminal (solder ball) 45 electrically connected to the pad electrode 43 through an internal wiring layer (not shown) is formed on the surface opposite to the surface.

  The first semiconductor element 10 is a semiconductor element in which a digital circuit (not shown) is formed on the upper surface (front surface) of a semiconductor substrate such as a P-type silicon substrate, for example, in a predetermined region on the wiring substrate 40. It is mounted via an adhesive layer 12 such as a die attach film. Here, the digital system circuit is a general term for circuits that use digital value signals as data, and examples of the digital system circuit include an arithmetic circuit, a CPU, a memory, an analog / digital converter (ADC) configured by various logic circuits ) Circuit, digital / analog converter (DAC) circuit, digital filter circuit, phase lock loop (PLL) circuit, and the like. In addition, the outer edge of the first semiconductor element 10 (the outer edge excluding the side on which the second semiconductor element 20 is mounted) is electrically connected to the digital circuit, and exchanges signals with the outside of the semiconductor element. A plurality of pad electrodes 13 are arranged for performing. The pad electrode 13 is electrically connected to the pad electrode 43 on the upper surface of the wiring board 40 by a bonding wire 14 such as gold.

  The second semiconductor element 20 is a semiconductor element in which an analog circuit including the first analog cell 21a and the second analog cell 21b is formed on the upper surface (front surface) of a semiconductor substrate such as a P-type silicon substrate. The first semiconductor element 10 is mounted on the first semiconductor element 10 with an adhesive layer 22 such as a die attach film in a state in which a part thereof protrudes from the outer edge of the first semiconductor element 10. That is, the second semiconductor element 20 after mounting has a region 20a that overlaps with the first semiconductor element 10 (a common region where both overlap when viewed from above) and a protruding portion 20b that protrudes from the outer edge of the first semiconductor element 10. Have Also, the second analog cell 21b of the analog circuit is a circuit region that is likely to generate heat at a higher temperature than the first analog cell 21a, and is a region that is hotter than the first analog cell 21a during circuit operation. is there. For this reason, the first analog cell 21 a and the second analog cell 21 b are arranged as shown in FIG. 2, and in particular, the second analog cell 21 b is arranged to include the protruding portion 20 b of the second semiconductor element 20. ing.

  In each cell, a plurality of pad electrodes 23a and a plurality of pad electrodes 23b for exchanging signals with the outside of the semiconductor element are arranged. Here, the pad electrode 23 a is disposed along the outer edge portion of the second semiconductor element 20, and the pad electrode 23 b is the first in the region 20 a where the first semiconductor element 10 and the second semiconductor element 20 overlap. Arranged along the outer edge of the semiconductor element 10. By doing so, since the first semiconductor element 10 supports the pressure by the bonding tool when wire bonding is performed to the pad electrode 23b of the second analog cell 21b, the pad electrode 23b is provided along the outer edge of the protruding portion 20b. Compared with the case where it is provided, damage to the end including the second analog cell 21b can be reduced.

  The pad electrode 23a and the pad electrode 23b in each cell are electrically connected to the pad electrode 43 on the upper surface of the wiring board 40 by a bonding wire 24a such as gold and a bonding wire 24b.

  The analog system circuit is a general term for circuits that use analog value signals as data. The analog system circuit includes, for example, a driver amplifier circuit (motor drive current generation output circuit), a transmission system high output amplifier circuit, and an output control logic. A circuit, an analog filter circuit, a pre-drive circuit (small signal amplification circuit), a protection circuit, and the like are included. Among them, a driver amplifier circuit and a transmission system high output amplifier circuit are cited as the second analog cell 21b.

  The sealing resin layer 50 is formed so as to cover the entire surface of the wiring substrate 40 and seals the first semiconductor element 10 and the second semiconductor element 20. The material of the sealing resin layer 50 is, for example, a thermosetting insulating resin such as an epoxy resin. The sealing resin layer 50 has a function of protecting each semiconductor element from the external environment. Here, as shown in FIG. 2, the sealing resin layer 50 includes an element end including the second analog cell 21 b of the second semiconductor element 20 and an outer wall surface of the corresponding sealing resin layer 50. The interval L1 is finished shorter than the intervals L2 to L4 at the other end portions of the element. In addition, a filler for increasing thermal conductivity may be added in the sealing resin layer 50.

  The first semiconductor element 10 is the “first semiconductor element” of the present invention, the first analog cell 21a is the “first circuit region” of the present invention, and the second analog cell 21b is the “first semiconductor element” of the present invention. 2 ”, the second semiconductor element 20 is the“ second semiconductor element ”of the present invention, the protrusion 20 b is the“ projection ”of the present invention, and the sealing resin layer 50 is the“ resin layer ”of the present invention. The pad electrode 23b is an example of the “electrode part” in the present invention.

  Hereinafter, the heat radiation effect of the protruding portion 20b in the second semiconductor element 20 that protrudes from the outer edge of the first semiconductor element 10 and is stacked will be described.

  In the semiconductor device having the conventional stack structure shown in FIG. 4, the heat generated from the second semiconductor element (second semiconductor chip 1120) during operation is generated by the first semiconductor element (first semiconductor) located on the lower layer side. Since the temperature difference between the two becomes small due to the influence of heat generated in the chip 1110) and it is difficult to dissipate to the lower layer side, a sealing resin layer (sealing resin layer 1150) provided on the upper surface side and the side surface of the second semiconductor element. It is dominant to be dissipated by heat conduction to). Further, depending on the amount of heat generated by the first semiconductor element, the second semiconductor element immediately above is heated by the heat, and heat dissipation from the second semiconductor element is not sufficient.

  On the other hand, in the semiconductor device of this embodiment, since the first semiconductor element 10 does not exist on the lower surface side of the protruding portion 20b of the second semiconductor element 20, heat generated from the second semiconductor element 20 during operation is It is dissipated by heat conduction to the sealing resin layer 50 provided on the upper surface side, side surface, and lower surface side. Furthermore, since the protrusion 20b is farther from the first semiconductor element 10 than the other overlapping region 20a, the influence of heat generated in the first semiconductor element 10 during operation is relatively small. For this reason, in the protrusion part 20b, the heat which generate | occur | produces from the 2nd semiconductor element 20 can be dissipated more efficiently.

(Production method)
FIG. 3 is a schematic cross-sectional view for explaining a manufacturing process of a semiconductor device having stacked semiconductor elements according to the first embodiment.

  First, as shown in FIG. 3A, it has a multilayer wiring structure (not shown) in which a plurality of wiring layers and insulating layers are alternately formed by a well-known technique, and the upper surface (semiconductor element mounting surface) is made of copper. A wiring substrate 40 having a plurality of pad electrodes 43 made of nickel, nickel, and gold is prepared. Then, a first semiconductor element 10 having a digital circuit (not shown) and a pad electrode 13 disposed on the outer periphery thereof on the upper surface of a semiconductor substrate such as a P-type silicon substrate is prepared using a well-known technique. The first semiconductor element 10 is mounted on a predetermined region on the wiring substrate 40 via an adhesive layer 12 such as a die attach film.

  As shown in FIG. 3B, the first analog cell 21a and the second analog cell (at a higher temperature than the first analog cell 21a) are formed on the upper surface of a semiconductor substrate such as a P-type silicon substrate by a known technique. A second semiconductor element 20 in which a pad circuit 23a and a pad electrode 23b disposed at a predetermined position in each cell are prepared. The semiconductor element 20 is mounted on the first semiconductor element 10 via an adhesive layer 22 such as a die attach film. At this time, the second semiconductor element 20 is laminated so that a part (the whole or part of the second analog cell 21 b) protrudes from the outer edge of the first semiconductor element 10. As a result, the second semiconductor element 20 is divided into a region 20a that overlaps the first semiconductor element 10 and a protrusion 20b that protrudes from the outer edge of the first semiconductor element 10, and the second semiconductor element 20 includes the protrusion 20b. Two analog cells 21b are arranged. Further, the pad electrode 23b of the second analog cell 21b is formed at a predetermined position (position along the outer edge portion of the first semiconductor element 10) in the region 20a where both overlap.

  As shown in FIG. 3C, an electrical connection is made between the pad electrode 13 of the first semiconductor element 10 and the pad electrode 43 provided on the upper surface of the wiring substrate 40 corresponding thereto by a bonding wire 14 such as gold. Connect. The pad electrode 23a of the first analog cell 21a and the pad electrode 23b of the second analog cell 21b in the second semiconductor element 20 and the pad electrode 43 provided on the upper surface of the wiring substrate 40 corresponding to these The gap is electrically connected by a bonding wire 24a such as gold and a bonding wire 24b. Here, since the first semiconductor element 10 exists in the lower layer of the pad electrode 23b of the second analog cell 21b, when the wire bonding is performed on the pad electrode 23b of the second analog cell 21b, the reduction force by the bonding tool is applied. Compared to the case where the first semiconductor element 10 is supported and the first semiconductor element 10 is not present in the lower layer (when the pad electrode 23b is provided along the outer edge of the protrusion 20b), the end including the second analog cell 21b is reached. Damage can be reduced.

  Then, in order to protect the first semiconductor element 10 and the second semiconductor element 20 provided on the wiring board 40, a sealing resin layer 50 is formed so as to cover the entire surface of the wiring board 40. For example, a thermosetting insulating resin such as an epoxy resin may be used for the sealing resin layer 50, and a filler for increasing thermal conductivity may be added to the sealing resin layer 50. At this time, the distance L1 between the element end including the second analog cell 21b of the second semiconductor element 20 and the outer wall surface of the sealing resin layer 50 corresponding thereto is the distance between the other three element ends. The positional relationship between the wiring board 40 and the second semiconductor element 20 is controlled so as to be finished shorter than L2 to L4.

  Finally, as shown in FIG. 1, the pad electrode 43 is formed on the lower surface (surface opposite to the semiconductor element mounting surface) of the wiring substrate 40 via an internal wiring layer (not shown) using a solder printing method. External connection terminals (solder balls) 45 that are electrically connected to each other are formed.

  Through these steps, the semiconductor device of this embodiment shown in FIG. 1 is manufactured.

  According to the semiconductor device of this embodiment, the following effects can be obtained.

  (1) The second analog cell 21b that is likely to generate heat at a higher temperature in the second semiconductor element 20 is disposed in a region including the protruding portion 20b that protrudes from the outer edge of the first semiconductor element 10. The heat generated from the second analog cell 21b is dissipated from the back surface side as well as from the top surface and side surfaces of the protrusion 20b. For this reason, compared with the case where it does not protrude from the outer edge of the first semiconductor element 10 (dissipation from the upper surface side and the side surface), the heat dissipation of the semiconductor device is increased, which can contribute to the stabilization of the operation. Therefore, the reliability of the semiconductor device can be improved.

  (2) The interval L1 between the end portion of the second semiconductor element 20 including the second analog cell 21b and the outer wall surface of the sealing resin layer 50 corresponding to the end portion is set to the interval L2 between the other end portions of the three sides. By making the length shorter than L4, the end including the second analog cell 21b is more easily cooled than the other end due to the influence of the external environment (external temperature of the semiconductor device). For this reason, the second analog cell 21b included in such an end portion is effectively cooled and can contribute to the stabilization of the operation of the semiconductor device. Therefore, the reliability of the semiconductor device can be improved.

  (3) Since the pad electrode 23b corresponding to the second analog cell 21b is disposed in the region 20a where the first semiconductor element 10 and the second semiconductor element 20 overlap each other, when wire bonding is performed to the pad electrode 23b. Since the first semiconductor element 10 supports the pressure by the bonding tool, damage to the end portion including the second analog cell 21b is reduced as compared with the case where the pad electrode 23b is provided on the protruding portion 20b. For this reason, when the temperature of the second analog cell 21b rises rapidly, it can be prevented from being thermally destroyed due to this damage. Therefore, the reliability of the semiconductor device can be improved.

(Second Embodiment)
FIG. 5 is a schematic cross-sectional view of a semiconductor device having stacked semiconductor elements according to the second embodiment, and FIG. 6 is a plan view (top view) of the semiconductor device. In the semiconductor device according to the second embodiment, the protrusion of the second semiconductor element is one side in the semiconductor device according to the first embodiment, whereas the protrusion of the second semiconductor element is four sides. The point is greatly different.

  The semiconductor device according to the present embodiment is stacked on the wiring substrate 140, the first semiconductor element 110 mounted on the wiring substrate, and the first semiconductor element 110, and the protrusion 120 b is the first semiconductor element 110. And a sealing resin layer 150 for sealing each semiconductor element. The second semiconductor element 120 protrudes from the outer edges of the four sides. The second semiconductor element 120 has a first analog cell 121a and a second analog cell 121b that easily generates heat at a temperature higher than that of the first analog cell 121a on the upper surface thereof. The cell 121b is disposed so as to include the protruding portion 120b of the second semiconductor element 120. Note that the first analog cell 121a and the second analog cell 121b are not limited to the upper surface of the second semiconductor element 120, but may be on the lower surface or the peripheral edge. Since the wiring board 140 is the same as the wiring board 40 according to the first embodiment, the description thereof is omitted.

  The first semiconductor element 110 is a semiconductor element in which a digital circuit (not shown) is formed on the upper surface (front surface) of a semiconductor substrate such as a P-type silicon substrate. The first semiconductor element 110 has a plurality of bumps (projection electrode terminals) 160 arranged in an array on the lower surface opposite to the upper surface side where the second semiconductor element 120 is laminated. The wiring board 140 is electrically connected through the bumps 160. By so-called flip chip mounting, the second semiconductor element 120 whose four sides are longer than the four sides of the first semiconductor element 110 is protruded from the outer edge of the first semiconductor element 110. Stacking on the first semiconductor element 110 is possible.

  The second semiconductor element 120 is, for example, a semiconductor element in which an analog circuit including the first analog cell 121a and the second analog cell 121b is formed on the upper surface (front surface) of a semiconductor substrate such as a P-type silicon substrate. The four sides are mounted on the first semiconductor element 110 via an adhesive layer 122 such as a die attach film in a state where the four sides protrude from the outer edge of the first semiconductor element 110. That is, the second semiconductor element 120 after mounting has a region 120a that overlaps with the first semiconductor element 110 (a common region where both overlap when viewed from above) and a protruding portion 120b that protrudes from the outer edge of the first semiconductor element 110. Have The second analog cell 121b of the analog circuit is a circuit region that easily generates heat at a temperature higher than that of the first analog cell 121a, and is a region that is hotter than the first analog cell 121a during circuit operation. is there. Therefore, the first analog cell 121a and the second analog cell 121b are arranged as shown in FIG. 6, and in particular, the second analog cell 121b is arranged so as to include the protruding portion 120b of the second semiconductor element 120. ing.

  In each cell, a plurality of pad electrodes 123a and a plurality of pad electrodes 123b for exchanging signals with the outside of the semiconductor element are arranged. Here, the pad electrode 123a is disposed along the outer edge portion of the region 120a where the second semiconductor element 120 and the first semiconductor element 110 overlap in the region where the first analog cell 121a is formed. The pad electrode 123b is disposed along the outer edge of the first semiconductor element 110 in the overlapping region 120a in the region where the second analog cell 121b is formed. By doing so, the first semiconductor element 110 supports the pressure applied by the bonding tool when wire bonding is performed to the pad electrode 123b of the second analog cell 121b. Therefore, the pad electrode 123b is provided along the outer edge of the protrusion 120b. Compared with the case of providing, damage to the end including the second analog cell 121b can be reduced.

  The pad electrode 123a and the pad electrode 123b in each cell are electrically connected to the pad electrode 143 on the upper surface of the wiring substrate 140 by a bonding wire 124a and a bonding wire 124b such as gold.

  The analog system circuit is a general term for circuits that use analog value signals as data. The analog system circuit includes, for example, a driver amplifier circuit (motor drive current generation output circuit), a transmission system high output amplifier circuit, and an output control logic. A circuit, an analog filter circuit, a pre-drive circuit (small signal amplification circuit), a protection circuit, and the like are included. Among them, a driver amplifier circuit and a transmission system high output amplifier circuit are cited as the second analog cell 121b.

  The sealing resin layer 150 is formed so as to cover the entire surface of the wiring substrate 140 and seals the first semiconductor element 110 and the second semiconductor element 120. The material of the sealing resin layer 150 is, for example, a thermosetting insulating resin such as an epoxy resin. The sealing resin layer 150 has a function of protecting each semiconductor element from the external environment. Here, as shown in FIG. 6, the sealing resin layer 150 includes an element end including the second analog cell 121b of the second semiconductor element 120 and a side wall (outer wall) of the sealing resin layer 150 corresponding thereto. The distance L1 to the surface is finished shorter than the distances L2 to L4 at the other end portions of the element. In addition, a filler for increasing the thermal conductivity may be added to the sealing resin layer 150.

  Note that the first semiconductor element 110 is the “first semiconductor element” of the present invention, the first analog cell 121 a is the “first circuit region” of the present invention, and the second analog cell 121 b is the “first semiconductor element” of the present invention. 2 ”, the second semiconductor element 120 is the“ second semiconductor element ”of the present invention, the protrusion 120b is the“ protrusion ”of the present invention, the sealing resin layer 150 is the“ resin layer ”of the present invention, The pad electrode 123b is an example of the “electrode part” in the present invention.

  Hereinafter, a heat dissipation effect of the protruding portion 120b in the second semiconductor element 120 that is stacked by protruding from the outer edge of the first semiconductor element 110 will be described.

  In the semiconductor device of the present embodiment, not only the protruding portion on one side of the second semiconductor element as in the semiconductor device of the first embodiment, but also the lower surface of the protruding portion 120b on the four sides of the second semiconductor element 120. Since the first semiconductor element 110 does not exist on the side, heat generated from the second semiconductor element 120 during operation is dissipated by heat conduction to the sealing resin layer 150 provided on the upper surface side, the side surface, and the lower surface side. Is done. Furthermore, since the protrusion 120b is farther from the first semiconductor element 110 than the other overlapping region 120a, the influence of heat generated in the first semiconductor element 110 during operation is relatively small. For this reason, in the protrusion part 120b, the heat generated from the second semiconductor element 120 can be more efficiently dissipated.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view of a semiconductor device having stacked semiconductor elements according to the third embodiment, and FIG. 8 is a plan view (top view) of the semiconductor device. In the semiconductor device according to the third embodiment, in the semiconductor device according to the second embodiment, the pad electrode is disposed in a region where the second semiconductor element and the first semiconductor element overlap, The difference is that the pad electrode is disposed on the protruding portion of the second semiconductor element. Since the other points are the same as those in the second embodiment, description thereof will be omitted as appropriate.

  In the semiconductor device according to the present embodiment, a plurality of pad electrodes 123c and a plurality of pad electrodes 123d are provided in each of the first analog cell 121a and the second analog cell 121b to exchange signals with the outside of the semiconductor element. . Here, the pad electrode 123c is disposed along the outer edge of the protruding portion 120b in the region where the first analog cell 121a is formed, and the pad electrode 123d is formed with the second analog cell 121b. In the region, the outer edge of the protruding portion 120b is arranged. In this way, the heat generated from the pad electrode 123d that tends to be a heat generating portion in the second analog cell 121b that is likely to generate heat at a high temperature is dissipated from the upper surface side and the side surface of the protruding portion 120b, and the back surface thereof. It will be dissipated from the side. For this reason, compared with the case where the pad electrode 123d is not disposed on the protruding portion 120b (dissipation from the upper surface side and the side surface), the heat dissipation of the semiconductor device is increased, which can contribute to the stabilization of the operation. Therefore, the reliability of the semiconductor device can be improved.

(Fourth embodiment)
FIG. 9 is a schematic cross-sectional view of a semiconductor device having stacked semiconductor elements according to the fourth embodiment, and FIG. 10 is a plan view (top view) of the semiconductor device. The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the second embodiment in that the pad electrode of the substrate connected to the pad electrode of the second analog cell via the bonding wire is second. The difference is that it is provided in a region different from the region between the analog cell and the corresponding side wall surface of the sealing resin layer. Since the other points are almost the same as those of the second embodiment, description thereof will be omitted as appropriate.

  In the semiconductor device according to the present embodiment, a plurality of pad electrodes 123a and a plurality of pad electrodes 123b are provided in each of the first analog cell 121a and the second analog cell 121b to exchange signals with the outside of the semiconductor element. . Here, the pad electrode 123a is disposed along the outer edge portion of the region 120a where the second semiconductor element 120 and the first semiconductor element 110 overlap in the region where the first analog cell 121a is formed. The pad electrode 123b is disposed along the outer edge of the first semiconductor element 110 in the overlapping region 120a in the region where the second analog cell 121b is formed. By doing so, the first semiconductor element 110 supports the pressure applied by the bonding tool when wire bonding is performed to the pad electrode 123b of the second analog cell 121b. Therefore, the pad electrode 123b is provided along the outer edge of the protrusion 120b. Compared with the case of providing, damage to the end including the second analog cell 121b can be reduced.

  In the semiconductor device according to the present embodiment, the pad electrode 123a of the first analog cell 121a is electrically connected to the pad electrode 143a on the upper surface of the wiring board 140 through the bonding wire 124a, and the second electrode The pad electrode 123b of the analog cell 121b is electrically connected to the pad electrode 143b on the upper surface of the wiring board 140 through the bonding wire 124b. Here, the pad electrode 143b of the wiring board 140 to which the bonding wire 124b is connected is a region R between the protruding portion 120b including the second analog cell 121b and the side wall surface 150a of the sealing resin layer 150 corresponding thereto. It is provided in a different area. By doing in this way, compared with the case where the pad electrode 143b is arrange | positioned in the area | region between the 2nd analog cell 121b and the side wall surface 150a of the sealing resin layer 150, the 2nd analog cell 121b is made more. Since it can approach the side wall surface 150a, the heat generated from the second analog cell 21b can be more efficiently dissipated from the side wall surface 150a.

  Further, in the semiconductor device according to the present embodiment, the distance L1 between the protrusion 120b including the second analog cell 121b and the side wall surface 150a of the sealing resin layer 150 corresponding to the protrusion 120b is the upper surface of the second semiconductor element 120. It is configured to be shorter than the distance H between 120 c and the upper surface 150 b of the sealing resin layer 150. By doing so, the distance L1 between the second analog cell 121b and the side wall surface 150a of the sealing resin layer 150 is such that the upper surface 120c of the second semiconductor element 120 and the upper surface 150b of the sealing resin layer 150 are the same. Compared to the case where the distance H is longer than the distance H, the heat generated from the second analog cell 21b can be more efficiently dissipated from the side wall surface 150a.

(Fifth embodiment)
Next, a portable device including the above-described semiconductor device will be described. In addition, although the example mounted in a mobile telephone is shown as a portable apparatus, electronic devices, such as a personal digital assistant (PDA), a digital video camera (DVC), and a digital still camera (DSC), may be sufficient, for example.

  FIG. 11 is a diagram illustrating a configuration of a mobile phone including the semiconductor device according to the present embodiment. The mobile phone 211 has a structure in which a first housing 212 and a second housing 214 are connected by a movable portion 220. The first housing 212 and the second housing 214 are rotatable about the movable portion 220 as an axis. The first housing 212 is provided with a display portion 218 and a speaker portion 224 that display information such as characters and images. The second housing 214 is provided with an operation unit 222 such as operation buttons and a microphone unit 226. The semiconductor device according to each of the above-described embodiments is mounted inside such a mobile phone 211.

  12 is a partial cross-sectional view of the mobile phone shown in FIG. 11 (cross-sectional view of the first housing 212). The semiconductor device 200 according to the present embodiment is mounted on a printed circuit board 228 via solder bumps 142 and is electrically connected to the display unit 218 and the like via such printed circuit board 228. Further, a heat radiating substrate 216 such as a metal substrate is provided on the back surface side (the surface opposite to the solder bump 142) of the semiconductor device 200. For example, heat generated from the semiconductor device is stored inside the first housing 212. It is possible to efficiently dissipate heat to the outside of the first housing 212 without making it.

  According to the portable device provided with the semiconductor device 200 according to the present embodiment, not only the operation inside the semiconductor device is stabilized, but also the noise emitted from the semiconductor device to the outside can be reduced, and the device is mounted inside the portable device. Since the influence of noise on other components can be reduced, the reliability of a portable device equipped with such a semiconductor device 200 is improved.

  The present invention is not limited to the above-described embodiment, and various modifications such as design changes can be added based on the knowledge of those skilled in the art, and the embodiment to which such a modification is added. Can also be included in the scope of the present invention.

  In the above embodiment, an example of a semiconductor device in which a sealing resin layer that seals each semiconductor element is formed is shown. However, the present invention is not limited to this, and for example, a sealing resin layer is not necessarily provided. It may be a semiconductor device not provided with a stop resin layer. In this case, the lower surface side of the protrusion is directly exposed to the atmosphere, and the generated heat can be dissipated more effectively.

  In the above embodiment, an example is shown in which the present invention is applied to a semiconductor device in which two semiconductor elements are stacked. However, the present invention is not limited to this, and may be applied to, for example, a semiconductor device in which three or more semiconductor elements are stacked. . Further, the present invention may be applied to a semiconductor device in which a plurality of semiconductor elements are arranged on one semiconductor element. Also in this case, the above effects can be enjoyed between the semiconductor elements.

  In the above-described embodiment, an example in which a semiconductor element in which an analog circuit is formed as the second semiconductor element is used has been described. However, the present invention is not limited thereto, and for example, an analog circuit and a digital circuit are formed. Alternatively, a semiconductor element (analog / digital mixed semiconductor element) may be employed. Also in this case, the above-mentioned effect can be enjoyed by arranging a circuit that easily generates heat at a high temperature in the protruding portion.

  In the above-described embodiment, an example in which a semiconductor element in which a digital circuit is formed as the first semiconductor element is employed has been described. However, the present invention is not limited thereto, and for example, a digital circuit and an analog circuit are formed. Alternatively, a semiconductor element (analog / digital mixed semiconductor element) may be employed. In this case, it is preferable that an analog circuit is selectively provided in a region where the second semiconductor element is not mounted. In general, it is known that the performance characteristics of transistors constituting an analog circuit or a digital circuit fluctuate due to the influence of stress. Especially in analog circuits that are more sensitive to such fluctuations than digital circuits, if stress is applied to some of the transistors that make up the circuits, the performance of the transistors will vary depending on the degree of the stress. May not perform a predetermined operation. For this reason, by selectively providing an analog circuit in a region where the second semiconductor element is not mounted, stress is applied to the analog circuit unevenly due to the outer edge portion of the second semiconductor element. It is possible to prevent the variation in circuit characteristics in the analog circuit. Therefore, the reliability of a semiconductor device having stacked semiconductor elements can be improved.

  Further, in the step of mounting the second semiconductor element on the first semiconductor element, the analog semiconductor circuit is selectively provided in a region where the second semiconductor element is not mounted, so that the second semiconductor element is mounted. A load (pressure) load on the first semiconductor element generated at this time is not applied to the analog system circuit, and the characteristic variation of the analog system circuit (physical damage to the transistor) is prevented. Thereby, the manufacturing yield of a semiconductor device having stacked semiconductor elements can be improved, and the cost of the semiconductor device can be reduced.

  Note that, in each of the semiconductor devices described above, the second analog cell has a second current cell based on the amount of current flowing through a bonding wire that connects the pad electrode included in the first analog cell and the pad electrode provided on the substrate. It is preferable to select one having a large amount of current flowing through a bonding wire that connects the pad electrode included in the analog cell and the pad electrode provided on the substrate. In general, if the amount of current is large, the amount of heat generated in the cell is expected to be high, so that each analog cell can be arranged at an appropriate position in the second semiconductor element according to the amount of current. it can. Here, the magnitude of the amount of current flowing through the bonding wire may be determined, for example, by comparing average currents per predetermined time. Alternatively, when each analog cell and the substrate are connected by a plurality of wires, the determination may be made by comparing the averages of the currents flowing through all the wires. The second analog cell 21b is exemplified as an output circuit having a large average output current value.

It is a schematic sectional drawing of the semiconductor device which has the laminated | stacked semiconductor element which concerns on this embodiment. It is a top view of the semiconductor device concerning this embodiment. (A)-(C) It is a schematic sectional drawing for demonstrating the manufacturing process of the semiconductor device which has the laminated | stacked semiconductor element which concerns on this embodiment. It is a schematic sectional drawing which shows the semiconductor device of the conventional stack structure. It is a schematic sectional drawing of the semiconductor device which has the laminated | stacked semiconductor element which concerns on 2nd Embodiment. It is a top view of the semiconductor device concerning a 2nd embodiment. It is a schematic sectional drawing of the semiconductor device which has the laminated | stacked semiconductor element which concerns on 3rd Embodiment. It is a top view of the semiconductor device concerning a 3rd embodiment. It is a schematic sectional drawing of the semiconductor device which has the laminated | stacked semiconductor element which concerns on 4th Embodiment. It is a top view of the semiconductor device concerning a 4th embodiment. It is a figure which shows the structure of the mobile telephone which concerns on 5th Embodiment. It is a fragmentary sectional view of the mobile phone shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor element, 12 ... Adhesion layer, 13 ... Pad electrode, 14 ... Bonding wire, 20 ... 2nd semiconductor element, 20a ... 1st semiconductor element 20b... Projection, 21a... First analog cell, 21b... Second analog cell, 22... Adhesive layer, 23a, 23b. .. Pad electrodes, 24a, 24b ... bonding wires, 40 ... wiring substrates, 43 ... pad electrodes, 45 ... external connection terminals (solder balls), 50 ... sealing resin layers.

Claims (11)

A first semiconductor element;
A second semiconductor element stacked on the first semiconductor element and having a protruding portion protruding from an outer edge of the first semiconductor element;
With
The second semiconductor element has a first circuit region and a second circuit region that easily generates heat at a temperature higher than that of the first circuit region, and the second circuit region includes the protruding portion. A semiconductor device characterized in that the semiconductor device is disposed. The first semiconductor element and the second semiconductor element are disposed on a substrate and sealed with a resin layer formed on the substrate,
The resin layer has an interval between the end portion including the second circuit region of the second semiconductor element and a side wall surface of the resin layer corresponding to the end portion shorter than an interval at the other end portion. The semiconductor device according to claim 1, wherein the semiconductor device is formed.   The amount of current flowing through the first wiring connecting the electrode portion included in the first circuit region and the terminal provided on the substrate is provided on the electrode portion and substrate included in the second circuit region. 3. The semiconductor device according to claim 2, wherein the amount of current is smaller than an amount of current flowing through the second wiring connecting to the terminal.   The terminal of the board to which the second wiring is connected is provided in a region different from the region between the end including the second circuit region and the corresponding side wall surface of the resin layer. The semiconductor device according to claim 3.   The resin layer is formed such that an interval between the end portion and a side wall surface of the resin layer corresponding to the end portion is shorter than an interval between the upper surface of the second semiconductor element and the upper surface of the resin layer. The semiconductor device according to claim 2, wherein the semiconductor device is provided.   The second semiconductor element is stacked on the first semiconductor element such that a plurality of sides of the second semiconductor element protrude from an outer edge of the first semiconductor element. The semiconductor device according to any one of 1 to 5.   2. The second semiconductor element is stacked on the first semiconductor element such that four sides of the second semiconductor element protrude from an outer edge of the first semiconductor element. The semiconductor device according to any one of 1 to 5.   The plurality of protruding electrode terminals connected to the substrate are formed on a surface of the first semiconductor element opposite to a side where the second semiconductor element is stacked. 8. A semiconductor device according to any one of 1 to 7. The second circuit region includes an electrode portion;
The semiconductor device according to claim 1, wherein the electrode portion is disposed in a region where the first semiconductor element and the second semiconductor element overlap each other. The second circuit region includes an electrode portion;
The semiconductor device according to claim 1, wherein the electrode portion is disposed on the protruding portion.   A portable device comprising the semiconductor device according to any one of claims 1 to 10.

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