JP2008177241A - Semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated semiconductor package with a means capable of effectively cooling only the intensive heat generating portion of any one of semiconductor chips making up the semiconductor package. <P>SOLUTION: The semiconductor package 10 is made by laminating a plurality of semiconductor chips 11, 12, and 13. On at least the semiconductor chip 12 out of the semiconductor chips, the heat generating portion 12A heated at a relatively high temperature is exposed locally, and is brought into contact with a heat sink member 17 to directly cool the heat generating portion 12A. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor package that can suppress, for example, high temperature in a circuit portion that requires high performance operation.

  In recent years, in order to realize a device such as a high-performance three-dimensional IC, a method (mounting method) in which at least one semiconductor chip is stacked on a wiring board to form a semiconductor device has been actively tried. At this time, in order to further reduce the size of the semiconductor device to be obtained, pads are formed in the peripheral portion of the semiconductor chip and the peripheral portion of the wiring board, and the pads are electrically connected by wires. A so-called wire bonding or a hole is formed directly in the semiconductor chip, and a conductive member is embedded in the hole, and the wiring board is electrically and mechanically joined through the conductive member. Flip chip-like bonding technology is being used.

  In the stacked semiconductor package as described above, for example, in a semiconductor chip in which a circuit requiring particularly high performance operation is incorporated, a region including the circuit part is heated due to heat generation in the circuit part. Thermal runaway and characteristic deterioration due to an increase in operating temperature become problems. Therefore, the development of a technique for cooling the heat generation portion of any semiconductor chip in the above-described stacked semiconductor package is regarded as important.

  Japanese Patent Application Laid-Open No. 11-74454 discloses that a module (package) having a sandwich structure composed of a ceramic substrate, a plurality of power semiconductor chips, and a molybdenum wafer is brought into contact with a heat diffusion plate. However, with such a method, the entire semiconductor chip, or the entire module (package), is cooled, and it is not possible to cool only a specific heat generation location in the semiconductor chip.

  Therefore, if the above-described heat generation point in the semiconductor chip is cooled to a predetermined temperature to suppress thermal runaway and characteristic deterioration due to an increase in operating temperature, the semiconductor chip and the entire package must be cooled more than necessary. In addition, the cooling efficiency is extremely deteriorated, and the accompanying heat generation due to overwork of the apparatus itself used for cooling becomes a problem.

  In particular, in a semiconductor chip stacked body in which a plurality of semiconductor chips are stacked, in a semiconductor chip located in the middle between the upper and lower semiconductor chips, the heat dissipation path is a path passing through the upper and lower semiconductor chips. In other words, the thermal resistance of the semiconductor chip becomes high, the semiconductor chip located in the middle cannot be sufficiently cooled, and the temperature of the upper and lower semiconductor chips also rises.

From such a point of view, there is a need for development of a technique capable of efficiently cooling only the heat generating portion of the semiconductor chip individually, particularly in a stacked semiconductor package.
JP-A-11-74454

  An object of the present invention is to make it possible to efficiently cool only a heat generation portion of an arbitrary semiconductor chip constituting a semiconductor package in a stacked semiconductor package.

In order to solve the above problems, one embodiment of the present invention provides:
A semiconductor package in which a plurality of semiconductor chips are stacked,
The present invention relates to a semiconductor package characterized in that in at least one of the semiconductor chips, a heat generating portion heated to a relatively high temperature is locally exposed and the heat generating portion is directly cooled.

  According to the above aspect, in the stacked semiconductor package, only the heat generating portion of an arbitrary semiconductor chip constituting the semiconductor package can be efficiently cooled.

  Hereinafter, specific embodiments of the present invention will be described.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor package in the first embodiment. In the semiconductor package 10 shown in FIG. 1, on the base substrate 14, the first semiconductor chip 11, the second semiconductor chip 12, the third semiconductor chip 13-1, and the fourth semiconductor chip 13-2 are sequentially formed. Are stacked. The base substrate 14 and the first semiconductor chip 11 and between the semiconductor chips are bonded and fixed to each other with a heat conductive paste 16. Note that solder or the like can be used instead of the heat conductive paste.

  Further, between the first semiconductor chip 11 and the second semiconductor chip 12 and the base substrate 14, and between the first semiconductor chip 11, the third semiconductor chip 13-1, and the fourth semiconductor chip 13-2. The gaps are electrically connected to each other by a wire 15 via a bonding pad (not shown). The base substrate 14 can be a lead frame, for example.

  In the semiconductor package 10 shown in FIG. 1, a large amount of heat is generated locally at the center of the second semiconductor chip 12 due to, for example, the logic circuit configuration during driving. Therefore, in the configuration shown in FIG. 1, the third and fourth semiconductor chips 13-1 and 13-2 are arranged so as to expose the region 12 </ b> A including the high heat generation portion of the second semiconductor chip 12. Next, the T-shaped heat sink member 17 is arranged so that the tip end portion thereof is in contact with the region 12A.

  As described above, in the configuration shown in FIG. 1, the second semiconductor chip 12 having the local high heat generation region 12A is exposed to the heat sink member 17 and cooled by exposing the high heat generation region 12A to the outside. I am doing so. Accordingly, only the high heat generation region 12A in the second semiconductor chip 12 can be locally and selectively cooled.

  As a result, thermal runaway and characteristic deterioration due to an increase in the operating temperature of the second semiconductor chip 12, and further thermal runaway and characteristic deterioration of the entire semiconductor package 10 can be suppressed. In addition, since only the heat generating area 12A in the second semiconductor chip 12 can be selectively cooled, the entire second semiconductor chip 12, and further the entire semiconductor package 10 accompanying the cooling of the heat generating area 12A. Therefore, the cooling efficiency of the second semiconductor chip 12 and further the semiconductor package 10 can be increased.

  The heat sink member 17 can be made of a member having excellent thermal conductivity, such as copper or aluminum. Furthermore, although the heat sink member 17 can be used alone, at least a part of the heat sink member 17 is brought into contact with the coolant, whereby the heat generating region 12A in the second semiconductor chip 12 can be cooled more efficiently.

  Further, in the case where the heat generating region is formed in the third semiconductor chip 13-1, the heat generating region is exposed as it is, so that a heat sink member is brought into contact with the heat generating region. It can be cooled directly.

  In this example, the high heat generation region 12A is formed in the central portion of the second semiconductor chip 12, but the formation region of the heat generation region varies depending on the configuration of the incorporated logic circuit or the like. Note that the location of the semiconductor chip (the third and fourth semiconductor chips 13-1 and 13-2 in this example) located thereabove can be appropriately changed depending on the location of the locally generated high heat generation region.

(Second Embodiment)
FIG. 2 is a cross-sectional view schematically showing the configuration of the semiconductor package in the second embodiment. Note that the same reference numerals are used for the same or similar components as those shown in FIG.

  In the semiconductor package 20 shown in FIG. 2, the first semiconductor chip 11, the second semiconductor chip 12, and the third semiconductor chip 13-1 are sequentially stacked on the base substrate 14. The base substrate 14 and the first semiconductor chip 11 and between the semiconductor chips are bonded and fixed to each other with solder balls 25, whereby the semiconductor package 20 has a so-called ball grid array (BGA) or flip chip-like structure. Presents. Therefore, the base substrate 14 has a function as a so-called mother board. The semiconductor chips and the semiconductor chips and the base substrate are electrically connected by solder balls 25, and wirings on the semiconductor chips and through via holes in the chips are appropriately formed as necessary.

  In the semiconductor package 20 shown in FIG. 2, at the time of driving the left end portion of the second semiconductor chip 12 and the right end portion and the center portion of the first semiconductor chip 11, for example, due to the logic circuit configuration or the like. It generates a lot of heat locally.

  Therefore, in the configuration shown in FIG. 2, the size of the third semiconductor chip 13-1 is about half the size of the second semiconductor chip 12 and arranged on the right end side, and the size of the second semiconductor chip 12 is One semiconductor chip 11 is arranged in the center as approximately half of the semiconductor chip 11. Therefore, the back surface of the high heat generation region 12A including the high heat generation location located at the left end of the second semiconductor chip 12 can be exposed, and the high heat generation location positioned at the right end of the first semiconductor chip 11 is included. The back surface of the high heat generation region 11B can be exposed.

  Further, in the configuration shown in FIG. 2, a hole perpendicular to the paper surface is formed in the base substrate 14 to expose the high heat generation region 11 </ b> A including the high heat generation portion located in the center of the first semiconductor chip 11. .

  Next, the tip portion of the clog-tooth shaped heat sink member 17-1 is in contact with the high heat generation region 12A and the high heat generation region 11B from the back side of the first semiconductor chip 11 and the second semiconductor chip 12. Deploy. Further, the T-shaped heat sink member 17-2 is arranged so that the tip portion thereof comes into contact with the high heat generation region 11 </ b> A from the surface side of the first semiconductor chip 11. Therefore, only the high heat generation regions 11A and 11B in the first semiconductor chip 11 and the high heat generation region 12A in the second semiconductor chip 12 can be locally and selectively cooled.

  As a result, it is possible to suppress thermal runaway and characteristic degradation due to an increase in the operating temperature of the first semiconductor chip 11 and the second semiconductor chip 12, and further thermal runaway and characteristic degradation of the entire semiconductor package 20. In addition, since only the high heat generation regions 11A and 11B in the first semiconductor chip 11 and the high heat generation region 12A in the second semiconductor chip 12 can be selectively cooled, these high heat generation regions are associated with cooling. It is not necessary to cool the entire first semiconductor chip 11 and the second semiconductor chip 12 and further the entire semiconductor package 20, and the first semiconductor chip 11 and the second semiconductor chip 12, and further the semiconductor package 20 Cooling efficiency can be increased.

  The heat sink members 17-1 and 17-2 can be made of a member having excellent thermal conductivity, such as copper or aluminum. Furthermore, the heat sink members 17-1 and 17-2 can be used alone, but by bringing at least a part of the heat sink members 17-1 and 17-2 into contact with the coolant, the high heat generation regions 11A and 11B in the first semiconductor chip 11 and the second Cooling of the high heat generation region 12A in the semiconductor chip 12 can be performed more efficiently.

  Also in this example, when the heat generating region is formed in the third semiconductor chip 13-1, the back surface of the high heat generating region is exposed as it is. It can cool by making a heat sink member contact.

  Further, in this example, the heat generating regions 11A and 11B are formed at the central portion and the right end portion of the first semiconductor chip 11, and the heat generating region 12A is formed at the left end portion of the second semiconductor chip 12. The location where the heat generating area is formed differs depending on the configuration of the incorporated logic circuit or the like. In addition, the arrangement | positioning location of the semiconductor chip (in this example, semiconductor chips 12 and 13-1) located in the upper part can be suitably changed with the place of the high heat_generation | fever area | region which arises locally.

(Third embodiment)
FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor package in the third embodiment. The semiconductor package 30 shown in FIG. 3 is basically the same in structure as the semiconductor package 10 shown in FIG. 1, but the means for cooling the high heat generation region is different from each other.

  That is, also in the semiconductor package 30 shown in FIG. 3, a high heat generation portion is formed at the center of the second semiconductor chip 12, and the high heat generation portion 12A including this heat generation portion is exposed, so that the third semiconductor chip 13 is exposed. -1 and the fourth semiconductor chip 13-2 are arranged. However, in this example, instead of the T-shaped heat sink member 17 as shown in FIG. 1, a refrigerant device 37 is provided above the high heat generation region 12 </ b> A of the second semiconductor chip 12. The refrigerant is sprayed toward the high heat generation region 12A.

  As described above, also in the configuration shown in FIG. 3, the second semiconductor chip 12 having the local high heat generation region 12 </ b> A exposes the high heat generation region 12 </ b> A to the outside and blows the refrigerant from the refrigerant device 37 to cool it. Like to do. Therefore, only the heat generating region 12A in the second semiconductor chip 12 can be locally and selectively cooled.

  As a result, thermal runaway and characteristic deterioration due to an increase in the operating temperature of the second semiconductor chip 12, and further thermal runaway and characteristic deterioration of the entire semiconductor package 10 can be suppressed. In addition, since only the high heat generation region 12A in the second semiconductor chip 12 can be selectively cooled, the entire second semiconductor chip 12 and further the semiconductor package 10 are accompanied by the cooling of the high heat generation region 12A. Therefore, the cooling efficiency of the second semiconductor chip 12 and further the semiconductor package 10 can be increased.

  As the refrigerant, non-reactive gas such as air, nitrogen gas, carbon dioxide gas or rare gas can be used. In addition, liquid refrigerants such as water, alcohol, and a mixture of water and alcohol can be used as long as the characteristics of the semiconductor chip are not affected. In the case of liquids, by using the inkjet method and fine nozzles to reduce the size of the droplets and supplying them to the cooling location, cooling can be performed more efficiently by using the latent heat of vaporization of the liquid at high heat generation locations. I can do it. Further, in some cases, it may be evaporated at a low temperature by lowering the atmospheric pressure.

  Further, in the case where the heat generation regions are formed in the third and fourth semiconductor chips 13-1 and 13-2, the high heat generation region is exposed as it is, so the high heat generation is performed. It can be cooled directly by spraying the area with coolant.

  Also in this example, the high heat generation region 12A is formed in the central portion of the second semiconductor chip 12, but the formation location of the high heat generation region differs depending on the configuration of the incorporated logic circuit or the like. Note that the location of the semiconductor chip (the third and fourth semiconductor chips 13-1 and 13-2 in this example) located thereabove can be appropriately changed depending on the location of the locally generated high heat generation region.

  3 are the same as those of the semiconductor package 10 shown in FIG. 1 except for the cooling structure of the semiconductor package 30 shown in FIG.

(Fourth embodiment)
FIG. 4 is a cross-sectional view schematically showing the configuration of the semiconductor package in the fourth embodiment. The semiconductor package 40 shown in FIG. 4 is basically the same in structure as the semiconductor package 20 shown in FIG. 2, but the means for cooling the heat generating region is different from each other.

  That is, also in the semiconductor package 40 shown in FIG. 4, the size of the third semiconductor chip 13-1 is arranged on the right end side as about half the size of the second semiconductor chip 12, and the size of the second semiconductor chip 12. Is disposed in the center of the first semiconductor chip 11 as a substantially half of the first semiconductor chip 11, and the back surface of the high heat generation region 12A including the high heat generation portion located at the left end of the second semiconductor chip 12 and the first semiconductor chip. 11, the back surface of the high heat generation region 11B including the high heat generation portion located at the right end is exposed. Further, a hole perpendicular to the paper surface is formed in the base substrate 14 to expose the high heat generation region 11A including the high heat generation portion located in the center of the first semiconductor chip 11.

  However, in this example, instead of the heat sink members 17-1 and 17-2 as shown in FIG. 2, a refrigerant device 37-1 is provided above the high heat generation region 12A of the second semiconductor chip 12, and this The refrigerant is blown from the refrigerant device 37-1 toward the back surface of the high heat generation region 12A. In addition, a refrigerant device 37-2 is provided above the high heat generation region 11B of the first semiconductor chip 11, and the refrigerant is sprayed from the refrigerant device 37-2 toward the back surface of the high heat generation region 11B. Further, a refrigerant device 37-3 is provided below the high heat generation region 11A of the first semiconductor chip 11, and the refrigerant is sprayed from the refrigerant device 37-3 toward the high heat generation region 11A.

  Therefore, only the high heat generation regions 11A and 11B in the first semiconductor chip 11 and the high heat generation region 12A in the second semiconductor chip 12 can be locally and selectively cooled.

  As a result, thermal runaway and characteristic deterioration due to an increase in operating temperature of the first semiconductor chip 11 and the second semiconductor chip 12, and further thermal runaway and characteristic deterioration of the entire semiconductor package 40 can be suppressed. In addition, since only the high heat generation regions 11A and 11B in the first semiconductor chip 11 and the high heat generation region 12A in the second semiconductor chip 12 can be selectively cooled, these high heat generation regions are associated with cooling. It is not necessary to cool the entire first semiconductor chip 11 and the second semiconductor chip 12, and further the entire semiconductor package 40, and the first semiconductor chip 11 and the second semiconductor chip 12, and further the semiconductor package 40 Cooling efficiency can be increased.

  As the refrigerant, non-reactive gas such as air, nitrogen gas, carbon dioxide gas or rare gas can be used. In addition, liquid refrigerants such as water, alcohol, and a mixture of water and alcohol can be used as long as the characteristics of the semiconductor chip are not affected. In the case of liquids, by using the inkjet method and fine nozzles to reduce the size of the droplets and supplying them to the cooling location, cooling can be performed more efficiently by using the latent heat of vaporization of the liquid at high heat generation locations. I can do it. Further, in some cases, it may be evaporated at a low temperature by lowering the atmospheric pressure.

  Further, in the case where the high heat generation region is formed in the third semiconductor chip 13-1, since the back surface of the high heat generation region is exposed as it is, the refrigerant is supplied to the high heat generation region. It can cool directly by spraying.

  Further, in this example, the high heat generation regions 11A and 11B are formed at the central portion and the right end portion of the first semiconductor chip 11, and the high heat generation region 12A is formed at the left end portion of the second semiconductor chip 12. However, the location where the heat generating area is formed differs depending on the configuration of the incorporated logic circuit or the like. In addition, the arrangement | positioning location of the semiconductor chip (in this example, semiconductor chips 12 and 13-1) located in the upper part can be suitably changed with the place of the high heat_generation | fever area | region which arises locally.

  4 are the same as those of the semiconductor package 20 shown in FIG. 2 except for the cooling structure of the semiconductor package 40 shown in FIG.

(Fifth embodiment)
FIG. 5 is a cross-sectional view schematically showing the configuration of the semiconductor package in the fifth embodiment. The same reference numerals are used for the same or similar components as those of the semiconductor package shown in FIGS.

  In the semiconductor package 50 shown in FIG. 5, the first semiconductor chip 11, the second semiconductor chip 12, and the third semiconductor chip 13-1 are sequentially stacked on the base substrate 14. The base substrate 14 and the first semiconductor chip 11 and between the semiconductor chips are bonded and fixed by solder balls 25, whereby the semiconductor package 20 has a so-called ball grid array (BGA) or flip chip-like structure. ing. Therefore, the base substrate 14 has a function as a so-called mother board. The semiconductor chips and the semiconductor chips and the base substrate are electrically connected by solder balls 25, and wirings on the semiconductor chips and through via holes in the chips are appropriately formed as necessary.

  In the semiconductor package 50 shown in FIG. 5, a large amount of heat is locally generated at the right end portion of the second semiconductor chip 12 due to, for example, the logic circuit configuration during driving. Therefore, in the configuration shown in FIG. 5, the right end portion of the second semiconductor chip 12 having the heat generation region 12A including the high heat generation portion is located on the right side of the first semiconductor chip 11 and the third semiconductor chip 13-1. I try to expose more. The exposed portion is sandwiched from above and below by a U-shaped heat sink member 57.

  Therefore, in the configuration shown in FIG. 5, the high heat generation region 12A of the second semiconductor chip 12 having the local high heat generation region 12A is exposed to the outside and sandwiched from above and below by the heat sink member 57. I'm trying to cool it down. In this case, since the heat radiation path can be formed vertically, it is possible to remarkably increase the cooling capacity. Therefore, even if the heat generation of the high heat generation region 12A in the second semiconductor chip 12 is great, it can be locally and selectively cooled.

  As a result, even if the second semiconductor chip 12 generates a large amount of heat, thermal runaway and characteristic degradation due to an increase in operating temperature, and further thermal runaway and characteristic degradation of the entire semiconductor package 50 can be suppressed. In addition, since only the high heat generation region 12A in the second semiconductor chip 12 can be selectively cooled, the entire second semiconductor chip 12 and further the semiconductor package 50 are accompanied by the cooling of the high heat generation region 12A. Therefore, the cooling efficiency of the second semiconductor chip 12 and further the semiconductor package 50 can be increased.

  The heat sink member 57 can be made of a member having excellent thermal conductivity, such as copper or aluminum. Furthermore, although the heat sink member 17 can be used alone, at least a part of the heat sink member 17 is brought into contact with the coolant, whereby the heat generating region 12A in the second semiconductor chip 12 can be cooled more efficiently. Actually, in the configuration shown in FIG. 5, a passage 57 </ b> A is formed in the heat sink member 57 so that the refrigerant flows through the passage 57 </ b> A. Therefore, the heat generating area 12A of the second semiconductor chip 12 can be cooled more effectively.

  Further, in this example, the case where the high heat generation region 12A is formed in the center portion of the second semiconductor chip 12 is shown, but the high heat generation region in the first semiconductor chip 11 or the third semiconductor chip 13-1. Even in the case where the heat generation region is formed, only the high heat generation region is obtained by exposing the heat generation region of the first semiconductor chip 11 or the third semiconductor chip 13-1 from the end portion and contacting the heat sink member for cooling. Can be selectively and effectively cooled.

  As the refrigerant, a non-reactive gas such as carbon dioxide gas or a rare gas can be used. Particularly in the case of the configuration shown in FIG. 5, a liquid state such as water, alcohol, a mixture of water and alcohol, or the like. The cooling capacity can be further increased by using this refrigerant.

  Further, in this example as well, the high heat generation region 12A is formed at the right end portion of the second semiconductor chip 12, but the formation location of the high heat generation region differs depending on the configuration of the incorporated logic circuit and the like. However, by designing the logic circuit or the like so that a high heat generation region is formed at the end portion of the semiconductor chip as in this example, the semiconductor chip positioned above the high heat generation region positioned at the end portion, for example, Since the region may be designed to be exposed, the formation can be easily performed without impairing the function of the semiconductor chip located above.

  While the present invention has been described in detail based on the above specific examples, the present invention is not limited to the above specific examples, and various modifications and changes can be made without departing from the scope of the present invention.

It is sectional drawing which shows schematic structure of the semiconductor device package in 1st Embodiment. It is sectional drawing which shows schematic structure of the semiconductor device package in 2nd Embodiment. It is sectional drawing which shows schematic structure of the semiconductor device package in 3rd Embodiment. It is sectional drawing which shows schematic structure of the semiconductor device package in 4th Embodiment. It is sectional drawing which shows schematic structure of the semiconductor device package in 5th Embodiment.

Explanation of symbols

10, 20, 30, 40, 50 Semiconductor package 11 First semiconductor chip 12 Second semiconductor chip 13-1 Third semiconductor chip 13-2 Fourth semiconductor chip 14 Base substrate 15 Wire 16 Thermal conductive paste 17, 17-1, 17-2, 57 Heat sink member 25 Solder balls 37, 37-1, 37-2 Cooling device

Claims (5)

A semiconductor package in which a plurality of semiconductor chips are stacked,
In at least one of the semiconductor chips, a heat generating portion heated to a relatively high temperature is locally exposed, and the heat generating portion is directly cooled.   The heat generating portion heated to a relatively high temperature includes a central portion of the at least one semiconductor chip, and at least the central portion is exposed to directly cool the heat generating portion. The semiconductor package described in 1.   The semiconductor package according to claim 1, wherein the heat generating portion heated to a relatively high temperature is cooled from below the at least one semiconductor chip.   3. The semiconductor package according to claim 1, wherein the heat generating portion heated to a relatively high temperature is cooled from above and below the at least one semiconductor chip.   5. The semiconductor package according to claim 1, wherein the heat-generating portion heated to a relatively high temperature is cooled by being brought into contact with a heat sink.

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