JP2008192938A5 - - Google Patents

Claims (12)

An insulating layer having a through hole;
A conductor layer laminated on the insulating layer and exposed at least partially through the through hole;
An underlayer connected to the conductor layer and covering the inner surface of the through hole;
Via conductors at least partially formed in the through holes so as to cover the foundation layer;
A wiring board comprising:
A wiring substrate, wherein a metal crystal of the metal material of the conductor layer and the metal material of the base layer is formed between the conductor layer and the base layer.   The wiring board according to claim 1, wherein a thickness of the oxide film between the conductor layer and the base layer is 80 nm or less. The conductor layer includes at least one metal material of copper, silver, gold, aluminum, nickel, chromium,
The wiring board according to claim 1, wherein the underlayer includes at least one metal material of copper, nickel, chromium, titanium, tungsten, and molybdenum.   The wiring board according to claim 1, wherein the metal crystal is formed in a region of 55% or more of a virtual interface between the conductor layer and the base layer.   The wiring board according to claim 1, wherein a metal crystal of a metal material of the base layer and a metal material of the via conductor is formed between the base layer and the via conductor. The underlayer includes at least one metal material of copper, nickel, chromium, titanium, tungsten and molybdenum;
The wiring board according to claim 5, wherein the via conductor is at least one of copper, silver, gold, aluminum, nickel, and chromium.   The wiring board according to claim 5, wherein the metal crystal is formed in a region of 55% or more of a virtual interface between the base layer and the via conductor.   The wiring board according to claim 1, wherein the inner surface of the through hole has a ten-point average roughness Rz of 1 μm or less.   The wiring board according to claim 8, wherein the ten-point average roughness Rz of the inner surface of the through hole is not less than 30 nm and not more than 300 nm. The insulating layer includes at least one of polyimide resin, acrylic resin, epoxy resin, cyanate resin, urethane resin, Teflon (registered trademark) resin, silicon resin, polyphenylene ether resin, bismaleimide triazine resin, and polyparaphenylene benzoxazole. Contains insulating material,
The wiring substrate according to claim 9, wherein the base layer includes at least one metal material of copper, nickel, chromium, titanium, tungsten, and molybdenum. The wiring board according to any one of claims 1 to 10,
A semiconductor element mounted on the wiring board;
A mounting structure characterized by comprising: A first step of forming a through hole so that a part of the conductor layer is exposed with respect to the insulating layer on which the conductor layer is formed;
A second step of forming a base layer so as to cover an exposed surface exposed from the through hole in the conductor layer and an inner surface of the through hole;
A third step of forming a via conductor so as to cover the underlayer;
A method of manufacturing a wiring board including:
The method of manufacturing a wiring board, wherein the second step is performed in a state where the ten-point average roughness Rz on the exposed surface is maintained at 1 μm or less.