JP2008187018A - Manufacturing method of chip resistor, and chip resistor - Google Patents

Manufacturing method of chip resistor, and chip resistor Download PDF

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JP2008187018A
JP2008187018A JP2007019384A JP2007019384A JP2008187018A JP 2008187018 A JP2008187018 A JP 2008187018A JP 2007019384 A JP2007019384 A JP 2007019384A JP 2007019384 A JP2007019384 A JP 2007019384A JP 2008187018 A JP2008187018 A JP 2008187018A
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resistor
insulating substrate
chip
recess
groove
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JP5179064B2 (en
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Masayuki Kuwabara
雅之 桑原
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Taiyosha Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To achieve a chip resistor having many kinds of resistance values with one kind of paste, moreover to achieve the chip resistor having a low-resistance value and a small change in a resistance value by a temperature, further, to achieve a small chip resistor excellent in an anti-surge characteristics, and to achieve a multiple chip resistor with a small type, a small profile and small crosstalk noise. <P>SOLUTION: Plural kinds of insulating substrates 10, having different depths of a groove-like concave portion 13, are prepared, and a resistor 15 is embedded to a front surface of the insulating substrate 10 in the groove-like concave portion 13. The thickness of the resistor 15 on the insulating substrate 10 can be changed, according to a type of the insulating substrate 10 by choosing the type of the insulating substrate 10. Thus, the chip resistor having many kinds of resistance values can be manufactured by using one kind of resistor paste. Since the resistor 15 is embedded in the groove-like concave portion 13, blots and sags can be prevented from occurring, when printing-drying-firing process of the resistor paste is carried out. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明はチップ抵抗器の製造方法及びチップ抵抗器に関する。   The present invention relates to a chip resistor manufacturing method and a chip resistor.

チップ抵抗器の製造に用いられる抵抗ペースト材料は高価であるにも拘わらず、市場で要求される多様な抵抗値に対応するため、従来は多種多様な抵抗率を持つ抵抗ペーストを用意した上で、スクリーン印刷の印刷条件を変化させることで印刷膜厚を微妙に制御して対応してきた。しかし、印刷条件を変えることで制御可能な抵抗値範囲は非常に狭く、結果としてトリミング前の初抵抗値が目標の抵抗値範囲に入らず廃棄せざるを得なくなるといった問題があった。   Despite the fact that the resistor paste material used in the manufacture of chip resistors is expensive, in order to meet the various resistance values required in the market, a resistor paste with various resistivities has been prepared in the past. The printing film thickness has been finely controlled by changing the screen printing conditions. However, the resistance value range that can be controlled by changing the printing conditions is very narrow, and as a result, the initial resistance value before trimming does not fall within the target resistance value range and must be discarded.

また、近年電流検出用として抵抗値が10mΩ前後で、しかも温度による抵抗値変化が小さいチップ抵抗器の要求があるが、従来の技術では抵抗ペーストの印刷・乾燥・焼成の際の滲みやダレにより、低抵抗値でしかも温度による抵抗値変化が小さいチップ抵抗器の実現が困難であった。   In recent years, there is a demand for a chip resistor having a resistance value of about 10 mΩ for current detection and a small change in resistance value due to temperature. However, in the conventional technology, due to bleeding and sagging during printing, drying, and firing of the resistor paste Therefore, it has been difficult to realize a chip resistor having a low resistance value and a small resistance value change due to temperature.

さらにまた、近年耐サージ特性に優れ、しかも小型のチップ抵抗器の要求があるが、従来のスクリーン印刷技術では抵抗ペーストの印刷・乾燥・焼成によりパターンの線幅は100〜150μmが限界であった。チップ抵抗器の耐サージ特性は抵抗パターンを長くして単位長さ当たりの電界強度を小さくすることにより向上する性質があるが、小型チップ抵抗器では抵抗パターンを蛇行して長く形成することが困難であった。   Furthermore, in recent years, there is a demand for a chip resistor having excellent surge resistance and a small size, but with conventional screen printing technology, the line width of the pattern is limited to 100 to 150 μm by printing, drying and firing of the resistance paste. . The surge resistance characteristics of chip resistors can be improved by increasing the resistance pattern and reducing the electric field intensity per unit length. However, it is difficult to make the resistance pattern meandering longer with a small chip resistor. Met.

また、近年、電子機器の小型化軽量化に伴い多連チップ抵抗器の小型化及び低背化の要求がある一方で、抵抗体の間隔が狭くなることにより、隣接する抵抗体に流れる信号がノイズとなるいわゆるクロストークノイズを低減する要求がある。従来の多連チップ抵抗器は基板の上面のみに複数の抵抗体を形成するため、抵抗体の間隔を大きくすることが困難であった。
引用なし
In recent years, there has been a demand for miniaturization and low profile of multi-chip resistors along with miniaturization and weight reduction of electronic devices. There is a need to reduce so-called crosstalk noise that becomes noise. Since the conventional multiple chip resistor forms a plurality of resistors only on the upper surface of the substrate, it is difficult to increase the interval between the resistors.
No quote

本発明は上記の諸課題を解決するものであり、1種類のペーストで多種類の抵抗値を有するチップ抵抗器を実現することを第1の目的とする。   The present invention solves the above-mentioned problems, and a first object thereof is to realize a chip resistor having various resistance values with one type of paste.

また、低抵抗値で、温度による抵抗値変化が小さいチップ抵抗器を実現することを第2の目的とする。   A second object is to realize a chip resistor having a low resistance value and a small change in resistance value due to temperature.

更に又、小型で耐サージ特性に優れたチップ抵抗器を実現することを第3の目的とする。   A third object is to realize a small chip resistor having excellent surge resistance.

また、小型・低背でクロストークノイズが小さい多連チップ抵抗器を実現することを第4の目的とする。   A fourth object is to realize a multiple chip resistor that is small and low in profile and has low crosstalk noise.

請求項1に記載の発明は、上面に設けられる凹部の形状が異なる複数種類の絶縁基板を製作する工程と、前記凹部に基板の上面と略同じ高さまで抵抗体を埋設する工程と、前記抵抗体の両端部に電気的に接続された一対の上面電極を形成する工程と、少なくとも前記抵抗体を被覆する保護膜を形成する工程とを有するチップ抵抗器の製造方法であって、抵抗体を調整する方法として前記複数種類から一種類の絶縁基板を選択する工程を含むことを特徴とする。 The invention described in claim 1 includes a step of manufacturing a plurality of types of insulating substrates having different concave shapes provided on the upper surface, a step of embedding a resistor in the concave portion to a height substantially equal to the upper surface of the substrate, and the resistance A method for manufacturing a chip resistor, comprising: a step of forming a pair of upper surface electrodes electrically connected to both ends of a body; and a step of forming a protective film covering at least the resistor. The adjusting method includes a step of selecting one type of insulating substrate from the plurality of types.

請求項2に記載の発明は、上面に設けられる凹部の形状が異なる複数種類の絶縁基板を製作する工程と、 前記凹部に基板の上面より高く抵抗体を埋設する工程と、埋設した抵抗体の表面を研磨して抵抗体の表面と基板の上面とを略面一にする工程と、前記抵抗体の両端部に電気的に接続された一対の上面電極を形成する工程と、前記抵抗体と上面電極の一部を被覆する保護膜を形成する工程と、を有するチップ抵抗器の製造方法であって、抵抗体を調整する方法として前記複数種類から一種類の絶縁基板を選択する工程を含むことを特徴とする。   According to a second aspect of the present invention, there are provided a step of manufacturing a plurality of types of insulating substrates having different shapes of concave portions provided on the upper surface, a step of embedding a resistor higher than the upper surface of the substrate in the concave portion, Polishing the surface to make the surface of the resistor substantially flush with the upper surface of the substrate, forming a pair of upper surface electrodes electrically connected to both ends of the resistor, and the resistor Forming a protective film covering a part of the upper surface electrode, and including a step of selecting one type of insulating substrate from the plurality of types as a method of adjusting the resistor. It is characterized by that.

請求項3に記載の発明は請求項1又は2に記載のチップ抵抗器の製造方法において、前記凹部が蛇行していることを特徴とする。   According to a third aspect of the present invention, in the method for manufacturing a chip resistor according to the first or second aspect, the concave portion is meandering.

請求項4に記載の発明は、チップ抵抗器であって、絶縁基板の表面に凹部を設けるとともに絶縁基板の裏面に凹部を表面の凹部の列に平行に設け、かつ絶縁体の表面の凹部と裏面の凹部が対向しないように表面の凹部と裏面の凹部を配置し、前記各凹部に絶縁基板の表面と略同じ高さまで抵抗体を埋設し、前記各抵抗体の端部に電気的に接続される一対の上面電極を前記絶縁体に被着し、前記各抵抗体及びその両端部の上面電極の一部を保護膜で被覆したことを特徴とする。   The invention according to claim 4 is a chip resistor, in which a recess is provided on the surface of the insulating substrate, a recess is provided on the back surface of the insulating substrate in parallel with the row of the recesses on the surface, and a recess on the surface of the insulator is provided. A concave portion on the front surface and a concave portion on the back surface are arranged so that the concave portions on the back surface do not face each other, and a resistor is embedded in each of the concave portions to approximately the same height as the surface of the insulating substrate, and is electrically connected to the end portion of each resistor. A pair of upper surface electrodes are attached to the insulator, and each resistor and a part of the upper surface electrodes at both ends thereof are covered with a protective film.

請求項1に記載の発明によれば、凹部の形状を異にする複数種類の絶縁基板を用意し、凹部に抵抗体を絶縁基板の表面まで埋設するので、絶縁基板の種類を選択することにより絶縁基板上の抵抗体の厚みを絶縁基板の種類に応じて変化させることができる。このため、一種類の抵抗体ペーストを用いて多種類の抵抗値を有するチップ抵抗器を製造できる。   According to the first aspect of the present invention, a plurality of types of insulating substrates having different concave shapes are prepared, and a resistor is embedded in the concave portion up to the surface of the insulating substrate. The thickness of the resistor on the insulating substrate can be changed according to the type of the insulating substrate. For this reason, the chip resistor which has many types of resistance values can be manufactured using one type of resistor paste.

また、抵抗体を凹部に埋設するので、抵抗ペーストの印刷・乾燥・焼成の際の滲みやダレの発生を防止できる。
また、凹状パターンは基板焼成前にプレス加工で形成するため、深さ方向を含めた形状制御が容易でありトリミングすることなく目標の抵抗値を得ることが出来る。
また、凹状パターンの溝を深くすることにより従来の技術では実現不可能な低抵抗値を持つチップ抵抗器の提供が可能となる。
In addition, since the resistor is embedded in the recess, it is possible to prevent bleeding and sagging during printing, drying, and firing of the resistor paste.
Further, since the concave pattern is formed by press work before firing the substrate, shape control including the depth direction is easy, and a target resistance value can be obtained without trimming.
Further, by deepening the groove of the concave pattern, it is possible to provide a chip resistor having a low resistance value that cannot be realized by the conventional technology.

請求項2に記載の発明によれば、凹部に基板の上面より高く埋設した抵抗体を研磨して抵抗体の表面と基板の上面とを面一にするので、凹部に埋設した抵抗体の厚みが凹部の深さに精確に一致する。このため抵抗体の抵抗値が凹部の深さの違いに基づいてより精確に設定できる。
また、埋め込みに用いるスクリーン印刷用のマスクに要求される精度は格段に低いため、効率の良い製造が可能となる。
According to the second aspect of the present invention, the resistor embedded in the recess higher than the upper surface of the substrate is polished so that the surface of the resistor and the upper surface of the substrate are flush with each other, so the thickness of the resistor embedded in the recess Exactly matches the depth of the recess. For this reason, the resistance value of the resistor can be set more accurately based on the difference in the depth of the recess.
In addition, since the accuracy required for the mask for screen printing used for embedding is remarkably low, efficient production becomes possible.

請求項3に記載の発明によれば、抵抗体が埋設される凹部を蛇行させたので、例えば線幅が50〜100μmと幅の狭い抵抗パターンを長く形成することが可能となる。このため、小型で耐サージ特性に優れたチップ抵抗器を製造できる。
また、凹状パターンの深さ、行路長を変化させることでトリミング前の初抵抗値を簡単に2倍、3倍と制御することが可能になるため、少ない種類の抵抗ペーストで多くの種類の抵抗値を得ることが可能になり、制御性の高い製造工程が実現出来る。
また、抵抗体と基板の接触面積を従来と比較して格段に大きく取る事ができ、その結果放熱性が向上し、同じチップ面積でより大きな定格電力を持つチップ抵抗器の提供が可能となる。
また、微細パターンの形成により行路長を長く取ることにより従来の技術では実現不可能な高抵抗値を持つチップ抵抗器の提供が可能となる。
According to the invention described in claim 3, since the concave portion in which the resistor is embedded is meandered, it is possible to form a long resistance pattern having a line width of 50 to 100 μm, for example. For this reason, a small chip resistor having excellent surge resistance can be manufactured.
In addition, by changing the depth and path length of the concave pattern, the initial resistance value before trimming can be easily controlled to be doubled or tripled. A value can be obtained, and a highly controllable manufacturing process can be realized.
Also, the contact area between the resistor and the substrate can be made much larger than before, and as a result, the heat dissipation is improved, and it is possible to provide a chip resistor having a larger rated power with the same chip area. .
In addition, it is possible to provide a chip resistor having a high resistance value that cannot be realized by the conventional technique by increasing the path length by forming a fine pattern.

請求項4に記載の発明によれば、絶縁基板の表裏両面に凹部を設け、かつ表面の凹部と裏面の凹部が対向しないように配置し、各凹部に抵抗体を埋設したので、絶縁基板に設けられる抵抗体の本数を少なくすることなく、隣接する抵抗体間の距離を大きくすることができる。このため、小型でクロストークノイズが小さい多連チップ抵抗器を製造できる。   According to the fourth aspect of the present invention, since the concave portions are provided on both the front and back surfaces of the insulating substrate, and the concave portions on the front surface and the concave surface on the back surface are not opposed to each other, and the resistor is embedded in each concave portion. The distance between the adjacent resistors can be increased without reducing the number of resistors provided. For this reason, a multiple chip resistor with small crosstalk noise can be manufactured.

以下に本発明の第1実施例に係るチップ抵抗器の製造方法を添付図面に基づき説明する。図1及び図2に示すように、大判の絶縁基板10に複数本の一次スリット11を等間隔で形成するとともに複数本の二次スリット12を等間隔で形成する。同時に、二次スリットで区画された短冊状基板の中央部分に基板の一端から他端まで延びる溝状凹部13を形成する。一次スリット11、二次スリット12及び溝状凹部13はグリーンシートにプレス加工で成形し、しかる後に焼成したり、焼成した絶縁基板に回転ディスクあるいはレーザー光で加工する。そして、大判の絶縁基板10に溝状凹部13を加工するに際し、例えば15μmと30μmのように溝状凹部13の深さが異なる複数種類の大判の絶縁基板10を製作する。   A method for manufacturing a chip resistor according to a first embodiment of the present invention will be described below with reference to the accompanying drawings. As shown in FIGS. 1 and 2, a plurality of primary slits 11 are formed at equal intervals on a large insulating substrate 10 and a plurality of secondary slits 12 are formed at equal intervals. At the same time, a groove-like recess 13 extending from one end of the substrate to the other end is formed in the central portion of the strip-shaped substrate defined by the secondary slit. The primary slit 11, the secondary slit 12, and the groove-shaped recess 13 are formed into a green sheet by press working and then fired, or the fired insulating substrate is processed with a rotating disk or laser light. When processing the groove-shaped recess 13 in the large-sized insulating substrate 10, a plurality of types of large-sized insulating substrates 10 having different depths of the groove-shaped recess 13 such as 15 μm and 30 μm are manufactured.

次に、図3に示すように、大判の絶縁基板10の裏面に電極ペーストを印刷、焼成して一対の下面電極14を形成する。
なお、図3〜図8には便宜上大判の絶縁基板10を一次スリット11と二次スリット12から分割して形成したチップ片10Aを図示している。
Next, as shown in FIG. 3, an electrode paste is printed and baked on the back surface of the large insulating substrate 10 to form a pair of lower surface electrodes 14.
3 to 8 show a chip piece 10A formed by dividing a large insulating substrate 10 from a primary slit 11 and a secondary slit 12 for convenience.

続いて、図4に示すように、大判の溝状凹部13に抵抗ペーストを印刷、焼成して抵抗体15を形成する。抵抗ペーストを溝状凹部13に印刷するとき、抵抗ペーストを焼成して形成される抵抗体15の表面と絶縁基板10の表面が略面一となるように、抵抗ペーストの印刷厚みを調整する。抵抗ペーストの材料としては例えば、酸化ルテニウム系ペーストを使用する。抵抗ペーストは溝状凹部13に印刷するので、端縁に滲みやダレが発生するのを防止でき、溝状凹部13の寸法によって定まる精確な幅と厚みを備え、焼成したとき所要の容積を得ることができる。このため、例えば溝状凹部の深さが15μmの絶縁基板10を使用した場合の抵抗体15の抵抗値が20Ωとすれば、同じ抵抗ペーストを溝状凹部13の深さが30μmの絶縁基板10に印刷、焼成して抵抗体15を形成したとき、10Ωの抵抗値を得ることができる。   Subsequently, as shown in FIG. 4, a resistor paste is formed by printing and baking a resistor paste in a large groove-like recess 13. When printing the resistance paste on the groove-shaped recess 13, the printing thickness of the resistance paste is adjusted so that the surface of the resistor 15 formed by firing the resistance paste is substantially flush with the surface of the insulating substrate 10. For example, a ruthenium oxide paste is used as the material of the resistance paste. Since the resistance paste is printed on the groove-shaped recess 13, it is possible to prevent bleeding and sagging from occurring at the edge, have an accurate width and thickness determined by the dimensions of the groove-shaped recess 13, and obtain a required volume when fired. be able to. Therefore, for example, if the resistance value of the resistor 15 is 20Ω when the insulating substrate 10 having a groove-like recess depth of 15 μm is used, the same resistance paste is used as the insulating substrate 10 having the groove-like recess 13 depth of 30 μm. When the resistor 15 is formed by printing and baking, a resistance value of 10Ω can be obtained.

次に図5に示すように、抵抗体15の両端部に電極ペースト16を印刷焼成して一対の上面電極を形成する。   Next, as shown in FIG. 5, the electrode paste 16 is printed and fired on both ends of the resistor 15 to form a pair of upper surface electrodes.

次に、図6に示すように、抵抗体15と両上面電極16の一部を被覆するようにガラスペーストを印刷、焼成して保護膜19を形成する。   Next, as shown in FIG. 6, a protective film 19 is formed by printing and baking a glass paste so as to cover a part of the resistor 15 and both upper surface electrodes 16.

保護膜19の形成後、図7に示すように、大判の絶縁基板10を一次スリット11から短冊状に分割し、短冊状の絶縁基板10の両分割面に電極ペーストを印刷、焼成して側面電極20を形成する。側面電極20となる電極ペーストは上面電極16と下面電極14が電気的に接続されるように印刷する。   After forming the protective film 19, as shown in FIG. 7, the large insulating substrate 10 is divided into strips from the primary slit 11, and electrode paste is printed and fired on both divided surfaces of the strip-shaped insulating substrate 10. The electrode 20 is formed. The electrode paste used as the side electrode 20 is printed so that the upper surface electrode 16 and the lower surface electrode 14 are electrically connected.

側面電極20の形成後、短冊状の絶縁基板10を二次スリット12から分割して個々のチップ片10Aを形成し、各チップ片10Aの上面電極16、側面電極20及び下面電極14にニッケルメッキ21及び錫めっき22を施す。図8に、第1実施例に係る製造方法によって製造したチップ抵抗器10Aの模式的断面図を示す。   After the formation of the side electrode 20, the strip-shaped insulating substrate 10 is divided from the secondary slit 12 to form individual chip pieces 10A, and the upper electrode 16, the side electrode 20, and the lower electrode 14 of each chip piece 10A are plated with nickel. 21 and tin plating 22 are applied. FIG. 8 shows a schematic cross-sectional view of a chip resistor 10A manufactured by the manufacturing method according to the first embodiment.

本実施例によれば、溝状凹部13の深さを異にする複数種類の絶縁基板10を用意し、溝状凹部13に抵抗体15を絶縁基板10の表面まで埋設するので、絶縁基板10の種類を選択することにより絶縁基板10上の抵抗体15の厚みを絶縁基板10の種類に応じて変化させることができる。このため、一種類の抵抗体ペーストを用いて多種類の抵抗値を有するチップ抵抗器を製造できる。   According to the present embodiment, a plurality of types of insulating substrates 10 having different depths of the groove-like recesses 13 are prepared, and the resistor 15 is embedded in the groove-like recesses 13 up to the surface of the insulating substrate 10. By selecting the type, the thickness of the resistor 15 on the insulating substrate 10 can be changed according to the type of the insulating substrate 10. For this reason, the chip resistor which has many types of resistance values can be manufactured using one type of resistor paste.

また、抵抗体15を溝状凹部13に埋設するので、抵抗ペーストの印刷・乾燥・焼成の際の滲みやダレの発生を防止できる。
また、凹状パターンは基板焼成前にプレス加工で形成するため、深さ方向を含めた形状制御が容易でありトリミングすることなく目標の抵抗値を得ることが出来る事が本発明の特徴であるが、必要に応じてカバーコートを形成してトリミングを行う事でより精密な抵抗値を実現する事を妨げない。また、実施例1では溝の本数を1本としたがこれに限らず複数本の溝を形成することにより初抵抗値を変化させることが出来る。また、実施例1では溝の形状を逆台形としたがこれに限らず矩形、半円形、半楕円形、半小判形など任意の形状にすることにより初抵抗値を変化させることが出来る。更に、実施例1では溝の形状を直線状としたが蛇行等により長さを変化させることにより初抵抗値を変化させることが出来る。また、言うまでもなく溝の幅を変えることにより初抵抗値を変化させることが出来る。
また、凹状パターンの溝を深くすることにより従来の技術では実現不可能な低抵抗値を持つチップ抵抗器の提供が可能となる。
In addition, since the resistor 15 is embedded in the groove-shaped recess 13, it is possible to prevent bleeding and sagging during printing, drying, and firing of the resistance paste.
In addition, since the concave pattern is formed by pressing before firing the substrate, the shape control including the depth direction is easy, and the target resistance value can be obtained without trimming. If necessary, it is possible to form a cover coat and perform trimming to prevent a more accurate resistance value from being realized. In the first embodiment, the number of grooves is one. However, the present invention is not limited to this, and the initial resistance value can be changed by forming a plurality of grooves. In the first embodiment, the shape of the groove is an inverted trapezoid. However, the shape of the groove is not limited to this, and the initial resistance value can be changed by using an arbitrary shape such as a rectangular shape, a semicircular shape, a semielliptical shape, and a semi-oval shape. Further, in Embodiment 1, the shape of the groove is linear, but the initial resistance value can be changed by changing the length by meandering or the like. Needless to say, the initial resistance value can be changed by changing the width of the groove.
Further, by deepening the groove of the concave pattern, it is possible to provide a chip resistor having a low resistance value that cannot be realized by the conventional technology.

本発明の第2実施例に係るチップ抵抗器の製造方法を図9〜図14に基づき説明する。図9に示すように、大判の絶縁基板30の表面に一次スリッ31トと二次スリット32を形成するとともに、一次スリット31と二次スリット32で区画されたチップ片30Aのそれぞれに溝状凹部33を形成する。この溝状凹部33は略W字形に蛇行する平面形状を有するように形成する。大判の絶縁基板30にこの溝状凹部33を形成する際、第1実施例の製造方法と同様に溝状凹部33の深さを異にする複数種類の大判絶縁基板30を製作する。種類としては溝状凹部33の深さが例えば10μmのものと20μmのものを用意する。   A method for manufacturing a chip resistor according to a second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 9, a primary slit 31 and a secondary slit 32 are formed on the surface of a large insulating substrate 30, and a groove-like recess is formed in each of the chip pieces 30A defined by the primary slit 31 and the secondary slit 32. 33 is formed. The groove-shaped recess 33 is formed to have a planar shape meandering in a substantially W shape. When the groove-shaped recess 33 is formed on the large-sized insulating substrate 30, a plurality of types of large-sized insulating substrates 30 having different depths of the groove-shaped recess 33 are manufactured as in the manufacturing method of the first embodiment. As types, for example, those having a depth of 10 μm and 20 μm of the groove-shaped recess 33 are prepared.

次に、図10に示すように、大判の絶縁基板30の裏面に電極ペーストを印刷、焼成して各チップ片30A毎に一対の下面電極34を形成する。   Next, as shown in FIG. 10, an electrode paste is printed and baked on the back surface of the large insulating substrate 30 to form a pair of lower surface electrodes 34 for each chip piece 30A.

続いて、図11に示すように、溝状凹部33に抵抗ペーストを印刷、焼成して抵抗体35を形成する。図12に示すように、このとき抵抗体35が絶縁基板30の表面より若干盛り上がって形成されるように、抵抗ペーストの印刷厚みを調整しておく。   Subsequently, as shown in FIG. 11, a resistor paste is formed by printing and baking a resistor paste in the groove-shaped recess 33. As shown in FIG. 12, the printing thickness of the resistance paste is adjusted so that the resistor 35 is slightly raised from the surface of the insulating substrate 30 at this time.

抵抗体35の形成後、図13に示す研磨装置60に大判の絶縁基板30をセットする。この研磨装置60は研磨盤61と、研磨盤61に対し上下動する基板ホルダー62から成る。基板ホルダー62に、抵抗体35が研磨盤61に対面するように大判の絶縁基板30を装着し、基板ホルダー62を下動して、絶縁基板30の表面から盛り上がった抵抗体35を研磨盤61に圧接させる。そして、研磨盤61を回転させ、盛り上がった抵抗体35を研磨し、抵抗体35の表面と絶縁基板30の面を略面一に形成する。   After the formation of the resistor 35, a large insulating substrate 30 is set in the polishing apparatus 60 shown in FIG. The polishing apparatus 60 includes a polishing board 61 and a substrate holder 62 that moves up and down relative to the polishing board 61. A large-sized insulating substrate 30 is mounted on the substrate holder 62 so that the resistor 35 faces the polishing plate 61, and the substrate holder 62 is moved downward to remove the resistor 35 raised from the surface of the insulating substrate 30. Pressure contact. Then, the polishing board 61 is rotated to polish the raised resistor 35 so that the surface of the resistor 35 and the surface of the insulating substrate 30 are substantially flush with each other.

次に、図14に示すように、研磨した大判の絶縁基板30に電極ペーストを印刷、焼成し、抵抗体35の両端部に電気的に接続される一対の上面電極36を形成する。続いて、両上面電極間36に露出している抵抗体35にガラスペーストを印刷、焼成してカバーコート層37を形成する。   Next, as shown in FIG. 14, an electrode paste is printed and baked on the polished large insulating substrate 30 to form a pair of upper surface electrodes 36 that are electrically connected to both ends of the resistor 35. Subsequently, a glass paste is printed and baked on the resistor 35 exposed between the upper surface electrodes 36 to form a cover coat layer 37.

そして、カバーコート層37の上からレーザートリミングで抵抗体35にトリミング溝38を形成し、抵抗体35の抵抗値を修正する。図15に示すように、トリミング溝38はW字形に蛇行している抵抗体35の中央切欠部35aが一次スリット31と平行方向に延長するように切り欠いて形成する。   Then, a trimming groove 38 is formed in the resistor 35 by laser trimming from above the cover coat layer 37 to correct the resistance value of the resistor 35. As shown in FIG. 15, the trimming groove 38 is formed by notching so that the central notch 35 a of the resistor 35 meandering in a W shape extends in a direction parallel to the primary slit 31.

レーザートリミングの後は第1実施例に係る製造方法と同様、順に保護膜と側面電極を形成し、ニッケルメッキと錫めっきを施す。
本実施例によれば、溝状凹部33に基板30の上面より高く埋設した抵抗体35を研磨して抵抗体35の表面と基板30の上面とを面一にするので、溝状凹部33に埋設した抵抗体35の厚みが溝状凹部33の深さに精確に一致する。このため抵抗体35の抵抗値が溝状凹部33の深さの違いに基づいてより精確に設定できる。
After the laser trimming, as in the manufacturing method according to the first embodiment, a protective film and side electrodes are sequentially formed, and nickel plating and tin plating are performed.
According to the present embodiment, the resistor 35 embedded in the groove-like recess 33 higher than the upper surface of the substrate 30 is polished so that the surface of the resistor 35 and the upper surface of the substrate 30 are flush with each other. The thickness of the buried resistor 35 exactly matches the depth of the groove-like recess 33. For this reason, the resistance value of the resistor 35 can be set more accurately based on the difference in the depth of the groove-shaped recess 33.

また、抵抗体35が埋設される溝状凹部33を蛇行させたので、例えば線幅が50〜100μmと幅の狭い抵抗パターンを長く形成することが可能となる。このため、小型で耐サージ特性に優れたチップ抵抗器を製造できる。
また、凹状パターンの深さ、行路長を変化させることでトリミング前の初抵抗値を簡単に2倍、3倍と制御することが可能になるため、少ない種類の抵抗ペーストで多くの種類の抵抗値を得ることが可能になり、制御性の高い製造工程が実現出来る。
また、抵抗体と基板の接触面積を従来と比較して格段に大きく取る事ができ、その結果放熱性が向上し、同じチップ面積でより大きな定格電力を持つチップ抵抗器の提供が可能となる。
また、微細パターンの形成により行路長を長く取ることにより従来の技術では実現不可能な高抵抗値を持つチップ抵抗器の提供が可能となる。
Further, since the groove-like recess 33 in which the resistor 35 is embedded is meandered, it is possible to form a long resistance pattern having a line width of 50 to 100 μm, for example. For this reason, a small chip resistor having excellent surge resistance can be manufactured.
In addition, by changing the depth and path length of the concave pattern, the initial resistance value before trimming can be easily controlled to be doubled or tripled. A value can be obtained, and a highly controllable manufacturing process can be realized.
Also, the contact area between the resistor and the substrate can be made much larger than before, and as a result, the heat dissipation is improved, and it is possible to provide a chip resistor having a larger rated power with the same chip area. .
In addition, it is possible to provide a chip resistor having a high resistance value that cannot be realized by the conventional technique by increasing the path length by forming a fine pattern.

本発明の第3実施例に係るチップ抵抗器の製造方法を図16〜図25に基づき説明する。図16、図17及び図18に示すように、大判の絶縁基板40に形成した一次スリット41と二次スリット42で区画されるチップ片40Aの表面と裏面に溝状凹部43の列を形成する。本実施例ではチップ片40Aごとに表面と裏面にそれぞれ2本の溝状凹部43からなる列を形成している。各溝状凹部43は二次スリット42と平行に形成する。そして、表面の溝状凹部43と裏面の溝状凹部43が対向することのないように、すなわち、表面の隣接する溝状凹部43の間の領域に裏面の溝状凹部43を配置し、かつ裏面の隣接する溝状凹部43の間の領域に表面の溝状凹部43を配置する。   A method for manufacturing a chip resistor according to a third embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 16, 17, and 18, a row of groove-like recesses 43 is formed on the front and back surfaces of a chip piece 40 </ b> A defined by a primary slit 41 and a secondary slit 42 formed on a large insulating substrate 40. . In the present embodiment, each chip piece 40A is formed with a row of two groove-like recesses 43 on the front surface and the back surface. Each groove-like recess 43 is formed in parallel with the secondary slit 42. And the groove-shaped recess 43 on the front surface is not opposed to the groove-shaped recess 43 on the back surface, that is, the groove-shaped recess 43 on the back surface is arranged in the region between the groove-shaped recesses 43 adjacent to the front surface, and The groove-shaped recess 43 on the front surface is arranged in a region between adjacent groove-shaped recesses 43 on the back surface.

次に、図19に示すように電極ペーストを絶縁基板の表裏両面の所定部位に印刷、焼成して下面電極44を形成する。各下面電極44は各溝状凹部43に対向するように、溝状凹部43を設けた面の反対面に設けられる。   Next, as shown in FIG. 19, the electrode paste is printed and baked on predetermined portions of the front and back surfaces of the insulating substrate to form the lower surface electrode 44. Each lower surface electrode 44 is provided on the surface opposite to the surface provided with the groove-shaped recess 43 so as to face each groove-shaped recess 43.

続いて、図20に示すように、各溝状凹部43に抵抗ペーストを印刷、焼成して抵抗体45を形成する。次に、図21に示すように、電極ペーストを印刷、焼成して上面電極46を形成し、図22に示すように、ガラスペーストを印刷、焼成してカバーコート47を形成し、レーザートリミングによりトリミング溝48を形成する。ついで、図23に示すように保護膜49を形成する。続いて、図24に示すように、側面電極50を形成し、ニッケルメッキと錫めっきを施す。図25に、本実施例に係る製造方法で製造したチップ抵抗器の断面図を示す。なお、図中51はニッケルメッキ、52は錫メッキを示す。   Subsequently, as shown in FIG. 20, a resistance paste 45 is formed by printing and baking a resistance paste in each groove-like recess 43. Next, as shown in FIG. 21, the electrode paste is printed and baked to form the upper surface electrode 46, and as shown in FIG. 22, the glass paste is printed and baked to form the cover coat 47, and laser trimming is performed. A trimming groove 48 is formed. Next, a protective film 49 is formed as shown in FIG. Subsequently, as shown in FIG. 24, side electrodes 50 are formed, and nickel plating and tin plating are performed. FIG. 25 is a cross-sectional view of the chip resistor manufactured by the manufacturing method according to this example. In the figure, 51 indicates nickel plating and 52 indicates tin plating.

本実施例によれば、絶縁基板40の表裏両面に溝状凹部43の列を設け、かつ表面の溝状凹部43と裏面の溝状凹部43が対向しないように配置し、各溝状凹部43に抵抗体45を埋設したので、絶縁基板40に設けられる抵抗体45の本数を少なくすることなく、隣接する抵抗体45間の距離を大きくすることができる。このため、小型・低背でクロストークノイズが小さい多連チップ抵抗器を製造できる。なお、本実施例では絶縁基板の表裏両面にそれぞれ2本の溝状凹部を設けたが、表裏に各1本の溝状凹部を設けるだけでも良い。
尚、実施例1、2、3において保護膜にガラスペーストを使用したが、これに限らず樹脂ペーストを使用しても良い。また、側面電極に焼成銀ペーストを使用したが、これに限らず樹脂銀ペーストや金属薄膜を使用しても良い。
また、実施例2、3において精密な抵抗値を実現するためカバーコートを形成した後、レーザートリミングを施したが、いうまでもなく実施例1のようにこれらの工程を省略してもよい。
According to the present embodiment, rows of groove-shaped recesses 43 are provided on both the front and back surfaces of the insulating substrate 40 and are arranged so that the groove-shaped recesses 43 on the front surface and the groove-shaped recesses 43 on the back surface do not face each other. Since the resistor 45 is embedded, the distance between the adjacent resistors 45 can be increased without reducing the number of the resistors 45 provided on the insulating substrate 40. For this reason, a multiple chip resistor with a small size, a low profile, and a small crosstalk noise can be manufactured. In this embodiment, two groove-like recesses are provided on both the front and back surfaces of the insulating substrate, but only one groove-like recess may be provided on the front and back surfaces.
In addition, although glass paste was used for the protective film in Examples 1, 2, and 3, it is not restricted to this, You may use resin paste. Moreover, although the baking silver paste was used for the side electrode, you may use not only this but a resin silver paste and a metal thin film.
In Examples 2 and 3, laser trimming was performed after a cover coat was formed in order to realize a precise resistance value. Needless to say, these steps may be omitted as in Example 1.

本発明の第1実施例に係るチップ抵抗器の製造に用いられる大判絶縁基板を示す斜視図である。It is a perspective view which shows the large-sized insulation board | substrate used for manufacture of the chip resistor which concerns on 1st Example of this invention. 図1の2−2線から切断した断面図である。It is sectional drawing cut | disconnected from the 2-2 line | wire of FIG. 本発明の第1実施例に係るチップ抵抗器を構成する絶縁基板のチップ片と下面電極を示す斜視図である。It is a perspective view which shows the chip piece and lower surface electrode of the insulated substrate which comprise the chip resistor which concerns on 1st Example of this invention. 同チップ片と下面電極及び抵抗体を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, and a resistor. 同チップ片と下面電極、抵抗体及び上面電極を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, and an upper surface electrode. 同チップ片と下面電極、抵抗体、上面電極及び保護膜を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, an upper surface electrode, and a protective film. 同チップ片と下面電極、抵抗体、上面電極、カバーコート層、保護膜及び側面電極を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, an upper surface electrode, a cover coat layer, a protective film, and a side electrode. 本発明の第1実施例に係るチップ抵抗器を示す断面図である。It is sectional drawing which shows the chip resistor which concerns on 1st Example of this invention. 本発明の第2実施例に係るチップ抵抗器の製造に用いられる大判絶縁基板を示す斜視図である。It is a perspective view which shows the large format insulated substrate used for manufacture of the chip resistor which concerns on 2nd Example of this invention. 本発明の第2実施例に係るチップ抵抗器を構成する絶縁基板のチップ片と下面電極を示す斜視図である。It is a perspective view which shows the chip piece and lower surface electrode of the insulated substrate which comprise the chip resistor which concerns on 2nd Example of this invention. 同チップ片と下面電極及び抵抗体を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, and a resistor. 図12の13−13線から切断した断面図である。It is sectional drawing cut | disconnected from the 13-13 line | wire of FIG. 本発明の第2実施例に係るチップ抵抗器の製造に用いられる研磨装置の構成を示す説明図である。It is explanatory drawing which shows the structure of the grinding | polishing apparatus used for manufacture of the chip resistor which concerns on 2nd Example of this invention. 本発明の第2実施例に係るチップ抵抗器を構成するチップ片と下面電極、抵抗体、上面電極及びカバーコート層を示す斜視図である。It is a perspective view which shows the chip piece which comprises the chip resistor which concerns on 2nd Example of this invention, a lower surface electrode, a resistor, an upper surface electrode, and a cover coat layer. 同チップ片と下面電極、抵抗体、上面電極、カバーコート層及びトリミング溝を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, an upper surface electrode, a cover coat layer, and a trimming groove. 本発明の第3実施例に係るチップ抵抗器の製造に用いられる大判絶縁基板を示す斜視図である。It is a perspective view which shows the large-sized insulation board | substrate used for manufacture of the chip resistor which concerns on 3rd Example of this invention. 本発明の第3実施例に係るチップ抵抗器を構成する絶縁基板のチップ片を示す斜視図である。It is a perspective view which shows the chip piece of the insulated substrate which comprises the chip resistor which concerns on 3rd Example of this invention. 図18の19−19線から切断した断面図である。It is sectional drawing cut | disconnected from the 19-19 line | wire of FIG. 本発明の第3実施例に係るチップ抵抗器を構成する絶縁基板のチップ片と下面電極を示す斜視図である。It is a perspective view which shows the chip piece and lower surface electrode of the insulated substrate which comprise the chip resistor which concerns on 3rd Example of this invention. 同チップ片と下面電極及び抵抗体を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, and a resistor. 同チップ片と下面電極、抵抗体及び上面電極を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, and an upper surface electrode. 同チップ片と下面電極、抵抗体、上面電極及びカバーコート層を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, an upper surface electrode, and a cover coat layer. 同チップ片と下面電極、抵抗体、上面電極、カバーコート層及び保護膜を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, an upper surface electrode, a cover coat layer, and a protective film. 同チップ片と下面電極、抵抗体、上面電極、カバーコート層、保護膜及び側面電極を示す斜視図である。It is a perspective view which shows the chip piece, a lower surface electrode, a resistor, an upper surface electrode, a cover coat layer, a protective film, and a side electrode. 図24の25−25線から切断した断面図である。It is sectional drawing cut | disconnected from the 25-25 line | wire of FIG.

符号の説明Explanation of symbols

10,30,40…絶縁基板
10A,30A,40A…チップ片
11,31,41…一次スリット
12,32,42…二次スリット
13,33,43…溝状凹部
14,34,44…下面電極
15,35,45…抵抗体
16,36,46…上面電極
17,37,47…カバーコート層
18,48…トリミング溝
19,49…保護膜
20,50…側面電極
10, 30, 40 ... insulating substrates 10A, 30A, 40A ... chip pieces 11, 31, 41 ... primary slits 12, 32, 42 ... secondary slits 13, 33, 43 ... groove-like recesses 14, 34, 44 ... bottom electrodes 15, 35, 45 ... resistors 16, 36, 46 ... upper surface electrodes 17, 37, 47 ... cover coat layers 18, 48 ... trimming grooves 19, 49 ... protective films 20, 50 ... side electrodes

Claims (4)

上面に設けられる凹部の形状が異なる複数種類の絶縁基板を製作する工程と、
前記凹部に基板の上面と略同じ高さまで抵抗体を埋設する工程と、前記抵抗体の両端部に電気的に接続された一対の上面電極を形成する工程と、少なくとも前記抵抗体を被覆する保護膜を形成する工程とを有するチップ抵抗器の製造方法であって、抵抗体を調整する方法として前記複数種類から一種類の絶縁基板を選択する工程を含むことを特徴とするチップ抵抗器の製造方法。
Producing a plurality of types of insulating substrates having different shapes of recesses provided on the upper surface;
A step of embedding a resistor in the recess to substantially the same height as the upper surface of the substrate, a step of forming a pair of upper surface electrodes electrically connected to both ends of the resistor, and a protection covering at least the resistor A method of manufacturing a chip resistor comprising a step of forming a film, the method including a step of selecting one type of insulating substrate from the plurality of types as a method of adjusting a resistor. Method.
上面に設けられる凹部の形状が異なる複数種類の絶縁基板を製作する工程と、
前記凹部に基板の上面より高く抵抗体を埋設する工程と、
埋設した抵抗体の表面を研磨して抵抗体の表面と基板の上面とを略面一にする工程と、
前記抵抗体の両端部に電気的に接続された一対の上面電極を形成する工程と、前記抵抗体と上面電極の一部を被覆する保護膜を形成する工程と、を有するチップ抵抗器の製造方法であって、
抵抗体を調整する方法として前記複数種類から一種類の絶縁基板を選択する工程を含むことを特徴とするチップ抵抗器の製造方法。
Producing a plurality of types of insulating substrates having different shapes of recesses provided on the upper surface;
Burying a resistor higher than the upper surface of the substrate in the recess;
Polishing the surface of the embedded resistor to make the surface of the resistor substantially flush with the upper surface of the substrate;
Manufacturing of a chip resistor having a step of forming a pair of upper surface electrodes electrically connected to both ends of the resistor, and a step of forming a protective film covering the resistor and a part of the upper surface electrode A method,
A method of manufacturing a chip resistor, comprising a step of selecting one type of insulating substrate from the plurality of types as a method of adjusting a resistor.
前記凹部が蛇行していることを特徴とする請求項1又は2に記載のチップ抵抗器の製造方法。   The method for manufacturing a chip resistor according to claim 1, wherein the concave portion is meandering. 絶縁基板の表面に凹部を設けるとともに絶縁基板の裏面に凹部を表面の凹部に平行に設け、かつ絶縁体の表面の凹部と裏面の凹部が対向しないように表面の凹部と裏面の凹部を配置し、
前記各凹部に絶縁基板の表面と略同じ高さまで抵抗体を埋設し、
前記各抵抗体の端部に電気的に接続される一対の上面電極を前記絶縁体に被着し、
前記各抵抗体及びその両端部の上面電極の一部を保護膜で被覆したことを特徴とするチップ抵抗器。
A recess is provided on the surface of the insulating substrate, a recess is provided on the back surface of the insulating substrate in parallel with the recess on the front surface, and a recess on the front surface and a recess on the back surface are arranged so that the recess on the surface of the insulator does not face the recess on the back surface. ,
In each of the recesses, a resistor is embedded to the same height as the surface of the insulating substrate,
A pair of upper surface electrodes that are electrically connected to the ends of the resistors are attached to the insulator,
A chip resistor, wherein each resistor and a part of the upper surface electrode at both ends thereof are covered with a protective film.
JP2007019384A 2007-01-30 2007-01-30 Chip resistor manufacturing method and chip resistor Expired - Fee Related JP5179064B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018137477A (en) * 2018-04-27 2018-08-30 ローム株式会社 Chip resistor and mounting structure for chip resistor
JP2021044585A (en) * 2020-12-10 2021-03-18 ローム株式会社 Chip resistor
CN114042810A (en) * 2021-11-16 2022-02-15 南京萨特科技发展有限公司 Multi-station continuous chip resistor stamping, resistance trimming and belt cutting all-in-one machine and production method
CN114171267A (en) * 2021-11-16 2022-03-11 宁波鼎声微电子科技有限公司 Anti-surge resistor and processing equipment thereof
US11728265B2 (en) * 2018-09-12 2023-08-15 Intel Corporation Selective deposition of embedded thin-film resistors for semiconductor packaging

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5649102U (en) * 1979-09-21 1981-05-01
JPH10135014A (en) * 1996-10-31 1998-05-22 Taiyo Yuden Co Ltd Manufacture of chip part
WO1998058390A1 (en) * 1997-06-16 1998-12-23 Matsushita Electric Industrial Co., Ltd. Resistance wiring board and method for manufacturing the same
JPH118108A (en) * 1997-06-17 1999-01-12 Taiyo Yuden Co Ltd Manufacture of chip part

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5649102U (en) * 1979-09-21 1981-05-01
JPH10135014A (en) * 1996-10-31 1998-05-22 Taiyo Yuden Co Ltd Manufacture of chip part
WO1998058390A1 (en) * 1997-06-16 1998-12-23 Matsushita Electric Industrial Co., Ltd. Resistance wiring board and method for manufacturing the same
JPH118108A (en) * 1997-06-17 1999-01-12 Taiyo Yuden Co Ltd Manufacture of chip part

Cited By (10)

* Cited by examiner, † Cited by third party
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JP2018137477A (en) * 2018-04-27 2018-08-30 ローム株式会社 Chip resistor and mounting structure for chip resistor
US11728265B2 (en) * 2018-09-12 2023-08-15 Intel Corporation Selective deposition of embedded thin-film resistors for semiconductor packaging
JP2021044585A (en) * 2020-12-10 2021-03-18 ローム株式会社 Chip resistor
JP2022160609A (en) * 2020-12-10 2022-10-19 ローム株式会社 chip resistor
JP2022166308A (en) * 2020-12-10 2022-11-01 ローム株式会社 chip resistor
JP7457763B2 (en) 2020-12-10 2024-03-28 ローム株式会社 chip resistor
JP7458448B2 (en) 2020-12-10 2024-03-29 ローム株式会社 chip resistor
CN114042810A (en) * 2021-11-16 2022-02-15 南京萨特科技发展有限公司 Multi-station continuous chip resistor stamping, resistance trimming and belt cutting all-in-one machine and production method
CN114171267A (en) * 2021-11-16 2022-03-11 宁波鼎声微电子科技有限公司 Anti-surge resistor and processing equipment thereof
CN114171267B (en) * 2021-11-16 2023-05-26 宁波鼎声微电子科技有限公司 Anti-surge resistor and processing equipment thereof

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