JP2022166308A - chip resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip resistor capable of improving heat dissipation.

SOLUTION: A chip resistor includes a substrate, a resistor, a bonding layer interposed between the substrate and the resistor, an insulating layer covering the resistor, a first electrode located on a side opposite to the substrate with respect to the insulating layer in a thickness direction of the substrate, electrically connected to the resistor, and located on the first direction side, and a second electrode located on the side opposite to the substrate with respect to the insulating layer in the thickness direction of the substrate, electrically connected to the resistor, and located on a second direction side opposite to the first direction with respect to the first electrode, and the substrate has a first substrate side surface facing the first direction, the resistor has a first resistor side surface facing the first direction, and the first resistor side surface is positioned closer to the second direction side than the side surface of the first substrate and is covered with the insulating layer.

SELECTED DRAWING: Figure 38

COPYRIGHT: (C)2023,JPO&INPIT

Description

The present invention relates to chip resistors.

2. Description of the Related Art Conventionally, chip resistors used in electronic equipment have been known. For example, a chip resistor includes two plate-shaped electrodes and a resistor. A resistor is placed on the two electrodes. For example, a chip resistor is disclosed in Patent Document 1.

JP 2007-142148 A

In conventional chip resistors, it is necessary to maintain the strength of the chip resistor itself, so the plate-shaped electrodes cannot be made too thin. Therefore, conventional chip resistors cannot be made thinner. Further, conventionally, there has been a demand for improved heat dissipation of chip resistors.

The present invention has been conceived under the circumstances described above, and its main object is to provide a chip resistor that can be made thinner. SUMMARY OF THE INVENTION The present invention has been conceived under the circumstances described above, and a main object of the present invention is to provide a chip resistor capable of improving heat radiation.

According to a first aspect of the present invention, an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, a first electrode electrically connected to the resistor, the first electrode A chip resistor is provided, comprising one electrode and a second electrode positioned in a second direction opposite to a first direction perpendicular to the thickness direction of the substrate.

Preferably, the substrate has a substrate surface and a substrate main surface facing opposite sides in a thickness direction of the substrate, and the resistor extends from the substrate surface toward the substrate main surface. I'm entangled.

Preferably, the entirety of the resistor overlaps the substrate in the thickness direction of the substrate.

Preferably, the substrate is in direct contact with the resistor.

Preferably, the substrate includes a resin portion and a glass fiber portion located within the resin portion, and the resistor is in direct contact with the glass fiber portion.

Preferably, the resin portion is made of epoxy resin.

Preferably, the resin portion constitutes the substrate surface and the substrate main surface.

Preferably, the maximum thickness of said substrate is between 60 and 300 μm.

Preferably, the substrate has a substrate side surface facing the first direction, and the resistor includes:
It has a resistor side surface facing the first direction, and the substrate side surface and the resistor side surface are flush with each other.

Preferably, the side surface of the substrate is directly covered with the first electrode.

Preferably, the resistor has a resistor surface and a resistor main surface facing opposite sides, and the resistor main surface is in direct contact with the substrate.

Preferably, the resistor surface is flush with the substrate surface.

Preferably, the thickness of the resistor is 50-200 μm.

Preferably, an insulating layer covering the resistor is further provided.

Preferably, the insulating layer has an insulating layer surface and an insulating layer main surface facing opposite sides in a thickness direction of the substrate, and the insulating layer main surface is in direct contact with the substrate and the resistor. there is

Preferably, the insulating layer has a portion interposed between the resistor and the first electrode and a portion interposed between the resistor and the second electrode.

Preferably, the first electrode and the second electrode are formed on the insulating layer surface.

Preferably, a portion of the insulating layer surface is exposed from the first electrode and the second electrode.

Preferably, the insulating layer has a thermal conductivity of 1.0 W/(m·K) to 5.0 W/(m·K).

Preferably, the insulating layer has an insulating layer end face, the substrate has a substrate end face, and both the substrate end face and the insulating layer end face are oriented in either the thickness direction of the substrate or the first direction. , and are flush with each other.

Preferably, the first electrode includes a plated layer formed by plating.

Preferably, the plated layer has a Cu layer and an Sn layer, and the Cu layer is interposed between the Sn layer and the resistor.

Preferably, the plated layer has a Ni layer, and the Ni layer is interposed between the Cu layer and the Sn layer.

Preferably, the first electrode includes an underlying layer in direct contact with the resistor, and the underlying layer is interposed between the plated layer and the resistor.

Preferably, the underlying layer overlaps the resistor when viewed in the thickness direction of the substrate and has a portion spaced apart from the resistor in the thickness direction.

Preferably, the underlayer has a thickness of 100 to 500 nm.

Preferably, the underlayer is formed by PVD, CVD, or printing.

Preferably, the underlayer is formed by sputtering.

Preferably, the underlying layer is made of Ni--Cr.

Preferably, the resistor is serpentine-shaped.

Preferably, the resistor is made of manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, or Fe--Cr alloy.

According to a second aspect of the present invention, a resistor, an insulating layer covering the resistor, a first electrode electrically connected to the resistor, and a first electrode electrically connected to the resistor and connected to the first electrode a second electrode positioned in a second direction opposite to the first direction, the first electrode including a base layer in direct contact with the resistor and a plated layer covering the base layer; A chip resistor is provided, wherein the insulating layer is interposed between the underlying layer and the resistor.

Preferably, the underlying layer is interposed between the plated layer and the insulating layer.

Preferably, the dimension of the underlayer in the first direction is one fourth or more of the dimension of the resistor in the first direction.

Preferably, the dimension of the underlayer in the first direction is one third or more of the dimension of the resistor in the first direction.

Preferably, the underlayer has a dimension in the first direction of 600 to 3200 μm.

Preferably, the thickness of the underlying layer is thinner than the thickness of the resistor.

Preferably, the underlayer has a thickness of 100 to 500 nm.

Preferably, the underlayer is formed by PVD, CVD, or printing.

Preferably, the underlayer is formed by sputtering.

Preferably, the underlayer is made of Ni--Cr.

Preferably, the plated layer is in direct contact with the insulating layer.

Preferably, the plated layer is in direct contact with a portion of the insulating layer located on the second direction side of the underlying layer.

Preferably, the plated layer has a Cu layer and an Sn layer, and the Cu layer is interposed between the Sn layer and the resistor.

Preferably, the plated layer has a Ni layer, and the Ni layer is interposed between the Cu layer and the Sn layer.

Preferably, the resistor has a first resistor side surface facing the first direction, the underlayer has a first underlayer side surface facing the first direction, and the first resistor side surface is , is flush with the side surface of the first underlayer.

Preferably, the side surface of the first resistor and the side surface of the first underlying layer are covered with the plated layer.

Preferably, the resistor has a resistor surface and a resistor main surface facing opposite sides, and the resistor surface is in direct contact with the insulating layer.

Preferably, the insulating layer has an insulating layer surface and an insulating layer main surface facing opposite sides, and the insulating layer surface is in direct contact with the underlying layer.

Preferably, the insulating layer has a portion interposed between the resistor and the first electrode and a portion interposed between the resistor and the second electrode.

Preferably, the first electrode and the second electrode are formed on the insulating layer surface.

Preferably, a portion of the insulating layer surface is exposed from the first electrode and the second electrode.

Preferably, the insulating layer has a thermal conductivity of 1.0 W/(m·K) to 5.0 W/(m·K).

Preferably, it further comprises a substrate on which the resistor is arranged.

Preferably, the substrate is made of an insulating material.

Preferably, the substrate has a substrate end face, the insulating layer has an insulating layer end face, and both the substrate end face and the insulating layer end face are oriented in either the thickness direction of the substrate or the first direction. , and are flush with each other.

Preferably, the substrate has a substrate surface and a substrate main surface facing opposite sides, the resistor is arranged on the substrate surface side, and the substrate main surface is exposed.

Preferably, the thermal conductivity of the material forming the insulating layer is higher than the thermal conductivity of the material forming the substrate.

Preferably, a bonding layer interposed between the substrate and the resistor is further provided.

Preferably, the bonding layer is made of an epoxy-based material.

Preferably, the resistor is serpentine-shaped.

Preferably, the resistor is made of manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, or Fe--Cr alloy.

According to a third aspect of the present invention, a chip resistor provided by the first aspect or the second aspect of the present invention, a mounting board on which the chip resistor is mounted, the mounting board and the chip resistor and a conductive joint interposed between the chip resistor and the chip resistor.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a cross-sectional view of a chip resistor mounting structure according to a first embodiment of the present invention; FIG. FIG. 2 is a view (partially transparent) of the chip resistor along line II-II in FIG. 1; FIG. 3 is a cross-sectional view of the chip resistor along line III-III of FIGS. 1 and 2; FIG. 3 is a cross-sectional view of the chip resistor taken along line IV-IV of FIGS. 1 and 2; FIG. 3 is a view (partially transparent) in which a first plated layer and a second plated layer are omitted from FIG. 2 ; 2 is a right side view (partially transparent) of the chip resistor shown in FIG. 1. FIG. 2 is a left side view (partially transparent) of the chip resistor shown in FIG. 1; FIG. FIG. 2 is a front view of the chip resistor shown in FIG. 1; 2 is a rear view of the chip resistor shown in FIG. 1; FIG. FIG. 2 is a plan view showing a step in the method of manufacturing the chip resistor shown in FIG. 1; 11 is a cross-sectional view along line XI-XI of FIG. 10; FIG. FIG. 11 is a back view showing a step following FIG. 10; FIG. 13 is a cross-sectional view along line XIII-XIII of FIG. 12; FIG. 13 is a back view showing a step following FIG. 12; FIG. 15 is a cross-sectional view along line XV-XV of FIG. 14; FIG. 15 is a back view showing a step following FIG. 14; FIG. 17 is a cross-sectional view along line XVII-XVII of FIG. 16; It is a sectional view showing the 1st modification of a 1st embodiment of the present invention. It is a sectional view showing the 2nd modification of a 1st embodiment of the present invention. FIG. 5 is a cross-sectional view of a chip resistor mounting structure according to a second embodiment of the present invention; 21 is a view (partially transparent) of the chip resistor along line XXI-XXI in FIG. 20; FIG. FIG. 22 is a cross-sectional view of the chip resistor along line XXII-XXII of FIGS. 20 and 21; FIG. 22 is a cross-sectional view of the chip resistor along line XXIII-XXIII of FIGS. 20 and 21; FIG. 22 is a view (partially transparent) in which the first plated layer and the second plated layer are omitted from FIG. 21; 21 is a right side view (partially transparent) of the chip resistor shown in FIG. 20; FIG. 21 is a left side view (partially transparent) of the chip resistor shown in FIG. 20; FIG. 21 is a front view of the chip resistor shown in FIG. 20; FIG. 21 is a rear view of the chip resistor shown in FIG. 20; FIG. FIG. 21 is a cross-sectional view showing a step in the manufacturing method of the chip resistor shown in FIG. 20; FIG. 30 is a plan view showing a step following FIG. 29; FIG. 31 is a cross-sectional view taken along line XXXI-XXXI of FIG. 30; FIG. 31 is a back view showing a step following FIG. 30; FIG. 33 is a cross-sectional view along line XXXIII-XXXIII of FIG. 32; FIG. 33 is a back view showing a step following FIG. 32; FIG. 35 is a cross-sectional view along line XXXV-XXXV of FIG. 34; FIG. 35 is a back view showing a step following FIG. 34; FIG. 37 is a cross-sectional view along line XXXVII-XXXVII of FIG. 36; It is a sectional view showing the 1st modification of a 2nd embodiment of the present invention. It is a sectional view showing the 2nd modification of a 2nd embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

<First Embodiment>
A first embodiment of the present invention will be described with reference to FIGS. 1 to 19. FIG.

FIG. 1 is a cross-sectional view of a chip resistor mounting structure according to a first embodiment of the present invention.

A chip resistor mounting structure 891 shown in FIG.

Mounting board 893 is, for example, a printed wiring board. The mounting substrate 893 includes, for example, an insulating substrate and pattern electrodes (not shown) formed on the insulating substrate. The insulating substrate is, for example, a glass epoxy resin substrate. Chip resistor 100 is mounted on mounting substrate 893 . A conductive joint 895 is interposed between the chip resistor 100 and the mounting board 893 . The conductive joint 895 joins the chip resistor 100 and the mounting board 893 . Conductive joint 895 is made of solder, for example.

FIG. 2 is a view (partially transparent) of the chip resistor along line II-II in FIG. FIG. 3 is a cross-sectional view of the chip resistor along line III-III of FIGS. 1 and 2. FIG. FIG. 4 is a cross-sectional view of the chip resistor taken along line IV-IV of FIGS. 1 and 2. FIG. FIG. 5 is a view (partially transparent) in which the first plated layer and the second plated layer are omitted from FIG. FIG. 6 is a right side view (partially transparent) of the chip resistor shown in FIG. FIG. 7 is a left side view (partially transparent) of the chip resistor shown in FIG. 8 is a front view of the chip resistor shown in FIG. 1. FIG. 9 is a rear view of the chip resistor shown in FIG. 1. FIG.

A chip resistor 100 shown in these figures comprises a substrate 1 , a resistor 2 , a first electrode 4 , a second electrode 5 and an insulating layer 6 .

The substrate 1 is plate-shaped. Substrate 1 is either insulating or conductive. When the substrate 1 is insulating, the material forming the substrate 1 includes, for example, resin or ceramic. When the material forming substrate 1 contains resin, the resin forming substrate 1 is, for example, an epoxy resin. When the material constituting the substrate 1 contains ceramics, such ceramics include, for example, Al2O3, AlN, and SiC. If the substrate 1 is conductive, the material forming the substrate 1 is, for example, Cu or Ag. In this embodiment, the substrate 1 is a glass epoxy resin substrate.

The substrate 1 has a substrate surface 11 , a substrate main surface 12 , a first substrate side surface 13 , a second substrate side surface 14 , a first substrate end surface 15 and a second substrate end surface 16 .

The substrate surface 11, the substrate main surface 12, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, and the second substrate end surface 16 are all flat. As shown in FIG. 1, the vertical direction in the figure is defined as the thickness direction Z1 of the substrate 1. As shown in FIG. Then, as shown in FIG. 2, the right direction in the figure is defined as a first direction X1, the left direction is defined as a second direction X2, the upward direction is defined as a third direction X3, and the downward direction is defined as a fourth direction X4. The maximum thickness of substrate 1 (maximum dimension in thickness direction Z1) is, for example, 60 to 300 μm. The thickness direction Z1 is orthogonal to the first direction X1, the second direction X2, the third direction X3, and the fourth direction X4. Also, the first direction X1 and the second direction X2 are orthogonal to the third direction X3 and the fourth direction X4, respectively.

The dimension of the chip resistor 100 in the first direction X1 is, for example, 5 to 10 mm, and the dimension of the chip resistor 100 in the third direction X3 is, for example, 2 to 10 mm.

The substrate surface 11 and the substrate main surface 12 face opposite to each other. The first substrate side surface 13 faces the first direction X1. The second substrate side surface 14 faces the second direction X2. That is, the first substrate side surface 13 and the second substrate side surface 14 face opposite to each other. The first substrate end face 15 faces the third direction X3. The second substrate end surface 16 faces the fourth direction X4. That is, the first substrate end face 15 and the second substrate end face 16 face opposite sides.

As described above, in this embodiment, the substrate 1 is a glass epoxy resin substrate. Therefore, substrate 1 includes glass fiber portion 191 and resin portion 192 .

The resin portion 192 defines the contour shape of the substrate 1 . Resin portion 192 is made of, for example, epoxy resin. The resin portion 192 constitutes the substrate surface 11 and the substrate main surface 12 .

The glass fiber portion 191 is made of glass fiber. Specifically, the glass fiber portion 191 is formed by stacking cloths made of glass fiber. The glass fiber portion 191 constitutes part of the first substrate side surface 13 , part of the second substrate side surface 14 , part of the first substrate end surface 15 , and part of the second substrate end surface 16 .

Unlike this embodiment, the substrate 1 may not be a glass epoxy resin substrate. In this case, the substrate 1 does not contain the glass fiber portion 191 .

As shown in FIG. 1, resistor 2 is arranged on substrate 1 . Specifically, the resistor 2 is arranged on the substrate surface 11 side of the substrate 1 . The thickness (dimension in the thickness direction Z1 direction) of resistor 2 is, for example, 50 to 200 μm. In this embodiment, the resistor 2 has a serpentine shape when viewed in the thickness direction Z1. The serpentine shape of the resistor 2 is preferable in that the resistance value of the resistor 2 can be increased. Unlike the present embodiment, the resistor 2 may be strip-shaped, for example, extending in the X1-X2 direction instead of being serpentine-shaped. The resistor 2 is made of a metallic resistance material such as manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, and Fe--Cr alloy, for example.

As shown in FIGS. 1 and 3 , the resistor 2 has a resistor surface 21 , a resistor main surface 22 , a first resistor side surface 23 and a second resistor side surface 24 . The resistor surface 21, the resistor main surface 22, the first resistor side surface 23, and the second resistor side surface 24 are all flat.

Resistor surface 21 and resistor main surface 22 face opposite to each other. The resistor surface 21 faces in the same direction as the substrate surface 11 (that is, downward in FIG. 1). On the other hand, the resistor main surface 22 faces the same direction as the substrate main surface 12 (that is, upward in FIG. 1). Resistor main surface 22 faces substrate 1 . The first resistor side surface 23 faces the first direction X1. In this embodiment, the first resistor side surface 23 is flush with the first substrate side surface 13 . The second resistor side surface 24 faces the second direction X2. In this embodiment, the second resistor side surface 24 is flush with the second substrate side surface 14 .

In this embodiment, resistor 2 is embedded in substrate 1 . Specifically, the chip resistor 100 has the configuration described below.

The resistor 2 is recessed into the substrate 1 from the substrate surface 11 toward the substrate principal surface 12 from the substrate surface 11 . The entire resistor 2 overlaps the substrate 1 in the thickness direction Z1. Resistor 2 is in direct contact with substrate 1 . Furthermore, in this embodiment in which the substrate 1 is a glass epoxy resin substrate, the resistor 2 is in direct contact with the glass fiber portion 191 of the substrate 1 .

The resistor surface 21 is flush with the substrate surface 11 of the substrate 1 . This is suitable for forming an insulating layer 6 described later on the resistor surface 21 and the substrate surface 11 . Resistor main surface 22 is in direct contact with substrate 1 . Furthermore, in this embodiment in which the substrate 1 is a glass epoxy resin substrate, the resistor main surface 22 is in direct contact with the glass fiber portion 191 of the substrate 1 .

Unlike this embodiment, the resistor 2 and the substrate 1 do not have to be in direct contact. For example, resistor 2 may be embedded in substrate 1 with a bonding layer interposed between resistor 2 and substrate 1 . The resistor 2 does not have to be in direct contact with the glass fiber portion 191 .

An insulating layer 6 covers the resistor 2 . Insulating layer 6 is in direct contact with resistor 2 and substrate 1 . The insulating layer 6 is in direct contact with the resistor surface 21 of the resistor 2 and the substrate surface 11 of the substrate 1 . The insulating layer 6 exposes a portion of the resistor 2 on the first direction X1 side and a portion of the resistor 2 on the second direction X2 side. Insulating layer 6 is made of, for example, a thermosetting material. The dimension of the insulating layer 6 in the third direction X3 is the same as the dimension of the substrate 1 in the third direction X3. The maximum thickness (maximum dimension in thickness direction Z1) of insulating layer 6 is, for example, 20 to 60 μm. Insulating layer 6 is made of resin, for example. Since the insulating layer 6 facilitates the dissipation of heat generated by the resistor 2 to the outside of the chip resistor 100, it is preferable to use a material having a high thermal conductivity as the material forming the insulating layer 6. FIG. The thermal conductivity of the insulating layer 6 is preferably higher than the thermal conductivity of the material forming the substrate 1 (the material forming the resin portion 192 in this embodiment). The thermal conductivity of insulating layer 6 is preferably, for example, 1.0 W/(m·K) to 5.0 W/(m·K).

The insulating layer 6 includes an insulating layer surface 61, an insulating layer main surface 62, a first insulating layer side surface 63, a second insulating layer side surface 64, a first insulating layer end surface 65, a second insulating layer end surface 66, have

Insulating layer surface 61 and insulating layer main surface 62 face opposite to each other. The insulating layer surface 61 faces the same direction as the resistor surface 21 (that is, downward in FIG. 1). A first electrode 4 and a second electrode 5 are formed on the insulating layer surface 61 . A portion of the insulating layer surface 61 (a region of the insulating layer surface 61 sandwiched between the first electrode 4 and the second electrode 5 ) is exposed from the first electrode 4 and the second electrode 5 . The insulating layer main surface 62 faces the same direction as the resistor main surface 22 (that is, upward in FIG. 1). In this embodiment, the insulating layer main surface 62 is in direct contact with the resistor 2 and the substrate 1 . Specifically, the insulating layer main surface 62 is in direct contact with the resistor surface 21 and the substrate surface 11 . The first insulating layer side surface 63 faces the first direction X1. The second insulating layer side surface 64 faces the second direction X2. The first insulating layer end surface 65 faces the third direction X3. In this embodiment, the first insulating layer end surface 65 is flush with the first substrate end surface 15 . The second insulating layer end surface 66 faces the fourth direction X4. The second insulating layer end surface 66 is flush with the second substrate end surface 16 .

The first electrode 4 is electrically connected to the resistor 2 . The first electrode 4 is for supplying power from the mounting substrate 893 on which the chip resistor 100 is mounted to the resistor 2 . The first electrode 4 is in direct contact with the resistor 2 . In this embodiment, the first electrode 4 is in direct contact with the resistor surface 21 of the resistor 2 . Further, in this embodiment, the first electrode 4 covers the first resistor side surface 23 of the resistor 2 and the insulating layer 6 . In this embodiment, an insulating layer 6 is interposed between the first electrode 4 and the resistor 2 . Further, in this embodiment, the first electrode 4 does not cover the main surface 12 side of the substrate. Unlike the present embodiment, the first electrode 4 may cover the main surface 12 of the substrate. As shown in FIG. 1 , in the mounting structure 891 , the first electrode 4 is in direct contact with the conductive joint 895 and is connected to the wiring pattern (not shown) on the mounting substrate 893 via the conductive joint 895 . Conducting.

The first electrode 4 includes a first underlying layer 41 and a first plated layer 43 .

The first underlayer 41 is in direct contact with the resistor 2 . In this embodiment, the first base layer 41 is formed to form the first plated layer 43 on the insulating layer 6 by plating. The first underlayer 41 is in direct contact with the portion of the resistor surface 21 exposed from the insulating layer 6 . The first underlayer 41 overlaps the resistor 2 when viewed in the thickness direction Z1 of the substrate 1 . Also, the first underlayer 41 has a portion spaced apart from the resistor 2 in the thickness direction Z1. An insulating layer 6 is interposed between the first base layer 41 and the resistor 2 . The first base layer 41 is interposed between the first plated layer 43 and the insulating layer 6 . In this embodiment, it is preferable that the dimension of the first underlayer 41 in the first direction X1 is large. Preferably, the dimension of the first underlayer 41 in the first direction X1 is a quarter or more of the dimension of the resistor 2 in the first direction X1, and more preferably the dimension of the resistor 2 in the first direction X1. is more than one-third of The dimension of the first underlayer 41 in the first direction X1 is, for example, 600 to 3200 μm. The thickness of the first underlayer 41 is thinner than the thickness of the resistor 2 . The first underlayer 41 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the first underlayer 41 is formed by sputtering of PVD. The thickness of the first underlayer 41 is, for example, 100-500 nm. First underlayer 41 contains, for example, Ni or Cr.

The first underlayer 41 has a first underlayer side surface 413 . The first underlayer side surface 413 faces the first direction X1. In this embodiment, the first base layer side surface 413 is flush with the first substrate side surface 13 and the first resistor side surface 23 .

The first plated layer 43 directly covers the first base layer 41 . A first plated layer 43 is formed on the resistor 2 . The first plated layer 43 is in direct contact with the insulating layer 6 . The first plated layer 43 is in direct contact with a portion of the insulating layer 6 located on the second direction X2 side of the first base layer 41 . In the chip resistor 100 before being mounted on the mounting board 893, the first plated layer 43 is exposed to the outside. Therefore, as shown in FIG. 1, in the mounting structure 891, the first plated layer 43 is in direct contact with the conductive joint 895, and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895. abbreviated). In addition, in this embodiment, the first plated layer 43 covers the first resistor side surface 23 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895 .

Specifically, in the present embodiment, the first plated layer 43 has a Cu layer 43a, a Ni layer 43b, and an Sn layer 43c. The Cu layer 43 a directly covers the first underlayer 41 . The Ni layer 43b directly covers the Cu layer 43a. The Sn layer 43c directly covers the Ni layer 43b. The Sn layer 43c is exposed to the outside. In the mounting structure 891 of the chip resistor 100, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 43c. The thickness of the Cu layer 43a is, for example, 10 to 50 μm, the thickness of the Ni layer 43b is, for example, 1 to 10 μm, and the thickness of the Sn layer 43c is, for example, 1 to 10 μm. Unlike this embodiment, the first plated layer 43 may not include the Ni layer 43b.

The second electrode 5 is located on the second direction X2 side with respect to the first electrode 4 . A second electrode 5 is electrically connected to the resistor 2 . The second electrode 5 is for supplying power from the mounting substrate 893 on which the chip resistor 100 is mounted to the resistor 2 . The second electrode 5 is in direct contact with the resistor 2 . In this embodiment, the second electrode 5 is in direct contact with the resistor surface 21 of the resistor 2 . Further, in this embodiment, the second electrode 5 covers the second resistor side surface 24 of the resistor 2 and the insulating layer 6 . In this embodiment, an insulating layer 6 is interposed between the second electrode 5 and the resistor 2 . Further, in this embodiment, the second electrode 5 does not cover the main surface 12 side of the substrate. Unlike the present embodiment, the second electrode 5 may cover the main surface 12 of the substrate. As shown in FIG. 1 , in the mounting structure 891 , the second electrode 5 is in direct contact with the conductive joint 895 and is connected to the wiring pattern (not shown) on the mounting substrate 893 via the conductive joint 895 . Conducting.

The second electrode 5 includes a second underlying layer 51 and a second plated layer 53 .

The second underlayer 51 is in direct contact with the resistor 2 . In this embodiment, the second base layer 51 is formed to form the second plated layer 53 on the insulating layer 6 by plating. The second underlayer 51 is in direct contact with the portion of the resistor surface 21 exposed from the insulating layer 6 . An insulating layer 6 is interposed between the second base layer 51 and the resistor 2 . The second base layer 51 is interposed between the second plated layer 53 and the insulating layer 6 . In the present embodiment, it is preferable that the dimension of the second underlayer 51 in the second direction X2 is large. Preferably, the dimension of the second underlayer 51 in the second direction X2 is 1/4 or more of the dimension of the resistor 2 in the second direction X2, and more preferably the dimension of the resistor 2 in the second direction X2. is more than one-third of The dimension of the second underlayer 51 in the second direction X2 is, for example, 600 to 3200 μm. The thickness of the second underlayer 51 is thinner than the thickness of the resistor 2 . The second underlayer 51 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the second underlayer 51 is formed by sputtering of PVD. The thickness of the second underlayer 51 is, for example, 0.5 to 1.0 nm. Second underlayer 51 contains, for example, Ni or Cr.

The second underlayer 51 has a second underlayer side surface 514 . The second underlayer side surface 514 faces the second direction X2. In this embodiment, the second underlayer side surface 514 is flush with the second substrate side surface 14 and the second resistor side surface 24 .

The second plated layer 53 directly covers the second base layer 51 . A second plated layer 53 is formed on the resistor 2 . The second plated layer 53 is in direct contact with the insulating layer 6 . The second plated layer 53 is in direct contact with a portion of the insulating layer 6 located on the first direction X1 side of the second base layer 51 . In the chip resistor 100 before being mounted on the mounting board 893, the second plated layer 53 is exposed to the outside. Therefore, as shown in FIG. 1, in the mounting structure 891, the second plated layer 53 is in direct contact with the conductive joint 895, and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895. abbreviated). In this embodiment, the second plated layer 53 covers the second resistor side surface 24 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895 .

Specifically, in the present embodiment, the second plated layer 53 has a Cu layer 53a, a Ni layer 53b, and an Sn layer 53c. The Cu layer 53 a directly covers the second underlayer 51 . The Ni layer 53b directly covers the Cu layer 53a. The Sn layer 53c directly covers the Ni layer 53b. The Sn layer 53c is exposed to the outside. In the mounting structure 891 of the chip resistor 100, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 53c. The thickness of the Cu layer 53a is, for example, 10 to 50 μm, the thickness of the Ni layer 53b is, for example, 1 to 10 μm, and the thickness of the Sn layer 53c is, for example, 1 to 10 μm. Unlike this embodiment, the second plated layer 53 may not include the Ni layer 53b.

Next, a method for manufacturing the chip resistor 100 will be briefly described.

First, as shown in FIGS. 10 and 11, a set sheet 850 is prepared. Assembled sheet 850 includes substrate sheet 810 and resistor assembly 820 . In this embodiment, the aggregate sheet 850 is formed in a state in which the resistor aggregates 820 are embedded in the substrate sheet 810 . Collective sheet 850 is formed using, for example, a vacuum press. In assembly sheet 850 , resistor assembly 820 is completely fixed to substrate sheet 810 .

The substrate sheet 810 is to be the substrate 1 described above. The resistor assembly 820 becomes the resistor 2 described above. Therefore, in the collective sheet 850 , the resistor aggregates 820 are in direct contact with the glass fiber portion 191 .

Also, the resistor assembly 820 has a plurality of portions to be the resistor 2 described above. In this embodiment, in order to form the serpentine-shaped resistor 2, a plurality of serpentine-shaped portions are previously formed in the resistor assembly 820 by etching or punching.

Next, the resistance value of the resistor 2 in the resistor assembly 820 is adjusted. Adjustment of the resistance value of the resistor 2 is performed by grinding the resistor assembly 820, for example.

Next, as shown in FIGS. 12 and 13, an insulating film 860 is formed. The insulating film 860 becomes the insulating layer 6 described above. The insulating film 860 is formed in a plurality of stripes extending along one direction. The insulating film 860 is formed by printing or coating, for example. A portion of the resistor assembly 820 is exposed from the insulating film 860 .

Next, as shown in FIGS. 14 and 15, a conductive material 840 is layered on the resistor assembly 820 . The conductive material 840 becomes the first underlayer 41 or the second underlayer 51 described above. The step of laminating the conductive material 840 uses PVD or CVD, and the PVD used for laminating the conductive material 840 includes, for example, sputtering. In this embodiment, in the step of laminating the conductive material 840 , the conductive material 840 is laminated along the extending direction of the insulating film 860 so as to form a belt shape. Therefore, part of the insulating film 860 is exposed from the laminated conductive material 840 . In order to stack the conductive material 840 in a strip shape, for example, masking may be performed. Conductive material 840 is, for example, Ni or Cr.

Next, as shown in FIGS. 16 and 17, a plurality of solid pieces 886 are obtained by cutting the resistor assembly 820 . In this embodiment, the assembly sheet 850 (resistor assembly 820 and substrate sheet 810) is cut together. A solid piece 886 is obtained, for example, by punching or dicing. In this embodiment, punching is performed to obtain solid pieces 886 .

By cutting when obtaining the solid piece 886, the above-described first substrate side surface 13, second substrate side surface 14, first substrate end surface 15, second substrate end surface 16, first resistor side surface 23, second resistor side surface 24, A first underlayer side surface 413, a second underlayer side surface 514, a first insulating layer end surface 65, and a second insulating layer end surface 66 are formed. By simultaneously cutting the substrate sheet 810, the resistor assembly 820, and the like, the first substrate side surface 13, the first resistor side surface 23, and the first base layer side surface 413 are flush with each other. Similarly, by simultaneously cutting the substrate sheet 810, the resistor assembly 820, and the like, the second substrate side surface 14, the second resistor side surface 24, and the second base layer side surface 514 are flush with each other. Become. Similarly, this cutting makes the first substrate end surface 15 and the first insulating layer end surface 65 flush with each other. Similarly, this cutting makes the second substrate end surface 16 and the second insulating layer end surface 66 flush with each other.

Next, on the solid piece 886, the first plated layer 43 (Cu layer 43a, Ni layer 43b, and Sn layer 43c) and the second plated layer 53 (Cu layer 53a, Ni layer 53b, and A Sn layer 53c) is formed. Barrel plating, for example, is used to form the first plating layer 43 and the second plating layer 53 . Through the above steps, the manufacture of the chip resistor 100 is completed.

Next, the effects of this embodiment will be described.

In this embodiment, resistor 2 is embedded in substrate 1 . According to such a configuration, it is possible to reduce the overall dimension of the assembly of the substrate 1 and the resistor 2 in the thickness direction Z1 of the substrate 1 . As a result, the thickness of the chip resistor 100 can be reduced.

Also, when manufacturing the chip resistor 100, an assembly sheet 850 in which the resistor assembly 820 is embedded in the substrate sheet 810 can be used. Therefore, in order to manufacture the chip resistor 100, it is sufficient to prepare the assembly sheet 850, and the trouble of attaching the resistor assembly 820 to the substrate sheet 810 can be reduced. This contributes to efficiency in manufacturing the chip resistor 100 .

In this embodiment, the thermal conductivity of the insulating layer 6 is 1.0 W/(m·K) to 5.0 W/(m·K), which is relatively high. With such a configuration, the heat generated by the resistor 2 can be easily released to the outside of the chip resistor 100 via the insulating layer 6 . Therefore, it is possible to prevent the chip resistor 100 from becoming excessively hot.

In this embodiment, the first electrode 4 includes a first base layer 41 directly contacting the resistor 2 and a first plated layer 43 covering the first base layer 41 . The insulating layer 6 is interposed between the first base layer 41 and the resistor 2 . With such a configuration, it is easy to form the first plated layer 43 on the insulating layer 6 . Therefore, the area of the first electrode 4 can be increased. If the area of the first electrode 4 can be increased, the heat generated by the resistor 2 can be easily released to the mounting board 893 via the first electrode 4 . That is, it is possible to improve the heat dissipation of the chip resistor 100 .

In this embodiment, the substrate 1 is made of an insulating material. In such a configuration, there is no need to use a relatively thick Cu electrode. Therefore, the labor for processing the Cu electrode can be reduced. This contributes to efficiency in manufacturing the chip resistor 100 .

In this embodiment, both the substrate 1 and the mounting substrate 893 are glass epoxy resin substrates. In such a configuration, the thermal expansion coefficients of each of substrate 1 and mounting substrate 893 are approximately the same. Therefore, even if the substrate 1 thermally expands during use of the chip resistor 100, it is considered that the mounting substrate 893 also thermally expands at the same rate. Therefore, it is possible to prevent problems (for example, breakage of the chip resistor 100) that may occur due to the effects of thermal expansion during use of the chip resistor 100. FIG.

<First Modification of First Embodiment>
A first modification of the first embodiment of the present invention will be described with reference to FIG.

FIG. 18 is a cross-sectional view showing a first modification of the first embodiment of the invention.

A chip resistor 101 shown in FIG. Mainly different. Other points are the same as those of the chip resistor 100, so description thereof will be omitted.

The chip resistor 101 also has the same effects as those described for the chip resistor 100 .

<Second Modification of First Embodiment>
A second modification of the first embodiment of the present invention will be described with reference to FIG.

FIG. 19 is a cross-sectional view showing a second modification of the first embodiment of the invention.

The chip resistor 102 shown in FIG. The main difference from the chip resistor 100 is that it is flush with the second base layer side surface 514 of the second base layer 51 . Other points are the same as those of the chip resistor 100, so description thereof will be omitted. In order to manufacture the chip resistor 102, a plated layer is formed prior to the step of cutting the assembly sheet 850 described with reference to FIGS.

The chip resistor 102 also has the same effects as those described with respect to the chip resistor 100 .

<Second embodiment>
A second embodiment of the present invention will be described with reference to FIGS. 20 to 39. FIG.

FIG. 20 is a cross-sectional view of a chip resistor mounting structure according to the second embodiment of the present invention.

A chip resistor mounting structure 892 shown in the figure includes a chip resistor 200 , a mounting substrate 893 , and a conductive joint 895 .

Since the description given in the first embodiment can be applied to the mounting substrate 893 and the conductive joint portion 895, the description thereof is omitted in the present embodiment.

21 is a view (partially transparent) of the chip resistor along line XXI-XXI of FIG. 20. FIG. 22 is a cross-sectional view of the chip resistor along line XXII-XXII of FIGS. 20 and 21. FIG. 23 is a cross-sectional view of the chip resistor along line XXIII-XXIII of FIGS. 20 and 21. FIG. FIG. 24 is a view (partially transparent) in which the first plated layer and the second plated layer are omitted from FIG. 25 is a right side view (partially transparent) of the chip resistor shown in FIG. 20. FIG. 26 is a left side view (partially transparent) of the chip resistor shown in FIG. 20. FIG. 27 is a front view of the chip resistor shown in FIG. 20. FIG. 28 is a rear view of the chip resistor shown in FIG. 20. FIG.

A chip resistor 200 shown in these figures includes a substrate 1 , a resistor 2 , a bonding layer 3 , a first electrode 4 , a second electrode 5 and an insulating layer 6 .

The substrate 1 is plate-shaped. Substrate 1 is either insulating or conductive. When the substrate 1 is insulating, the material forming the substrate 1 includes, for example, resin or ceramic. When the material forming substrate 1 contains resin, the resin forming substrate 1 is, for example, an epoxy resin. When the material constituting the substrate 1 contains ceramics, such ceramics include, for example, Al2O3, AlN, and SiC. If the substrate 1 is conductive, the material forming the substrate 1 is, for example, Cu or Ag. In this embodiment, the substrate 1 is a glass epoxy resin substrate.

The substrate 1 has a substrate surface 11 , a substrate main surface 12 , a first substrate side surface 13 , a second substrate side surface 14 , a first substrate end surface 15 and a second substrate end surface 16 .

The substrate surface 11, the substrate main surface 12, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, and the second substrate end surface 16 are all flat. As shown in FIG. 20, the vertical direction in the drawing is defined as the thickness direction Z1 of the substrate 1. As shown in FIG. Then, as shown in FIG. 21, the right direction in the figure is defined as a first direction X1, the left direction is defined as a second direction X2, the upward direction is defined as a third direction X3, and the downward direction is defined as a fourth direction X4. The maximum thickness of substrate 1 (maximum dimension in thickness direction Z1) is, for example, 60 to 300 μm. The thickness direction Z1 is orthogonal to the first direction X1, the second direction X2, the third direction X3, and the fourth direction X4. Also, the first direction X1 and the second direction X2 are orthogonal to the third direction X3 and the fourth direction X4, respectively.

The dimension of the chip resistor 200 in the first direction X1 is, for example, 5 to 10 mm, and the dimension of the chip resistor 200 in the third direction X3 is, for example, 2 to 10 mm.

The substrate surface 11 and the substrate main surface 12 face opposite to each other. The first substrate side surface 13 faces the first direction X1. The second substrate side surface 14 faces the second direction X2. That is, the first substrate side surface 13 and the second substrate side surface 14 face opposite to each other. The first substrate end surface 15 faces the third direction X3. The second substrate end surface 16 faces the fourth direction X4. That is, the first substrate end face 15 and the second substrate end face 16 face opposite sides.

As shown in FIG. 20, resistor 2 is arranged on substrate 1 . Specifically, the resistor 2 is arranged on the substrate surface 11 side of the substrate 1 . The thickness (dimension in the thickness direction Z1 direction) of resistor 2 is, for example, 50 to 200 μm. In this embodiment, the resistor 2 has a serpentine shape when viewed in the thickness direction Z1. The serpentine shape of the resistor 2 is preferable in that the resistance value of the resistor 2 can be increased. Unlike the present embodiment, the resistor 2 may be strip-shaped, for example, extending in the X1-X2 direction instead of being serpentine-shaped. The resistor 2 is made of a metallic resistance material such as manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, and Fe--Cr alloy, for example.

As shown in FIGS. 21 and 22 , the resistor 2 has a resistor surface 21 , a resistor main surface 22 , a first resistor side surface 23 and a second resistor side surface 24 . The resistor surface 21, the resistor main surface 22, the first resistor side surface 23, and the second resistor side surface 24 are all flat.

Resistor surface 21 and resistor main surface 22 face opposite to each other. The resistor surface 21 faces in the same direction as the substrate surface 11 (that is, downward in FIG. 20). On the other hand, the resistor main surface 22 faces the same direction as the substrate main surface 12 (that is, upward in FIG. 20). Resistor main surface 22 faces substrate 1 . The first resistor side surface 23 faces the first direction X1. In this embodiment, the first resistor side surface 23 is flush with the first substrate side surface 13 . The second resistor side surface 24 faces the second direction X2. In this embodiment, the second resistor side surface 24 is flush with the second substrate side surface 14 .

Bonding layer 3 is interposed between substrate 1 and resistor 2 . Specifically, the bonding layer 3 is interposed between the substrate surface 11 of the substrate 1 and the resistor 2 . The bonding layer 3 bonds the resistor 2 to the substrate surface 11 . The bonding layer 3 is preferably made of an insulating material. Such an insulating material includes an epoxy-based material. The thickness (dimension in the thickness direction Z1) of the bonding layer 3 is, for example, 30 to 100 μm. As shown in FIGS. 20 and 22, the bonding layer 3 covers the entire surface of the substrate surface 11 in this embodiment.

Unlike this embodiment, the bonding layer 3 may be formed only on a part of the substrate surface 11 . For example, the bonding layer 3 may be formed only on a region of the substrate surface 11 that overlaps the resistor 2 .

As shown in FIGS. 20 and 22, the bonding layer 3 has a bonding layer surface 31 and a bonding layer main surface 32 facing opposite sides. The bonding layer surface 31 faces the same direction as the substrate surface 11 (that is, downward in FIG. 20). The bonding layer surface 31 is in direct contact with the resistor 2 . The bonding layer main surface 32 is in direct contact with the substrate 1 .

An insulating layer 6 covers the resistor 2 . The insulating layer 6 is arranged on the resistor 2 and the substrate 1 with the bonding layer 3 interposed therebetween. The insulating layer 6 is in direct contact with the resistor surface 21 of the resistor 2 . The insulating layer 6 exposes a portion of the resistor 2 on the first direction X1 side and a portion of the resistor 2 on the second direction X2 side. Insulating layer 6 is made of, for example, a thermosetting material. The dimension of the insulating layer 6 in the third direction X3 is the same as the dimension of the substrate 1 in the third direction X3. The maximum thickness (maximum dimension in thickness direction Z1) of insulating layer 6 is, for example, 60 to 150 μm. Insulating layer 6 is made of resin, for example. Since the insulating layer 6 facilitates the dissipation of heat generated by the resistor 2 to the outside of the chip resistor 200, it is preferable to use a material having a high thermal conductivity as the material forming the insulating layer 6. FIG. The thermal conductivity of the insulating layer 6 is preferably higher than that of the material forming the substrate 1 . The thermal conductivity of insulating layer 6 is preferably, for example, 1.0 W/(m·K) to 5.0 W/(m·K).

The insulating layer 6 includes an insulating layer surface 61, an insulating layer main surface 62, a first insulating layer side surface 63, a second insulating layer side surface 64, a first insulating layer end surface 65, a second insulating layer end surface 66, have

Insulating layer surface 61 and insulating layer main surface 62 face opposite to each other. The insulating layer surface 61 faces the same direction as the resistor surface 21 (that is, downward in FIG. 20). A first electrode 4 and a second electrode 5 are formed on the insulating layer surface 61 . A portion of the insulating layer surface 61 (a region of the insulating layer surface 61 sandwiched between the first electrode 4 and the second electrode 5 ) is exposed from the first electrode 4 and the second electrode 5 . The insulating layer main surface 62 faces the same direction as the resistor main surface 22 (that is, upward in FIG. 20). In this embodiment, it is in direct contact with the bonding layer 3 . Specifically, the insulating layer main surface 62 is in direct contact with the bonding layer surface 31 . The first insulating layer side surface 63 faces the first direction X1. The second insulating layer side surface 64 faces the second direction X2. The first insulating layer end surface 65 faces the third direction X3. In this embodiment, the first insulating layer end surface 65 is flush with the first substrate end surface 15 . The second insulating layer end surface 66 faces the fourth direction X4. The second insulating layer end surface 66 is flush with the second substrate end surface 16 .

The first electrode 4 is electrically connected to the resistor 2 . The first electrode 4 is for supplying power from the mounting substrate 893 on which the chip resistor 200 is mounted to the resistor 2 . The first electrode 4 is in direct contact with the resistor 2 . In this embodiment, the first electrode 4 is in direct contact with the resistor surface 21 of the resistor 2 . Further, in this embodiment, the first electrode 4 covers the first resistor side surface 23 of the resistor 2 and the insulating layer 6 . In this embodiment, an insulating layer 6 is interposed between the first electrode 4 and the resistor 2 . Further, in this embodiment, the first electrode 4 does not cover the main surface 12 side of the substrate. Unlike the present embodiment, the first electrode 4 may cover the main surface 12 of the substrate. As shown in FIG. 20 , in the mounting structure 892 , the first electrode 4 is in direct contact with the conductive joint 895 and is connected to the wiring pattern (not shown) on the mounting substrate 893 via the conductive joint 895 . Conducting.

As shown in FIG. 20 , the first electrode 4 includes a first underlayer 41 and a first plated layer 43 .

The first underlayer 41 is in direct contact with the resistor 2 . In this embodiment, the first underlying layer 41 is formed to form the first plated layer 43 on the insulating layer 6 by plating. The first underlayer 41 is in direct contact with the portion of the resistor surface 21 exposed from the insulating layer 6 . The first underlayer 41 overlaps the resistor 2 when viewed in the thickness direction Z1 of the substrate 1 . Also, the first underlayer 41 has a portion spaced apart from the resistor 2 in the thickness direction Z1. An insulating layer 6 is interposed between the first base layer 41 and the resistor 2 . The first base layer 41 is interposed between the first plated layer 43 and the insulating layer 6 . In this embodiment, it is preferable that the dimension of the first underlayer 41 in the first direction X1 is large. Preferably, the dimension of the first underlayer 41 in the first direction X1 is a quarter or more of the dimension of the resistor 2 in the first direction X1, and more preferably the dimension of the resistor 2 in the first direction X1. is more than one-third of The dimension of the first underlayer 41 in the first direction X1 is, for example, 600 to 3200 μm. The thickness of the first underlayer 41 is thinner than the thickness of the resistor 2 . The first underlayer 41 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the first underlayer 41 is formed by sputtering of PVD. The thickness of first underlayer 41 is, for example, 0.5 to 1.0 nm. First underlayer 41 contains, for example, Ni or Cr.

The first underlayer 41 has a first underlayer side surface 413 . The first underlayer side surface 413 faces the first direction X1. In this embodiment, the first base layer side surface 413 is flush with the first substrate side surface 13 and the first resistor side surface 23 .

The first plated layer 43 directly covers the first base layer 41 . A first plated layer 43 is formed on the resistor 2 . The first plated layer 43 is in direct contact with the insulating layer 6 . The first plated layer 43 is in direct contact with a portion of the insulating layer 6 located on the second direction X2 side of the first base layer 41 . In the chip resistor 200 before being mounted on the mounting board 893, the first plated layer 43 is exposed to the outside. Therefore, as shown in FIG. 20, in the mounting structure 892, the first plated layer 43 is in direct contact with the conductive joint 895, and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895. abbreviated). In addition, in this embodiment, the first plated layer 43 covers the first resistor side surface 23 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895 .

Specifically, in the present embodiment, the first plated layer 43 has a Cu layer 43a, a Ni layer 43b, and an Sn layer 43c. The Cu layer 43 a directly covers the first underlayer 41 . The Ni layer 43b directly covers the Cu layer 43a. The Sn layer 43c directly covers the Ni layer 43b. The Sn layer 43c is exposed to the outside. In the mounting structure 892 of the chip resistor 200, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 43c. The thickness of the Cu layer 43a is, for example, 10 to 50 μm, the thickness of the Ni layer 43b is, for example, 1 to 10 μm, and the thickness of the Sn layer 43c is, for example, 1 to 10 μm. Unlike this embodiment, the first plated layer 43 may not include the Ni layer 43b.

The second electrode 5 is located on the second direction X2 side with respect to the first electrode 4 . A second electrode 5 is electrically connected to the resistor 2 . The second electrode 5 is for supplying power to the resistor 2 from the mounting board 893 on which the chip resistor 200 is mounted. The second electrode 5 is in direct contact with the resistor 2 . In this embodiment, the second electrode 5 is in direct contact with the resistor surface 21 of the resistor 2 . Further, in this embodiment, the second electrode 5 covers the second resistor side surface 24 of the resistor 2 and the insulating layer 6 . In this embodiment, an insulating layer 6 is interposed between the second electrode 5 and the resistor 2 . Further, in this embodiment, the second electrode 5 does not cover the main surface 12 side of the substrate. Unlike the present embodiment, the second electrode 5 may cover the main surface 12 of the substrate. As shown in FIG. 20 , in the mounting structure 892 , the second electrode 5 is in direct contact with the conductive joint 895 and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895 . Conducting.

As shown in FIG. 20 , the second electrode 5 includes a second underlying layer 51 and a second plated layer 53 .

The second underlayer 51 is in direct contact with the resistor 2 . In this embodiment, the second base layer 51 is formed to form the second plated layer 53 on the insulating layer 6 by plating. The second underlayer 51 is in direct contact with the portion of the resistor surface 21 exposed from the insulating layer 6 . An insulating layer 6 is interposed between the second base layer 51 and the resistor 2 . The second base layer 51 is interposed between the second plated layer 53 and the insulating layer 6 . In the present embodiment, it is preferable that the dimension of the second underlayer 51 in the second direction X2 is large. Preferably, the dimension of the second underlayer 51 in the second direction X2 is 1/4 or more of the dimension of the resistor 2 in the second direction X2, and more preferably the dimension of the resistor 2 in the second direction X2. is more than one-third of The dimension of the second underlayer 51 in the second direction X2 is, for example, 600 to 3200 μm. The thickness of the second underlayer 51 is thinner than the thickness of the resistor 2 . The second underlayer 51 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the second underlayer 51 is formed by sputtering of PVD. The thickness of the second underlayer 51 is, for example, 0.5 to 1.0 nm. Second underlayer 51 contains, for example, Ni or Cr.

The second underlayer 51 has a second underlayer side surface 514 . The second underlayer side surface 514 faces the second direction X2. In this embodiment, the second underlayer side surface 514 is flush with the second substrate side surface 14 and the second resistor side surface 24 .

The second plated layer 53 directly covers the second base layer 51 . A second plated layer 53 is formed on the resistor 2 . The second plated layer 53 is in direct contact with the insulating layer 6 . The second plated layer 53 is in direct contact with a portion of the insulating layer 6 located on the first direction X1 side of the second base layer 51 . In the chip resistor 200 before being mounted on the mounting board 893, the second plated layer 53 is exposed to the outside. Therefore, as shown in FIG. 20, in the mounting structure 892, the second plated layer 53 is in direct contact with the conductive joint 895, and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895. abbreviated). In this embodiment, the second plated layer 53 covers the second resistor side surface 24 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895 .

Specifically, in the present embodiment, the second plated layer 53 has a Cu layer 53a, a Ni layer 53b, and an Sn layer 53c. The Cu layer 53 a directly covers the second underlayer 51 . The Ni layer 53b directly covers the Cu layer 53a. The Sn layer 53c directly covers the Ni layer 53b. The Sn layer 53c is exposed to the outside. In the mounting structure 892 of the chip resistor 200, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 53c. The thickness of the Cu layer 53a is, for example, 10 to 50 μm, the thickness of the Ni layer 53b is, for example, 1 to 10 μm, and the thickness of the Sn layer 53c is, for example, 1 to 10 μm. Unlike this embodiment, the second plated layer 53 may not include the Ni layer 53b.

Next, a method for manufacturing the chip resistor 200 will be briefly described.

First, as shown in FIG. 29, a substrate sheet 810 is prepared. The substrate sheet 810 is to be the substrate 1 described above. The substrate sheet 810 is made of an insulating material. The substrate sheet 810 is made of ceramic or resin. Ceramics include, for example, Al2O3, AlN, and SiC. The substrate sheet 810 has a sheet surface 811 and a sheet back surface 812 facing away from each other.

Next, as shown in FIGS. 30 and 31, a bonding material 830 is bonded to the sheet surface 811 of the substrate sheet 810 . The bonding material 830 becomes the bonding layer 3 described above. In this embodiment, the bonding material 830 is a thermally conductive adhesive sheet. Then, in the state shown in FIG. 31, the bonding material 830 is preliminarily thermocompression bonded to the sheet surface 811 of the substrate sheet 810 .

Next, as shown in FIGS. 30 and 31 , a resistor assembly 820 is joined to the sheet surface 811 with a joining material 830 . In this embodiment, the resistor assembly 820 is temporarily pressure-bonded to the bonding material 830 in the state shown in FIGS. The resistor assembly 820 has a plurality of portions to become the resistor 2 described above. In this embodiment, before bonding the resistor assembly 820 to the sheet surface 811 to form the serpentine-shaped resistor 2, a plurality of serpentine-shaped portions are formed in the resistor assembly 820 by etching or stamping. ing. Next, the resistor assembly 820 is trimmed (not shown). This is for adjusting the resistance value of the resistor 2 . Trimming is performed using, for example, a laser, sandblast, dicer, grinder, or the like.

Unlike this embodiment, a liquid adhesive may be used instead of using a sheet member as the bonding material 830 to bond the resistor assembly 820 to the sheet surface 811 of the substrate sheet 810 .

Next, as shown in FIGS. 32 and 33, an insulating film 860 is formed. The insulating film 860 becomes the insulating layer 6 described above. The insulating film 860 is formed in a plurality of stripes extending along one direction. The insulating film 860 is formed by printing or coating, for example. A portion of the resistor assembly 820 is exposed from the insulating film 860 .

Next, as shown in FIGS. 34 and 35, a conductive material 840 is laminated on the resistor assembly 820. Then, as shown in FIGS. The conductive material 840 becomes the first underlayer 41 or the second underlayer 51 described above. The step of laminating the conductive material 840 uses PVD or CVD, and the PVD used for laminating the conductive material 840 includes, for example, sputtering. In this embodiment, in the step of laminating the conductive material 840 , the conductive material 840 is laminated along the extending direction of the insulating film 860 so as to form a belt shape. Therefore, part of the insulating film 860 is exposed from the laminated conductive material 840 . In order to stack the conductive material 840 in a strip shape, for example, masking may be performed. Conductive material 840 is, for example, Ni or Cr.

Next, as shown in FIGS. 36 and 37, a plurality of solid pieces 886 are obtained by cutting the resistor assembly 820 . In this embodiment, the resistor assembly 820 and the substrate sheet 810 are cut together. A solid piece 886 is obtained, for example, by punching or dicing. In this embodiment, punching is performed to obtain solid pieces 886 .

By cutting when obtaining the solid piece 886, the above-described first substrate side surface 13, second substrate side surface 14, first substrate end surface 15, second substrate end surface 16, first resistor side surface 23, second resistor side surface 24, A first underlayer side surface 413, a second underlayer side surface 514, a first insulating layer end surface 65, and a second insulating layer end surface 66 are formed. By simultaneously cutting the substrate sheet 810, the resistor assembly 820, and the like, the first substrate side surface 13, the first resistor side surface 23, and the first base layer side surface 413 are flush with each other. Similarly, by simultaneously cutting the substrate sheet 810, the resistor assembly 820, and the like, the second substrate side surface 14, the second resistor side surface 24, and the second base layer side surface 514 are flush with each other. Become. Similarly, this cutting makes the first substrate end surface 15 and the first insulating layer end surface 65 flush with each other. Similarly, this cutting makes the second substrate end surface 16 and the second insulating layer end surface 66 flush with each other.

Next, on the solid piece 886, the first plated layer 43 (Cu layer 43a, Ni layer 43b, and Sn layer 43c) and the second plated layer 53 (Cu layer 53a, Ni layer 53b, and A Sn layer 53c) is formed. Barrel plating, for example, is used to form the first plating layer 43 and the second plating layer 53 . Through the above steps, the chip resistor 200
manufacturing is completed.

Next, the effects of this embodiment will be described.

In this embodiment, the thermal conductivity of the insulating layer 6 is 1.0 W/(m·K) to 5.0 W/(m·K), which is relatively high. With such a configuration, the heat generated by the resistor 2 can be easily released to the outside of the chip resistor 200 via the insulating layer 6 . Therefore, it is possible to prevent the chip resistor 200 from becoming excessively hot.

In this embodiment, the first electrode 4 includes a first base layer 41 directly contacting the resistor 2 and a first plated layer 43 covering the first base layer 41 . The insulating layer 6 is interposed between the first base layer 41 and the resistor 2 . With such a configuration, it is easy to form the first plated layer 43 on the insulating layer 6 . Therefore, the area of the first electrode 4 can be increased. If the area of the first electrode 4 can be increased, the heat generated by the resistor 2 can be easily released to the mounting board 893 via the first electrode 4 . That is, it is possible to improve the heat dissipation of the chip resistor 200 . This can prevent the chip resistor 200 from becoming excessively hot.

In this embodiment, the substrate 1 is made of an insulating material. In such a configuration, there is no need to use a relatively thick Cu electrode. Therefore, the labor for processing the Cu electrode can be reduced. This contributes to efficiency in manufacturing the chip resistor 200 .

In this embodiment, both the substrate 1 and the mounting substrate 893 are glass epoxy resin substrates. In such a configuration, the thermal expansion coefficients of each of substrate 1 and mounting substrate 893 are approximately the same. Therefore, even if the substrate 1 thermally expands during use of the chip resistor 200, it is considered that the mounting substrate 893 also thermally expands at the same rate. Therefore, it is possible to prevent problems (for example, breakage of the chip resistor 200) that may occur due to the effects of thermal expansion during use of the chip resistor 200. FIG.

<First Modification of Second Embodiment>
A first modification of the second embodiment of the present invention will be described with reference to FIG.

FIG. 38 is a cross-sectional view showing a first modification of the second embodiment of the invention.

A chip resistor 201 shown in FIG. differ mainly from Other points are the same as those of the chip resistor 200, so description thereof will be omitted.

The chip resistor 201 also has the same effects as those described with respect to the chip resistor 200 .

<Second Modification of Second Embodiment>
A second modification of the second embodiment of the present invention will be described with reference to FIG.

FIG. 39 is a cross-sectional view showing a second modification of the second embodiment of the invention.

The chip resistor 202 shown in FIG. The main difference from the chip resistor 200 is that it is flush with the second base layer side surface 514 of the second base layer 51 . Other points are the same as those of the chip resistor 200, so description thereof will be omitted. In order to manufacture the chip resistor 202, a plated layer is formed before the step of cutting the substrate 1 sheet 810 and the resistor assembly 820 described with reference to FIGS.

The chip resistor 202 also has the same effects as those described with respect to the chip resistor 200 .

The invention is not limited to the embodiments described above. The specific configuration of each part of the present invention can be changed in various ways.

1 substrates 100, 101, 102, 200, 201, 202 chip resistor 11 substrate surface 12 substrate main surface 13 first substrate side surface 14 second substrate side surface 15 first substrate end surface 16 second substrate end surface 191 glass fiber portion 192 resin portion 2 resistor 21 resistor surface 22 resistor main surface 23 first resistor side surface 24 second resistor side surface 3 bonding layer 31 bonding layer surface 32 bonding layer main surface 4 first electrode 41 first base layer 413 first base layer Side surface 43 First plated layer 43a Cu layer 43b Ni layer 43c Sn layer 5 Second electrode 51 Second base layer 514 Second base layer side surface 53 Second plated layer 53a Cu layer 53b Ni layer 53c Sn layer 6 Insulating layer 61 Insulating layer Surface 62 Insulating layer principal surface 63 First insulating layer side surface 64 Second insulating layer side surface 65 First insulating layer end surface 66 Second insulating layer end surface 810 Substrate sheet 811 Sheet surface 812 Sheet back surface 820 Resistor assembly 830 Joining material 840 Conductive material 850 Assembly sheet 860 Insulating film 886 Solid piece 891, 892 Mounting structure 893 Mounting substrate 895 Conductive joint X1 First direction X2 Second direction X3 Third direction X4 Fourth direction Z1 Thickness direction

Claims (8)

a substrate;
a resistor;
a bonding layer interposed between the substrate and the resistor;
an insulating layer covering the resistor;
a first electrode located on the side opposite to the substrate with respect to the insulating layer in the thickness direction of the substrate, electrically connected to the resistor, and located on the first direction side;
A second electrode located on the side opposite to the substrate with respect to the insulating layer in the thickness direction of the substrate, electrically connected to the resistor, and opposite to the first direction with respect to the first electrode a second electrode located on the direction side;
The substrate has a first substrate side surface facing the first direction,
The resistor has a first resistor side surface facing the first direction,
The chip resistor, wherein the side surface of the first resistor is positioned closer to the second direction than the side surface of the first substrate and is covered with the insulating layer. The insulating layer has a first insulating layer outer surface facing the first direction,
2. The chip resistor according to claim 1, wherein the outer side surface of said first insulating layer and the side surface of said first substrate are flush with each other. the first electrode includes a first base layer directly contacting the resistor, and a first plated layer covering the first base layer,
The first plating layer includes a first metal layer directly covering the first underlayer, a second metal layer directly covering the first metal layer, and a third metal layer directly covering the second metal layer,
3. The chip resistor according to claim 2, wherein said third metal layer overlaps a part of said first insulating layer outer surface when viewed in said first direction. 4. The chip resistor according to claim 3, wherein said second metal layer overlaps a part of said first insulating layer outer surface when viewed in said first direction. The substrate has a second substrate side surface facing the second direction,
The resistor has a second resistor side surface facing the second direction,
5. The chip resistor according to claim 1, wherein said second resistor side surface is positioned closer to said first direction than said second substrate side surface and is covered with said insulating layer. The insulating layer has a second insulating layer outer surface facing the second direction,
6. The chip resistor according to claim 5, wherein said outer side surface of said second insulating layer and said side surface of said second substrate are flush with each other. The second electrode includes a second base layer directly contacting the resistor and a second plated layer covering the second base layer,
The second plated layer includes a fourth metal layer that directly covers the second base layer, a fifth metal layer that directly covers the fourth metal layer, and a sixth metal layer that directly covers the fifth metal layer,
7. The chip resistor according to claim 6, wherein said sixth metal layer overlaps a part of said second insulating layer outer surface when viewed in said first direction. 8. The chip resistor according to claim 7, wherein said fifth metal layer overlaps a part of said second insulating layer outer surface when viewed in said first direction.

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