JP2008177452A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly integrated IC package, in which short-circuit of a lead pin and non-connection of solder can be checked easily by viewing. <P>SOLUTION: A lead pin of IC package is constituted by a solder plating lead pin 12, and a gilded lead pin 13. The solder plating lead pin 12 and the gilded lead pin 13 are arranged by turns. Then, identification by viewing of both lead pins is made easy, and further distinction of short-circuit between lead pins and whether there is solder connection of the lead pins or not is made easy. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a configuration of a lead pin of an IC package of the semiconductor device.

  A semiconductor device is generally composed of one or more IC packages and a printed circuit board on which the IC packages are mounted. The lead pins of the IC package are mounted on the board terminals of the printed circuit board, and each lead pin and the corresponding board terminal are soldered. IC packages include a QFP (Quad Flat Package) type package in which lead pins extend from four side surfaces of a rectangular parallelepiped package and an SOP (small outline package) type package in which lead pins extend from two side surfaces of the package.

  FIG. 7 is a perspective view of a conventional QFP type IC package. This type of IC package is described in, for example, Patent Document 1. The IC package 100 includes a mold case 11 that constitutes a rectangular parallelepiped package body, and a large number of lead pins 12 that extend from four side surfaces of the mold case 11. Each lead pin 12 includes a first portion extending from the side surface of the mold case 11 in a direction orthogonal to the side surface, a second portion bent at a right angle from the first portion and parallel to the side surface, and extending to the lower printed circuit board (not shown), The third part is bent at a right angle from the two parts and solder-connected to the board terminal of the printed circuit board. Each lead pin 12 is entirely plated with solder, and is solder-connected to cream solder attached to the surface of the substrate terminal of the printed circuit board.

  In recent years, the number of lead pins of an IC package has been steadily increasing due to the progress of high integration and multi-functionality of devices. In addition, the overall external shape of the IC package is smaller than before. For this reason, the arrangement intervals of the lead pins of the IC package are becoming narrower, and it is extremely difficult to detect electrical shorts between the lead pins or unconnected solder in the inspection after the IC package is solder-mounted on the printed circuit board. It has become.

  In addition, since the pin arrangement interval is narrow, it is difficult to visually identify a terminal to which a probe such as an oscilloscope or a lock analyzer is connected even when performing a debug test.

  In Patent Document 1, in view of the fact that it is difficult to identify each lead pin as a result of narrowing the interval between the lead pins in an IC package, an identification number is assigned to each lead pin, and a pin for specific use is identified. It has been proposed to add identification marks such as colors and recesses. Further, Patent Document 2 proposes that a color corresponding to the identification number is attached to the tip of the lead pin instead of giving the pin identification number of the LSI.

Japanese Utility Model Publication No. 6-2706 Japanese Utility Model Publication No.59-164178

  As described in Patent Documents 1 and 2, if lead pins with an identification number or color are provided, the identification of each lead pin is facilitated. However, the narrowing of the interval between lead pins of an IC package is increasing, and it is difficult not only to identify pins but also to identify the boundary between adjacent lead pins. It is also difficult to determine whether the solder connection between the lead pin and the printed circuit board terminal has been completed. In particular, the conventional lead pins are usually plated with the same color as the cream solder on the board terminals of the printed circuit board. For this reason, the IC package is mounted on the printed circuit board, and the lead pins and the board terminals overlap. In this state, it is difficult to determine whether the solder connection is completed at each pin or whether the solder connection is normally performed.

  In view of the problem of the lead pins of the conventional IC package, the present invention has been improved to facilitate both the identification of the boundary portion between adjacent lead pins and the identification of the solder connection state between the lead pin and the terminal of the printed circuit board. Another object of the present invention is to provide a semiconductor device including an IC package having lead pins.

  In order to achieve the above object, the semiconductor device of the present invention is configured such that the lead pins of the IC package are composed of lead pins that are entirely solder-plated and lead pins that are entirely treated with a color different from that of the solder plating. It is characterized by.

  In the semiconductor device of the present invention, the lead pin is composed of a lead pin whose entire pin is solder-plated and a lead pin whose entire surface is treated with a color different from that of the solder plating. It becomes easy and visibility of the entire lead pin is improved. Further, it is easy to visually determine whether or not the solder connection is completed between the lead pin whose surface is processed with a color different from the color of the solder plating and the substrate terminal.

  In the semiconductor device of the present invention, the surface treatment of the different color may be gold plating. In the case of gold plating, there is an advantage that the reliability of the lead pin is improved, for example, the corrosion resistance of the lead pin is increased.

  Further, it is preferable that the lead pins plated with the entire solder and the lead pins plated with the whole are alternately arranged. In this case, since the visibility is particularly improved, it is easy to determine whether or not there is a short between the lead pins.

  Instead of the above, the lead pins plated with gold as a whole may be arranged at predetermined intervals. In this case, for example, it is easy to identify which pin corresponds to a pin in which a short circuit occurs or a pin not connected to solder.

  In addition, the semiconductor device may include a printed circuit board on which the IC package is mounted and having solder-plated board terminals connected to lead pins of the IC package. When the gold-plated lead pin is above the solder-plated board terminal, the board terminal is used as a background to improve the visibility between the two, making it easy to determine whether or not there is a solder connection.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to make an understanding of this invention easy, the same code | symbol is attached | subjected and shown to the same element in all the accompanying drawings. FIG. 1 is a perspective view showing an IC package of a semiconductor device according to the first embodiment of the present invention. The IC package 10 is a QFP type package, which includes a semiconductor integrated circuit inside, and forms a mold case 11 constituting the package body and external connection terminals of the semiconductor integrated circuit, and is externally exposed from four side surfaces of the mold case. It has a number of lead pins 12 and 13 extending. Each lead pin 12, 13 extends from a side surface of the mold case 11 in a lateral direction, and extends toward a printed circuit board (not shown) that is bent at a right angle from the first portion and disposed downward in the drawing. The second portion includes a third portion that is bent at a right angle from the second portion and extends in the lateral direction, and is solder-connected to the terminals of the printed circuit board. The lead pins 12 and the lead pins 13 are alternately arranged.

  The lead pin 12 is entirely plated with solder in the same manner as a conventional lead pin, and the lead pin 13 is entirely plated with gold for identification from the lead pin 12. That is, in the semiconductor device according to the present embodiment, the lead pins 12 are subjected to a normal surface treatment, and the lead pins 13 are subjected to a plating process different from the color of the solder plating, thereby identifying the pin positions and pin states. And visibility are improved. The lead pin 13 may be coated with a conductive paint or the like instead of gold plating. Since the lead pin 13 is gold-plated, the discrimination and visibility are improved with respect to the cream solder of the terminal of the printed circuit board disposed below the lead pin 13, and in particular, connected or unconnected solder connection is easy. Can be determined. In addition, if the lead pin 12 and the lead pin 13 are short-circuited by solder or the like, the determination to that effect becomes easy. In this manner, the lead pins 12 that have been subjected to solder plating and the colored lead pins 13 for identification that have been surface-treated with a color different from that of the solder plating are alternately arranged, thereby making it possible to distinguish between both lead pins and between the lead pins. An electrical short circuit and confirmation of solder connection between the lead pin and the terminal can be easily made by visual inspection.

  In addition to the arrangement of the identification colored lead pins 13 as described above, it is also possible to assign an identification colored lead pin of a different color to a lead pin for a desired application. This makes it easy to identify measurement points using an oscilloscope, logic analyzer, or multimeter. For example, by assigning different colored lead pins for identifying different colors to the power supply terminal and the ground terminal, it is possible to identify the necessary lead pins at a glance when performing a short circuit between the power supply and GND during the test. It is also possible to provide contrast in the hue instead of different identification colors. In this case, since each pin can be visually confirmed, it is easy to visually confirm the pin, and it is possible to smoothly identify the test target pin in the manufacturing inspection and the debug evaluation. In addition, the gold-plated lead pins 13 have the advantage of improving not only the identification and visibility of solder connection but also the durability.

  In particular, the identification colored lead pins 13 are entirely surface-treated with a material having a color different from that of the solder plating, and the degree of cream solder formed on the connection terminals of the printed circuit board can be easily visually confirmed. it can. In addition, by arranging the lead pins 12 alternately with the lead pins 12 processed by solder plating, it is possible to easily determine an electrical short between adjacent lead pins. In the above embodiment, the lead pins 12 and the lead pins 13 are alternately arranged. However, instead of this, the gold-plated lead pins 13 and the solder-plated lead pins 12 are regularly arranged at 2: 1. May be. In this case, the discriminability between the lead pins is somewhat impaired, but the number of lead pins capable of determining the presence or absence of solder connection increases.

  FIG. 2 is a perspective view showing an IC package 20 of a semiconductor device according to the second embodiment of the present invention. This embodiment is an example in which the lead pin structure of the present invention is applied to an SOP type package. In the present embodiment, solder plating lead pins 22 and gold plating lead pins 23 are alternately arranged on two opposing side surfaces of the mold case 21. The operations and effects of the present embodiment are the same as the operations and effects of the first embodiment.

  FIG. 3 is a perspective view showing an IC package 10A of a semiconductor device according to the third embodiment of the present invention. This embodiment is an example in which one gold-plated lead pin 13 is disposed for a predetermined number of normal solder-plated lead pins 12 (for example, one for four). As described above, the gold-plated lead pins 13 are regularly arranged for each predetermined number of lead pins, thereby improving the overall distinguishability of the lead pins 12 and 13. In addition, the gold-plated lead pins 13 have the advantage of improving not only the identification and visibility of solder connection but also the durability.

  In the conventional semiconductor device, the pin number of the IC package is written on the printed board by silk printing so that the pin position of the IC package can be visually confirmed. However, in recent years, since the scale and density of circuit mounting on a printed circuit board have been rapidly improved, there is a case where an area for displaying a pin number by silk printing cannot be secured on the printed circuit board. Therefore, in the present embodiment, the gold-plated lead pins 13 that are colored lead pins for identification are regularly arranged for each predetermined number of lead pins, and there is no silk-printed notation of the pin number on the terminal of the printed circuit board. The pin position of the IC device can be visually and easily confirmed. Further, it is easy to identify the presence or absence of solder connection in the gold-plated lead pins 13.

  FIG. 4 is a perspective view showing an IC package 20A of a semiconductor device according to the fourth embodiment of the present invention. The present embodiment is an example in which the structure of the present invention is applied to an SOP type package. Like the third embodiment, gold-plated lead pins 23 are arranged for each predetermined number of lead pins.

  FIG. 5 is a perspective view showing an IC package 10B of the semiconductor device according to the fifth embodiment of the present invention. The present embodiment is an example in which the structure of the present invention is applied to a QFP, and the lead pin for a power supply terminal is a gold-plated lead pin 13. In the present embodiment, the identification colored lead pin 13 is assigned to, for example, the power supply terminal + Vcc. This makes it particularly easy to check the presence or absence of solder connection at the power supply terminal and the connection state. Further, when the electrical short between the power source and the GND is confirmed, the measurement point can be specified easily and quickly, and the efficiency of manufacturing inspection can be improved. In addition, if assigned to a bus signal line or the like, it is possible to easily specify a probe connection destination such as an oscilloscope or a logic analyzer when performing a debug test.

  FIG. 6 is a perspective view showing an IC package 20B of the semiconductor device according to the sixth embodiment of the present invention. This embodiment is an example in which the present invention is applied to an SOP type package. Similar to the fifth embodiment, identification colored lead pins 23 are assigned to specific terminals.

  In the IC package disposed in the semiconductor device of the above embodiment, the cream solder attached to the substrate terminal of the printed circuit board has a shade with respect to the lead pins of the QFP type and SOP type IC packages soldered and mounted on the printed circuit board. By applying different surface treatments, the cream solder and lead pins are not assimilated. For this reason, the presence / absence of the solder connection of the lead pins and the connection state can be easily visually confirmed.

  In addition, the lead pins with identification colors have a narrow pin width and pin interval, and even in highly integrated IC packages where pin identification is usually difficult, identification between adjacent lead pins is easy, and 1 pin 1 pin Since it is easy to follow with the eyes, it is easy to confirm the pin position visually. For this reason, the visibility of the test object pin in manufacturing inspection and debug evaluation can be improved.

  Although the present invention has been described based on the preferred embodiments, the semiconductor device of the present invention is not limited to the configuration of the above embodiments, and various modifications and changes can be made from the configuration of the above embodiments. Those applied are also included in the scope of the present invention.

1 is a perspective view of an IC package according to a first embodiment of the present invention. The perspective view of the IC package which concerns on the 2nd Embodiment of this invention. The perspective view of the IC package which concerns on the 3rd Embodiment of this invention. The perspective view of the IC package which concerns on the 4th Embodiment of this invention. The perspective view of the IC package which concerns on the 5th Embodiment of this invention. The perspective view of the IC package which concerns on the 6th Embodiment of this invention. The perspective view of the conventional IC package.

Explanation of symbols

10, 20: IC package 11, 21: Mold case 12, 22: Solder plating lead pin 13, 23: Gold plating (with identification color) lead pin

Claims (5)

  1. A semiconductor device comprising: a lead pin of an IC package comprising a lead pin that is entirely solder plated and a lead pin that is entirely treated with a color different from that of solder plating.   2. The semiconductor device according to claim 1, wherein the surface treatment of the different color is gold plating.   3. The semiconductor device according to claim 2, wherein the lead pins plated with the entire solder and the lead pins plated with the whole are alternately arranged.   3. The semiconductor device according to claim 2, wherein the lead pins plated with gold as a whole are arranged at predetermined intervals.   5. The semiconductor device according to claim 1, further comprising: a printed circuit board having a solder-plated board terminal mounted with the IC package and connected to a lead pin of the IC package. 6. .

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