JP2018046082A - Circuit device and television apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device and a television apparatus capable of simplifying inspection of an IC and performing in a short time, when inspecting a circuit device where a plurality of ICs of the same function and the same terminal arrangement are mounted on one or a plurality of printed circuit boards.SOLUTION: In a circuit device where a plurality of ICs 10, 10, 10of the same function and the same terminal arrangement are mounted on one printed circuit board 100, for example, a pattern of wiring 2 of an IC in a region 4 surrounded by a dotted-line and including the mounting places of the same IC10, 10, 10mounted on the printed circuit board 100, is commonalized in each IC. Consequently, when cutting a printed circuit board including the IC and its peripheral region 4, checker pin arrangement of an inspection apparatus can be commonalized, because the wiring pattern of cutout is commonalized, and inspection of the same IC can be carried out efficiently in a short time.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a circuit device and a television device, and more particularly to a circuit device and a television device that can improve the efficiency of inspection of an IC mounted on the circuit device.

  In a circuit device of an electronic device, an IC (Integrated Circuit) such as a CPU and many memories is mounted on a printed circuit board. In order to inspect the mounting board on which the IC is mounted, for example, as disclosed in Patent Documents 1 and 2, a test land is provided on the surface of the printed board or the side surface of the printed board. Yes. However, with regard to ICs such as memory mounted on a printed circuit board, although they were normal at the time of shipment and in the shipping inspection after mounting the product, a failure may be found when they are put on the market. .

  As described above, for electronic devices in which a failure is found after shipment, the connection between the IC wired on the mounting board and the mounting component including the other IC is disconnected in order to identify the malfunction of each IC. The condition needs to be inspected. However, among IC failures, there are migration and the like as an example in which a short circuit inside the IC proceeds in the market. When the inside of the IC is short-circuited due to the occurrence of migration, if the heat is applied to remove the solder-connected IC from the printed circuit board, the short-circuited part may be eliminated, so the cause of the failure cannot be identified Occurs. For this reason, when inspecting an IC, it is difficult to remove the IC from the printed circuit board without applying heat. Therefore, it is necessary to cut out the peripheral printed circuit board including the IC and perform the inspection.

JP 2008-66373 A JP 2000-162237 A

  Then, with respect to the cut out substrate, vias, wiring patterns, soldered portions, and failure portions inside the IC are separated using a TDR (Time Domain Reflectometry) inspection device or the like. On the other hand, in an electronic device, a plurality of ICs having the same terminal arrangement are often used as a memory. And even if the IC has the same function and the same terminal arrangement, the wiring pattern around the IC is individually determined from the arrangement position on the printed board on which the IC is mounted and the connection relationship with the mounted electronic components including other ICs. Decided. However, when inspecting a defect of an electronic device equipped with an IC having the same function and the same terminal arrangement, a wiring pattern from a pad (land) of the printed circuit board to which an IC terminal mounted on each printed circuit board is connected. If the position and wiring length are not uniform, it will be necessary to change the placement of the checker pins of the inspection device or to correct the impedance due to the difference in wiring length. It will also take.

  The present invention has been made in view of these circumstances, and has the same function and the same terminal arrangement when inspecting a circuit device in which a plurality of ICs having the same function and the same terminal arrangement are mounted on one or a plurality of printed circuit boards. It is an object of the present invention to provide a circuit device and a television device that can efficiently and quickly perform an IC inspection.

  In order to solve the above problems, a first technical means of the present invention is a circuit device in which a plurality of ICs having the same function and the same terminal arrangement are mounted on one or a plurality of printed boards, The wiring pattern of the IC in a region including the mounting location of the mounted IC is common.

  According to a second technical means, in the first technical means, when the printed circuit board is a multilayer wiring printed circuit board and the region including the IC mounting portion is cut out from the printed circuit board as a cut piece, The exposed wiring pattern is shared by the cut pieces.

  According to a third technical means, in the second technical means, a via reaching the surface of the printed circuit board is formed on the cut-out surface.

  According to a fourth technical means, in any one of the first to third technical means, a marking serving as a mark at the time of cutting is applied to an area including the mounting position of the IC on the printed circuit board. It is characterized by.

  According to a fifth technical means, in the fourth technical means, the marking is silk printing applied to a surface of the printed circuit board.

  According to a sixth technical means, in the fourth technical means, the marking is a via provided in the printed circuit board.

  According to a seventh technical means, in any one of the first to sixth technical means, the wiring pattern includes a data line, an address line, and a clock line.

  According to an eighth technical means, in any one of the first to seventh technical means, the IC is a DDR (Double Data Rate) memory.

A ninth technical means is a television apparatus, and includes any one of the first to eighth technical means.

  According to the present invention, since the cut-out IC and the wiring pattern of the peripheral printed circuit board including this IC are shared, the arrangement of the checker pins (test pins) of the inspection apparatus can be shared, and the same function In addition, the inspection of ICs having the same terminal arrangement can be performed efficiently and in a short time.

1 is a schematic diagram of a circuit device according to a first embodiment of the present invention. It is a schematic diagram of the cutout piece of the printed circuit board carrying one IC cut out from the circuit apparatus shown in FIG. It is a perspective view of the cut piece shown in FIG. It is a mimetic diagram in case a circuit device concerning a 1st embodiment of the present invention has a plurality of printed circuit boards. It is a flowchart for demonstrating the defect inspection of IC and a board | substrate. It is a schematic diagram of the circuit apparatus which concerns on the 2nd Embodiment of this invention. FIG. 7 is a schematic diagram of a cut-out piece of a printed board on which one IC cut out from the circuit device shown in FIG. 6 is mounted. It is a perspective view of the cut piece shown in FIG. It is a schematic diagram in case the circuit device which concerns on the 2nd Embodiment of this invention has several printed circuit boards. It is a schematic diagram of the circuit apparatus which concerns on the 3rd Embodiment of this invention. It is a schematic diagram of the cut piece of the printed circuit board carrying one IC cut out from the circuit apparatus shown in FIG. It is a perspective view of the cut piece shown in FIG. It is a schematic diagram of the cutout piece of the printed circuit board carrying one IC cut out from the circuit apparatus which concerns on the 4th Embodiment of this invention.

  Hereinafter, preferred embodiments of a circuit device and a television device of the present invention will be described with reference to the drawings. In the following description, the configurations denoted by the same reference numerals in different drawings are the same, and the description thereof may be omitted. In the following description and the present invention, the same function means that the function as a memory and the function as a processor are the same. Therefore, for example, in the case of a DDR memory, a 1 Gb (gigabit) memory and a 4 Gb memory are ICs having the same function. Further, the same terminal arrangement means that the terminals assigned to the respective roles in order to perform the function of the IC have the same arrangement with respect to the IC package.

(First embodiment)
FIG. 1 is a diagram schematically showing a circuit device according to a first embodiment of the present invention, and this circuit device is a circuit board mounted on, for example, a television device. The circuit board consists of a printed circuit board 100, and a large number of electronic components such as ICs, resistors, capacitors, etc. are fixed on the surface, and the components are connected to each other by the surface or surface of the insulating substrate and wiring provided in the interior. It constitutes an electronic circuit.

A printed circuit board 100 shown in FIG. 1 has a large number of electronic components mounted thereon. For example, only _three ICs 10 ₁ , 10 ₂ , and 10 ₃ that are DDR (Double Data Rate) memories and the CPU 11 are illustrated. . The three ICs 10 ₁ , 10 ₂ , and 10 ₃ are ICs having the same function and the same terminal arrangement, and the electrodes of the ICs 10 ₁ , 10 ₂ , and 10 ₃ are on the electrode pad 1 formed on the printed circuit board 100. Electrical connection is made using bumps such as solder and gold. Each electrode pad 1 is provided with a wiring 2 made of a copper foil or the like formed on the printed board 100. In this embodiment, the wiring 2 is drawn as a wiring pattern on the printed board 100. The wiring 2 includes data lines, address lines, and clock lines for the ICs 10 ₁ , 10 ₂ , 10 ₃ .

In the present embodiment, an example in which the ICs 10 ₁ , 10 ₂ , 10 ₃ are soldered to the printed circuit board 100 is shown. Therefore, in FIG. 1, for the sake of convenience, in order to illustrate the electrode pad 1 and the wiring 2 formed on the printed circuit board 100, the ICs 10 ₁ , 10 ₂ , and 10 ₃ are indicated by two-dot chain lines. ICs 10 ₁ , 10 ₂ , and 10 ₃ are mounted on the rectangle shown, but not shown. In FIG. 1, only the periphery of each of the ICs 10 ₁ , 10 ₂ , and 10 ₃ is shown for the sake of convenience, but the wiring of the CPU 11 and other electronic components is also formed on the surface of the printed circuit board 100. Yes.

In the peripheral area including the mounting locations of the ICs 10 ₁ , 10 ₂ , and 10 ₃ , four hook-shaped silk prints 3 are applied as markings. The wiring 2 in the region 4 surrounded by the cocoon-shaped silk print 3 is formed so that all of the ICs 10 ₁ , 10 ₂ , and 10 ₃ having the same function and the same terminal arrangement have the same wiring pattern. . The outside of the region 4 may be provided with different wiring patterns for the ICs 10 ₁ , 10 ₂ , 10 ₃ .

FIG. 2 is a schematic view of a cut piece of a printed circuit board on which one IC cut out from the circuit device shown in FIG. 1 is mounted, and FIG. 3 is a perspective view of the cut piece shown in FIG. When each IC 10 ₁ , 10 ₂ , 10 ₃ is cut out from the printed board 100 shown in FIG. 1 along the dotted line using the silk printing 3 as a marking, the cut pieces 20 ₁ , 20 of the printed board are cut out. ₂ and 20 ₃ have the same wiring pattern. Therefore, when the individual ICs 10 ₁ , 10 ₂ , 10 ₃ are inspected, for example, the ICs 10 ₁ , 10 ₂ , 10 ₃ can be inspected without changing the arrangement of the checker pins of the inspection device. It becomes. The silk printing 3 as the marking is not limited to the hook shape, and may be a frame or a line. Further, a test land may be provided in which a checker pin is brought into contact with a predetermined portion of the wiring 2 of the cut pieces 20 ₁ , 20 ₂ , 20 ₃ .

FIG. 4 is a schematic diagram when the circuit device according to the first embodiment of the present invention has a plurality of printed boards. In the embodiment shown in FIG. 4, ICs 10 ₁ , 10 ₂ , and 10 ₃ having the same function and the same terminal arrangement are mounted on a plurality of printed boards, for example, three printed boards 101, 102, and 103. In a circuit device, as shown in FIG. 1, ICs having the same function and the same terminal arrangement may be mounted on the same printed circuit board or a plurality of printed circuit boards. Also in the circuit device shown in FIG. 4, in the peripheral area including the mounting positions of the ICs 10 ₁ , 10 ₂ , 10 ₃ mounted on the respective printed circuit boards 101, 102, 103, there are four hook-shaped silks as markings. Printing 3 is given. Then, the wiring 2 in the region 4 surrounded by the cocoon-shaped silk print 3 is formed so that all of the ICs 10 ₁ , 10 ₂ , 10 ₃ having the same function and the same terminal arrangement have the same wiring pattern. Yes.

Therefore, when the portion of the region 4 is cut out along the dotted line from the printed boards 101, 102, and 103 using the silk print 3 as a mark, the printed board having the same wiring pattern as shown in FIG. 2 or FIG. 3 is cut out. Pieces 20 ₁ , 20 ₂ , 20 ₃ are obtained. Therefore, when the individual ICs 10 ₁ , 10 ₂ , 10 ₃ are inspected, for example, the ICs 10 ₁ , 10 ₂ , 10 ₃ can be inspected without changing the arrangement of the checker pins of the inspection device. It becomes.

  Next, an inspection procedure when the circuit device has a defect will be described. FIG. 5 is a flowchart for explaining a defect inspection of an IC and a substrate, and assumes a case where there is a read / write defect of, for example, a DDR memory as an IC. First, when a read / write failure of the DDR memory is found, a waveform between predetermined terminals of the circuit device is confirmed with an oscilloscope (step S1). It is determined whether or not the waveform is normal (step S2). If the signal is normal (in the case of YES), the process proceeds to step S3, which is not a hardware failure or a hardware failure. Since it is a defect inside the I / O buffer of the IC, it is determined that it cannot be determined by measurement from the outside of the IC.

  If the waveform is not normal in step S2 (NO), the process moves to step S4, and the wiring pattern of the printed circuit board and the electrode pad are confirmed by X-ray. If the wiring pattern or electrode pad is abnormal (in the case of NO), it is determined that there is a problem with the printed circuit board or soldering (step S6). If normal (in the case of YES), the process proceeds to step S7, and TDR measurement is performed using a predetermined terminal (test land) of the printed circuit board.

If the result of the TDR measurement in step S7 is not different from the normal print board (in the case of YES), it is determined that the problem is an IC I / O buffer problem or an internal problem (step S9). If the TDR measurement result is different from the normal base (in the case of NO), the process proceeds to step S10, where the substrate is cut at a predetermined location, and the TDR measurement is performed using the cut-out piece of the printed board. To implement. In this case, in the present embodiment, the printed circuit board in the region 4 including the ICs 10 ₁ , 10 ₂ , and 10 ₃ along the dotted line surrounded by the silk print 3 of the marking is printed from the printed circuit board 100 shown in FIG. After cutting and obtaining the cut pieces 20 ₁ , 20 ₂ , and 20 ₃ as shown in FIGS. 2 and ₃ , the cut pieces 20 ₁ , 20 ₂ , and 20 ₃ are inspected using a TDR inspection apparatus.

  Then, it is determined whether or not the measurement result is the same as the data of the cutout piece of the normal printed circuit board (step S11). If there is no difference from the normal cutout piece (in the case of YES), the IC to be inspected is not defective. It is determined that there is a problem on the SoC side (step S12). When there is a difference from a normal cut piece (in the case of NO), it is determined that the IC to be inspected is defective. In this case, the S parameter of the normal cutout piece is grasped in advance and compared with the S parameter obtained from the cutout piece of the printed circuit board to be inspected. Whether there is a problem with the pad or an internal problem of the IC can be determined (step S13).

As described above, in this embodiment, since each of the cut pieces 20 ₁ , 20 ₂ , and 20 ₃ has the same wiring pattern, it is possible to inspect under the same conditions when inspecting individual ICs. . For this reason, by obtaining values such as reference S parameters in advance for cutout pieces of a printed circuit board having the same wiring pattern on which a normal IC is mounted, a printed circuit board having the same wiring pattern on which the same IC is mounted. It can be applied to cutout inspection. Therefore, since it is possible to use a common value for the reference inspection value without changing the arrangement of the test pins, the inspection can be performed efficiently and the inspection time can be shortened.

(Second Embodiment)
FIG. 6 is a schematic diagram of a circuit device according to the second embodiment of the present invention. A large number of electronic components are mounted on the printed circuit board 200. In FIG. 6, three ICs 10 ₁ that are DDR memories are provided. , 10 ₂ , 10 ₃ and only the CPU 11 are shown as examples. The three ICs 10 ₁ , 10 ₂ , 10 ₃ are the same IC, and the electrodes of the ICs 10 ₁ , 10 ₂ , 10 ₃ are bumps such as solder and gold on the electrode pads 1 formed on the printed circuit board 200. It is soldered using.

The printed circuit board 200 is formed of a multilayer wiring board, and signals and the like are transmitted to the electrode pads 1 for the ICs 10 ₁ , 10 ₂ , and 10 ₃ through the internal wiring 5 disposed in the inner layer (inside) of the printed circuit board 200. I / O is performed. The electrode pad 1 and the internal wiring 5 are electrically connected by forming a via (also referred to as a through hole) at the position of the electrode pad 1 and providing copper plating in the via or filling it with a conductive pace. It is carried out.

In FIG. 6, for the sake of convenience, in order to illustrate the electrode pad 1 and the internal wiring 5, the ICs 10 ₁ , 10 ₂ , and 10 ₃ are indicated by two-dot chain lines, and above the rectangle indicated by the two-dot chain lines. ICs 10 ₁ , 10 ₂ , 10 ₃ are mounted. Then, four vias 6 are formed as markings in the peripheral area including the mounting locations of the ICs 10 ₁ , 10 ₂ , 10 ₃ , respectively. The inner surface of the via 7 does not need to be plated with copper. The internal wiring 5 in the region 4 indicated by the dotted line surrounded by the via 6 is formed to have the same wiring pattern for the ICs 10 ₁ , 10 ₂ , 10 ₃ having the same function and the same terminal arrangement. . The outside of the region 4 may be provided with different wiring patterns for the ICs 10 ₁ , 10 ₂ , 10 ₃ . In addition, vias 7 are provided at locations intersecting the sides of the region 4 indicated by the dotted lines of the internal wiring 5, and each internal wiring 5 is connected to a test land provided on the surface of the printed circuit board 200 via the via 7. And is electrically connected.

FIG. 7 is a schematic view of a cutout piece of a printed board on which one IC cut out from the circuit device shown in FIG. 6 is mounted, and FIG. 8 is a perspective view of the cutout piece shown in FIG. When the ICs 10 ₁ , 10 ₂ , and 10 ₃ are cut out from the printed board 200 shown in FIG. 6 along the dotted line using the vias 6 that serve as markings, the printed board cut pieces 30 ₁ and 30 ₂ are cut out. , 30 ₃ have the same wiring pattern. In the present embodiment, the internal wiring 5 is exposed at the cut end faces of the cut pieces 30 ₁ , 30 ₂ , 30 ₃ , and the printed circuit board 200 is connected via the via 7 formed in the exposed portion of the internal wiring 5. The test land provided on the surface of is electrically connected.

For this reason, when inspecting the cutout pieces 30 ₁ , 30 ₂ , 30 ₃ , the internal wiring 5 exposed at the cut end face may be used as a test land, and the surface of the printed circuit board 200 via the via 7. A test land formed in the above may be used. Furthermore, in the present embodiment, vias are used as markings, but silk printing may be used as in the first embodiment. Also in this embodiment, since each of the cut-out pieces 30 ₁ , 30 ₂ , 30 ₃ has the same wiring pattern, it is possible to inspect under the same conditions when inspecting individual ICs. Therefore, the inspection can be performed efficiently and the inspection time can be shortened.

FIG. 9 is a schematic view when a circuit device according to another embodiment of the present invention has a plurality of printed boards. In the embodiment shown in FIG. 9, ICs 10 ₁ , 10 ₂ , 10 ₃ having the same function and the same terminal arrangement are mounted on a plurality of printed boards, for example, three printed boards 201, 202, 203. As described above, even when ICs having the same function and the same terminal arrangement are mounted on a plurality of substrates, the mounting positions of the ICs 10 ₁ , 10 ₂ , 10 ₃ mounted on the respective printed circuit boards 201, 202, 203 are included. The wirings 2 in the peripheral region 4 are all formed to have the same wiring pattern. The wiring of the present invention includes a conductor in a via formed in a multilayer wiring board.

As a result, when the printed circuit boards 201, 202, and 203 are cut out along the region 4 using the via 6 as a mark, the printed circuit board cut pieces 30 having the same wiring pattern as shown in FIG. 7 or FIG. ₁ , 30 ₂ and 30 ₃ are obtained. For this reason, when inspecting each IC, the inspection can be performed under the same conditions, and the inspection can be made more efficient and the inspection time can be shortened. In the second embodiment, all the wirings to the ICs 10 ₁ , 10 ₂ , 10 ₃ are close to the internal wiring 5, but some of the wirings are internal wirings and the other wirings are on the printed circuit board surface. A wiring may be used.

(Third embodiment)
FIG. 10 is a schematic diagram of a circuit device according to the third embodiment of the present invention. Although many electronic components are mounted on the printed circuit board 300, FIG. 10 illustrates only _three ICs 10 ₁ , 10 ₂ , and 10 ₃ that are DDR memories and the CPU 11 as an example. The three ICs 10 ₁ , 10 ₂ , 10 ₃ are the same IC, and the electrodes of the ICs 10 ₁ , 10 ₂ , 10 ₃ are bumps such as solder and gold on the electrode pads 1 formed on the printed circuit board 200. Are electrically connected.

The printed circuit board 300 is composed of a multilayer wiring board, and the internal wiring 5 is connected to the electrode pads 1 for the ICs 10 ₁ , 10 ₂ , 10 ₃ through the vias 7 as in the second embodiment. ing. In FIG. 10, for the sake of convenience, in order to illustrate the electrode pad 1 and the internal wiring 5, the ICs 10 ₁ , 10 ₂ , and 10 ₃ are indicated by two-dot chain lines, and above the rectangle indicated by the two-dot chain lines. ICs 10 ₁ , 10 ₂ , 10 ₃ are mounted. Similar to the second embodiment, four vias 6 are formed as markings in the peripheral region including the mounting locations of the ICs 10 ₁ , 10 ₂ , and 10 ₃ , respectively.

In the present embodiment, a via 8 is provided at a predetermined location of the internal wiring 5 located in a region 4 indicated by a dotted line surrounded by the via 6, and a test land is provided on the surface corresponding to the via 8 of the printed board 300. The internal wiring 5 in the region 4 is formed so that all of the ICs 10 ₁ , 10 ₂ , 10 ₃ having the same function and the same terminal arrangement have the same wiring pattern, and the via 8 provided in the internal wiring of the region 4 Are formed so as to be the same position in the ICs 10 ₁ , 10 ₂ , 10 ₃ having the same function and the same terminal arrangement. The outside of the region 4 may be provided with different wiring patterns for the ICs 10 ₁ , 10 ₂ , 10 ₃ .

11 is a schematic diagram of a cutout piece of a printed board on which one IC cut out from the circuit device shown in FIG. 10 is mounted, and FIG. 12 is a perspective view of the cutout piece shown in FIG. When the ICs 10 ₁ , 10 ₂ , 10 ₃ are cut out from the printed circuit board 300 shown in FIG. 11 along the dotted line using the marking vias, the printed circuit board cutouts 30 ₁ , 30 ₂ , Each of 30 ₃ has the same wiring pattern. In the present embodiment, the internal wiring 5 is exposed at the cut end surfaces of the cut pieces 40 ₁ , 40 ₂ , and 40 ₃ , and the internal wiring 5 is connected to the surface of the printed circuit board 300 via the vias 8. The provided test land is exposed.

For this reason, when the cut pieces 40 ₁ , 40 ₂ , and 40 ₃ are inspected, the internal wiring 5 exposed at the cut end face may be used as a test land, and the surface of the printed circuit board 200 via the vias 8. A test land formed in the above may be used. Also in this embodiment, since each of the cut-out pieces 40 ₁ , 40 ₂ , 40 ₃ has the same wiring pattern, it is possible to inspect under the same conditions when inspecting individual ICs. Therefore, the inspection can be performed efficiently and the inspection time can be shortened.

In consideration of the depth of the via and the length of the internal wiring 5, the via 8 is located at a position where the wiring length of the conductor from the electrode pad 1 to the test land on the surface of the printed circuit board 300 is the same for each electrode pad 1. If this is provided, the electrical impedance from each electrode of the IC to the test land can be made substantially uniform. Thereby, the wiring distance from the test land on the printed circuit board to each electrode of the ICs 10 ₁ , 10 ₂ , 10 ₃ can be made equal, and the timing of the inspection signal to the electrode of the IC can be matched.

(Fourth embodiment)
FIG. 13 is a schematic diagram of a cut-out piece of a printed circuit board on which one IC cut out from a circuit device according to the fourth embodiment of the present invention is mounted. In this embodiment, a part of the first embodiment is changed. In the present embodiment, the lengths of the wirings 2 for the respective electrode pads 1 are all made equal in the cut-out piece of the cut-out printed board. For this reason, the meander wiring 9 is provided in the middle of the wiring 2 for the wiring 2 having a short line length to the periphery of the cut piece.

  As a result, when inspecting a cutout piece of a printed circuit board, the test pins are arranged using the wiring around the cutout piece as a measurement point, so that the wiring distance from the test pin to each electrode of the IC is equal. The timing of the inspection signal to the IC electrode can be adjusted. When the meander wiring 9 is provided, it is necessary to make all the wiring patterns of the cutout pieces including the meander wiring 9 common when the IC having the same function and the same terminal arrangement is cut out.

  As described above, in each embodiment of the present invention, in a circuit device having an IC having the same function and the same terminal arrangement, a wiring pattern including a via is common when the base of the IC having the same function and the same terminal arrangement is cut out. However, it is desirable to determine the wiring pattern so as to match the shape of a jig such as a checker pin of the inspection apparatus. In addition, although the example of silk printing or a via | veer was shown as marking for cutting out a printed circuit board, if it becomes a mark, it will not be restricted to these. Furthermore, as an IC mounted on a printed circuit board, an IC of a BGA (Ball Grid Array) package has been illustrated, but the IC has other packages such as an SOP (Small Outline Package) and a QFP (Quad Flat Package). There may be. Further, in each embodiment, the DDR memory is described as an example of the IC. However, an IC having another function such as a CPU may be used as long as the IC has the same function and the same terminal arrangement. Even if the IC is an IC having other functions such as a CPU, the wiring pattern includes a data line, an address line, and a clock line.

1 ... electrode pad, 2 ... wire, 3 ... silk printing, 4 ... region, 5 ... internal wiring, 6-8 ... via, 9 ... meander _{lines, 10 1, 10 2, 10} 3 ··· IC, 11 ... CPU , 20 ₁ , 20 ₂ , 20 ₃ , 30 ₁ , 30 ₂ , 30 ₃ , 40 ₁ , 40 ₂ , 40 ₃ ... Cutout piece, 100 to 103, 200 to 203, 300 to 303.

Claims (9)

  A circuit device in which a plurality of ICs having the same function and the same terminal arrangement are mounted on one or a plurality of printed boards, and the wiring pattern of the ICs in a region including the same IC mounting locations mounted on the printed boards Is a common circuit device.   The printed circuit board is composed of a multilayer wiring printed circuit board, and when the region including the IC mounting location is cut out from the printed circuit board as a cut piece, the wiring pattern exposed on the cut surface is shared by the cut piece. The circuit device according to claim 1.   The circuit board according to claim 2, wherein a via reaching the surface of the printed board is formed on the cut-out surface.   4. The circuit device according to claim 1, wherein an area including a mounting position of the IC on the printed board is provided with a marking as a mark at the time of cutting. 5.   The circuit device according to claim 4, wherein the marking is silk printing applied to a surface of the printed board.   The circuit device according to claim 4, wherein the marking is a via provided in the printed board.   The circuit device according to claim 1, wherein the wiring pattern includes a data line, an address line, and a clock line.   The circuit device according to claim 1, wherein the IC is a DDR (Double Data Rate) memory. A television apparatus comprising the circuit device according to claim 1.

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