JP2008176336A - Control circuit for electronic component, electro-optical device, electronic apparatus, and method of controlling the electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit suitable for accurately controlling a brightness value of a pixel by suppressing dispersions in the luminance. <P>SOLUTION: A data line drive circuit 102 controls the current value of a control signal, on the basis of digital data DAB of high-order eight bits among digital data In by each cycle T<SB>1</SB>. Based on the digital data SUB of low-order two bits among digital data In, the pulse width control for cycle T<SB>2</SB>is performed, with respect to a portion subjected to D/A conversion, on the basis of the same digital data among the control signals. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for generating a programming current supplied to a pixel circuit of a light emitting element for setting a light emission gradation based on a digital signal, and in particular, to suppress variations in luminance and to reduce the luminance of a pixel. The present invention relates to an electronic element control circuit, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device, an electronic apparatus, and an electronic element control method suitable for controlling a value with high accuracy.

An electro-optical device using an electro-optical element such as a liquid crystal element, an organic EL element (Organic Electroluminescent element), an electrophoretic element, or an electron-emitting element is suitable as a display device.
An active drive type electro-optical device including a pixel circuit is suitable as a high-quality display device (see, for example, Patent Document 1).

International Publication WO98 / 36407 Pamphlet

  However, in the electro-optical device, when adjusting the pixel to a low luminance value, there is a problem that the luminance varies greatly even if the same luminance value is set due to variations in pixel circuits. In particular, in an electro-optical device provided with a current drive element such as an organic EL element, the current is reflected as it is as the luminance, so that the problem of variation in luminance is remarkable.

On the other hand, in order to create a display device with higher added value, further improvement is required in terms of moving image characteristics and visibility.
Therefore, the present invention has been made paying attention to such an unsolved problem of the conventional technology, and is suitable for suppressing variation in luminance and controlling the luminance value of a pixel with high accuracy. It is an object of the present invention to provide an electronic element control circuit, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device, an electronic apparatus, and an electronic element control method.

  In order to solve the above-described problem, an electro-optical device according to the invention includes a pixel matrix in which pixels including light-emitting elements are arranged in a matrix, and is arranged along one of a row direction and a column direction of the pixel matrix. A plurality of scanning lines respectively connected to the pixel group, a plurality of data lines respectively connected to the pixel group arranged along the other of the row direction and the column direction of the pixel matrix, and connected to the plurality of scanning lines. In addition, a scanning line driving circuit that selects one of the rows and columns of the pixel matrix and a control signal having a current value corresponding to the light emission gradation of the light emitting element are generated based on the digital signal. A data line driving circuit for outputting a control signal to the plurality of data lines, the electro-optical device comprising: a set of digital data constituting the digital signal; In other words, data signals supplied to the plurality of pixel circuits via the plurality of data lines are generated based on the first digital data, and light emitting elements included in each of the plurality of pixel circuits according to the data signals The signal level supplied to the light emitting element for emitting light is determined, and the light emission timing of the light emitting element in a predetermined period is controlled based on the second digital data of the digital data. .

  With such a configuration, the light emission start timing and the light emission period of the light emitting element in a predetermined period (for example, one frame period) are controlled based on the second digital data of the digital data. Thereby, for example, impulse driving is possible, and it is possible to improve display characteristics during moving image display and to reduce visibility degradation factors such as pseudo contours.

  In the electro-optical device, the first digital data may be assigned upper bit data of the digital data, and the second digital data may be assigned lower bit data of the digital data.

  In the electro-optical device, it is preferable that the light emission timing of the light emitting element is controlled every time one of the plurality of scanning lines is selected by the scanning line driving circuit.

  In the electro-optical device, it is preferable that at least one light emission period of the light emitting element is provided in a predetermined period.

  In the electro-optical device, the data line driving circuit preferably includes a current addition type current generation circuit. It is further preferable to include a gate voltage generation circuit including an offset current generation circuit and a current mirror circuit.

  Furthermore, in the above electro-optical device, an output range of the current value output to the data line may be determined based on a reference voltage input to a current addition type current generation circuit.

[First embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 to 9 are diagrams showing a first embodiment of an electronic element control circuit, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device and an electronic apparatus, and an electronic element control method according to the present invention. .

  In this embodiment, a control circuit for an electronic element, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device, an electronic apparatus, and an electronic element control method according to the present invention are given from a computer 110 as shown in FIG. The present invention is applied to the case where the display panel unit 101 in which light emitting elements made of organic EL elements are arranged in a matrix is driven based on the digital data.

First, the configuration of the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a circuit configuration of an electro-optical device 100 as an embodiment of the present invention.
As shown in FIG. 1, the electro-optical device 100 includes a display panel unit 101 (also referred to as “pixel region”) in which light-emitting elements are arranged in a matrix, and a data line drive that drives data lines of the display panel unit 101. A circuit 102, a scanning line driving circuit 103 (also referred to as a “gate driver”) for driving the scanning lines of the display panel unit 101, a memory 104 for storing display data supplied from the computer 110, and other reference operation signals. A timing generation circuit 106 that supplies the components, a power supply circuit 107, and a control circuit 105 for controlling each component in the electro-optical device 100.

  Each of the components 101 to 107 of the electro-optical device 100 may be configured by independent components (for example, a one-chip semiconductor integrated circuit device), or all or part of the components 101 to 107. However, it may be configured as an integrated part. For example, the data line driving circuit 102 and the scanning line driving circuit 103 may be integrally formed on the display panel unit 101. Further, all or part of the constituent elements 102 to 106 may be configured by a programmable IC chip, and the function may be realized by software by a program written in the IC chip.

Next, the internal configurations of the display panel unit 101 and the data line driving circuit 102 will be described in detail with reference to FIG. FIG. 2 is a diagram illustrating an internal configuration of the display panel unit 101 and the data line driving circuit 102.
As shown in FIG. 2, the display panel unit 101 includes a plurality of pixel circuits 200 arranged in a matrix, and each pixel circuit 200 includes an organic EL element 220. The matrix of the pixel circuit 200 includes a plurality of data lines X _m (m = 1 to M) extending along the column direction and a plurality of scanning lines Y _n (n = 1 to N) extending along the row direction. Are connected to each other. The data line is also called a “source line”, and the scanning line is also called a “gate line”. In the present embodiment, the pixel circuit 200 is also referred to as “unit circuit” or “pixel”. Transistors in the pixel circuit 200 are usually composed of TFTs.

Scanning line drive circuit 103 is adapted to select one row of a group of pixel circuits 200 selectively drives one of among a plurality of scanning lines Y _n.
The data line driving circuit 102 converts a plurality of single line drivers 300 for driving each data line _Xm , a gate voltage generating circuit 400 for generating a gate voltage, and display data given from the control circuit 105. Data conversion circuit 500.

The gate voltage generation circuit 400 supplies a gate control signal having a predetermined voltage value to the single line driver 300. Details of the internal configuration of the gate voltage generation circuit 400 will be described later.
Single-line driver 300 is adapted to supply data signals to the pixel circuits 200 via the respective data lines X _m. When an internal state (described later) of the pixel circuit 200 is set according to the data signal, the current value flowing through the organic EL element 220 is controlled according to this, and as a result, the light emission gradation of the organic EL element 220 is changed. Be controlled. Details of the internal configuration of the single line driver 300 will be described later.

The data conversion circuit 500 operates in accordance with the timing signal from the timing generation circuit 106, and converts a 10-bit digital signal given as display data from the control circuit 105 into an 8-bit digital signal. Details of the internal configuration of the data conversion circuit 500 will be described later.
As shown in FIG. 1, the control circuit 105 converts display data representing the display state of the display panel unit 101 into matrix data representing the light emission gradation of each organic EL element 220. The matrix data includes a scanning line driving signal for sequentially selecting a group of pixel circuits 200 for one row and a data line driving signal indicating the level of a data line signal supplied to the organic EL element 220 of the selected pixel circuit 200 group. Including. The scanning line driving signal and the data line driving signal are supplied to the scanning line driving circuit 103 and the data line driving circuit 102, respectively. In addition, the control circuit 105 performs timing control of driving timings of the scanning lines and the data lines.

Next, the internal configuration of the pixel circuit 200 will be described in detail with reference to FIG. FIG. 3 is a diagram illustrating the internal structure of the pixel circuit 200.
The pixel circuit 200, as shown in FIG. 3 is a circuit disposed at the intersection of the m-th data line and the n th scan line Y _n. Note that the scanning line Y _n includes two sub-scanning lines V1 and V2.

The pixel circuit 200 is a current program circuit for adjusting the grayscale of the organic EL element 220 in accordance with the current flowing through the data line X _m. Specifically, the pixel circuit 200 includes four transistors 211 to 214 and a holding capacitor 230 (also referred to as “holding capacitor” or “storage capacitor”) in addition to the organic EL element 220. Holding capacitor 230 holds an electric charge corresponding to the data signal supplied through the data line X _m, thereby, is used to adjust the tone of the light emission of the organic EL element 220. In other words, the holding capacitor 230 holds a voltage corresponding to the current flowing through the data line X _m. The first to third transistors 211 to 213 are n-channel FETs, and the fourth transistor 214 is a p-channel FET. Since the organic EL element 220 is a current injection type (current drive type) light emitting element similar to a photodiode, it is represented by a symbol of a diode here.

The source of the first transistor 211 is connected to the drain of the second transistor 212, the drain of the third transistor 213, and the drain of the fourth transistor 214. The drain of the first transistor 211 is connected to the gate of the fourth transistor 214. The holding capacitor 230 is connected between the source and gate of the fourth transistor 214. The source of the fourth transistor 214 is also connected to the power supply potential V _dd .

The source of the second transistor 212 is connected to the single-line driver 300 (Fig. 2) via the data line X _m. The organic EL element 220 is connected between the source of the third transistor 213 and the ground potential.
The gates of the first and second transistors 211 and 212 are commonly connected to the first sub-scanning line V1. The gate of the third transistor 213 is connected to the second sub-scanning line V2.

  The first and second transistors 211 and 212 are switching transistors that are used when electric charge is accumulated in the holding capacitor 230. The third transistor 213 is a switching transistor that is kept on during the light emission period of the organic EL element 220. The fourth transistor 214 is a drive transistor for controlling the current value flowing through the organic EL element 220. The current value of the fourth transistor 214 is controlled by the amount of charge held in the holding capacitor 230 (accumulated charge amount).

Next, the operation of the pixel circuit 200 will be described in detail with reference to FIG. FIG. 4 is a timing chart showing the operation of the pixel circuit 200. In the figure, the voltage value of the first sub-scanning line V1 (hereinafter also referred to as “first gate signal V1”) and the voltage value of the second sub-scanning line V2 (hereinafter referred to as “second gate signal”). and V2 "is also referred to.), the current value I _out of the data line X _m (" data signal I _out "is also referred to.), it is shown and the current value I _EL flowing to the organic EL element 220.

Driving cycle T _c is divided into a programming period T _pr and a light emitting period T _el. Here, the “driving cycle T _c ” means a cycle in which the gradation of light emission of all the organic EL elements 220 in the display panel unit 101 is updated once, and is the same as a so-called frame cycle. is there. The gradation is updated for each group of pixel circuits 200 for one row, and the gradation of the pixel circuits 200 for N rows is sequentially updated during the driving cycle _Tc . For example, when the gradation of all the pixel circuits is updated at 30 [Hz], the drive cycle T _c is about 33 [ms].

The programming period T _pr is a period for setting the light emission gradation of the organic EL element 220 in the pixel circuit 200. In the present embodiment, the setting of gradation in the pixel circuit 200 is called “programming”. For example, when the driving period T _c is about 33 [ms] and the total number N of the scanning lines Y _n is 480, the programming period T _pr is about 69 [μs] (= 33 [ms] / 480. )

In the programming period T _pr , first, the second gate signal V2 is set to a low level to keep the third transistor 213 in an off state (closed state). Then, while flowing a current value I _m corresponding to the emission grayscale on the data line X _m, the first of the first and second on-state transistors 211 and 212 sets the gate signal V1 to the high level ( Open). In this case, the single-line driver 300 of the data lines X _m (Fig. 2) functions as a constant current source for supplying a constant current value I _m corresponding to the light emission gradation. As shown in FIG. 4C, the current value _Im is set to a value corresponding to the light emission gradation of the organic EL element 220 within a predetermined current value range RI.

The storage capacitor 230, the charge corresponding to the current value I _m flowing through the fourth transistor 214 (driving transistor) is retained. As a result, the voltage stored in the holding capacitor 230 is applied between the source / gate of the fourth transistor 214. In the present embodiment, the current value I _m of the data signal used for programming is referred to as “programming current value I _m ”.

When the programming is completed, the scanning line driving circuit 103 sets the first gate signal V1 to a low level to turn off the first and second transistors 211 and 212, and the data line driving circuit 102 outputs the data signal I Stop _out .
In the emission period T _el, the first and second transistors 211 and 212 to maintain the first gate signal V1 to the low level while maintaining the OFF state, to set the second gate signal V2 to the high level The third transistor 213 is set to an on state. Since the voltage corresponding to the programming current value I _m is stored in the holding capacitor 230 in advance, a current substantially the same as the programming current value I _m flows through the fourth transistor 214. Therefore, almost the same current flows programming current value I _m to the organic EL element 220 emits light at the gradation corresponding to the current value I _m. Thus, the type of the pixel circuit 200 the voltage of storage capacitor 230 (or charge) is written by the current value I _m is referred to as "current program circuit."

On the other hand, the timing generation circuit 106 supplies the timing signal REQ_A having the same period T _{1 as} the programming period T _pr to the control circuit 105 and the timing signal REQ_T having a period T _{2 that is} a quarter of the period T ₁ to the data line driving circuit 102. Each is designed to output. As a result, the control circuit 105 operates in the cycle T ₁ , and the data line driving circuit 102 operates in the cycle T ₂ that is a quarter cycle thereof.

Next, the internal configurations of the single line driver 300 and the gate voltage generation circuit 400 will be described in detail with reference to FIG. FIG. 5 is a circuit diagram showing the internal configuration of the single line driver 300 and the gate voltage generation circuit 400.
The single line driver 300 includes an 8-bit D / A converter unit 310 and an offset current generation circuit 320 as shown in FIG.

  The D / A converter unit 310 has eight current lines IU1 to IU8 connected in parallel. In the first current line IU1, a switching transistor 81, a resistance transistor 41 functioning as a kind of resistance element, and a driving transistor 21 functioning as a constant current source for supplying a predetermined current are connected to the data line 302 and the ground potential. Are connected in series. The other current lines IU2 to IU8 have the same configuration. These three types of transistors 81 to 88, 41 to 48, and 21 to 28 are all n-channel FETs in the example of FIG. The gates of the eight drive transistors 21 to 28 are commonly connected to the first common gate line 303. The gates of the eight resistance transistors 41 to 48 are connected in common to the second common gate line 304. A digital signal indicating each bit of the 8-bit gradation data DATA provided from the data conversion circuit 500 (FIG. 1) is input to each gate of the eight switching transistors 81 to 88 via the signal input line 301. .

The ratio K of the gain coefficients β of the eight drive transistors 21 to 28 is set to 1: 2: 4: 8: 16: 32: 64: 128. That is, the relative value K of the gain coefficient β of the nth (n = 1 to N) driving transistor is set to 2 ⁿ⁻¹ . Here, the gain coefficient β is defined by β = Kβ ₀ = (μC ₀ W / L) as is well known. Here, K is a relative value, β ₀ is a predetermined constant, μ is carrier mobility, C ₀ is a gate capacitance, W is a channel width, and L is a channel length. The number N of driving transistors is an integer of 2 or more. It should be noted that the number N of driving transistors is irrelevant to the number of scanning lines Y _n.

  The eight drive transistors 21 to 28 function as constant current sources. Since the current drive capability of the transistors is proportional to the gain coefficient β, the ratio of the current drive capabilities of the eight drive transistors 21 to 28 is 1: 2: 4: 8: 16: 32: 64: 128. In other words, the relative value K of the gain coefficient of each of the drive transistors 21 to 28 is set to a value associated with the weight of each bit of the gradation data DATA.

  Note that the current drive capability of the resistance transistors 41 to 48 is normally set to a value equal to or greater than the current drive capability of the corresponding drive transistors 21 to 28. Accordingly, the current drive capability of each of the current lines IU1 to IU8 is determined by the drive transistors 21 to 28. The resistance transistors 41 to 48 have a function as a noise filter that removes noise of a current value.

  The offset current generation circuit 320 has a configuration in which a resistance transistor 52 and a drive transistor 32 are connected in series between a data line 302 and a ground potential. The gate of the driving transistor 32 is connected to the first common gate line 303, and the gate of the resistance transistor 52 is connected to the second common gate line 304. The relative value of the gain coefficient β of the driving transistor 32 is Kb. In the offset current generation circuit 320, no switching transistor is provided between the drive transistor 32 and the data line 302, and this is different from each current line in the D / A converter unit 310.

The current line I _offset of the offset current generation circuit 320 is connected in parallel with the eight current lines IU1 to IU8 of the D / A converter unit 310. Therefore, the total of the currents flowing through these nine current lines I _offset and IU1 to IU8 is output on the data line 302 as a programming current. That is, the single line driver 310 is a current addition type current generation circuit. In the following, the symbols I _offset and IU1 to IU8 indicating the current lines are also used as symbols indicating the current flowing through them.

  The gate voltage generation circuit 400 includes a current mirror circuit unit composed of two transistors 71 and 72. The gates of the two transistors 71 and 72 are connected to each other, and the gate and drain of the first transistor 71 are also connected to each other. One terminal (source) of each of the two transistors 71 and 72 is connected to the power supply potential VDREF for the gate voltage generation circuit 400. A drive transistor 73 is connected in series on the first wiring 401 between the other terminal (drain) of the first transistor 71 and the ground potential. A control signal VRIN having a predetermined voltage level is input from the control circuit 105 to the gate of the drive transistor 73. On the second wiring 402 between the other terminal (drain) of the second transistor 72 and the ground potential, both the resistance transistor 51 and the constant voltage generating transistor 31 (“control electrode signal generating transistor”) Are connected in series. The relative value of the gain coefficient β of the constant voltage generating transistor 31 is Ka.

  The gate and the drain of the constant voltage generating transistor 31 are connected to each other, and these are connected to the first common gate line 303 of the single line driver 300. The gate and drain of the resistance transistor 51 are also connected to each other, and these are connected to the second common gate line 304 of the single line driver 300.

In the example of FIG. 5, the two transistors 71 and 72 constituting the current mirror circuit unit are configured by p-channel FETs, and the other transistors are configured by n-channel FETs.
When a control signal VRIN having a predetermined voltage level is input to the gate of the driving transistor 73 of the gate voltage generation circuit 400, a constant reference current I _const corresponding to the voltage level of the control signal VRIN is generated on the first wiring 401. appear. Since the two transistors 71 and 72 constitute a current mirror circuit section, the same reference current I _const flows also on the second wiring 402. However, the currents flowing through the two wirings 401 and 402 do not have to be the same, and in general, the first wiring so that a current proportional to the reference current I _const of the first wiring 401 flows on the second wiring 402. And the 2nd transistors 71 and 72 should just be comprised.

Predetermined gate voltages Vg1 and Vg2 corresponding to the current I _const are generated between the gates / drains of the two transistors 31 and 51 on the second wiring 402, respectively. The first gate voltage Vg <b> 1 is applied in common to the gates of the nine drive transistors 32 and 21 to 28 in the single line driver 300 via the first common gate line 303. The second gate voltage Vg <b> 2 is commonly applied to the gates of the nine resistance transistors 52 and 41 to 48 through the second common gate line 304.

The current drive capability of each current line I _offset , IU1 to IU8 is determined by the gain coefficient β of each drive transistor 32, 21 to 28 and the applied voltage. Therefore, a current value proportional to the relative value K of the gain coefficient β of each drive transistor can flow in each current line I _offset , IU1 to IU8 of the single line driver 300 according to the gate voltage Vg1. At this time, when 8-bit gradation data DATA is given from the control circuit 105 via the signal input line 301, the eight switching transistors 81 to 88 are turned on / off in accordance with the value of each bit of the gradation data DATA. Is done. As a result, the programming current I _m having a current value corresponding to the value of the grayscale data DATA is output on the data line 302.

Incidentally, the single-line driver 300, because it has an offset current generation circuit 320, the values and the programming current I _m of the grayscale data DATA, instead of the full proportional passing through the origin, has an offset Yes. Providing such an offset increases the degree of freedom in setting the programming current value range, so that the programming current value can be easily set within a preferred range.

FIG. 6 is an explanatory diagram illustrating Examples 1 to 5 of the relationship between the output current I _out of the data line driving circuit 102 and the value of the gradation data DATA (gradation value). In the table of FIG. 6A, a standard example 1 and examples 2 to 5 when the following four parameters are changed are shown.
(1) VRIN: the voltage value of the gate signal of the drive transistor 73 of the gate voltage generation circuit 400.
(2) VDREF: power supply voltage of the current mirror circuit section of the gate voltage generation circuit 400. (3) Ka: Relative value of the gain coefficient β of the constant voltage generating transistor 31 of the gate voltage generating circuit 400.
(4) Kb: relative value of the gain coefficient β of the drive transistor 32 of the offset current generation circuit 320.

  FIG. 6B is a graph showing the relationship of FIG. Note that Example 1 which is “standard” is an example in which each parameter is set to a predetermined standard value. Example 2 is an example in which only the voltage VRIN of the drive transistor 73 is set to a higher value than the standard example 1. Example 3 is an example in which only the power supply voltage VDREF of the current mirror circuit section is set to a higher value than in the standard example 1. Example 4 is an example in which only the relative value Ka of the gain coefficient β of the constant voltage generating transistor 31 is set to a larger value than in the standard example 1. Example 5 is an example in which only the relative value Kb of the gain coefficient β of the drive transistor 32 is set to a larger value than the standard example 1.

These as shown in Table and graphs, the value of the output current I _out, each parameter VRIN, VDREF, Ka, changes according to Kb. Therefore, by changing one or more values of these parameters, the range of current values used for controlling the light emission gradation can be changed. Note that the values of the parameters VRIN, VDREF, Ka, and Kb are set by adjusting design values of circuit portions related to the parameters VRIN, VDREF, Ka, and Kb. In the circuit configuration shown in FIG. 5, four parameters VRIN, VDREF, Ka, since both Kb influences the range of the output current I _out, a high degree of freedom in setting the range of output current I _out, There is an advantage that it can be easily set to an arbitrary range.

By the way, the output current I _out is proportional to the reference current I _const in the gate voltage generation circuit 400. Accordingly, the reference current I _const is determined according to the range of current values required for the output current I _out (ie, the programming current I _m ). At this time, if the value of the reference current I _const is set in the vicinity of both ends of the current value range required as the output current I _out , a small variation (error) in the reference current I _const depending on the performance of the circuit component. However, there is a possibility that a large variation (error) of the output current _Iout may occur. Therefore, in order to reduce the error of the output current I _out is the value of the reference current I _const, it is preferable to set the value of the intermediate vicinity of the maximum value and the minimum value of the range of the current value of the output current I _out. Here, “in the vicinity of the maximum value and the minimum value” means a range of about ± 10% of the average value (that is, the median value) of the maximum value and the minimum value.

Next, the configuration of the data conversion circuit 500 will be described in detail with reference to FIGS. FIG. 7 is a diagram illustrating a conversion rule of the data conversion circuit 500. FIG. 8 is a time chart showing the operation of the data conversion circuit 500. For description, FIGS. 7 and 8 focus on one line in the Y direction. (Same operation as when N = 1.)
As shown in FIGS. 7 and 8, the data conversion circuit 500 inputs 10-bit digital data In as display data from the memory 104 every cycle T ₁ , and converts the input digital data In to the upper 8-bit first data. 1 digital data DAB and second low-order second digital data SUB are output, and 8-bit digital data Out is output to single line driver 300 based on the value of digital data SUB every period T _2. It is supposed to be.

In FIG. 8, REQ_A is a timing signal of period T ₁ , REQ_T is a timing signal of period T ₂ , and R [9: 0] is 10-bit digital data In indicating red light emission gradation. , G [9: 0] indicate 10-bit digital data In indicating green light emission gradation, and B [9: 0] indicate 10-bit digital data In indicating blue light emission gradation. . Also, R [9: 2] is 8-bit digital data Out indicating red light emission gradation, G [9: 2] is 8-bit digital data Out indicating green light emission gradation, and B [ 9: 2] respectively indicate 8-bit digital data Out indicating the light emission gradation of blue.

Specifically, when the value of the digital data SUB is “00”, the cycle T ₁ is configured to be exactly four times the cycle T ₂ as shown in the first row of the table on the right side of FIG. Therefore, the digital data DAB is output to the single line driver 300 as the digital data Out until the period T ₁ elapses. This conversion output is performed for each element of RGB data. Thus, from the single-line driver 300, the current I _out expressed by the following equations (1) when viewed on average in the period T ₁ is outputted. In the following equation (1), k is a predetermined coefficient, and DAB is a value when the digital data DAB is converted into a decimal number.
_Iout = K * DAB * 4/4 (1)

When the value of the digital data SUB is "01", as shown in the second row of FIG. 7 right side of the table, the first T _s1 period T ₂ from the beginning of the period T ₁ is passed Until this time, the digital data DAB plus “1” is output to the single line driver 300 as digital data Out, and the digital data DAB is converted into digital data until the remaining time of the period T ₁ elapses. Output to the single line driver 300 as Out. This conversion output is performed for each element of RGB data. Thus, from the single-line driver 300, output current I _out expressed by the following equations (2) when in the cycle T ₁ has on average.
I _out = K × {(DAB + 1) + DAB × 3} / 4 (2)

When the value of the digital data SUB is “10”, as shown in the third row of the table on the right side of FIG. 7, the second T _s2 of the cycle T ₂ elapses from the beginning of the cycle T _1. Until this time, the digital data DAB plus “1” is output to the single line driver 300 as digital data Out, and the digital data DAB is converted into digital data until the remaining time of the period T ₁ elapses. Output to the single line driver 300 as Out. This conversion output is performed for each element of RGB data. Thus, from the single-line driver 300, output current I _out expressed by the following equations (3) when in the cycle T ₁ has on average.
I _out = K × {(DAB + 1) × 2 + DAB × 2} / 4 (3)

When the value of the digital data SUB is “11”, the third T _s3 of the cycle T ₂ elapses from the beginning of the cycle T ₁ as shown in the fourth row of the table on the right side of FIG. Until this time, the digital data DAB plus “1” is output to the single line driver 300 as digital data Out, and the digital data DAB is converted into digital data until the remaining time of the period T ₁ elapses. Output to the single line driver 300 as Out. This conversion output is performed for each element of RGB data. Thus, from the single-line driver 300, output current I _out expressed by the following equations (4) when in the cycle T ₁ has on average.
I _out = K × {(DAB + 1) × 3 + DAB} / 4 (4)

  Next, the operation of the present embodiment will be described with reference to FIG. FIG. 9 is a graph showing a change in luminance value of the pixel circuit 200 according to the value of the digital data In.

When the pixel circuit 200 in the display panel unit 101 is caused to emit light, the control circuit 105 operates in accordance with the timing signal REQ_A from the timing generation circuit 106 when the number of scanning lines is N, and operates every cycle T ₁ / N. The circuit 102 and the scanning line driving circuit 103 are controlled.
First, the control circuit 105 controls the scanning line driving circuit 103. As a result, the scanning line Y _n is driven by the scanning line driving circuit 103 and one row of the pixel matrix in the display panel unit 101 is selected. Thereby, the pixel circuit 200 group arranged along the row direction of the pixel matrix is selected.

On the other hand, the control circuit 105 controls the data line driving circuit 102 independently of this. In the control of the data line driving circuit 102, the display data is read from the memory 104 in units of 10 bits every cycle T ₁ / N by the timing signal REQ_A from the timing generation circuit 106, and indicates the read display data. A digital signal is input to the data line driving circuit 102.

In the data line driving circuit 102, when a digital signal is given, the digital data In inputted by the data conversion circuit 500 every cycle T ₁ / N is converted into upper 8 bits of digital data DAB and lower 2 bits of digital data. The 8-bit digital data Out is output to the single line driver 300 based on the value of the digital data SUB for each period T ₂ / N.

If the value of the digital data SUB is “00”, the digital data DAB is output to the single line driver 300 as the digital data Out until the period T ₁ elapses. As a result, the current I _out corresponding to the value of the digital data Out is output from the single line driver 300, and the control signal of the current I _out is input to the group of pixel circuits 200 arranged along the column direction of the pixel matrix. The Therefore, since the pixel circuit 200 programs the control signal with the same programming period T _{pr as} the period T ₁ / N, the pixel circuit 200 group selected by the scanning line driving circuit 103 and the data line driving circuit 102 are controlled. The pixel circuit 200 common to the group of pixel circuits 200 to which the signal is input emits light with a luminance value corresponding to the current I _out that is a value represented by the above formula (1).

If the value of the digital data SUB is "01", between the beginning of the period T ₁ until the first T _s1 period T ₂ has elapsed, those obtained by adding "1" to the digital data DAB The digital data DAB is output to the single line driver 300 as the digital data Out until the remaining time of the period T ₁ elapses. As a result, the current I _out corresponding to the value of the digital data Out is output from the single line driver 300, and the control signal of the current I _out is input to the group of pixel circuits 200 arranged along the column direction of the pixel matrix. The Therefore, since the pixel circuit 200 programs the control signal with the same programming period T _{pr as} the period T ₂ / N, the pixel circuit 200 group selected by the scanning line driving circuit 103 and the data line driving circuit 102 are controlled. The pixel circuit 200 common to the group of pixel circuits 200 to which the signal is input emits light with a luminance value corresponding to the current I _out having a value represented by the above equation (2).

If the value of the digital data SUB is "10", between the beginning of the period T ₁ until the second T _s2 of the cycle T ₂ has elapsed, those obtained by adding "1" to the digital data DAB The digital data DAB is output to the single line driver 300 as the digital data Out until the remaining time of the period T ₁ elapses. As a result, the current I _out corresponding to the value of the digital data Out is output from the single line driver 300, and the control signal of the current I _out is input to the group of pixel circuits 200 arranged along the column direction of the pixel matrix. The Therefore, since the pixel circuit 200 programs the control signal with the same programming period T _{pr as} the period T ₂ / N, the pixel circuit 200 group selected by the scanning line driving circuit 103 and the data line driving circuit 102 are controlled. The pixel circuit 200 common to the group of pixel circuits 200 to which the signal is input emits light with a luminance value corresponding to the current _Iout having a value represented by the above equation (3).

If the value of the digital data SUB is "11", between the beginning of the period T ₁ to the third T _s3 of the cycle T ₂ has elapsed, those obtained by adding "1" to the digital data DAB The digital data DAB is output to the single line driver 300 as the digital data Out until the remaining time of the period T ₁ elapses. As a result, the current I _out corresponding to the value of the digital data Out is output from the single line driver 300, and the control signal of the current I _out is input to the group of pixel circuits 200 arranged along the column direction of the pixel matrix. The Therefore, since the pixel circuit 200 programs the control signal with the same programming period T _{pr as} the period T ₂ / N, the pixel circuit 200 group selected by the scanning line driving circuit 103 and the data line driving circuit 102 are controlled. The pixel circuit 200 common to the group of pixel circuits 200 to which the signal is input emits light with a luminance value corresponding to the current _Iout having a value represented by the above equation (4).

FIG. 9 shows a comparison in the case where the pixel circuit 200 is driven using the 8-bit D / A converter unit 310 between the present embodiment and the analog system. In the analog method, when the control circuit 105 gives 10-bit digital data In to the data line driving circuit 102, the upper 2 bits of digital data or the lower 2 bits of digital data are ignored, and the remaining 8 bits of digital data are converted. Since the D / A conversion is performed based on this, as shown by the circled plots and dotted lines in FIG. 9, it is only possible to set the luminance value in a stepwise manner for each of the four data (data for 2 bits). On the other hand, in the present embodiment, when the control circuit 105 gives 10-bit digital data to the data line driving circuit 102, D / A conversion is performed based on the upper 8-bit digital data DAB. However, based on the lower 2 bits of the digital data SUB, the pulse width control of the period T ₂ is performed on the part of the control signal that is D / A converted based on the same digital data In. As shown by the plot and solid line, different brightness values can be set for each data.

  Therefore, when the same D / A converter unit 310 is used, the luminance value of the pixel circuit 200 can be adjusted with four times the accuracy as compared with the analog method. On the other hand, in order to achieve the same accuracy, the D / A converter unit 310 can be configured with 6 bits, so that the circuit scale is reduced as compared with the analog system.

On the other hand, in comparison with the conventional digital method, when the operating frequency of the data line driving circuit 102 is set to the same frequency, the accuracy is complemented by D / A conversion in addition to the pulse width control. Compared with the digital method, the luminance value of the pixel circuit 200 can be adjusted with high accuracy. On the contrary, when the same accuracy is to be realized, for the same reason, it is not necessary to set the frequency of the period T ₂ / N higher than that of the conventional digital method.

Thus, in the present embodiment, the data line driving circuit 102 controls the current value of the control signal based on the upper 8 bits of the digital data DAB in the digital data In every cycle T ₁ / N, Based on the low-order 2-bit digital data SUB of the digital data In, the pulse width control of the cycle T ₂ / N is performed on the portion of the control signal that is D / A converted based on the same digital data. .

Accordingly, the pixel circuit 200 can be controlled with relatively high accuracy without using a transistor with a small capacitance as the single line driver 300. Also, it is not necessary to set the frequency of the period T ₂ higher than when the same accuracy is realized by the digital method. Accordingly, it is possible to suppress the luminance variation and control the luminance value of the pixel with relatively high accuracy as compared with the related art.

In the first embodiment, the pixel circuit 200 corresponds to the electronic device of the inventions 1 to 4, 19 to 21, or the light emitting device of the invention 11, 13 or 16, and the cycle T ₁ is the inventions 1 to 3, Corresponding to the first period of 11, 12, 14, 19 or 20, the period T ₂ corresponds to the second period of the inventions 1 to 3, 11, 12, 14, 19 or 20. The data conversion circuit 500 and the single line driver 300 correspond to the first current value setting means of the invention 2, 3, 11 or 12, or the second current value setting means of the invention 2, 3, 11 or 12, The D / A conversion by the data conversion circuit 500 and the single line driver 300 corresponds to the first current value setting step of the invention 19 or 20.

In the first embodiment, the pulse width control by the data conversion circuit 500 and the single line driver 300 corresponds to the second current value setting step of the invention 19 or 20.
In the first embodiment, the pixel circuit 200 corresponds to the electronic element of the invention 5, and the data conversion circuit 500 and the single line driver 300 correspond to the sub period setting means of the invention 5.
The upper 2 bits may be the second digital data SUB, and the lower 8 bits may be the first digital data DAB. In other words, the number of data for setting the period may be larger than the number of data for setting the luminance level. As a result, it is possible to set many sub-periods or improve the time resolution.
By appropriately selecting the number of data for setting the period and the number of data for setting the luminance level, it is possible to give priority to either the time-axis resolution or the luminance level resolution.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a diagram showing a second embodiment of an electronic element control circuit, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device and an electronic device, and an electronic element control method according to the present invention. Hereinafter, only different parts from the first embodiment will be described, and overlapping parts will be denoted by the same reference numerals and description thereof will be omitted.

In this embodiment, a control circuit for an electronic element, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device, an electronic apparatus, and an electronic element control method according to the present invention are given from a computer 110 as shown in FIG. The present invention is applied to the case of driving the display panel unit 101 in which light emitting elements composed of organic EL elements are arranged in a matrix based on the digital data, and differs from the first embodiment in that the period is is the portion for performing pulse width control of T _2.

First, the configuration of the present embodiment will be described with reference to FIG. FIG. 10 is a time chart showing the output of the digital data Out during the period T ₁ . For the sake of explanation, FIG. 10 focuses on one line in the Y direction. (The operation is the same as when N = 1.) In FIG. 10, DAB is the value of digital data DAB, and SUB is the value of digital data SUB.

The timing generation circuit 106 outputs a timing signal REQ_A having a period T ₁ to the control circuit 105 and a timing signal REQ_T having a period T _{2 that} is 1/16 of the period T ₁ to the data line driving circuit 102. As a result, the control circuit 105 operates in the cycle T ₁ , and the data line driving circuit 102 operates in the cycle T ₂ that is 1/16 of the cycle.

The single line driver 300 includes a 4-bit D / A converter unit 310 and an offset current generation circuit 320.
As shown in FIG. 10, the data conversion circuit 500 inputs 8-bit digital data In as display data from the control circuit 105 every cycle T ₁ , and converts the input digital data In into higher-order 4-bit digital data DAB. If, separated into lower 4-bit digital data SUB, in every cycle T _2, and outputs a 4-bit digital data Out to the single-line driver 300 based on the value of the digital data SUB. Specifically, since the cycle T ₁ is configured to be exactly 16 times the cycle T ₂ , the digital data SUB is regarded as a numerical value from “0” to “15”, and as shown in FIG. _From the beginning of ₁ until the time obtained by multiplying the value of the digital data SUB by the period T ₂ , the digital data DAB plus “1” is output to the single line driver 300 as the digital data Out, The digital data DAB is output to the single line driver 300 as digital data Out until the remaining time elapses in the period T ₁ .

Next, the operation of the present embodiment will be described.
When the pixel circuit 200 in the display panel unit 101 is caused to emit light, the control circuit 105 operates in accordance with the timing signal REQ_A from the timing generation circuit 106 when the number of scanning lines is N, and operates every cycle T ₁ / N. The circuit 102 and the scanning line driving circuit 103 are controlled.

First, the control circuit 105 controls the scanning line driving circuit 103. As a result, the scanning line Y _n is driven by the scanning line driving circuit 103 and one row of the pixel matrix in the display panel unit 101 is selected. Thereby, the pixel circuit 200 group arranged along the row direction of the pixel matrix is selected.
On the other hand, the control circuit 105 controls the data line driving circuit 102 independently of this. In the control of the data line driving circuit 102, the display data is read from the memory 104 in units of 8 bits for each cycle T ₁ / N by the timing signal REQ_A from the timing generation circuit 106, and indicates the read display data. A digital signal is input to the data line driving circuit 102.

In the data line driving circuit 102, when a digital signal is given, the digital data In input by the data conversion circuit 500 every cycle T ₁ / N is converted into upper 4 bits of digital data DAB and lower 4 bits of digital data. 4 bits of digital data Out are output to the single line driver 300 on the basis of the value of the digital data SUB every period T ₂ / N.

Specifically, digital data DAB is obtained by adding “1” to digital data DAB from the beginning of period T ₁ / N until the time obtained by multiplying the value of digital data SUB by period T ₂ / N has elapsed. The digital data DAB is output to the single line driver 300 as the digital data Out until the remaining time of the period T ₁ / N elapses. As a result, the current I _out corresponding to the value of the digital data Out is output from the single line driver 300, and the control signal of the current I _out is input to the group of pixel circuits 200 arranged along the column direction of the pixel matrix. The Therefore, since the pixel circuit 200 programs the control signal with the same programming period T _{pr as} the period T ₂ / N, the pixel circuit 200 group selected by the scanning line driving circuit 103 and the data line driving circuit 102 are controlled. The pixel circuit 200 common to the group of pixel circuits 200 to which the signal is input emits light with a luminance value corresponding to the value of the digital data In. That is, even if the resolution of the D / A converter unit 310 is 4 bits, the luminance value of the pixel circuit 200 can be adjusted with an accuracy of 8 bits.

Thus, in the present embodiment, 8-bit digital data In is input as display data from the control circuit 105 every cycle T ₁ / N, and the input digital data In is converted into the upper 4-bit digital data DAB. And the lower 4 bits of the digital data SUB, and from the beginning of the cycle T ₁ / N until the time obtained by multiplying the value of the digital data SUB by the cycle T ₂ / N has elapsed, 1 "is output to the single line driver 300 as the digital data Out, and the digital data DAB is used as the digital data Out until the remaining time elapses in the period T ₁ / N. Therefore, an effect equivalent to that of the first embodiment can be obtained.

In the second embodiment, the pixel circuit 200 corresponds to the electronic device of the inventions 1 to 4, 19 to 21, or the light emitting device of the invention 11, 13 or 16, and the cycle T ₁ is the inventions 1 to 3, Corresponding to the first period of 11, 12, 14, 19 or 20, the period T ₂ corresponds to the second period of the inventions 1 to 3, 11, 12, 14, 19 or 20. The data conversion circuit 500 and the single line driver 300 correspond to the first current value setting means of the invention 2, 3, 11 or 12, or the second current value setting means of the invention 2, 3, 11 or 12, The D / A conversion by the data conversion circuit 500 and the single line driver 300 corresponds to the first current value setting step of the invention 19 or 20.

In the second embodiment, the pulse width control by the data conversion circuit 500 and the single line driver 300 corresponds to the second current value setting step of the invention 19 or 20.
In the second embodiment, the pixel circuit 200 corresponds to the electronic element of the invention 5, and the data conversion circuit 500 and the single line driver 300 correspond to the sub period setting means of the invention 5.

[Third embodiment]
Next, a third embodiment of the present invention will be described with reference to the drawings. 11 and 12 are diagrams showing a third embodiment of the electronic element control circuit, the electronic circuit, the electro-optical device, the semiconductor integrated circuit device, the electronic apparatus, and the electronic element control method according to the present invention. . Hereinafter, only different parts from the first embodiment will be described, and overlapping parts will be denoted by the same reference numerals and description thereof will be omitted.

In this embodiment, a control circuit for an electronic element, an electronic circuit, an electro-optical device, a semiconductor integrated circuit device, an electronic apparatus, and an electronic element control method according to the present invention are given from a computer 110 as shown in FIG. The present invention is applied to the case of driving the display panel unit 101 in which light emitting elements composed of organic EL elements are arranged in a matrix based on the digital data, and differs from the first embodiment in that the period is is the portion for performing pulse width control of T _2.

First, the configuration of the present embodiment will be described with reference to FIG. 11 and FIG. FIG. 11 is a block diagram showing a configuration of the data conversion circuit 500. FIG. 12 is a time chart showing the output of the digital data Out during the period T ₁ . For explanation, FIGS. 11 and 12 focus on one line in the Y direction. (Same operation as when N = 1.)
The timing generation circuit 106 outputs a timing signal REQ_A having a period T ₁ to the control circuit 105 and a timing signal REQ_T having a period T _{2 that} is 1/16 of the period T ₁ to the data line driving circuit 102. As a result, the control circuit 105 operates in the cycle T ₁ , and the data line driving circuit 102 operates in the cycle T ₂ that is 1/16 of the cycle.

The single line driver 300 includes a 4-bit D / A converter unit 310 and an offset current generation circuit 320.
As shown in FIG. 11, the data conversion circuit 500 includes an adder 501 that adds the digital data In and the previous digital data Out in the memory 104, and the lower order of the digital data (8 bits) that is the addition result of the adder 501. An arithmetic unit 502 that sets 4 bits to “0” and a subtracting unit 503 that subtracts the digital data (8 bits) that is the operation result of the arithmetic unit 502 from the digital data that is the addition result of the adder 501. In addition, the digital data (8 bits) as the calculation result of the calculation unit 502 is output to the single line driver 300 as the digital data Out, and the digital data as the subtraction result of the subtraction unit 503 is stored in the memory 104. ing.

This is because, for each period T ₁ , 8-bit digital data In is input as display data from the control circuit 105, and the input digital data In is converted into upper 4-bit digital data DAB and lower 4-bit digital data SUB. The digital data SUB is added by the components 501 to 503 every cycle T ₂ , and when a carry of the fourth bit occurs, “1” is added to the digital data DAB (by carry) This is a circuit that operates so as to output the added data to the single line driver 300 as digital data Out, and to output the digital data DAB to the single line driver 300 as digital data Out otherwise.

For example, when the digital data SUB is “0001”, the 16th T _s16 of the cycle T ₂ in the cycle T ₁ is output by adding “1” to the digital data DAB, and the digital data SUB is “0010”. ", The digital data DAB plus" 1 "is output for the _{eighth and sixteenth} T _s8 and T _s16 of the cycle T ₂ in the cycle T ₁ . That is, the digital data DAB added with “1” is output in a distributed manner rather than continuously from the beginning during the period T ₁ .

Next, the operation of the present embodiment will be described.
When the pixel circuit 200 in the display panel unit 101 is caused to emit light, the control circuit 105 operates every cycle T ₁ by the timing signal REQ_A from the timing generation circuit 106, and the data line driving circuit 102 and the scanning line driving circuit 103 respectively control. Is done.

First, the control circuit 105 controls the scanning line driving circuit 103. As a result, the scanning line Y _n is driven by the scanning line driving circuit 103 and one row of the pixel matrix in the display panel unit 101 is selected. Thereby, the pixel circuit 200 group arranged along the row direction of the pixel matrix is selected.
On the other hand, the control circuit 105 controls the data line driving circuit 102 independently of this. In the control of the data line driving circuit 102, the display data is read from the memory 104 in units of 8 bits at every cycle T ₁ by the timing signal REQ_A from the timing generation circuit 106, and a digital signal indicating the read display data Is input to the data line driving circuit 102.

In the data-line drive circuit 102, when a digital signal is applied, the data conversion circuit 500, a digital data In input in every cycle T ₁ is a upper 4-bit digital data DAB and lower 4-bit digital data SUB are separated, in every cycle T _2, based on the value of the digital data SUB is 4-bit digital data Out is output to the single-line driver 300.

Specifically, the digital data SUB is added every cycle T ₂ , and when there is a carry of the fourth bit, the digital data DAB plus “1” is the single digital data Out. In other cases, the digital data DAB is output to the single line driver 300 as digital data Out. As a result, the current I _out corresponding to the value of the digital data Out is output from the single line driver 300, and the control signal of the current I _out is input to the group of pixel circuits 200 arranged along the column direction of the pixel matrix. The Therefore, since the pixel circuit 200 programs the control signal in the same programming period T _{pr as} the period T ₁ , the control signal is transmitted from the pixel circuit 200 group selected by the scanning line driving circuit 103 and the data line driving circuit 102. The pixel circuit 200 common to the input pixel circuit 200 group emits light with a luminance value corresponding to the value of the digital data In. That is, even if the resolution of the D / A converter unit 310 is 4 bits, the luminance value of the pixel circuit 200 can be adjusted with an accuracy of 8 bits.

Thus, in the present embodiment, 8-bit digital data In is input as display data from the control circuit 105 every cycle T ₁ , and the input digital data In is converted into the upper 4-bit digital data DAB, This is separated into the lower 4 bits of digital data SUB, and the digital data SUB is added every cycle T _2. When there is a carry of the 4th bit, “1” is added to the digital data DAB. Is output to the single line driver 300 as digital data Out, and otherwise, the digital data DAB is output to the single line driver 300 as digital data Out. The same effect can be obtained.

In the third embodiment, the pixel circuit 200 corresponds to the electronic device of the inventions 1 to 4, 19 to 21, or the light emitting device of the invention 11, 13 or 16, and the cycle T ₁ is the inventions 1 to 3, Corresponding to the first period of 11, 12, 14, 19 or 20, the period T ₂ corresponds to the second period of the inventions 1 to 3, 11, 12, 14, 19 or 20. The data conversion circuit 500 and the single line driver 300 correspond to the first current value setting means of the invention 2, 3, 11 or 12, or the second current value setting means of the invention 2, 3, 11 or 12, The D / A conversion by the data conversion circuit 500 and the single line driver 300 corresponds to the first current value setting step of the invention 19 or 20.

In the third embodiment, the pulse width control by the data conversion circuit 500 and the single line driver 300 corresponds to the second current value setting step of the invention 19 or 20.
In the third embodiment, the pixel circuit 200 corresponds to the electronic element of the invention 5, and the data conversion circuit 500 and the single line driver 300 correspond to the sub period setting means of the invention 5.

[Fourth Embodiment]
It is also possible to directly generate a period control signal based on a part of the digital data In.
For example, the digital data In is separated by the data separation circuit 600 into the first digital data DAB and the second digital data SUB, and the first digital data DAB is input to the data conversion circuit 500. Here, the data conversion circuit 500 may have a function of changing the number of bits of the input first digital data DAB. Further, parallel may be converted into serial, or conversely, serial may be converted into parallel according to the transmission format of the data signal to the data line.

On the other hand, the second digital data SUB is input to the timing control circuit 601. A timing control circuit 601 generates a period control signal based on the second digital data SUB, and a second gate signal V2 functioning as a period control signal is supplied to each pixel via the scanning line driving circuit 103. Supplied to the circuit.
As shown in FIG. 14, the digital data In includes first digital data DAB composed of data corresponding to the data signals X _{1 to} X _m to be supplied to the respective data lines and second digital data that is the basis of the timing control signal. It consists of data SUB. As described above, the first digital data DAB is supplied to the data line driving circuit, the data signal supplied to the data line is generated, and is supplied via the scanning line driving circuit based on the second digital data SUB. A light emission period control signal or timing control signal is generated.

  FIG. 15 shows a timing chart of the first gate signal V1 and the second gate signal V2 in the pixel circuit shown in FIG. Within a period in which a data signal is written by supplying a first gate signal V1 that turns on a transistor 211 that controls conduction between the data line and a transistor 212 that controls conduction between the drain and gate of the transistor 214. Supplies a second gate signal for turning off the transistor 213 that controls the conduction state between the transistor 214 and the organic EL element 220. After writing the data signal to the pixel circuit, even if the first gate signal V1 for turning off the transistor 211 and the transistor 212 starts to be supplied, the transistor 213 is turned off for a while and the organic EL element 220 is supplied to the organic EL element 220. Current supply is stopped. After that, a second gate signal for turning on the transistor 213 is supplied to electrically connect the organic EL element 220 and the transistor 214, and the organic EL element 220 emits light with luminance according to the data signal.

  The first gate signal V1 for turning off the transistor 211 for controlling the conduction state with the data line and the transistor 212 for controlling the conduction state between the drain and the gate of the transistor 214 is supplied, and at the same time, the Y counter of the timing control circuit 601 Is reset. The second gate signal for turning on the transistor 213 is supplied until the data of the sub period set in the second digital data SUB becomes equal to the value of the Y counter.

By setting the second digital data SUB corresponding to a desired sub-period or sub-frame, as shown in FIG. 16, the sub-period is set for each frame (corresponding to the cycle T ₁ in this embodiment). Can be set.

[Fifth Embodiment]
In order to improve moving image characteristics, it may be preferable that the pixel circuits provided for a plurality of scanning lines simultaneously perform black display or set the luminance to 0.
In the present embodiment, as shown in FIG. 17, sub-periods with luminance 0 (shown as Off) are simultaneously set for pixel circuits corresponding to a plurality of scanning lines.
Hereinafter, a method for simultaneously setting periods of luminance 0 (illustrated as Off) for pixel circuits corresponding to a plurality of scanning lines will be specifically described.
For ease of explanation, it is assumed that there are four scanning lines, the time from when one scanning line is selected and the data signal is written is equal to the second period (T ₂ ). In the second digital data SUB shown in FIG. 18, “1” corresponds to a state where the transistor 214 and the organic EL element 220 are electrically connected via the transistor 213, and “0” corresponds to the transistor 214. This corresponds to a state where the organic EL element 220 is electrically disconnected. In FIG. 18, the initial position of the second digital data SUB is shown to be shifted for easy understanding.

Since the data signal is written with the transistor 213 turned off, the second digital data SUB starts from “0”. “0” of the second digital data SUB is input corresponding to the sub-period of luminance 0 having a length corresponding to three of the second period (T ₂ ).
At the same time when the first gate signal V1 through the scanning line Y ₁ (Y ₁₎ is supplied, a second gate which is generated based on the second digital data SUB corresponding to the scanning line Y ₁ (Y ₁₎ Supply of the signal V2 (Y ₁ ) is started. As described above, the second gate signal V2 (Y ₂ ) for turning off the transistor 213 corresponding to “0” at the left end of the second digital data SUB (Y ₁ ), corresponding to the next “1”. and, a second gate signal to the transistor 213 in the oN state V2 (Y ₂₎ · · ·, a second gate signal based on the second digital data SUB (Y ₁₎ and so V2 (Y ₁₎ Is supplied. The supply of the first gate signal V1 (Y ₂ ) of the next scanning line Y ₂ starts after a predetermined time delay from the supply start time of the first gate signal V1 (Y ₁ ). Here, it starts with a delay of the second period T _2. Similarly, for the scanning line Y _2, the second gate signal V2 generated based on the second digital data _{SUB (Y 2) (Y 2} ) it is supplied.
Thereafter, the same operation is performed. As a result, an off period in which the luminance of the organic EL element 220 is simultaneously set to 0 is set for all the scanning lines.

In the first to third embodiments, the display device using the organic EL element has been described. However, the display device using the organic EL element may be a mobile personal computer, a mobile phone, a digital device, or the like. The present invention can be applied to various electronic devices such as a still camera.
FIG. 19 is a perspective view illustrating a configuration of a mobile personal computer. The personal computer 1000 includes a main body 1040 including a keyboard 1020 and a display unit 1060 using an organic EL element.

FIG. 20 is a perspective view of a mobile phone. The cellular phone 2000 includes a plurality of operation buttons 2020, an earpiece 2040, a mouthpiece 2060, and a display panel 2080 using an organic EL element.
FIG. 21 is a perspective view showing the configuration of the digital still camera 3000. Note that the connection with an external device is also shown in a simplified manner. A normal camera sensitizes a film with an optical image of a subject, whereas a digital still camera 3000 generates an imaging signal by photoelectrically converting an optical image of an object by an image sensor such as a CCD (Charge Coupled Device). is there. Here, a display panel 3040 using an organic EL element is provided on the back surface of the case 3020 of the digital still camera 3000, and display is performed based on an image pickup signal by the CCD. Therefore, the display panel 3040 functions as a finder that displays the subject. A light receiving unit 3060 including an optical lens, a CCD, and the like is provided on the observation side (the back side in the drawing) of the case 3020.

  Here, when the photographer confirms the subject image displayed on the display panel 3040 and presses the shutter button 3080, the CCD image pickup signal at that time is transferred and stored in the memory of the circuit board 3100. In the digital still camera 3000, a video signal output terminal 3120 and an input / output terminal 3140 for data communication are provided on the side surface of the case 3020. As shown in the figure, a television monitor 4300 is connected to the former video signal output terminal 3120 and a personal computer 4400 is connected to the latter input / output terminal 3140 for data communication as required. The Further, an imaging signal stored in the memory of the circuit board 3100 is output to the television monitor 4300 or the personal computer 4400 by a predetermined operation.

  In addition to the personal computer shown in FIG. 19, the mobile phone shown in FIG. 20, and the digital still camera shown in FIG. 21, the electronic equipment includes a TV, a viewfinder type and a monitor direct view type video tape recorder, a car navigation device, a pager. Electronic notebooks, calculators, word processors, workstations, video phones, POS (Point Of Sale) terminals, devices equipped with touch panels, and the like. As the display unit of these various electronic devices, the above display device using an organic EL element is applicable.

The present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.
In the above embodiment, the cycle T ₂ is set as the same cycle as the drive cycle T _c , but the programming period T _pr and the cycles T ₁ and T ₂ do not necessarily have a dependency. For example, the period T ₁ may be set equal to the programming period T _pr . In this case, the programming period is switched at a short time interval by the pulse width control of the period T ₁ .

  In the example of FIG. 5, the resistance transistors 52 and 41 to 48 are connected to the drive transistors 32 and 21 to 28. However, the resistance transistors 52 and 41 to 48 are connected to other resistance elements (resistance adding means). It is also possible to replace it. Further, such a resistance element is not necessarily connected to all the drive transistors 32 and 21 to 28, and may be provided as necessary.

  Further, a part of the circuit configuration of FIG. 5 may be omitted. For example, the offset current generation circuit 320 may be omitted. However, if the offset current generation circuit 320 is provided, the degree of freedom in setting the range of the programming current value is increased, and there is an advantage that the programming current value can be easily set in a preferable range.

In the above embodiment, some or all of the transistors may be replaced with bipolar transistors, thin film diodes, or other types of switching elements.
Further, in the above embodiment, the display panel unit 101 has a set of pixel circuit matrices, but the display panel unit 101 may have a plurality of sets of pixel circuit matrices. For example, when configuring a large panel, the display panel unit 101 may be divided into a plurality of adjacent regions, and one set of pixel circuit matrix may be provided for each region. Further, three sets of pixel circuit matrices corresponding to three colors of RGB may be provided in one display panel unit 101. In the case where there are a plurality of pixel circuit matrices, the above embodiment can be applied to each matrix.

Further, in the pixel circuits used in the first embodiment, as shown in FIG. 5, although the programming period T _pr and a light emitting period T _el is divided, the programming period T _pr is the light emission period T _el one It is also possible to use a pixel circuit that overlaps the part. This For such a pixel circuit, is initially set to the gradation of the programming performed by light emission of the light-emitting period T _el is then continued emission at the set gradation. The data line driver circuit 102 can also be applied to a device using such a pixel circuit.

  In the above embodiment, an example of a display device using an organic EL element has been described. However, the present invention can also be applied to a display device or an electronic device using a light emitting element other than an organic EL element. For example, the present invention can also be applied to an apparatus having other types of light emitting elements (LED, FED (Field Emission Display), etc.) whose light emission gradation can be adjusted according to the drive current.

Further, the present invention is not limited to a circuit or device driven by an active driving method having a pixel circuit, but can also be applied to a circuit or device driven by a passive driving method having no pixel circuit.
In the first to third embodiments, the signal is supplied at a predetermined period. However, the present invention is not limited to this, and there may be cases where the signal is not necessarily periodic.

  In the above embodiment, the digital data DAB and SUB are generated by dividing one set of digital data into two. However, in some cases, the digital data is divided into three and one of them is generated. May be used for γ correction (for example, reading the memory 104). Of course, it is not limited to three, and it is possible to divide into four or more.

1 is a block diagram illustrating a circuit configuration of an electro-optical device 100 as an embodiment of the present invention. FIG. 2 is a diagram showing an internal configuration of a display panel unit 101 and a data line driving circuit 102. FIG. 2 is a diagram illustrating an internal structure of a pixel circuit 200. FIG. 3 is a timing chart showing the operation of the pixel circuit 200. 3 is a circuit diagram showing the internal configuration of a single line driver 300 and a gate voltage generation circuit 400. FIG. The output current I _out of the data line driving circuit 102 is an explanatory diagram showing the examples 1 to 5 of the relationship between the value of the grayscale data DATA (grayscale value). 6 is a diagram illustrating a conversion rule of the data conversion circuit 500. FIG. 3 is a time chart showing the operation of the data conversion circuit 500. It is a graph which shows the change of the luminance value of the pixel circuit 200 according to the value of digital data In. Between the period T ₁ is a time chart illustrating an output of digital data Out. 2 is a block diagram showing a configuration of a data conversion circuit 500. FIG. Between the period T ₁ is a time chart illustrating an output of digital data Out. 2 is a diagram showing an internal configuration of a display panel unit 101 and a data line driving circuit 102. FIG. It is a figure which shows the structural example of digital data. It is a figure which shows the timing chart of a control signal. It is a figure which shows the change of a brightness | luminance. It is a figure which shows the timing chart of a control signal, and the change of a brightness | luminance. It is a figure which shows the structural example of the 2nd digital data SUB. It is a perspective view which shows the structure of a mobile type personal computer. It is a perspective view of a mobile phone. 2 is a perspective view illustrating a configuration of a digital still camera 3000. FIG.

Explanation of symbols

21 to 28 Drive transistor 31 Constant voltage generating transistor 32 Drive transistor 41 to 48 Resistor transistor 51 Resistor transistor 52 Resistor transistors 71 and 72 Transistor 73 Drive transistors 81 to 88 Switching transistor 100 Electro-optical device 101 Display panel unit 102 Data Line drive circuit 103 Scan line drive circuit 104 Memory 105 Control circuit 106 Timing generation circuit 107 Power supply circuit 110 Computer 200 Pixel circuit 211-214 Transistor 220 Organic EL element 230 Holding capacitor 300 Single line driver 301 Signal input line 302 Output signal line ( Data line)
303 First common gate line 304 Second common gate line 310 D / A converter unit 320 Offset current generation circuit 400 Gate voltage generation circuit 401 First wiring 402 Second wiring 500 Data conversion circuit 1000 Personal computer 1020 Keyboard 1040 Main body 1060 Display unit 2000 Mobile phone 2020 Operation button 2040 Earpiece 2060 Mouthpiece 2080 Display panel 3000 Digital still camera 3020 Case 3040 Display panel 3060 Light receiving unit 3080 Shutter button 3100 Circuit board 3120 Video signal output terminal 3140 Input / output terminal 4300 Television Monitor 4400 Personal computer

Claims (11)

A pixel matrix in which pixels including light emitting elements are arranged in a matrix, and
A plurality of scanning lines respectively connected to a pixel group arranged along one of a row direction and a column direction of the pixel matrix;
A plurality of data lines respectively connected to a pixel group arranged along the other of the row direction and the column direction of the pixel matrix;
A scanning line driving circuit connected to the plurality of scanning lines and selecting any one of the rows and columns of the pixel matrix;
A data line driving circuit for generating a control signal having a current value corresponding to the light emission gradation of the light emitting element based on the digital signal, and outputting the generated control signal to the plurality of data lines;
An electro-optical device comprising:
A data signal to be supplied to the plurality of pixel circuits via the plurality of data lines is generated based on first digital data among a set of digital data constituting the digital signal, and according to the data signal The signal level supplied to the light emitting element for the light emitting element included in each of the plurality of pixel circuits to emit light is determined,
An electro-optical device, wherein a light emission timing of the light emitting element in a predetermined period is controlled based on second digital data of the digital data. The electro-optical device according to claim 1.
The first digital data is assigned upper bit data of the digital data,
An electro-optical device, wherein the second digital data is assigned lower bit data of the digital data. The electro-optical device according to claim 1,
The electro-optical device, wherein the light emission timing of the light emitting element is a light emission start time and a light emission period of the light emitting element in the predetermined period. The electro-optical device according to any one of claims 1 to 3,
The electro-optical device is characterized in that the light emission timing of the light emitting element is controlled every time one of the plurality of scanning lines is selected by the scanning line driving circuit. The electro-optical device according to any one of claims 1 to 4,
The electro-optical device is characterized in that at least one light emission period is provided in the predetermined period. The electro-optical device according to any one of claims 1 to 5,
The electro-optical device, wherein the data line driving circuit includes a current addition type current generation circuit. The electro-optical device according to claim 1,
The electro-optical device, wherein the data line driving circuit further includes an offset current generating circuit. The electro-optical device according to any one of claims 1 to 7,
The electro-optical device, wherein the data line driving circuit further includes a gate voltage generation circuit including a current mirror circuit. The electro-optical device according to claim 6,
An electro-optical device, wherein an output range of the current value output to the data line is determined based on a reference voltage input to a current addition type current generation circuit.   An electronic apparatus comprising the electro-optical device according to claim 1 mounted thereon. A pixel matrix in which pixels including light emitting elements are arranged in a matrix, and
A plurality of scanning lines respectively connected to a pixel group arranged along one of a row direction and a column direction of the pixel matrix;
A plurality of data lines respectively connected to a pixel group arranged along the other of the row direction and the column direction of the pixel matrix;
A scanning line driving circuit connected to the plurality of scanning lines and selecting any one of the rows and columns of the pixel matrix;
An electro-optical device comprising: a data line driving circuit that generates a control signal having a current value corresponding to a light emission gradation of the light emitting element based on a digital signal and outputs the generated control signal to the plurality of data lines Driving method,
A data signal to be supplied to the plurality of pixel circuits via the plurality of data lines is generated based on first digital data among a set of digital data constituting the digital signal, and according to the data signal The signal level supplied to the light emitting element for the light emitting element included in each of the plurality of pixel circuits to emit light is determined,
A driving method of an electro-optical device, wherein the light emission timing of the light emitting element in a predetermined period is controlled based on second digital data of the digital data.

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