JP2003233347A - Supply of programming current to pixels - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of easily setting a range of a programming current value. <P>SOLUTION: A data line driving circuit is provided with a single line driver 300 and a gate voltage generation circuit 400. The single line driver 300 is constituted of N sets (N is an integer of two or larger) of the series connections of driving transistors 1-28 and switching transistors 81-88 connected in parallel. The gate voltage generation circuit 400 comprises two transistors 71, 72 constituting a current mirror circuit part, a driving transistor 73, and a constant voltage generating transistor 31. The range of an output current Iout can be adjusted by changing the design values of various parameters (relative values Ka, Kb of gain coefficients of the transistors 31, 32, power source voltage VDREF of the gate voltage generation circuit 400, and the gate signal VRIN of the driving transistor 73). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for generating a programming current supplied to a pixel circuit of a light emitting element to set a light emission gradation.

[0002]

2. Description of the Related Art In recent years, organic EL devices (Organic ElectroL
Electro-optical devices using uminescent devices have been developed. Since the organic EL element is a self-luminous element and does not require a backlight, it is expected that a display device with low power consumption, a wide viewing angle, and a high contrast ratio can be achieved.
In the present specification, the "electro-optical device" means a device that converts an electric signal into light. The most common form of electro-optical device is a display device that converts electrical signals representative of an image into light representative of the image.

In an active-matrix driven electro-optical device using organic EL elements, for each organic EL element,
A pixel circuit for adjusting the emission gradation is provided. The setting of the light emission gradation in each pixel circuit is performed by supplying a voltage value or a current value according to the light emission gradation to the pixel circuit. A method of setting the light emission gradation by the voltage value is called a voltage programming method, and a method of setting the light emission gradation by the current value is called a current programming method. Where "programming"
Is used to mean “setting of light emission gradation”. In the current programming method, the current for programming the pixel circuit is called "programming current". In the current programming electro-optical device,
For the pixel circuit of each organic EL element, a current generation circuit that generates a programming current having an accurate current value according to the gradation of light emission and supplies the programming current to each pixel circuit is used.

[0004]

The programming current value according to the light emission gradation depends on the configuration of the pixel circuit. On the other hand, the configuration of the pixel circuit is often slightly changed according to the design of the electro-optical device. Therefore, as the current generation circuit, a circuit in which the range of the output current value (programming current value) can be easily set in accordance with the actual configuration of the pixel circuit has been desired.

The present invention has been made to solve the above-mentioned conventional problems, and a first object thereof is to provide a technique capable of easily setting the range of the current value of the program current. . In addition, a current generating circuit with a simple circuit configuration and excellent productivity and durability, and its driving method,
A second object is to provide an electro-optical device, a semiconductor integrated circuit device, and an electronic device using the same.

[0006]

In order to achieve at least a part of the above-mentioned object, a first electro-optical device of the present invention is an electro-optical device, which is a pixel including a light emitting element. A matrix of pixels arranged in a matrix, a plurality of scanning lines connected to the pixel groups arranged in the row direction of the pixel matrix, and a pixel group arranged in the column direction of the pixel matrix. A plurality of data lines respectively connected to the plurality of scanning lines, a scanning line driving circuit connected to the plurality of scanning lines for selecting one row of the pixel matrix, and a current according to a gradation of light emission of the light emitting element. A data line driving circuit capable of generating a data signal having a value and outputting the data signal on at least one data line of the plurality of data lines. Connected in series with the first drive transistor for generating the current of N and the first switching transistor which is on / off controlled according to the control signal given from the external circuit, where N sets (N is an integer of 2 or more). ) A current addition type current generation circuit having a configuration of being connected in parallel to each other, and a control for generating a control electrode signal having a predetermined signal level and commonly supplying it to the control electrodes of the N first driving transistors. And an electrode signal generation circuit.

According to this structure, the current driving capability of each of the N first driving transistors of the current generating circuit can be set by adjusting the design values, so that the current value of the data line (program current value) ) Range can be easily set. Further, since the control electrode signal generation circuit commonly supplies the control electrode signal to the control electrodes of the N first driving transistors, it is possible to generate a data signal having a stable and accurate current value. is there.

The control electrode signal generation circuit has a first
A control electrode signal generating transistor for generating the control electrode signal from the first control electrode, and a constant current circuit for supplying a constant current to the control electrode signal generating transistor. You may have. At this time, the first control electrode of the control electrode signal generating transistor and the control electrodes of the N first driving transistors of the current generating circuit are connected to each other.

According to this structure, the range of the current value of the data line can be set also by adjusting the design value of the constant current value flowing in the constant current circuit.

The constant current circuit has two transistors respectively connected to the first and second wirings, and generates a current value in the second wiring which is proportional to the current value generated in the first wiring. And a first current mirror circuit section for
A second line connected to the first line and generating a predetermined current on the first line according to a control signal given from an external circuit.
Drive transistor, and the control electrode signal generating transistor is connected to the second wiring.

According to this configuration, the range of the current value of the data line can be set by adjusting the configuration of the current mirror circuit section and the design value of the current driving capability of the second drive transistor. Become.

The current generation circuit further includes a third drive transistor for generating an offset current, which is provided in parallel with N sets of the series connection of the first drive transistor and the first switching transistor. No switching transistor is provided between the third drive transistor and the data line, and the control electrode of the third drive transistor is the first control of the control electrode signal generating transistor. It may be configured to be connected to the electrodes.

According to this structure, an offset can be provided in the relationship between the light emission gradation of the light emitting element and the current value of the data line, so that the current value of the data line can be set within a preferable range.

Each series connection of the first drive transistor and the first switching transistor may include a resistive element.

According to this structure, the noise of the data signal can be reduced.

The resistance element is, for example, a transistor.

Of the N first driving transistors, the n-th (n is an integer from 1 to N) transistor has N-th transistors so that the relative value of the gain coefficient is 2 ^n-1 . One drive transistor may be configured.

According to this structure, it is possible to secure a wide range of the current value of the data signal.

The pixel matrix may be driven by an active matrix driving method. Alternatively, the pixel matrix may be driven by a passive matrix driving method.

A current generating circuit according to the present invention is based on a constant current generating means, a signal input line, an output terminal, a reference current generated by the constant current generating means, and a signal supplied to the signal input line. Current output means for outputting the output current generated by the above to the output end.

This current generating circuit has various excellent features such as a simple circuit configuration and excellent productivity and durability.

The constant current generating means may include a current mirror circuit.

Further, the constant current generating means is at least one.
It may be configured with one reference voltage source.

The current output means may include a plurality of first transistors having different gain coefficients.

The current output means may be means for generating the output current by combining the currents flowing in the transistors selected by the signal among the plurality of first transistors.

The constant current generating means may be configured to include a second transistor connected to the gate electrode of the first transistor.

The second transistor may have a function of converting the reference current into gate voltages of the plurality of first transistors.

A first resistance adding means corresponding to at least one of the plurality of first transistors may be provided between the output end and the plurality of first transistors.

The first resistance adding means may be a third transistor.

The constant current generating means may include a fourth transistor connected to the gate electrode of the third transistor.

The current output means may include an offset current path defining a lower limit value of the output current.

The offset current path may include a fifth transistor whose gate electrode is connected to the second transistor.

Second resistance adding means may be provided between the output terminal and the fifth transistor.

The second resistance adding means may be a sixth transistor.

The reference current may be set to a value near the middle of the maximum value and the minimum value of the output current.

The output current may be controlled by changing the gain coefficient of the fifth transistor.

A second electro-optical device according to the present invention comprises a plurality of scanning lines, a plurality of data lines, and an electro-optical element arranged at an intersection of the scanning lines and the data lines.
An electro-optical device comprising a scanning line driving circuit for driving the scanning lines and a data line driving circuit for driving the data lines, wherein the data line driving circuit includes any one of the current generating circuits described above, A means for inputting the output current of the current generation circuit to the data line is provided.

The electro-optical element may be a current-driven element.

Further, the current drive type element may be an organic electroluminescence element.

The present invention can be realized in various forms. For example, a data line driving circuit, an electro-optical device or a display device including the data line driving circuit, and an electro-optical device or a display device thereof. Electronic devices including the above, a method for driving those devices, a computer program for realizing the functions of the method, a recording medium recording the computer program, a data signal embodied in a carrier wave including the computer program, etc. Can be realized in the form of

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in the following order based on examples. A. Overall configuration of device: B. First Example: C.I. Second embodiment: D. Application example to electronic device: E. Modification

A. Overall Configuration of Device: FIG. 1 is a block diagram showing a circuit configuration of an electro-optical device 100 as an embodiment of the present invention. The electro-optical device 100 includes a display panel unit 101 (also referred to as a “pixel region”) in which light emitting elements are arranged in a matrix, a data line driving circuit 102 that drives a data line of the display panel unit 101, and a display panel unit. 1
A scan line driver circuit 103 (also referred to as a “gate driver”) that drives a scan line 01 (also referred to as a “gate line”);
A memory 104 that stores display data supplied from the computer 110, an oscillation circuit 106 that supplies a reference operation signal to other components, a power supply circuit 107, and each component in the electro-optical device 100 are controlled. Control circuit 10
5 and.

The respective constituent elements 101 to 101 of the electro-optical device 100.
107 may be configured by independent components (for example, a one-chip semiconductor integrated circuit device), or all or some of the constituent elements 101 to 107 are configured as an integrated component. May be. For example, the data line driving circuit 102 and the scanning line driving circuit 103 may be integrally formed in the display panel unit 101. Further, all or a part of the constituent elements 102 to 106 may be configured by a programmable IC chip, and the function thereof may be realized by software by a program written in the IC chip.

FIG. 2 shows the internal structure of the display panel section 101 and the data line drive circuit 102. Display panel section 1
01 is a plurality of pixel circuits 20 arranged in a matrix.
0, and each pixel circuit 200 has an organic EL element 22.
It has 0 respectively. The matrix of the pixel circuit 200 includes a plurality of data lines Xm extending in the column direction.
(M = 1 to M) and a plurality of scanning lines Yn (n = 1 to N) extending in the row direction are connected to each other. The data line is also called a "source line", and the scanning line is also called a "gate line". Further, in the present specification, the pixel circuit 200 is also referred to as a “unit circuit” or a “pixel”. The transistors in the pixel circuit 200 are usually TFTs.
Composed of.

The scanning line drive circuit 103 includes a plurality of scanning lines Y.
One of n is selectively driven to select one row of pixel circuit groups. The data line drive circuit 102 controls each data line Xm
A plurality of single line drivers 3 for driving each
00 and a gate voltage generation circuit 400. The gate voltage generation circuit 400 supplies a gate control signal having a predetermined voltage value to the single line driver 300. The internal configurations of the gate voltage generation circuit 400 and the single line driver 300 will be described later.

The single line driver 300 supplies a data signal to the pixel circuit 200 via each data line Xm.
When the internal state (described later) of the pixel circuit 200 is set according to this data signal, the organic EL element 2 is accordingly
The value of the current flowing through 20 is controlled, and as a result, the gradation of light emission of the organic EL element 220 is controlled.

The control circuit 105 (FIG. 1) outputs display data (image data) representing the display state of the display panel section 101,
It is converted into matrix data representing the gradation of light emission of each organic EL element 220. The matrix data includes a scanning line drive signal for sequentially selecting the pixel circuit groups for one row and a data line drive signal indicating the level of the data line signal supplied to the organic EL element 220 of the selected pixel circuit group. Contains.
The scan line drive signal and the data line drive signal are supplied to the scan line drive circuit 103 and the data line drive circuit 102, respectively. The control circuit 105 also controls the timing of driving the scanning lines and the data lines.

FIG. 3 is a circuit diagram showing the internal structure of the pixel circuit 200. The pixel circuit 200 is a circuit arranged at the intersection of the m-th data line Xm and the n-th scanning line Yn. The scanning line Yn is composed of two sub-scanning lines V
1 and V2 are included.

The pixel circuit 200 is a current program circuit for adjusting the gradation of the organic EL element 220 according to the value of the current flowing through the data line Xm. Specifically, this pixel circuit 2
00 has four transistors 211 to 214 and a holding capacitor 230 (also referred to as “holding capacitor” or “storage capacitor”) in addition to the organic EL element 220. The holding capacitor 230 holds a charge according to the data signal supplied via the data line Xm, and thereby adjusts the gradation of light emission of the organic EL element 220. In other words, the storage capacitor 23
0 holds the voltage according to the current flowing through the data line Xm. The first to third transistors 211 to 213 are n
It is a channel type FET, and the fourth transistor 214
Is a p-channel FET. Organic EL element 220
Is a current injection type (current drive type) light emitting element similar to a photodiode, and therefore is indicated by the symbol of a diode here.

The source of the first transistor 211 is connected to the drain of the second transistor 212, the drain of the third transistor 213, and the drain of the fourth transistor 214, respectively. The drain of the first transistor 211 is connected to the fourth transistor 214
Is connected to the gate. The storage capacitor 230 is
It is connected between the source and the gate of the fourth transistor 214. The source of the fourth transistor 214 is also connected to the power supply potential Vdd.

The source of the second transistor 212 is the single line driver 300 (FIG. 2) via the data line Xm.
It is connected to the. The organic EL element 220 is connected between the source of the third transistor 213 and the ground potential.

First and second transistors 211, 212
The gates of are commonly connected to the first sub-scanning line V1. The gate of the third transistor 213 is connected to the second sub scan line V2.

First and second transistors 211 and 212
Is a switching transistor used when accumulating charges in the holding capacitor 230. The third transistor 213 is a switching transistor that is kept in the ON state during the light emission period of the organic EL element 220.
In addition, the fourth transistor 214 is the organic EL element 22.
It is a drive transistor for controlling the value of the current flowing to zero. The current value of the fourth transistor 214 is controlled by the charge amount (accumulated charge amount) held in the holding capacitor 230.

FIG. 4 is a timing chart showing the operation of the pixel circuit 200. Here, the first sub-scan line V
Voltage value of 1 (hereinafter, also referred to as "first gate signal V1")
, The voltage value of the second sub-scanning line V2 (hereinafter, also referred to as “second gate signal V2”), and the current value Iou of the data line Xm.
t (also called “data signal Iout”) and the organic EL element 2
The current value IEL flowing through 20 is shown.

The driving period Tc is the programming period Tp.
It is divided into r and the light emission period Tel. Here, the “driving cycle Tc” means a cycle in which the gradation of the light emission of all the organic EL elements 220 in the display panel section 101 is updated once, and is the same as a so-called frame cycle. . The gradation is updated for each pixel circuit group for one row, and the gradation of the pixel circuit group for N rows is sequentially updated during the driving cycle Tc. For example, when the gradation of all pixel circuits is updated at 30 Hz, the driving cycle Tc is about 33 ms.

The programming period Tpr is a period in which the gradation of light emission of the organic EL element 220 is set in the pixel circuit 200. In the present specification, setting of gradation in the pixel circuit 200 is called “programming”. For example, the driving cycle Tc is about 33 ms, and the total number N of scanning lines Yn is 48.
When the number is 0, the programming cycle Tpr is about 6
It becomes 9 μs (= 33 ms / 480) or less.

In the programming period Tpr, first, the second gate signal V2 is set to the L level to keep the third transistor 213 in the off state (closed state). Next, the first gate signal V1 is set to the H level and the first and second transistors 211 and 212 are turned on (open state) while flowing the current value Im according to the light emission gradation on the data line Xm. ). At this time, the single line driver 300 (FIG. 2) of the data line Xm functions as a constant current source that supplies a constant current value Im according to the light emission gradation. As shown in FIG. 4C, this current value Im is set to a value according to the gradation of light emission of the organic EL element 220 within a predetermined current value range RI.

The holding capacitor 230 has a current value Im flowing through the fourth transistor 214 (driving transistor).
The electric charge corresponding to is retained. As a result, the voltage stored in the storage capacitor 230 is applied between the source and gate of the fourth transistor 214. In this specification, the current value Im of the data signal used for programming is referred to as “programming current value Im”.

When the programming is completed, the scanning line driving circuit 103 sets the first gate signal V1 to the L level to turn off the first and second transistors 211 and 212, and the data line driving circuit 102 becomes Data signal Iou
stop t

In the light emission period Tel, the first gate signal V
1 is maintained at the L level and the first and second transistors 21
The second gate signal V2 is set to the H level and the third transistor 213 is set to the ON state while keeping 1 and 212 in the OFF state. Since the voltage corresponding to the programming current value Im is stored in advance in the holding capacitor 230, a current substantially equal to the programming current value Im flows through the fourth transistor 214. Therefore, organic E
A current that is substantially the same as the programming current value Im also flows through the L element 220, and light is emitted with a gradation according to the current value Im.
In this way, the pixel circuit 200 of the type in which the voltage (that is, the charge) of the holding capacitor 230 is written by the current value Im is called a “current program circuit”.

B. First Embodiment: FIG. 5 is a circuit diagram showing the internal configuration of a single line driver 300 and a gate voltage generation circuit 400. The single line driver 300 has an 8-bit D / A converter unit 310 and an offset current generation circuit 320.

The D / A converter unit 310 has eight current lines IU1 to IU8 connected in parallel.
In the first current line IU1, a switching transistor 81, a resistance transistor 41 functioning as a kind of resistance element, and a driving transistor 21 functioning as a constant current source for flowing a predetermined current are connected to a data line 302 and a ground potential. And are connected in series. Other current line IU
2 to IU8 also have the same configuration. These three types of transistors 81-88, 41-48, 21-28
Are all n-channel FETs in the example of FIG. The gates of the eight drive transistors 21 to 28 are commonly connected to the first common gate line 303. The gates of the eight resistance transistors 41 to 48 are
It is commonly connected to the second common gate line 304. 8
The control circuit 105 (FIG. 1) is provided to each gate of the individual switching transistors 81 to 88 via the signal input line 301.
Each bit of the 8-bit grayscale data DATA given from is input.

Gain of eight drive transistors 21-28
The ratio K of the coefficient β is 1: 2: 4: 8: 16: 32: 64:
It is set to 128. That is, nth (n = 1 to 1)
The relative value K of the gain coefficient β of the driving transistor of N) is 2
^n-1Is set to. Here, the gain coefficient β is well known.
As shown, β = Kβ₀ = (ΜC₀ W / L)
Is meant Where K is a relative value, β₀ Is a predetermined constant, μ
Is the carrier mobility, C ₀ Is the gate capacity, W is the channel
L width and L are channel lengths. Number of drive transistors
N is an integer of 2 or more. In addition, this drive transistor
The number N of scan lines is independent of the number of scan lines Yn.

The eight drive transistors 21 to 28 function as a constant current source. Since the current drive capacity of the transistor is proportional to the gain coefficient β, the eight drive transistors 2
The ratio of the current drivability of 1 to 28 is 1: 2: 4: 8: 1.
It is 6: 32: 64: 128. In other words, the relative value K of the gain coefficient of each drive transistor 21-28 is set to a value associated with the weight of each bit of the grayscale data DATA.

The current drivability of the resistance transistors 41 to 48 is usually the same as that of the corresponding driving transistor 2.
It is set to a value equal to or higher than the current drive capacity of 1 to 28. Therefore, the current drive capability of each of the current lines IU1 to IU8 is determined by the drive transistors 21 to 28. In addition,
The resistance transistors 41 to 48 have a function as a noise filter that removes noise of the current value.

The offset current generating circuit 320 has a structure in which the resistance transistor 52 and the driving transistor 32 are connected in series between the data line 302 and the ground potential. The gate of the drive transistor 32 is connected to the first common gate line 303, and the gate of the resistance transistor 52 is connected to the second common gate line 304. The relative value of the gain coefficient β of the drive transistor 32 is Kb. Note that the offset current generation circuit 320 is not provided with a switching transistor between the drive transistor 32 and the data line 302, and is different from each current line in the D / A converter unit 310 in this respect.

The current line Ioffset of the offset current generating circuit 320 is connected in parallel with the eight current lines IU1 to IU8 of the D / A converter unit 310. Therefore, these nine current lines Ioffset, IU1 to IU
The sum of the currents flowing through 8 is output on the data line 302 as the programming current. That is, the single line driver 310 is a current addition type current generation circuit. In the following, reference numerals Ioffset and IU indicating each current line are used.
1 to IU8 are also used as symbols to indicate the currents flowing through them.

The gate voltage generating circuit 400 includes a current mirror circuit section composed of two transistors 71 and 72. The gates of the two transistors 71 and 72 are connected to each other, and the gate and drain of the first transistor 71 are also connected to each other. Two
One terminal (source) of each of the two transistors 71 and 72 is a power supply potential for the gate voltage generation circuit 400.
Connected to VDREF. The first wiring 4 between the other terminal (drain) of the first transistor 71 and the ground potential
The drive transistor 73 is connected in series on 01. The control circuit 1 is provided at the gate of the drive transistor 73.
A control signal VRIN having a predetermined voltage level is input from 05. The resistor transistor 51 and the constant voltage generating transistor 31 are provided on the second wiring 402 between the other terminal (drain) of the second transistor 72 and the ground potential.
(Also referred to as “control electrode signal generation transistor”) are connected in series. Constant voltage generating transistor 31
The relative value of the gain coefficient β of is Ka.

The gate and drain of the constant voltage generating transistor 31 are connected to each other, and these are connected to the first common gate line 303 of the single line driver 300. The gate and drain of the resistor transistor 51 are also connected to each other, and these are connected to the second common gate line 304 of the single line driver 300.

In the example of FIG. 5, the two transistors 71 and 72 forming the current mirror circuit section are p-channel FETs, and the other transistors are n-channel FETs.
It is composed of a channel type FET.

When the control signal VRIN having a predetermined voltage level is input to the gate of the drive transistor 73 of the gate voltage generation circuit 400, the control signal VRIN is provided on the first wiring 401.
A constant reference current Iconst corresponding to the voltage level of IN is generated. Since the two transistors 71 and 72 form a current mirror circuit section, the same reference current Iconst also flows on the second wiring 402. However, two wires 40
The currents flowing through the first and second wirings 402 and 402 do not have to be the same, and generally, the first and second wirings 402 and 402 are arranged so that a current proportional to the reference current Iconst of the first wiring 401 flows on the second wiring 402.
It is sufficient that the transistors 71 and 72 are configured.

Between the gate / drain of the two transistors 31, 51 on the second wiring 402, this current Icon
Predetermined gate voltages Vg1 and Vg2 corresponding to t are generated, respectively. The first gate voltage Vg1 is applied to the 9th voltage in the single line driver 300 via the first common gate line 303.
It is commonly applied to the gates of the two drive transistors 32, 21 to 28. In addition, the second gate voltage Vg2 is
Is commonly applied to the gates of the nine resistance transistors 52 and 41 to 48 via the common gate line 304 of the above.

The current drivability of each current line Ioffset, IU1 to IU8 is equal to that of each drive transistor 32, 21 to 28.
It is determined by the gain coefficient β and the applied voltage. Therefore, each current line Ioffse of the single line driver 300 is
t, IU1 to IU8, depending on the gate voltage Vg1
A current value that is proportional to the relative value K of the gain coefficient β of each drive transistor can flow. At this time, when 8-bit gradation data DATA is given from the control circuit 105 via the signal input line 301, the eight switching transistors 81 to 88 are turned on / off according to the value of each bit of the gradation data DATA. Controlled. As a result, the gradation data DATA
A programming current Im having a current value corresponding to the value of is output on the data line 302.

The single line driver 300 is
Since the offset current generating circuit 320 is included, the value of the grayscale data DATA and the programming current Im do not have a perfect proportional relationship passing through the origin, but have an offset. By providing such an offset, the degree of freedom in setting the programming current value range increases,
There is an advantage that the programming current value can be easily set in a preferable range.

FIG. 6 is an explanatory diagram showing Examples 1 to 5 of the relationship between the output current Iout of the data line drive circuit 102 and the value (gradation value) of the gradation data DATA. The table of FIG. 6A shows a standard example 1 and examples 2 to 5 when the following four parameters are changed. (1) VRIN: voltage value of the gate signal of the drive transistor 73 of the gate voltage generation circuit 400. (2) VDREF: Power supply voltage of the current mirror circuit section of the gate voltage generation circuit 400. (3) Ka: Relative value of the gain coefficient β of the constant voltage generating transistor 31 of the gate voltage generating circuit 400. (4) Kb: Relative value of the gain coefficient β of the drive transistor 32 of the offset current generation circuit 320.

FIG. 6 (b) is a graph showing the relationship shown in FIG. 6 (a). It should be noted that the example 1 which is regarded as "standard"
Shows an example in which each parameter is set to a predetermined standard value. The example 2 is an example in which only the voltage VRIN of the drive transistor 73 is set to a higher value than the standard example 1. Example 3 is an example in which only the power supply voltage VDREF of the current mirror circuit unit is set to a higher value than in the standard example 1. Example 4 is an example in which only the relative value Ka of the gain coefficient β of the constant voltage generating transistor 31 is set to a larger value than in the standard example 1. Example 5 is a standard example 1
Than the relative value K of the gain coefficient β of the drive transistor 32
In this example, only b is set to a large value.

As shown in these tables and graphs, the value of the output current Iout depends on each parameter VRIN,
It changes according to VDREF, Ka, Kb. Therefore, by changing the value of one or more of these parameters, it is possible to change the range of the current value used for controlling the light emission gradation. In addition, each parameter VRIN, VDR
The values of EF, Ka, Kb are set by adjusting the design values of the circuit parts related to each. In the circuit configuration shown in FIG. 5, four parameters VRIN and VDR are used.
Since EF, Ka, and Kb all affect the range of the output current Iout, the degree of freedom in setting the range of the output current Iout is high, and there is an advantage that the range can be easily set to an arbitrary range.

The output current Iout is proportional to the reference current Iconst in the gate voltage generation circuit 400. Therefore, the reference current Iconst is determined according to the range of the current value required for the output current Iout (that is, the programming current Im). At this time, if the value of the reference current Iconst is set near both ends of the current value range required as the output current Iout, a small variation (error) in the reference current Iconst may occur depending on the performance of the circuit components. Current I
There is a possibility that a large variation (error) in out may occur.
Therefore, in order to reduce the error of the output current Iout, it is preferable to set the value of the reference current Iconst to a value near the middle of the maximum value and the minimum value of the current value range of the output current Iout. Here, the “near the middle of the maximum value and the minimum value” means a range of about ± 10% of the average value (that is, the median value) of the maximum value and the minimum value.

FIG. 7 is a graph showing an example of the relationship between the output current Iout and the light emission gradation. In this example, 0-255
0nA to 5000 to express 256 gradations up to
An output current Iout in the nA range is utilized. At this time,
The value of the reference current Iconst is an intermediate value of 2500n.
It is preferably set to about A.

In the circuit of FIG. 5, the reference current Ico
In order to set the value of nst equal to the value of the output current Iout corresponding to the median value of gradation (= 128), the relative value Ka of the gain coefficient β of the constant voltage generating transistor 31 is set to the median value of gradation. May be set to a value equal to (128).

As described above, the data line driving circuit 102 of the first embodiment arbitrarily changes the design value of one or more parameters to output the output current Iout.
This has the advantage that the range of (programming current Im) can be adjusted arbitrarily. In addition, this circuit 1
02 has an advantage that it has excellent durability and productivity because it has a very simple structure.

C. Second Embodiment: FIG. 8 shows a display panel section 101a and a data line driving circuit 102a according to the second embodiment.
Shows the internal configuration of the. In this display device, one single line driver 300 and a shift register 500 are provided instead of the plurality of single line drivers 300 in the configuration of FIG. In addition, the display panel unit 1
Each data line of 01a has a switching transistor 5
20 are provided. Switching transistor 52
One terminal of 0 is connected to each data line Xm, and the other terminal is an output signal line 30 of the single line driver 300.
2 is commonly connected. The shift register 500 is
An ON / OFF control signal is supplied to the switching transistor 520 of each data line Xm, so that the data lines Xm are sequentially selected one by one.

In this display device, the pixel circuits 200 are updated dot-sequentially. That is, only one pixel circuit 200 existing at the intersection of the gate line Yn selected by the scanning line driving circuit 103 and the data line Xm selected by the shift register 500 is updated by one programming. For example, the M pixel circuits 200 selected by the nth gate line Yn are sequentially programmed one by one, and after that, the M pixels on the next (n + 1) th gate line are programmed.
The pixel circuits 200 are programmed one by one.
On the other hand, in the above-described first embodiment, the operation is different from the display device shown in FIG. 8 in that the pixel circuit groups for one row are programmed at the same time (that is, line-sequentially). .

Even when the pixel circuit 200 is programmed in a dot-sequential manner like the display device of FIG. 8, the same single line driver 300 and gate voltage generation circuit 400 as in the first embodiment described above are used. It is possible to generate the output current Iout (programming current Im) in a desired current range.

D. Application example to electronic device: A display device using an organic EL element can be applied to various electronic devices such as a mobile personal computer, a mobile phone, and a digital still camera.

FIG. 9 is a perspective view showing the structure of a mobile personal computer. The personal computer 1000 includes a main body 10 including a keyboard 1020.
40 and a display unit 1060 using an organic EL element.

FIG. 10 is a perspective view of a mobile phone. This mobile phone 2000 includes a plurality of operation buttons 2020, an earpiece 2040, a mouthpiece 2060, and a display panel 2080 using an organic EL element.

FIG. 11 shows a digital still camera 300.
It is a perspective view which shows the structure of 0. Note that the connection with external devices is also shown in a simplified manner. In contrast to a normal camera that exposes a film to an optical image of an object, a digital still camera 3000 uses an optical image of the object as a CCD.
An image pickup signal is generated by photoelectric conversion of an image pickup device such as (Charge Coupled Device). Here, on the back surface of the case 3020 of the digital still camera 3000,
A display panel 3040 using an organic EL element is provided, and display is performed based on an image pickup signal from the CCD. Therefore, the display panel 3040 functions as a finder that displays the subject. On the observation side (the back side in the figure) of the case 3020, an optical lens or CCD
A light receiving unit 3060 including the above is provided.

Here, the photographer confirms the subject image displayed on the display panel 3040, and the shutter button 3080
When is pressed, the CCD image signal at that time is
It is transferred and stored in the memory of the circuit board 3100. Also,
In this digital still camera 3000, on the side surface of the case 3020, a video signal output terminal 3120,
An input / output terminal 3140 for data communication is provided. Then, as shown in the figure, the television monitor 4300 is also connected to the former video signal output terminal 3120.
A personal computer 4400 is connected to the latter input / output terminal 3140 for data communication as needed. Further, by a predetermined operation, the circuit board 310
The image pickup signal stored in the memory 0
00 or the personal computer 4400.

As the electronic equipment, in addition to the personal computer shown in FIG. 9, the mobile phone shown in FIG. 10, the digital still camera shown in FIG. 11, a television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation system, etc. Examples thereof include a device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel. Organic EL is used as the display unit of these various electronic devices.
The above-described display device using an element can be applied.

E. Modifications: The present invention is not limited to the above-described embodiments and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are also possible. is there.

E1: In the embodiment shown in FIG. 5, the driving transistors 32, 21 to 28 are connected to the resistance transistor 52,
41 to 48 were connected, but the resistor transistor 5
It is also possible to replace 2, 41 to 48 with another resistance element (resistance adding means). Further, such a resistance element is not necessarily used for all the drive transistors 32, 21-2.
It is not necessary to connect to 8 and may be provided as needed.

E2: It is possible to omit a part of the circuit configuration of FIG. For example, the offset current generation circuit 320 may be omitted. However, if the offset current generating circuit 320 is provided, the degree of freedom in setting the range of the programming current value increases, so that there is an advantage that the programming current value can be easily set in the preferable range.

E3: In the above-described embodiment, some or all of the transistors may be replaced with bipolar transistors, thin film diodes, or other types of switching elements. The gate electrode of the FET and the base electrode of the bipolar transistor correspond to the "control electrode" of the present invention.

E4: In each of the above-described embodiments, the display panel section 101 has one set of pixel circuit matrices, but the display panel section 101 may have a plurality of sets of pixel circuit matrices. For example, when configuring a large-sized panel, the display panel unit 101 may be divided into a plurality of adjacent regions, and one set of pixel circuit matrices may be provided for each region. Further, three sets of pixel circuit matrices corresponding to three colors of RGB may be provided in one display panel unit 101. When there are a plurality of pixel circuit matrices, the above-described embodiment can be applied to each matrix.

E5: In the pixel circuit used in each of the above-described embodiments, the programming period Tpr and the light emission period Tel are separated as shown in FIG. 5, but the programming period Tpr overlaps a part of the light emission period Tel. It is also possible to use such a pixel circuit. For such a pixel circuit, programming is performed at the beginning of the light emission period Tel to set the gradation of light emission, and thereafter, light emission continues at the set gradation. The data line driving circuit described above can be applied to a device using such a pixel circuit.

E6: In each of the above-mentioned embodiments, an example of a display device using an organic EL element has been described, but the present invention is also applicable to a display device and an electronic device using a light emitting element other than the organic EL element. Is. For example, another type of light emitting element (LED or FED) whose gradation of light emission can be adjusted according to the drive current
(Field Emission Display) etc. can also be applied to the device.

E7: The present invention is not limited to circuits and devices driven by an active driving method having a pixel circuit, but can be applied to circuits and devices driven by a passive driving method having no pixel circuit.

[Brief description of drawings]

FIG. 1 is an electro-optical device 100 as an embodiment of the invention.
Block diagram showing the circuit configuration of FIG.

FIG. 2 shows a display panel section 101 and a data line driving circuit 102.
Block diagram showing the internal configuration of FIG.

FIG. 3 is a circuit diagram showing an internal configuration of a pixel circuit 200.

FIG. 4 is a timing chart showing the operation of the pixel circuit 200.

FIG. 5 is a circuit diagram showing internal configurations of a single line driver 300 and a gate voltage generation circuit 400.

FIG. 6 is an explanatory diagram showing an example of a relationship between an output current Iout of the data line driving circuit 102 and a gradation value.

FIG. 7 is a graph showing an example of the relationship between output current Iout and light emission gradation.

FIG. 8 is a block diagram showing an internal configuration of a display panel section 101a and a data line driving circuit 102a in a second embodiment.

FIG. 9 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which the display device according to the present invention is applied.

FIG. 10 is a perspective view showing a configuration of a mobile phone as an example of an electronic device to which the display device according to the present invention is applied.

FIG. 11 is a perspective view showing the configuration on the back side of a digital still camera as an example of an electronic apparatus to which the display device according to the present invention is applied.

[Explanation of symbols]

21-28 ... Driving transistor 31 ... Transistor for generating constant voltage 32 ... Drive transistor 41-48 ... Transistor for resistance 51 ... Transistor for resistance 52 ... Resistor transistor 71, 72 ... Transistor 73 ... Drive transistor 81-88 ... Switching transistors 100 ... Electro-optical device 101 ... Display panel section 102 ... Data line drive circuit 103 ... Scan line drive circuit 104 ... memory 105 ... Control circuit 106 ... Oscillation circuit 107 ... Power supply circuit 110 ... Computer 200 ... Pixel circuit 211-214 ... Transistors 220 ... Organic EL element 230 ... Storage capacitor 300 ... Single line driver 301 ... Signal input line 302 ... Output signal line (data line) 303 ... First common gate line 304 ... Second common gate line 310 ... D / A converter section 320 ... Offset current generation circuit 400 ... Gate voltage generation circuit 401 ... First wiring 402 ... second wiring 500 ... Shift register 520 ... Switching transistor 1000 ... personal computer 1020 ... keyboard 1040 ... main body 1060 ... Display unit 2000 ... Mobile phone 2020 ... Operation button 2040 ... Earpiece 2060 ... mouthpiece 2080 ... Display panel 3000 ... Digital still camera 3020 ... Case 3040 ... Display panel 3060 ... Light receiving unit 3080 ... Shutter button 3100 ... Circuit board 3120 ... Video signal output terminal 3140 ... Input / output terminal 4300 ... TV monitor 4400 ... Personal computer

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 624 G09G 3/20 624B 631 631U 641 641D

Claims (33)

[Claims] 1. An electro-optical device comprising: a pixel matrix in which pixels including light emitting elements are arranged in a matrix; and a plurality of scans respectively connected to pixel groups arranged in a row direction of the pixel matrix. A line, a plurality of data lines respectively connected to the pixel groups arranged along the column direction of the pixel matrix, and a plurality of data lines connected to the plurality of scanning lines.
A scanning line driving circuit for selecting one row, and a data signal having a current value according to a gradation of light emission of the light emitting element is generated and output on at least one data line of the plurality of data lines. And a data line drive circuit capable of controlling the ON / OFF control according to a control signal given from an external circuit and a first drive transistor for generating a predetermined current. And a first switching transistor connected in series, N sets (N is an integer of 2 or more) connected in parallel to each other, a current addition type current generation circuit, and a control electrode signal having a predetermined signal level And a control electrode signal generation circuit for commonly supplying the control electrodes to the N control electrodes of the first drive transistors. 2. The electro-optical device according to claim 1, wherein the control electrode signal generation circuit has a first control electrode, and the control electrode signal is generated from the first control electrode. A control electrode signal generating transistor; and a constant current circuit for supplying a constant current to the control electrode signal generating transistor, wherein the first control electrode of the control electrode signal generating transistor and the current generation An electro-optical device, wherein the control electrodes of the N first drive transistors of the circuit are connected to each other. 3. The electro-optical device according to claim 2, wherein the constant current circuit has two transistors connected to the first and second wirings, respectively, and a current generated in the first wiring is generated. A current mirror circuit unit for generating a current value proportional to the value in the second wiring, and a predetermined current according to a control signal provided from an external circuit, which is connected to the first wiring. A second driving transistor generated on a wiring, wherein the control electrode signal generating transistor is connected to the second wiring. 4. The electro-optical device according to claim 2, wherein the current generation circuit further includes N sets of the first drive transistor and the first switching transistor connected in series. A third drive transistor for generating an offset current is provided, and a switching transistor is not provided between the third drive transistor and the data line. An electro-optical device, wherein a control electrode is connected to the first control electrode of the control electrode signal generating transistor. 5. The electro-optical device according to claim 1, wherein each series connection of the first drive transistor and the first switching transistor includes a resistance element.
Electro-optical device. 6. The electro-optical device according to claim 5, wherein: An electro-optical device, wherein the resistive element is a transistor. 7. The electro-optical device according to claim 1, wherein the n-th (n-th) of the N first drive transistors is provided.
Is an integer from 1 to N), and the N first driving transistors are configured such that the relative value of the gain coefficient of the transistors is 2 ^n-1 . 8. The electro-optical device according to claim 1, wherein the pixel matrix is driven by an active matrix driving method. 9. The electro-optical device according to claim 1, wherein the pixel matrix is driven by a passive matrix driving method. 10. Data for outputting a data signal having a current value according to a gradation of light emission of the light emitting element to a data line connected to the pixel when driving a matrix of pixels including the light emitting element. In the line drive circuit, a first drive transistor for generating a predetermined current and a first switching transistor that is on / off controlled in response to a control signal given from an external circuit are connected in series to each other. A group (N is an integer of 2 or more) of current addition type current generation circuits having a configuration in which they are connected in parallel to each other, and a control electrode signal having a predetermined signal level for generating N control electrodes And a control electrode signal generation circuit commonly supplied to the control electrode. 11. A constant current generating means, a signal input line, an output end, an output current generated based on a reference current generated by the constant current generating means and a signal supplied to the signal input line. And a current output unit that outputs the current to the output end. 12. The current generating circuit according to claim 11, wherein the constant current generating means includes a current mirror circuit. 13. The current generation circuit according to claim 11 or 12, wherein the constant current generation means includes at least one reference voltage source. 14. The current generation circuit according to claim 11, wherein the current output means includes a plurality of first transistors having different gain coefficients. Current generation circuit. 15. The current generation circuit according to claim 14, wherein the current output means combines the currents flowing in the transistors selected by the signal among the plurality of first transistors to output the current. A current generation circuit, which is means for generating a current. 16. The current generating circuit according to claim 14, wherein the constant current generating means includes a second transistor connected to a gate electrode of the first transistor. Current generation circuit characterized by. 17. The current generation circuit according to claim 16, wherein the second transistor has a function of converting the reference current into gate voltages of the plurality of first transistors. Current generation circuit. 18. The current generation circuit according to claim 14, wherein the output terminal and the plurality of first terminals are provided.
And a first resistance adding unit corresponding to at least one of the plurality of first transistors between the current generation circuit and the transistor. 19. The current generating circuit according to claim 18, wherein the first resistance adding means is a third transistor. 20. The current generating circuit according to claim 19, wherein the constant current generating means includes a fourth transistor connected to the gate electrode of the third transistor. Current generation circuit. 21. The current generation circuit according to claim 11, wherein the current output means includes an offset current path that defines a lower limit value of the output current. . 22. The current generating circuit according to claim 16, wherein the offset current path includes a fifth transistor whose gate electrode is connected to the second transistor. Current generation circuit. 23. The current generating circuit according to claim 22, further comprising a second resistance adding unit between the output end and the fifth transistor. 24. The current generating circuit according to claim 23, wherein the second resistance adding means is a sixth transistor. 25. The method of driving the current generating circuit according to claim 11, wherein the reference current is set to a value near an intermediate value between the maximum value and the minimum value of the output current. A method for driving a characteristic current generation circuit. 26. The method for driving the current generating circuit according to claim 22, wherein the output current is controlled by changing a gain coefficient of the fifth transistor. Method for driving a current generating circuit. 27. A plurality of scanning lines, a plurality of data lines,
An electro-optical device including an electro-optical element arranged corresponding to an intersection of the scanning line and the data line, a scanning line driving circuit that drives the scanning line, and a data line driving circuit that drives the data line. An apparatus, wherein the data line drive circuit comprises the current generation circuit according to any one of claims 11 to 24, and means for inputting an output current of the current generation circuit to the data line. Electro-optical device. 28. The electro-optical device according to claim 27, wherein the electro-optical element is a current-driven element. 29. The electro-optical device according to claim 28, wherein the current-driven element is an organic electroluminescent element. 30. The electro-optical device according to claim 27, wherein the memory stores data supplied to the electro-optical element, and the data read from the memory is used as the signal for the scanning. An electro-optical device comprising: a line driving circuit or the data line driving circuit, and a control circuit for controlling the operations of the scanning line driving circuit and the data line driving circuit. 31. The electro-optical device according to claim 27, further comprising an oscillation circuit that supplies a reference operation signal to a predetermined circuit that constitutes the drive system. apparatus. 32. A semiconductor integrated circuit device having the current generation circuit according to claim 11 mounted therein. 33. An electronic device on which the electro-optical device according to claim 27 is mounted.