JPH04353823A - Driving method for liquid crystal display element - Google Patents

Abstract

PURPOSE:To make a multistage gradiational display on the liquid crystal display element without using a drive signal of multistage voltage level by controlling the transmissivity of picture elements by varying voltages applied between picture element electrodes and counter electrodes. CONSTITUTION:The respective picture elements of the liquid crystal display element are formed of the picture element electrode, counter electrodes and liquid crystal between them, and its display driving is performed by applying a sequential scanning signal Ss to, for example, the respective counter electrodes, applying a data signal SD to respective signal lines in synchronism with the application of the scanning signal, and performing time-division driving wherein the respective picture elements are selected m order. Namely, a voltage Va-c which has a voltage value and pulse width or has the number of pulses corresponding to image data is applied between the input terminal and counter electrode of an active element in a selection period Ts and then a voltage whose value corresponds to the pulse width of the voltage Va-c is applied between the picture element and counter electrode connected to the active element to control the transmissivity of the picture element.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a liquid crystal display element.

0002

2. Description of the Related Art There are two types of liquid crystal display elements used in display devices such as television sets and personal computers: simple matrix type and active matrix type.

A simple matrix liquid crystal display element has a pair of transparent substrates facing each other with a liquid crystal layer in between, and a plurality of scanning electrodes are provided on one substrate in parallel with each other, and a plurality of scanning electrodes are provided on the other substrate at right angles to the scanning electrodes. This liquid crystal display element is time-divisionally driven by sequentially selecting a plurality of pixels formed by a scanning electrode, a signal electrode, and liquid crystal therebetween.

[0004] Furthermore, in an active matrix liquid crystal display element, one of a pair of transparent substrates facing each other with a liquid crystal layer in between is
On one substrate, pixel electrodes arranged in the row and column directions, active elements connected to each of these pixel electrodes, and signal lines for supplying drive signals to the active elements are provided, and the other substrate is provided with The liquid crystal display element has a structure in which a counter electrode facing the pixel electrode is provided on the top, and a plurality of pixels formed by the pixel electrode, the counter electrode, and the liquid crystal therebetween are sequentially selected and driven in a time division manner. has been done.

[0005] The active matrix liquid crystal display device includes one in which a thin film transistor is used as the active element, and one in which a nonlinear resistance element such as a thin film diode or an MIM (metal-insulating film-metal multilayer element) is used as the active element. Active elements made of thin film diodes include those called diode rings and those called back-to-back.

[0006] All of these liquid crystal display elements are capable of displaying gradations by changing the degree of brightness of pixels, and the gradation display of simple matrix liquid crystal display elements and active matrix liquid crystal display elements using MIM as active elements This is performed using a driving method called pulse width modulation.

The driving method using pulse width modulation described above controls the behavior of the liquid crystal by changing the effective value of the voltage applied to the liquid crystal by changing the pulse width of the driving signal according to image data. This is a method of changing the transmittance of the image in stages according to the image data.

However, in the simple matrix liquid crystal display element described above, the number of time divisions cannot be increased because crosstalk occurs between each pixel, and when the number of time divisions is increased, the contrast of the display decreases. This has the problem that image display deteriorates and gradation display becomes difficult.

In addition, in an active matrix liquid crystal display device using an MIM as an active element, a current flows through the MIM in response to a drive signal supplied from a signal line, and this current causes a gap between the two electrodes of the pixel (the pixel electrode and the counter electrode). Charge is accumulated between the two electrodes), and a voltage corresponding to the accumulated charge is applied to the liquid crystal. However, since the current-voltage characteristics of the MIM described above are slow, the rate of increase of the voltage between the two electrodes is slow. This is slow, and it is difficult to increase the voltage between the electrodes of the pixel within a predetermined selection period.

[0010] This is because the current flowing through the MIM is a tunnel current based on the tunnel effect, and since the area of the MIM used as an active element of a liquid crystal display element is limited, it is difficult to increase the current flowing through the MIM. This is because it is difficult.

[0011] Therefore, active matrix liquid crystal display elements using MIM as active elements have poor heavy electric characteristics for accumulating charges between the electrodes of the pixel. The width of change in the voltage between the pixel electrodes in response to changes in the applied selection voltage is small, and it is not possible to clearly distinguish the voltage between the pixel electrodes that corresponds to the pulse width of the selection voltage. In order to obtain the adjustment display, the voltage value of the selection voltage must be increased, and in particular, in the case of high time division driving, the selection period becomes short, so a higher voltage is required.

Therefore, an active matrix liquid crystal display device using MIM as an active element consumes a large amount of power, and the drive circuit for generating a high-voltage drive signal is required to have a high withstand voltage, so the drive circuit is not integrated. The problem is that it is difficult to create a circuit.

On the other hand, in an active matrix liquid crystal display element using a thin film diode or a thin film transistor as an active element, since the active element is a semiconductor element, the current-voltage characteristic of this active element is rapid.
The voltage between the electrodes of the pixel can be changed within a predetermined selection period.

For this reason, the gradation display of the active matrix liquid crystal display element using the thin film diode or thin film transistor is performed by a driving method called voltage modulation.

[0015] In this voltage modulation driving method, a voltage value corresponding to image data is applied between the drive signal input terminal of the semiconductor active element and the counter electrode during the selection period in which the semiconductor active element consisting of a thin film diode or thin film transistor is turned on. A selection voltage is applied, and during this selection period, charges are rapidly accumulated between the two electrodes of the pixel, and the voltage between the two electrodes is increased to a voltage value corresponding to the image data, causing the liquid crystal of the pixel to have a predetermined value. A voltage is applied thereto, and gradation display is performed by controlling the voltage value of the selection voltage in accordance with image data.

[0016]

[Problems to be Solved by the Invention] However, since the driving method using voltage modulation described above performs gradation display by changing the voltage value of the selection voltage, as a driving signal,
The number of voltage signals required is the same as the number of display gradations, and therefore, as the number of display gradations increases, a power supply circuit that outputs voltage at multiple voltage levels is required, and the drive circuit becomes more complex. I have a problem.

The present invention is directed to a method for driving a liquid crystal display element using a semiconductor active element, and an object thereof is to drive the liquid crystal display element in multiple gradations without using a drive signal with multiple voltage levels. The object of the present invention is to provide a driving method capable of displaying gray scales.

[0018]

[Means for Solving the Problems] The present invention provides a plurality of pixel electrodes arranged in the row and column directions on one of a pair of transparent substrates facing each other with a liquid crystal layer in between, and a plurality of pixel electrodes arranged in the row and column directions. A liquid crystal display element is provided with a semiconductor active element connected to each electrode and a signal line for supplying a drive signal to the active element, and a counter electrode facing the pixel electrode is provided on the other substrate. A method of sequentially selecting and time-divisionally driving a plurality of pixels formed by an electrode, the counter electrode, and a liquid crystal therebetween,

The first aspect of the invention is to apply a selection voltage having a voltage value and a pulse width according to image data between the drive signal input terminal of the active element and the counter electrode during the selection period. The transmittance of the pixel is controlled by applying a voltage corresponding to the voltage value and pulse width of the selection voltage between the pixel electrode connected to the pixel electrode and the counter electrode.

[0020] Furthermore, the second invention is characterized in that a selection voltage having a voltage value and a number of pulses corresponding to the image data is applied between the drive signal input terminal of the active element and the counter electrode during the selection period. The transmittance of the pixel is controlled by applying a voltage corresponding to the voltage value of the selection voltage and the number of pulses between the pixel electrode connected to the active element and the counter electrode. be.

[0021]

[Operation] That is, the present invention provides a modulation method (first invention) that combines modulation by voltage and modulation by pulse width, or modulation by voltage and modulation by pulse number, for liquid crystal display elements using semiconductor active elements. The semiconductor active element is driven by a modulation method (second invention) that combines modulation with Since charge is rapidly accumulated between the pixel electrode and the counter electrode, the voltage applied between the pixel electrode and the counter electrode is equal to the voltage value of the selection voltage applied between the drive signal input terminal of the active element and the counter electrode. It also changes depending on the pulse width or number of pulses.

Therefore, if the voltage value and pulse width or the voltage value and the number of pulses of the selection voltage are controlled according to the image data, the voltage applied between the pixel electrode and the counter electrode can be changed to transmittance can be controlled.

According to the above-mentioned modulation method that combines modulation by voltage and modulation by pulse width, or modulation method by combination of modulation by voltage and modulation by the number of pulses, the number of stages of the voltage value of the selected voltage is By controlling the pulse width or number of pulses for each voltage value,
Since the voltage applied between the pixel electrode and the counter electrode can be changed in multiple steps, the above-mentioned liquid crystal display It is possible to cause the element to display multiple gradations.

[0024]

【Example】

(Embodiments of the first invention) Examples of the first invention will be described below with reference to FIGS. 1 to 16.

First, to explain the structure of the active matrix liquid crystal display element driven by the driving method of this embodiment, FIG. 13 is a plan view of a part of the above liquid crystal display element, and here, a diode ring is used as the semiconductor active element. The figure shows the one using .

This liquid crystal display element has a plurality of pixel electrodes 1 arranged in the row and column directions on one of a pair of transparent substrates (none of which are shown) facing each other with a liquid crystal layer in between. , a semiconductor active element 2 connected to each of these pixel electrodes, and a signal line 3 for supplying a drive signal to the active element 2 are provided, and a counter electrode 4 facing the pixel electrode 1 is provided on the other substrate. It was established.

The semiconductor active element 2 is a so-called diode ring in which the same number of diodes 5 and 6 are connected in parallel in opposite directions, one end of which is connected to the pixel electrode 1 and the other end connected to the signal line 3. has been done.

Although FIG. 13 shows one diode 5 and one diode 6 constituting the diode ring, the forward circuit and reverse circuit of this diode ring are formed by connecting a plurality of diodes in series. It is composed of

The signal line 3 is provided for each active element group arranged in the row direction (horizontal direction in the figure), and the semiconductor active elements 2 are connected to the signal line 3 in each row. Further, the counter electrode 4 is provided for each pixel electrode group arranged in the column direction (vertical direction in the figure), and each counter electrode 4 faces the pixel electrode 1 of each column via a liquid crystal (not shown). . Each pixel of this liquid crystal display element is formed by the pixel electrode 1, the counter electrode 4, and liquid crystal therebetween.

FIG. 14 is an equivalent circuit diagram of one pixel display element of the liquid crystal display element, in which the pixel electrode 1 and the counter electrode 4
Since the pixel formed by the pixel and the liquid crystal between them is equivalent to a capacitor, the pixel display element composed of the pixel and the active element 2 has a capacitance (hereinafter referred to as , pixel capacitance) and an active element 2 consisting of a diode ring are connected in series.

The diodes 5 and 6 constituting the diode ring, which is the active element 2, are thin film diodes in which a pair of electrodes are laminated with a semiconductor layer having a P-I-N junction structure in between. , 6 have a capacitance, the active element 2 also has a capacitance corresponding to the sum of the capacitances of the thin film diodes 5 and 6. Therefore, in the above equivalent circuit, when the diode ring is off,
It is represented by a series connection circuit of the pixel capacitance CCL and the capacitance of the active element 2 (hereinafter referred to as element capacitance) CD, as shown in FIG. 14(b).

This liquid crystal display element is driven to display by applying a drive signal to each signal line 3 and each counter electrode 4, and this display drive is performed, for example, by applying a drive signal to each counter electrode 4.
A scanning signal is sequentially applied to each signal line 3 in synchronization with this.
This is performed by time-division driving in which each pixel is sequentially selected by applying a data signal to the pixel.

To explain this driving method, FIG. 1 is a waveform diagram of the above driving signal, in which (a) shows the waveform of the scanning signal SS applied to the counter electrode 4 of the first row, and (b) shows the waveform of one signal. The waveform of the data signal SD applied to the line 3 is shown, and (c) shows the waveform between the drive signal input end of the active element 2 (the connection end with the signal line 3) and the counter electrode 4 (point a and point c in FIG. (between)
The waveform of the voltage Va-c applied to is shown. Figure 1
In , TS is one field TF divided by the number of rows of pixels (
This is a selection period divided according to the number of signal lines).

The scanning signal SS is a signal that has a selection potential VC1 during the selection period TS and a non-selection potential VC2 during the non-selection period TO, and its polarity is inverted every field TF.

The data signal SD is a signal in which the potential and pulse width of the data pulse for each selection period TS of each opposing electrode 4 differ depending on the image data. The potential of each data pulse of this data signal SD is a value selected from one of two stages, VS1 and VS2, depending on the image data. In this embodiment, the values of the potentials VS1 and VS2 are set to VS1=VS2. /2. The polarity of this data signal SD is opposite to the polarity of the scanning signal SS that is sequentially applied to each counter electrode 4, and the polarity is reversed every field TF.

Note that the data signal SD shown in FIG.
Pulse width W1 of selection period TS1 of counter electrode 4 in the first row
is 2/10 of the selection period (the potential is VS1), the pulse width W2 of the selection period TS2 of the counter electrode 4 in the second row is 6/10 of the selection period (the potential is VS2), and the selection of the counter electrode 4 in the third row The pulse width W3 of period TS3 is 3/10 of the selection period (potential is VS1), but the pulse width W1 of each selection period TS1, TS2, TS3... of this data signal SD is
, W2, W3... are 0/10 (no pulse) to 1 of the selection period TS, depending on the image data and the potential of either VS1 or VS2 selected according to the image data.
It is controlled within a range of 0/10 (same width as the selection period TS).

When the scanning signal SS and the data signal SD are applied to the counter electrode 4 and the signal line 3, the signal line 3
A scanning signal SS and a data signal SD are combined between the drive signal input terminal (hereinafter simply referred to as input terminal) of the active element 2 connected to the counter electrode 4 and the counter electrode 4, as shown in FIG. 1(c). A waveform voltage Va-c (voltage corresponding to the potential difference between the scanning signal SS and the data signal SD) is applied.

Of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4, the selection period TS
The selection voltage applied thereto is the same as the selection potential VC1 of the scanning signal SS when the potential of the data signal SD is 0, and when the potential of the data signal SD becomes the potential VS1 or VS2 of the data pulse, scanning signal SS
A high voltage VC1+VS1 or VC in which the voltage VS1 or VS2 of the data pulse is superimposed on the selection potential VC1 of
It becomes 1+VS2.

Note that the selection voltage (hereinafter referred to as reference selection voltage) VC1 when the potential of the data signal SD is 0 is higher than the threshold voltage of each thin film diode 5, 6 of the diode ring, which is the active element 2. voltage, and the potential of the data signal SD is the data pulse potential VS1 or VS2.
Select voltage VC1+VS1 or VC1+ when
VS2S is an even higher voltage.

Further, the voltage (non-selection voltage) applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period TO is equal to the scanning signal when the potential of the data signal SD is 0. It is the same as the non-selection potential VC2 of the scanning signal SS, and when the potential of the data signal SD becomes the data pulse potential VS, the voltage VC2+VS is obtained by superimposing the data pulse voltage VS1 or VS2 on the non-selection potential VC2 of the scanning signal SS.
1 or VC2+VS2. This voltage VC2+VS
1 or VC2+VS2 is a voltage lower than the reference selection voltage VC1 of the selection voltage applied during the selection period TS. Then, when a selection voltage is applied between the input end of the active element 2 and the counter electrode 4, the pixel electrode 1 connected to the active element 2
A voltage is applied between the electrode 4 and the counter electrode 4.

That is, in FIG. 14, when the selection voltage is applied between a and c, the potential difference between both ends of the active element 2 consisting of a diode ring becomes higher than its threshold voltage, and the active element 2 is turned on. However, a current flows through the pixel electrode 1, and a voltage is applied between b and c (between the pixel electrode 1 and the counter electrode 4).

As described above, when a voltage is applied between b and c, charging of the pixel capacitor CLC formed by the pixel electrode 1, the counter electrode 4, and the liquid crystal therebetween starts. This charging of the pixel capacitor CLC continues during the selection period TS.

Further, when the selection period TS passes and the non-selection period TO begins, charging of the pixel capacitor CLC has progressed and the charging voltage has become high, and the signal line 3 is connected to the non-selection period TO. Since the voltage applied to the input terminal of the active element 2 becomes lower, the potential difference between both ends of the active element 2 becomes smaller, the active element 2 is turned off, and charging to the pixel capacitor CLC is stopped.

In this case, when the active element 2 is turned off, this active element 2 acts as a capacitor, so as shown in FIG.
4 (voltage between the input terminal of the active element 2 and the counter electrode 4) Va-c (selection period TS
and the voltage of the non-selection period TO) is
Pixel capacitor CLC and active element 2 connected in series with each other
The voltage is divided into the element capacitance CD at a ratio opposite to the capacitance ratio.

Therefore, the voltage held in the pixel capacitor CLC during the non-selection period TO is determined by the decrease in the a-c voltage Va-c from the voltage charged during the selection period TS to the pixel capacitor CLC. The voltage will be reduced by the partial voltage value.

[0046]The liquid crystal has a pixel electrode 1 and a counter electrode 4.
It operates by the voltage held between the Note that due to its responsiveness, the liquid crystal does not operate even when a high electric field is applied during the extremely short selection period TS, but operates in response to the voltage held in the pixel capacitor CLC during the non-selection period TO.

Note that since the data signal SD having the waveform as shown in FIG. 1(b) having image data for driving the pixels of each row is applied to the signal line 3, the selection period TS
The image data supplied to the active element 2 of the pixel in the other row is also applied to the input terminal of the active element 2 of the pixel that is in the non-selected state after passing through, together with the data signal SD. The potential at the input terminal fluctuates.

In this way, the active element 2
When the potential at the input terminal of changes, the voltage between a-c Va-c
The holding voltage of the pixel capacitance CLC changes due to the fluctuation of the pixel capacitance CLC due to the fluctuation of the voltage between a and c.
Similar to the voltage change when changing from the selection period TS to the non-selection period TO, the change in the holding voltage of
Of the voltage divided at a ratio opposite to the capacitance ratio with D, only the voltage divided to the pixel capacitance CLC is used, so if the value of the element capacitance CD is made smaller than the pixel capacitance CLC, the Changes in the holding voltage of the pixel capacitor CLC due to changes in the voltage Va-c between a and c during the selection period TO are reduced, thereby reducing changes in the electric field applied to the liquid crystal (voltage between the pixel electrode 1 and the counter electrode 4). can do.

Furthermore, when the next selection period TS begins, a selection voltage with a polarity opposite to that of the previous selection period TS is applied between a and c in FIG. The potential difference becomes higher than its threshold voltage, the active element 2 is turned on, and the pixel capacitor CLC is charged to the opposite polarity. The following operation is similar to the above operation. Next, gradation display using the above driving method will be explained.

FIG. 2 is a waveform diagram of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the selection period TS. Select voltage accordingly.

Among the selection voltages (1) to (14), the selection voltages (1) to (7) all have voltage values VC1+VS1 (selection potential VC1 of the scanning signal SS).
The data pulse voltage VS1 of the data signal SD is superimposed on the data pulse voltage VS1 of the data signal SD), and only the pulse width W is different. In addition, the selection voltages in (8) to (14) all have the same voltage value VC1+VS2 (selection potential V of the scanning signal SS
The data pulse voltage VS2 of the data signal SD is superimposed on C1), and only the pulse width W is different. Note that the pulse widths W of the selection voltages in (8) to (14) are the same as the pulse widths W of the selection voltages in (1) to (7), respectively, and the pulse widths of the selection voltages in (7) and (14) are W
has the same width as the selection period TS.

FIG. 3 shows the input end of the active element 2 and the counter electrode 4.
shows the voltage applied between the pixel electrode 1 and the counter electrode 4 when the selection voltages of (1) to (14) above are applied between them, and the voltages of (1) to (7) are shown. When a selection voltage (a voltage with a voltage value of VC1+VS1) is applied, the voltage applied between the electrodes rises for a time corresponding to the pulse width of the selection voltage on the rising curve of A, and (8) to (14)
When the selection voltage (the voltage value is VC1+VS2) is applied, the voltage applied between the electrodes rises for a time corresponding to the pulse width of the selection voltage on the rising curve of B.

In FIG. 3, (1) to (14) indicate the rise values of the voltage applied between the electrodes when the selected voltages (1) to (14) above are applied;
The selection voltages in (7) have the same voltage value but different pulse widths, so the rise value of the voltage applied between the electrodes when these selection voltages (1) to (7) are applied is different for each selection voltage. different. This is the same when applying the selection voltages (8) to (14), and these (8) to (14)
) selection voltages have the same voltage value, but the pulse width is different, so the rise value of the voltage applied between the electrodes when applying these selection voltages (8) to (14) is also different for each selection voltage. different.

Furthermore, the pulse width W of the selection voltage in (8) to (14) is the same as the pulse width W of the selection voltage in (2) to (7), respectively; Since the selection voltage and the selection voltages (2) to (7) are different in voltage value, the rise values of the voltage applied between the electrodes when the selection voltages (8) to (14) are applied are as follows: (2) to
This value is different from the rising value of the voltage applied between the electrodes when the selection voltage (7) is applied. Note that the rise values of the voltage applied between the electrodes when the selection voltage (7) is applied and when the selection voltage (8) is applied are almost the same.

4 to 8 show the waveforms of the voltage Va-c applied between the input end of the active element 2 and the counter electrode 4, and the waveform of the voltage Vb applied between the pixel electrode 1 and the counter electrode 4. -c shows the relationship.

FIG. 4 shows the state when the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 0/10 (no pulse) of the selection period TS. A selection voltage having a waveform as shown in (a) is applied between the input end of the element 2 and the counter electrode 4.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
and the interelectrode voltage Vb-c applied between the counter electrode 4
As shown in (b), rises with a rising curve corresponding to the reference selection voltage VC1 throughout the selection period TS.

Then, when the selection period TS passes and the non-selection period TO begins, and the active element 2 is turned off, the voltage of the pixel capacitor CLC changes from the voltage charged during the selection period TS to the voltage Va between a and c. -c pixel capacitance C
The pixel capacitance C is the inverse ratio of the capacitance ratio of LC and element capacitance CD.
The voltage V0 is reduced by the voltage divided by the LC, and this voltage V0 becomes the holding voltage between the pixel electrode 1 and the counter electrode 4.

FIG. 5 shows the state when the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 2/10 of the selection period TS, and its voltage value is set to VS1. A selection voltage having a waveform as shown in (a) is applied between the input end of the active element 2 and the counter electrode 4. This selection voltage is the voltage (1) shown in FIG.

Note that in this embodiment, the data signal SD
, the data pulse rises a time corresponding to the pulse width from the end of the selection period TS, and the selection period T
Therefore, the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 is the reference selection voltage VC1 from the beginning to the end of the selection period TS. At the end of the period TS, the voltage VS of the data pulse is set to the reference selection voltage VC1.
1 is superimposed, resulting in a high voltage VC1+VS1.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
and the interelectrode voltage Vb-c applied between the counter electrode 4
As shown in (b), from the beginning to the end of the selection period TS, rises according to the rise curve according to the reference selection voltage VC1, and further rises with the high voltage VC at the end of the selection period TS.
By applying 1+VS1, the voltage rises rapidly and becomes as shown in Fig. 3.
The voltage value of (1) is reached.

Further, when the selection period TS passes and the non-selection period TO begins, the voltage of the pixel capacitor CLC becomes the voltage V1 which is decreased at a constant ratio, and this voltage V1 is the voltage between the pixel electrode 1 and the counter electrode 4. The holding voltage will be between.

FIG. 6 shows the state when the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is the same as that in FIG. 5, and its voltage value is VS2,
At this time, a selection voltage having a waveform as shown in (a) is applied between the input end of the active element 2 and the counter electrode 4. This selection voltage is the voltage (8) in FIG.

In this case, since the data pulse width of the selection voltage is the same as the data pulse width of the selection voltage in FIG. -c rises rapidly at the same time and for the same time as in FIG. 5(b), as shown in (b), but the voltage value VC1+VS2 of the selection voltage at this time is the voltage value VC1+VS1 of the selection voltage in FIG. 5(a). Because it is higher, the interelectrode voltage Vb
-c rise is even more rapid than in FIG. 5(b), so the interelectrode voltage Vb-c is (8
) rises to the voltage value.

In this case as well, when the selection period TS passes and the non-selection period TO begins, the voltage of the pixel capacitor CLC decreases at a constant ratio to the voltage V8, and this voltage V8 is applied to the pixel electrode 1 and the counter electrode. The holding voltage will be between 4 and 4.

FIG. 7 also shows that the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 5.
/10, and the voltage value is VS2. In this case, a selection voltage with a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. . This selection voltage is the voltage (10) in FIG.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
and the interelectrode voltage Vb-c applied between the counter electrode 4
As shown in (b), from the beginning to the middle of the selection period TS, rises according to the rise curve according to the reference selection voltage VC1, and furthermore, in the middle of the selection period TS, the voltage VS2 of the data pulse is superimposed on the reference selection voltage VC1. The voltage rises rapidly by applying the high voltage VC1+VS2. At this time, since the voltage value of the selection voltage is the same as in FIG. 6(a),
The rising curve of the interelectrode voltage Vb-c when the selection voltage becomes the data pulse superimposed voltage (VC1 + VS2) is the same as in Fig. 6(b), but the data pulse width of the selection voltage is different from Fig. 6(a). Since the data pulse superimposed voltage is applied for a long time, the interelectrode voltage Vb-c rises to the voltage value (10) in FIG. 3.

Further, when the selection period TS passes and the non-selection period TO begins, the voltage of the pixel capacitor CLC decreases at a constant ratio to the voltage V10, and this voltage V10 is applied between the pixel electrode 1 and the counter electrode 4. The holding voltage will be .

Furthermore, in FIG. 8, the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 10/10 of the selection period TS (same width as the selection period TS), and the voltage value is set to VS2. In this state, a selection voltage having a waveform as shown in (a) is applied between the input end of the active element 2 and the counter electrode 4. This selection voltage is the voltage (14) in FIG.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
The voltage Vb-c applied between and the counter electrode 4 is (b
), the voltage rises rapidly from the beginning of the selection period TS by application of a high voltage VC1+VS2, in which the data pulse voltage VS2 is superimposed on the reference selection voltage VC1.

Further, when the selection period TS passes and the non-selection period TO begins, the voltage of the pixel capacitor CLC decreases at a certain ratio to the voltage V3, and this voltage V3 is applied between the pixel electrode 1 and the counter electrode 4. The holding voltage will be .

The selection period TS in FIGS. 4 to 8 above
The voltage V applied between the pixel electrode 1 and the counter electrode 4 during
Peak value of b-c (voltage value at the end of selection period TS)
are the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, the current-voltage characteristics of the diode ring which is the active element 2, and the time (selection period) TS during which the selection voltage is applied. Determined by

That is, during the selection period TS, the pixel electrode 1
and the interelectrode voltage Vb-c applied between the counter electrode 4
rises according to a rising curve determined by the current-voltage characteristics of the active element 2 according to the selected voltage value of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4, and the selected period TS is When the selection voltage is no longer applied after a certain period of time, the rise stops.

[0074] Then, the input end of the active element 2 and the counter electrode 4
The selection voltage applied between the reference selection voltage VC1 and the first data pulse voltage V
First data pulse superimposed voltage VC1+V superimposed by S1
S1, and a second data pulse superimposed voltage VC in which a second data pulse voltage VS2 is superimposed on the reference selection voltage VC1.
1+VS2, the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4 is equal to this voltage VC when the reference selection voltage VC1 is applied.
1, and when the first data pulse superimposed voltage VC1+VS1 is applied, it rises with a steep rising curve corresponding to this voltage VC1+VS2, and the second data pulse superimposed voltage VC1+V
When S1 is applied, the voltage rises at an even steeper rise curve in accordance with this voltage VC1+VS1.

[0075] Furthermore, these applied voltages VC1, VC1+V
The above interelectrode voltage Vb-c for S1, VC1+VS2
The rise amount of each voltage VC1, VC1+VS1,
In order to correspond to the application time of VC1+VS2, the voltage Vb-
The peak value of c is determined by the application time of the reference selection voltage VC1 during the selection period TS and the data pulse superimposed voltage VC1+V.
It changes depending on the ratio to the application time of S1 and VC1+VS2.

Therefore, the voltage held in the pixel capacitor CCL when the selection period TS passes and the non-selection period TO begins (from the voltage charged during the selection period TS, a
Vb-c (voltage decreased by the divided voltage value to the pixel capacitance CLC out of the decrease in the voltage between Depends on data pulse width.

That is, for example, when the selection voltage is a voltage with a data pulse width of 0 (no pulse), the voltage Vb-c held in the pixel capacitor CCL falls within the voltage control range as shown in FIG. becomes the lowest voltage V0 among them,
If the selection voltage has a data pulse with the same width as the selection period TS as shown in (14) in FIG. The voltage Vb-c becomes the highest voltage Vmax in the voltage control range as shown in FIG.

Furthermore, even if the selection voltage is a voltage having a data pulse having the same width as the selection period TS as shown in (7) in FIG. 2, the voltage value is lower than the first data pulse voltage VS2. or the selected voltage is (1) in Figure 2.
~ (6) and (8) ~ (13) If the voltage has a data pulse in a part of the selection period TS,
The voltage Vb-c held in the pixel capacitor CCL is a voltage between the lowest value and the highest value of the voltage control range, and this voltage changes depending on the data pulse width of the selection voltage and its voltage value.

Note that the selection voltage having a data pulse in a part of the selection period TS is not limited to the waveforms (1) to (6) and (8) to (13) in FIG.
It may be a waveform in which a data pulse is superimposed on the initial or middle period of S.

FIG. 9 shows an example in which the selection voltage has a waveform in which a data pulse is superimposed at the beginning of the selection period TS.
shows an example in which the selection voltage is a waveform in which a data pulse is superimposed in the middle of the selection period TS, and in this case also, the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4
When the reference selection voltage VC1 is applied, it rises with a rising curve corresponding to this voltage VC1, and while the voltage on which a data pulse is superimposed (VC1+VS1 in the figure) is applied, it rises with a rising curve corresponding to this data pulse superimposed voltage. The voltage Vb-c held in the pixel capacitor CCL is
The value corresponds to the data pulse width of the selection voltage and its voltage value. Note that the selection voltages shown in FIGS. 9 and 10(a) have data pulse widths and voltage values as shown in FIG.
is the same as the selection voltage shown in (a) of
Voltage Vb- applied between pixel electrode 1 and counter electrode 4
c is the same as the voltage V1 shown in FIG. 5(b).

On the other hand, the alignment state of the liquid crystal varies depending on the value of the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4 and maintained in the pixel capacitor CLC, and the transmittance of the pixel varies depending on the liquid crystal molecules. It changes depending on the rising angle with respect to the substrate surface.

Therefore, as mentioned above, the selection period TS
A selection voltage having a pulse width according to image data is applied between the input end of the active element 2 in the middle and the counter electrode 4, and the voltage is applied between the pixel electrode 1 connected to the active element 2 and the counter electrode 4. By applying a voltage having a value corresponding to the data pulse width of the selection voltage, it is possible to control the transmittance of the pixel and realize gradation display.

The number of gradations in the gradation display described above is determined by how many levels the value of the voltage Vb-c to charge the pixel capacitance CCL can be selected during the limited selection period TS.

[0084] Then, the input end of the active element 2 and the counter electrode 4
In gradation display using pulse width modulation, in which the voltage applied between the pixel electrode 1 and the counter electrode 4 is controlled by changing the pulse width of the selection voltage applied between the pixels, the pixel corresponding to the data pulse width of the selection voltage is Although the change in the applied voltage between the electrode 1 and the counter electrode 4 is determined by the current-voltage characteristics of the active element,
The liquid crystal display element using the semiconductor active element 2 consisting of a diode ring has rapid current-voltage characteristics and high responsiveness, so that the voltage applied between the pixel electrode 1 and the counter electrode 4 is reduced. The voltage can be changed significantly.

FIG. 15 shows the active element 2 of the above liquid crystal display element.
The current-voltage characteristics of the diode ring are shown in comparison with the current-voltage characteristics of the MIM that utilizes the tunneling effect.As shown in this figure, the diode ring is
Compared to IM, current-voltage characteristics are rapid and responsiveness is also high.

Therefore, the above-mentioned liquid crystal display element using a diode ring as the active element 2 can display gradations in high time division driving without increasing the applied voltage unlike the liquid crystal display element using MIM as an active element. is possible.

The current-voltage characteristics of the diode ring can be arbitrarily selected by changing the thickness of the I-type semiconductor layer of the thin film diodes 5 and 6.
The above current-voltage characteristics can also be arbitrarily selected by changing the number of thin film diodes 5 and 6 between a and b in (a).

That is, the current-voltage characteristics of the diode ring become sharper as the thickness of the I-type semiconductor layer of the thin film diodes 5 and 6 becomes thinner. The smaller the number, the faster it becomes.

FIG. 16 shows the diode ring as active element 2.
2 is a diagram showing the charging characteristics of the pixel capacitance CLC with respect to the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4 of the liquid crystal display element, in which (a) is a typical current - Pixel capacitance charging characteristics of a liquid crystal display element using a diode ring with voltage characteristics; (b) shows the pixel capacitance charging characteristics of a liquid crystal display element using a diode ring with steeper current-voltage characteristics. .

The pixel capacitance charging characteristic shown in FIG. 16(a) is a characteristic in which the charging voltage of the pixel capacitance CLC active element 2 reaches its peak in a charging time of about 40 μs, and a liquid crystal display having this pixel capacitance charging characteristic The element has a selection period TS of approximately 40
Suitable for high time division driving with a time division number of microseconds.

Therefore, the gradation display of this liquid crystal display element can be performed by controlling the pulse width of the selection voltage within the range of 0 to about 40 μsec.
In the case of a negative display type liquid crystal display element, the pixels transmit light when a voltage is applied between them. It is sometimes darkest, and brightest when a selected voltage with a pulse width of about 40 μs is applied, and when a selected voltage with a pulse width in the range of 0 to about 40 μs is applied, the brightness changes depending on this pulse width. It's going to be.

By the way, as mentioned above, the number of display gradations is determined by the voltage V charged to the pixel capacitor CCL during the selection period TS.
Although it depends on how many levels of b-c values can be selected, in order to obtain a gradation display with clear gradation differences, it is necessary to
It is necessary to maintain a somewhat large difference in the voltage applied between the two.

For this reason, the pulse width of the selection voltage needs to be controlled with a width difference that allows the pixel capacitor CLC to be charged with a voltage difference Vb-c that provides a clear gradation difference. ,Therefore, there is a restriction on the number of pulse width steps.

Therefore, in the above driving method, not only the pulse width of the selection voltage applied between the input end of the active element 2 and the counter electrode 4 is changed depending on the image data, but also the voltage value of the selection voltage is changed. , VS1 and VS2 depending on the image data
The gradation is displayed using a modulation method that combines voltage modulation and pulse width modulation. Note that the voltage values VS1 and VS2 of the selection voltages may both be considerably lower than the voltage required to cause a liquid crystal display element having an MIM as an active element to display gradations.

In this way, when the voltage value of the selection voltage is changed in two steps, VS1 and VS2, the rise curve of the interelectrode voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4 becomes Since the selection voltage changes to either of the two rising curves A and B shown in FIG. 3 depending on the voltage values VS1 and VS2, two voltage levels are applied to the pixel electrode 1 and the counter electrode 4 for the same pulse width. Therefore, even if there is a restriction on the number of pulse width steps, it is possible to increase the number of voltage steps charged in the pixel capacitor CLC and perform multi-step gradation display.

That is, the voltage value of the selection voltage is set to VS1 and V
S2, and the pulse width of the selection voltage is changed to 7 for each voltage value VS1 and VS2, for example, as shown in FIG.
In the case of a stepwise change, voltages (1) to (14) shown in FIG. 3 can be applied between the pixel electrode 1 and the counter electrode 4 to realize a multi-step gradation display. can. In addition,
In this example, the voltage between the electrodes when the selection voltages (7) and (8) in Figure 2 are applied are almost the same value as in (7) and (8) in Figure 2, so (7) As for the selection voltage in (8), only one of them needs to be adopted, so
In this example, the number of display gradations is 13 (however, 14 if the gradation when a non-pulse selection voltage is applied is added).

This also applies to the liquid crystal display element having the pixel capacitance charging characteristic shown in FIG. 16(b). Note that the pixel capacitance charging characteristic shown in FIG. 16(b) is 10
The charging voltage of the pixel capacitance CLC active element 2 reaches its peak in a charging time of ~15 μs, and a liquid crystal display element having this pixel capacitance charging characteristic has a selection period TS of 10 to 1
Since it can be done in a very short time of 5 μs, the number of display gradations can be reduced as shown in Figure 16 (
Although the liquid crystal display element has the same pixel capacitance charging characteristics as shown in a), it can be time-divisionally driven with a much larger number of time-divisions.

[0098] The above driving method drives a liquid crystal display element using a semiconductor active element 2 consisting of a diode ring.
Because it is driven by a modulation method that combines voltage modulation and pulse width modulation, it is capable of multiple voltage levels, unlike the voltage modulation method conventionally used to drive liquid crystal display elements using semiconductor active elements. There is no need to use a drive signal of 1, and therefore, the liquid crystal display element can display multiple gradations with a drive circuit having a simple configuration.

Further, in the above embodiment, the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the selection period TS has the waveforms (1) to (14) shown in FIG. However, this selection voltage may be a voltage having waveforms (1) to (11) as shown in FIG. 11, for example.
In that case, 11 of (1) to (11) shown in Figure 12
Voltages in stages are applied between the pixel electrode 1 and the counter electrode 4 to display 11 gray scales (12 stages if you add the gray scale when a non-pulse selection voltage is applied). be able to.

Note that the reference selection voltage VC1 of the selection voltages shown in FIG. 11 and the data pulse superimposed voltage VC1+VS1,V
Of C1+VS2, the reference selection voltage VC1 and the second data pulse superimposed voltage VC1+VS2 are the voltages VC1 and VC1 in FIG.
It is the same as VC1+VS2. Further, the voltage VS1 of the first data pulse is approximately 2/3 of the voltage VS2 of the second data pulse, and therefore the first data pulse superimposed voltage VC1+VS1 has a value slightly higher than the voltage VC1+VS1 in FIG. . (Embodiment of the second invention) Next, an embodiment of the second invention will be described with reference to FIGS. 17 to 21. Note that descriptions of matters that overlap with the embodiment of the first invention described above will be omitted.

To explain the driving method of this embodiment, FIG.
7 is a waveform diagram of a drive signal, (a) is a waveform of a scanning signal SS applied to the counter electrode 4 of the first row of the liquid crystal display element shown in FIG. 13, and (b) is a waveform diagram of one signal line 3. (c) is the waveform of the data signal SD applied to the active element 2 between the drive signal input end (the connection end with the signal line 3) and the counter electrode 4 (between the point a and the point c in FIG. 14) The voltage Va applied to
-c waveform is shown.

The scanning signal SS is the same signal as in the first embodiment of the invention, and during the selection period TS the selection potential VC is
1. During the non-selection period TO, the non-selection potential VC2 becomes 1.
The polarity is reversed for each field TF.

On the other hand, the data signal SD is a signal in which the potential and the number of data pulses for each selection period TS of each counter electrode 4 differ depending on the image data, and the pulse width of each data pulse is constant. .

The potential of each data pulse of this data signal SD is a value selected from one of two stages, VS1 and VS2, depending on the image data. In this embodiment, the values of the potentials VS1 and VS2 are set to VS1=VS2/2. The polarity of this data signal SD is opposite to the polarity of the scanning signal SS that is sequentially applied to each counter electrode 4, and the polarity is reversed every field TF.

It should be noted that the data signal SD shown in FIG.
, the number of pulses in the selection period TS2 of the counter electrode 4 in the second row is 5.
, the number of pulses in the selection period TS3 of the counter electrode 4 in the third row is 3.
However, each selection period TS of this data signal SD
The number of pulses for each of TS1, TS2, TS3, .

When the scanning signal SS and the data signal SD are applied to the counter electrode 4 and the signal line 3, the signal line 3
17(c) between the drive signal input terminal (hereinafter simply referred to as input terminal) of the active element 2 connected to the
A voltage Va-c having a waveform obtained by combining the scanning signal SS and the data signal SD (a voltage corresponding to the potential difference between the scanning signal SS and the data signal SD) Va-c is applied.

The voltage value of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4, that is, the selection voltage VC1, VC1+V applied during the selection period TS.
The values of S1, VC1+VS2 and the voltages VC2, VC2+VS1, VC2+VS2 applied during the non-selection period TO
The value of is the same as in the first embodiment of the invention.

[0108] Then, the input end of the active element 2 and the counter electrode 4
When a selection voltage is applied between the pixel electrode 1 and the counter electrode 4 connected to the active element 2, a voltage is applied between the pixel electrode 1 and the counter electrode 4 connected to the active element 2.
Charging of the pixel capacitor CLC formed by the pixel electrode 1, the counter electrode 4, and the liquid crystal therebetween is started.

Further, when the selection period TS passes and the non-selection period TO begins, and the voltage Va-c between a and c becomes low, the active element 2 is turned off and charging to the pixel capacitance CLC is stopped, and the pixel capacitance The voltage of CLC is changed from the voltage during the selection period TS to the divided voltage value to the pixel capacitance CLC of the decrease in the a-c voltage Va-c (the capacitance between the pixel capacitance CLC and the element capacitance CD of the active element 2). The voltage is lowered by the voltage divided by the pixel capacitor CLC among the voltages divided at a ratio opposite to the ratio.

Note that even when the data signal SD is a signal in which the number of data pulses for each selection period TS of each counter electrode 4 is different depending on the image data, the holding voltage of the pixel capacitor CLC is different from that of the pixels in other rows. Although the value of the element capacitance CD changes depending on the fluctuation of the voltage Va-c between a and c due to the influence of the image data supplied to the active element 2, as in the embodiment of the first invention, the value of the element capacitance CD is If it is set to a small value, changes in the holding voltage of the pixel capacitor CLC due to fluctuations in the voltage Va-c between a and c during the non-selection period TO can be made small, and the electric field applied to the liquid crystal (between the pixel electrode 1 and the counter electrode 4) can be reduced. fluctuations in voltage) can be reduced. Next, gradation display by the above driving method will be explained. This gradation display is basically performed in the same manner as in the embodiment of the first invention described above.

18 to 20 show the waveform of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4, and
Voltage Vb- applied between pixel electrode 1 and counter electrode 4
It shows the relationship with c.

FIG. 18 shows the active element 2 during the selection period TS.
This is the state when the number of data pulses of the data signal SD applied to is 2 and the voltage value is VS1, and (a)
is the waveform of the selection voltage applied between the input end of the active element 2 and the counter electrode 4, and (b) is the waveform of the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4.

FIG. 19 shows the active element 2 during the selection period TS.
Figure 18 shows the number of data pulses of the data signal SD applied to
(a) is the waveform of the selection voltage applied between the input end of the active element 2 and the counter electrode 4, (b) ) is the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4
This is the waveform of

FIG. 20 shows the state when the number of data pulses of the data signal SD applied to the active element 2 during the selection period TS is the maximum allowable number of pulses n, and the voltage value is VS2, and (a ) is the waveform of the selection voltage applied between the input end of the active element 2 and the counter electrode 4, and (b) is the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4.
This is the waveform of

Note that when the number of data pulses of the data signal SD applied to the active element 2 during the selection period TS is 0 (no pulse), between the pixel electrode 1 and the counter electrode 4,
Waveform similar to (b) in FIG. 4 (however, the non-selection period TO
A voltage Vb-c (with different waveforms) is applied.

[0116] Also, in the driving method of this embodiment,
Voltage Vb- applied between pixel electrode 1 and counter electrode 4
When the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 is the reference selection voltage VC1, c rises with a rising curve corresponding to this voltage VC1, and when the selection voltage reaches the reference selection voltage VC1. first data pulse voltage V
When S1 reaches the superimposed voltage VC1+VS1, it rises with a steep rising curve corresponding to this voltage VC1+VS1, and the selection voltage becomes second to the reference selection voltage VC1.
The voltage VC1+VS which is superimposed with the data pulse voltage VS2 of
2, the voltage rises with a steeper rising curve according to the voltage VC1+VS2, but since the selection voltage is a voltage with a different number of data pulses depending on the image data, the pixel electrode 1 and the counter electrode 4 The voltage Vb-c applied between the two rises in a stepwise manner according to the number of data pulses of the selection voltage.

That is, FIG. 21 shows an enlarged view of the rising state of the voltage Vb-c applied between the pixel electrode and the counter electrode shown in FIG. 19(b), and this voltage Vb-c is Voltage V superimposed with data pulse voltage VS
When it becomes C1+VS2, it rises with a steep rise curve for a time corresponding to this data pulse width, and when the selection voltage reaches the reference selection voltage VC1, it rises for that time (
The voltage rises according to a rise curve corresponding to the voltage VC1 (time between pulses), and rises in a stepwise manner by repeating this process.

Therefore, the voltage held in the pixel capacitor CCL when the selection period TS passes and the non-selection period TO begins (from the voltage charged during the selection period TS, a
Vb-c (voltage decreased by the divided voltage value to the pixel capacitance CCL out of the decrease in the voltage between Depends on the number of pulses.

For example, when the selection voltage is a voltage at which the number of data pulses is 0 (no pulse), the pixel capacitance C
The voltage Vb-c held at CL is the lowest voltage V0 (see Figure 4) in its voltage control range, and the selection voltage is a voltage with data pulses of the maximum allowable number n of pulses as shown in Figure 20. In this case, the voltage Vb-c held in the pixel capacitor CCL is the highest voltage V in the voltage control range.
becomes max.

[0120] Furthermore, when the selection voltage is a voltage having a data pulse in a part of the selection period TS, the voltage Vb-c held in the pixel capacitance CCL is between the lowest value and the highest value of the voltage control range. The voltage between the values (Fig. 18 and Fig. 1
9, the voltage becomes V1, V2), and this voltage changes depending on the voltage value of the selection voltage and the number of pulses.

Note that the selection voltage shown in (a) of FIGS. 18 and 19 (voltage during the selection period TS of Va-c)
is a waveform in which a data pulse is superimposed at the end of the selection period TS, but the timing at which the data pulse of this selection voltage is superimposed may be at the beginning or middle of the selection period TS.

The rising angle of the liquid crystal is determined by the voltage applied between the pixel electrode 1 and the counter electrode 4 (pixel capacitance CL
The transmittance of the pixel changes depending on the rising angle of the liquid crystal.

Therefore, as described above, the selection period TS
A selected voltage with a voltage value and number of pulses corresponding to the image data is applied between the input end of the active element 2 inside and the counter electrode 4,
By applying a voltage corresponding to the voltage value of the selection voltage and the pulse width between the pixel electrode 1 connected to the active element 2 and the counter electrode 4, the transmittance of the pixel can be controlled and gradation display can be performed. It can be realized.

The number of gradations in this gradation display is determined by the voltage Vb-c charged to the pixel capacitor CCL during the limited selection period TS.
As explained in the embodiment of the first invention, the above-mentioned liquid crystal display element using the semiconductor active element 2 consisting of a diode ring is determined by how many levels of the value can be selected.
Since the current-voltage characteristics of the active element 2 are rapid and the responsiveness is high, by controlling the voltage value and the number of pulses of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, the pixel The voltage applied between the electrode 1 and the counter electrode 4 can be changed greatly.

[0125] The above driving method drives a liquid crystal display element using a semiconductor active element 2 consisting of a diode ring.
Since it is driven using a modulation method that changes the number of data pulses of the selection voltage depending on the image data, it is not multi-stage like the voltage modulation method that is conventionally used as a method for driving liquid crystal display elements using semiconductor active elements. It is not necessary to use a drive signal with a voltage level of 1, and therefore the liquid crystal display element can display multiple gradations with a drive circuit having a simple configuration.

[0126] Also in the driving method of this embodiment,
As a liquid crystal display element, a diode ring which is an active element 2 has a sharp current-voltage characteristic (thin film diode 5,
By reducing the thickness of the I-type semiconductor layer 6 or by reducing the number of thin film diodes 5 and 6), the selection period TS can be shortened and time-division driving can be performed with a larger number of time divisions. Can be done. (Other application examples of the present invention)

[0127] In the embodiments of the first invention and the second invention, the voltage value of the selection voltage is set to two of VS1 and VS2.
Although the selection voltage is selected in stages, the voltage value of this selection voltage may be selected in two or more stages.In this way, the voltage value of the selection voltage can be controlled in many stages, and the pulse width or number of pulses can be adjusted for each voltage value. By controlling , it is possible to display a larger number of gradations. However, even in this case, the number of steps of the voltage value of the selection voltage is much smaller than when displaying multiple gradations using only voltage modulation, so a drive signal with multiple voltage levels is used. There's no need.

Further, the embodiments of the first invention and the second invention described above are directed to a liquid crystal display element using a diode ring as the active element 2, but the driving method of the present invention Various types of semiconductors include not only liquid crystal display elements with active elements, but also active elements with a back-to-back structure consisting of thin film diodes, active elements in which the insulating film of MIM is replaced with a semiconducting film with a semiconductor function, and thin film transistors. It can be widely applied to liquid crystal display elements using active elements.

[0129]

Effects of the Invention The present invention drives a liquid crystal display element using a semiconductor active element using a modulation method that combines modulation by voltage and modulation by pulse width or number of pulses. It is possible to cause the liquid crystal display element to perform multi-gradation display without using a drive signal with multiple voltage levels as in the driving method according to the present invention.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram of a scanning signal, a data signal, and a voltage applied between a signal input terminal of an active element and a counter electrode, showing an embodiment of the first invention.

FIG. 2 is a waveform diagram of various selection voltages applied between an input end of an active element and a counter electrode.

FIG. 3 is a diagram showing an inter-electrode voltage applied between a pixel electrode and a counter electrode when the selection voltage shown in FIG. 2 is applied.

FIG. 4 shows the voltage applied between the input end of the active element and the counter electrode and the pixel electrode when the pulse width of the data signal applied to the active element is 0/10 of the selection period (no pulse). FIG. 3 is a waveform diagram of a voltage applied between and a counter electrode.

[Fig. 5] The voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied to the active element is 2/10 of the selection period and the voltage value is VS1. , a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

[Fig. 6] The voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied to the active element is 2/10 of the selection period and the voltage value is VS2. , a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

[Fig. 7] The voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied to the active element is 5/10 of the selection period and the voltage value is VS2. , a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 8 shows the voltage applied between the input end of the active element and the counter electrode when the pulse width of the data signal applied to the active element is 10/10 of the selection period and the voltage value is VS2. , a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 9 is a diagram showing a modified example of the waveform in FIG. 5;

10 is a diagram showing another modification of the waveform shown in FIG. 5. FIG.

FIG. 11 is a waveform chart showing other examples of various selection voltages applied between the input end of the active element and the counter electrode.

FIG. 12 is a diagram showing an inter-electrode voltage applied between a pixel electrode and a counter electrode when the selection voltage shown in FIG. 11 is applied.

FIG. 13 is a plan view of a portion of a liquid crystal display element.

FIG. 14 is an equivalent circuit diagram of one pixel display element of a liquid crystal display element.

FIG. 15 is a current-voltage characteristic diagram of a diode ring and MIM, which are active elements.

FIG. 16 is a diagram showing charging characteristics of a pixel capacitance with respect to applied voltage of a liquid crystal display element having a diode ring as an active element.

FIG. 17 is a waveform diagram of a scanning signal, a data signal, and a voltage applied between a signal input terminal of an active element and a counter electrode, showing an embodiment of the second invention.

[Fig. 18] When the number of pulses of the data signal applied to the active element is 2 and the voltage value is VS1, the voltage applied between the input end of the active element and the opposing electrode, and the voltage applied between the pixel electrode and the opposing electrode. A waveform diagram of the voltage applied between the electrodes.

FIG. 19 shows the voltage applied between the input end of the active element and the opposing electrode, and the voltage applied between the input end of the active element and the opposing electrode, when the number of pulses of the data signal applied to the active element is 2, and the voltage value is VS2. A waveform diagram of the voltage applied between the electrodes.

FIG. 20 shows the voltage applied between the input end of the active element and the counter electrode, when the number of pulses of the data signal applied to the active element is the maximum permissible number of pulses n, and the voltage value is VS2; FIG. 3 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 21 is an enlarged view of the rising state of the voltage shown in FIG. 20(b).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...Pixel electrode, 2...Active element, 3...Signal line, 4...Counter electrode, TS...Selection period, TO...Non-selection period, SS...
Scanning signal, AD...data signal, Va-c...voltage applied between the input end of the active element and the counter electrode. Vb-c
...Voltage applied between the pixel electrode and the counter electrode.

Claims (2)

[Claims] Claim 1: A plurality of pixel electrodes arranged in row and column directions on one of a pair of transparent substrates facing each other with a liquid crystal layer in between, and a semiconductor active electrode connected to each of these pixel electrodes. A liquid crystal display element is provided with an element and a signal line for supplying a drive signal to the active element, and a counter electrode facing the pixel electrode is provided on the other substrate. In a method in which multiple pixels formed by a liquid crystal are sequentially selected and time-divisionally driven, a voltage value and pulse width are applied between the drive signal input terminal of the active element and the counter electrode during the selection period according to the image data. By applying a selection voltage of 1. A method for driving a liquid crystal display element, the method comprising controlling the ratio. 2. A plurality of pixel electrodes arranged in row and column directions on one of a pair of transparent substrates facing each other with a liquid crystal layer in between, and a semiconductor active electrode connected to each of these pixel electrodes. A liquid crystal display element is provided with an element and a signal line for supplying a drive signal to the active element, and a counter electrode facing the pixel electrode is provided on the other substrate. In a method of sequentially selecting and time-divisionally driving multiple pixels formed by a liquid crystal, a voltage value and number of pulses are applied between the drive signal input terminal of the active element and the counter electrode during the selection period according to image data. By applying a selection voltage of , a voltage corresponding to the voltage value of the selection voltage and the number of pulses is applied between the pixel electrode connected to the active element and the counter electrode, and the transmission of the pixel is 1. A method for driving a liquid crystal display element, the method comprising controlling the ratio.