JP3211270B2 - Driving method of liquid crystal display element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving an active matrix liquid crystal display device using a non-linear resistance element as an active element.

[0002]

2. Description of the Related Art As an active matrix liquid crystal display element used for a display device such as a television set or a personal computer, there is an active element using a non-linear resistance element as an active element.

An active matrix liquid crystal display element using this nonlinear resistance element as an active element is composed of pixel electrodes arranged in a row direction and a column direction on one of a pair of transparent substrates opposed to each other with a liquid crystal layer interposed therebetween. And an active element composed of a non-linear resistance element connected to each of the pixel electrodes, and a signal line for supplying a drive signal to the active element. A counter electrode facing the pixel electrode is provided on the other substrate. This liquid crystal display element has a configuration in which a scanning signal is supplied to one of the signal line and the counter electrode, and a data signal is supplied to the other, so that the pixel electrode and the counter electrode and the liquid crystal between them are connected. Are sequentially selected and driven in a time-division manner.

As a non-linear resistance element used for an active element of this active matrix liquid crystal display element, MI
An element having an M structure (metal-insulating film-metal laminated structure) (hereinafter, referred to as an M-structure)
MIM) and an element having a semiconductor such as a thin-film diode. Active elements including the thin-film diode include a diode ring and a back-to-back active element.

However, the active matrix liquid crystal display element using the MIM as an active element has a pixel electrode voltage (pixel electrode and counter electrode) corresponding to a selection voltage applied between the drive signal input terminal of the MIM and the counter electrode. ) Has a problem of poor followability.

That is, in an active matrix liquid crystal display element using an MIM as an active element, a current flows through the MIM according to a drive signal supplied from a signal line, and this current causes electric charges to be accumulated between both electrodes of a pixel. A voltage corresponding to the accumulated charge is applied to the liquid crystal.
Has a slow current-voltage characteristic and does not allow a sufficient current to flow, so that the speed at which the voltage between both electrodes rises is slow. Therefore, the voltage between the electrodes of the pixel cannot be increased within the limited selection period, and the voltage between the electrodes of the pixel follows the selection voltage applied between the input terminal of the MIM and the counter electrode. It does not change.

This is because the current flowing through the MIM is a tunnel current based on the tunnel effect, and the MIM used as an active element of the liquid crystal display element has a limited element area, so that it is difficult to increase the tunnel current. Because.

For this reason, a liquid crystal display element using an MIM as an active element needs to be driven at a considerably high voltage (especially, in the case of high time division driving, the selection period is short, so that a higher voltage is required). Therefore, power consumption is large, and a driving circuit for generating a high-voltage driving signal is required to have a high withstand voltage. Therefore, it is difficult to integrate the driving circuit into an integrated circuit.

In addition, since the current-voltage characteristic of the MIM is slow in the liquid crystal display element using the MIM as an active element, the selection voltage applied between the input terminal of the active element and the counter electrode is low. In order to perform a gradation display in which the change width of the pixel electrode voltage with respect to the change of the pixel is small and the degree of brightness of the pixel is changed, it is necessary to change the voltage value of the selection voltage with an extremely large width. Key display was also difficult.

On the other hand, an active matrix liquid crystal display element using a non-linear resistance element having a semiconductor, for example, a thin film diode as an active element, has a current-
Since the voltage characteristics are steep, it can be driven at a relatively low voltage, and a gradation display is also possible. Conventionally, gradation display of this active matrix liquid crystal display element is performed by a driving method called voltage modulation.

This driving method by voltage modulation is a method of controlling the voltage value of the selection voltage according to the image data. The voltage value according to the image data is applied between the input terminal of the active element and the counter electrode during the selection period. When the selection voltage is applied, electric charge is accumulated between both electrodes of the pixel during the selection period, and the voltage between the electrodes increases to a voltage value corresponding to the image data. A voltage is applied.

[0012]

However, in the above-mentioned conventional driving method, the gradation value is displayed by controlling the voltage value of the selection voltage according to the image data. Therefore, there is a problem that as the number of display gray scales increases, a power supply circuit that outputs voltages of multiple voltage levels is required, and the driving circuit becomes more complicated.

In addition, in the conventional driving method, the voltage stored in the pixel during the selection period fluctuates during the non-selection period due to the influence of image data for driving other pixels in the same column. There is a problem that the light transmittance of the pixel fluctuates.

This is because the active element has a capacitance, and the active element made of a nonlinear resistance element having a semiconductor such as a thin film diode is much smaller than the capacitance of the above-mentioned MIM. It has a certain amount of capacitance between the bodies (between the upper and lower electrodes in a thin film diode).

Therefore, when the active element is in an ON state, the pixel and the active element in the active matrix liquid crystal display element have a capacitance (hereinafter, referred to as a pixel) of a pixel including a pixel electrode, a counter electrode, and liquid crystal therebetween. CLC and an active element are represented by an equivalent circuit in which the active element is connected in series. When the active element is turned off, the pixel capacitance CLC and the capacitance of the active element (hereinafter referred to as element capacitance)
CD is represented by an equivalent circuit connected in series.

Therefore, the inter-electrode voltage VLC of the pixel, during the selection period in which the active element is on, changes the current-voltage characteristic of the active element up to the voltage applied between the input terminal of the active element and the counter electrode. And rises in a rising curve according to the charging characteristic of the pixel capacitance CLC. However, when the selection period elapses and the non-selection period occurs, the applied voltage decreases to the non-selection voltage and the active element is turned off. To act as
The decrease in the voltage between the input terminal of the active element and the counter electrode (the voltage difference between the selection voltage and the non-selection voltage) is added to the pixel capacitance CLC connected in series with the element capacitance CD of the active element. The voltage is divided at a ratio opposite to the capacity ratio.

For this reason, the voltage held in the pixel capacitor CLC during the non-selection period is changed from the voltage charged during the selection period to the voltage between the input terminal of the active element and the counter electrode at the time of the non-selection period. Becomes a value reduced by the partial pressure to the pixel capacitance CLC.

The liquid crystal between the two electrodes of the pixel does not operate due to its responsiveness with the voltage applied during the extremely short selection period, and the voltage between the electrodes of the pixel during the non-selection period (the holding voltage of the pixel capacitance CLC). ), The effective voltage for operating the liquid crystal becomes low if the inter-electrode voltage VLC greatly decreases during the non-selection period.

For this reason, the active matrix liquid crystal display element is provided between the input terminal of the active element and the counter electrode.
The pixel is driven by applying a voltage that allows for a drop in the inter-electrode voltage of the pixel when the non-selection period is reached. If a selection voltage having such a voltage value is applied, the selection period ends and the non-selection is performed. Since the voltage VLC between the electrodes of the pixel at the time of the period becomes a voltage value corresponding to the image data, the transmittance of the pixel can be set to a gradation corresponding to the image data.

However, the active matrix liquid crystal display element is driven in a time-division manner by supplying a scanning signal to one of a signal line for supplying a driving signal to the active element and a counter electrode and supplying a data signal to the other. The image data for driving the other pixels in the same column is applied to the counter electrode of the pixel that has entered the non-selection period or the input terminal of the active element together with the data signal after the selection period has elapsed. The voltage between the input terminal of the active element of the middle pixel and the counter electrode fluctuates.

When the voltage between the input terminal of the active element and the counter electrode fluctuates in this way, the voltage between the electrodes of the pixel, that is, the holding voltage of the pixel capacitance CLC changes. The change in the holding voltage of the pixel capacitor CLC is the same as the voltage change when the selection period is changed from the selection period to the non-selection period. Capacity CD
Of the voltage divided at a ratio opposite to the capacitance ratio of the pixel capacitance C
This is the voltage divided into LC.

The liquid crystal between the two electrodes of the pixel operates according to the voltage between the electrodes of the pixel during the non-selection period (the holding voltage of the pixel capacitor CLC) as described above. If the holding voltage of the pixel capacitor CLC changes due to the influence of image data for driving another pixel, the transmittance of the pixel changes accordingly, and a display of a correct gradation corresponding to the image data cannot be obtained.

The present invention is directed to a method of driving an active matrix liquid crystal display element using an active element comprising a nonlinear resistance element having a semiconductor.
Multi-gradation display can be performed without using driving signals of multi-step voltage levels, and the variation in transmittance due to the influence of image data for driving other pixels can be reduced. An object of the present invention is to provide a driving method capable of obtaining a display of a correct gradation according to image data.

[0024]

According to the driving method of the present invention, a voltage value corresponding to image data and a pulse width or voltage value are provided between a drive signal input terminal of an active element and a counter electrode during a selection period. The data signal having the number of pulses and the scanning signal overlap.
Apply a selection voltage of either one of the positive and negative polarities and drive other pixels during the non-selection period when other pixels are selected.
The data signal and the scanning signal are superimposed on each other, and the potential changes in a cycle shorter than the selection period. wherein the area of the negative side is applied a voltage equal correct waveform.

In this driving method, for example, one of the signal line and the counter electrode is connected to the center of the potential change width during the selection period.
A scanning signal that maintains a potential of one of the positive and negative polarities with respect to the reference potential, and a positive or negative polarity during a non-selection period and a potential that is lower than the potential during the selection period. to have the potential and the pulse width or voltage value and the number of pulses corresponding to the image data, and the potential changes at substantially equal amplitude and positive and negative with respect to the reference potential at a period obtained by dividing the selection period into a plurality The present invention can be implemented by supplying a data signal.

[0026]

According to the driving method of the present invention, a liquid crystal display element using an active element composed of a nonlinear resistance element having a semiconductor is driven by a modulation method in which modulation by voltage and modulation by pulse width or pulse number are combined. It is.

That is, an active element made of a non-linear resistance element having a semiconductor has a rapid current-voltage characteristic and a high responsiveness, so that charges are rapidly accumulated between a pixel electrode and a counter electrode. Therefore, the rising speed of the voltage between the two electrodes with respect to the time during which the voltage is applied between the two electrodes is high. Therefore, the voltage applied between the pixel electrode and the counter electrode changes according to the voltage value of the selection voltage applied between the drive signal input terminal of the active element and the counter electrode and the pulse width or the number of pulses. .

Therefore, if the voltage value and the pulse width or the number of pulses of the selection voltage are controlled in accordance with the image data, the voltage applied between the pixel electrode and the counter electrode is changed to increase the transmittance of the pixel. Can be controlled.

In the present invention, the liquid crystal display device using the semiconductor active device is driven not by the conventional voltage modulation system but by the modulation system in which the modulation by the voltage and the modulation by the pulse width or the number of pulses are combined. Therefore, the voltage applied between the pixel electrode and the counter electrode can be changed in multiple steps by controlling the pulse width or number of pulses for each voltage value, even if the number of steps of the selection voltage is small. Therefore, it is possible to cause the liquid crystal display element to perform a multi-gradation display without using a driving signal of a multi-step voltage level unlike the conventional driving method.

Further, in the present invention, between the drive signal input terminal of the active element and the counter electrode, during the selection period, the voltage value corresponding to the image data and the pulse width or the pulse number of either one of the positive and negative polarities. In a non-selection period in which a selection voltage is applied and another pixel is selected, the potential changes in a cycle shorter than the selection period, and the positive and negative areas around the potential in the non-selection period of the scanning signal are reduced. Since the voltages having substantially the same waveform are applied, the transmittance of the pixel hardly changes during the non-selection period.

That is, the voltage between the electrodes of the pixel during the non-selection period fluctuates every time under the influence of image data for driving other pixels. If the voltage applied between the common electrode and the counter electrode is a voltage having the above-described waveform, the fluctuation of the inter-electrode voltage of the pixel is
Since the fluctuation of the voltage to the positive side and the fluctuation of the voltage to the negative side become substantially equal around the potential of the scanning signal during the non-selection period, the effective value of the inter-electrode voltage of the pixel during the non-selection period (Holding voltage) hardly changes.

Therefore, since the holding voltage of the pixel during the non-selection period does not fluctuate, the transmittance of the pixel becomes the transmittance corresponding to the voltage accumulated between the electrodes of the pixel according to the selection voltage applied during the selection period. Will be kept. Therefore, it is possible to obtain a display of a correct gradation according to the image data.

[0033]

【Example】

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

First, the configuration of an active matrix liquid crystal display element driven by the driving method of this embodiment will be described. FIG. 9 is a plan view of a part of the liquid crystal display element. 1 shows an element using a diode ring made of a thin film diode as an active element made of.

This liquid crystal display element has a plurality of pixel electrodes 1 arranged in a row direction and a column direction on one of a pair of transparent substrates (both not shown) opposed to each other with a liquid crystal layer interposed therebetween. , An active element 2 connected to each of the pixel electrodes, and a signal line 3 for supplying a drive signal to the active element 2.
And a counter electrode 4 facing the pixel electrode 1 is provided on the other substrate.

The active element 2 is a so-called diode ring in which the same number of thin-film diodes 5 and 6 are connected in parallel in opposite directions, and one end is connected to the pixel electrode 1 and the other end is connected to the signal line 3. Have been.

Although FIG. 9 shows one thin film diode 5 and 6 constituting a diode ring, the forward circuit and the reverse circuit of the diode ring generally include a plurality of thin film diodes. It is configured by connecting in series.

The signal lines 3 are provided for each active element group arranged in the row direction (horizontal direction in the figure), and the semiconductor active elements 2 are connected to the signal lines 3 for each row. Further, the counter electrode 4 is provided for each pixel electrode group arranged in the column direction (vertical direction in the drawing), and each counter electrode 4 faces the pixel electrode 1 of each column via a liquid crystal (not shown). . Each pixel of the liquid crystal display element is formed by the pixel electrode 1, the counter electrode 4, and the liquid crystal therebetween.

FIG. 10 is an equivalent circuit diagram of one pixel display element of the above-mentioned liquid crystal display element.
Since the pixel formed by the pixel and the liquid crystal between them is equivalent to a capacitor, the pixel display element composed of the pixel and the active element 2 has a capacitance (hereinafter referred to as a pixel) as shown in FIG. , A pixel capacitance) and an active element 2 formed of a diode ring are connected in series.

The thin film diodes 5 and 6 constituting the diode ring as the active element 2 have a pair of electrodes opposed to each other with a semiconductor layer having a PIN junction structure therebetween. 5 and 6 have a capacitance, and therefore the active element 2 also has the above-mentioned thin-film diode 5,
6 has a capacity equivalent to the sum of the capacities of the six.

Therefore, when the diode ring is off, the equivalent circuit described above includes a series connection of the pixel capacitance CLC and the capacitance of the active element 2 (hereinafter referred to as element capacitance) CD as shown in FIG. It is represented by a connection circuit.

The liquid crystal display element is driven for display by supplying a drive signal to each signal line 3 and each counter electrode 4. In this display drive, for example, a scanning signal is sequentially applied to each signal line 3. Supply, and in synchronization with this, each counter electrode 4
And time-division driving for sequentially selecting each pixel.

This driving method will be described. FIG. 1 is a waveform diagram of the driving signal. FIG. 1A shows the waveform of the scanning signal SS supplied to the signal line 3 in the first row, and FIG. The waveform of the data signal SD supplied to the counter electrode 4 is shown, and (c) shows the position between the drive signal input end (connection end to the signal line 3) of the active element 2 and the counter electrode 4 (point a in FIG. between point c)
5 shows the waveform of the voltage Va-c applied to the. In FIG. 1, TS is a selection period in which one field TF is divided according to the number of rows of pixels (the number of signal lines).

The scanning signal SS has the selection potential VC1 during the selection period TS, and has the non-selection potential VC2 during the non-selection period TO.
The polarity is inverted between the positive side and the negative side around the reference potential VG in a cycle corresponding to one field TF.

The selection potential VC1 is a potential whose potential difference from the reference potential VG is higher than the threshold voltage of the active element (diode ring) 2, and the non-selection potential VC2 is a potential difference between the reference potential VG and the active element. 2 is lower than the threshold voltage.

The data signal SD is a signal having a data pulse having a potential and a pulse width corresponding to image data supplied from outside in synchronization with the selection period TS1, TS2, TS3... Of the pixels in each row. The data signal SD is applied to the selection period TS1 for each selection period TS1, TS2, TS3,.
The potential changes between a positive side and a negative side with respect to the reference potential VG in a cycle obtained by equally dividing the reference potential VG into an even number, for example, in a cycle obtained by dividing the selection period TS into two equal parts.

That is, the data signal SD is a signal having a data pulse having a potential and a pulse width corresponding to the image data in each of 1/2 periods 1 / 2TS of the selection period TS. The first half data pulse and the second half data pulse of the selection period TS have opposite polarities with respect to the reference potential VG. The data pulses in the first half and the second half of one selection period TS are pulses corresponding to the same image data. Therefore, the positive side pulse and the negative side pulse have the same width and the absolute value of the potential. equal.

That is, in the data signal SD, the waveform of each selection period TS has a waveform area on the positive side centered on the reference potential VG (the area of the area shown by oblique lines rising to the right in the figure) A1 and a negative area. This is a signal having a waveform whose area is substantially equal to the area B1 of the waveform on the side (the area of the hatched area in the figure).

In this embodiment, the potentials (absolute values) of the data pulses on the positive and negative sides of the data signal SD are set to a low level potential VS1 and a double high level potential VS2 (VS2).
= 2 · VS1), and one of the two levels of potentials VS1 and VS2 is selected according to image data.

Further, the data signal SD shown in FIG. 1 is such that the pulse width of the selection period TS1 of the pixels in the first row is 1/10 of the selection period.
(The potential is VS1), the pulse width of the selection period TS2 of the pixels in the second row is 4/10 of the selection period (potential is VS2), and the pulse width of the selection period TS3 of the pixels in the third row is 3/10 of the selection period. (The potential is VS1)
Of the data signal SD in each selection period TS.
The pulse width of each of 1, TS2, TS3,... Is 0/10 (no pulse) to 5/10 (no pulse) of the selection period TS according to the image data and the pulse potential VS1 or VS2 selected according to the image data. It is controlled within the range of (選 択 the full width of the selection period TS).

When the scanning signal SS and the data signal SD having such waveforms are supplied to the signal line 3 and the counter electrode 4, the drive signal input terminal (hereinafter simply referred to as input) of the active element 2 connected to the signal line 3. A voltage having a waveform obtained by combining the scanning signal SS and the data signal SD (corresponding to the potential difference between the scanning signal SS and the data signal SD) as shown in FIG. Voltage) Va-c is applied.

During the selection period TS, the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4 has a voltage value corresponding to the image data and one of the positive and negative polarities of the pulse width. In the non-selection period TO in which another pixel in the same column is selected, the potential is changed in a half cycle of the selection period TS.

That is, of the voltages Va-c, the selection voltage applied during the selection period TS is the same as that of the data signal SD.
Is the same as the selection potential VC1 of the scanning signal SS when the potential of the data pulse is the reference potential VG, and when the potential of the data signal SD becomes the potential of the data pulse, the selection potential VC1 of the scanning signal SS becomes the potential VS1,. -VS1 or VS2, -V
Voltage VC1 + VS1, VC1-VS1 or VC1 + on which S2 is superimposed
VS2, VC1-VS2.

Note that the potential of the data signal SD is equal to the reference potential V.
Selection voltage when G (hereinafter referred to as reference selection voltage)
VC1 is a voltage higher than the threshold voltage of each thin film diode 5, 6 of the diode ring as the active element 2. The selection voltages VC1 + VS1, VC1 + VS2 when the potential of the data signal SD becomes the potential VS1, VS2 of the data pulse on the positive side with respect to the reference potential VG are higher than the reference selection voltage VC1, and The potential of SD is the potential −VS 1, − of the data pulse on the negative side with respect to the reference potential VG.
The selection voltages VC1-VS1 and VC1-VS2 at the time of reaching VS2 are higher voltages lower than the reference selection voltage VC1.

The voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period T0 (hereinafter referred to as non-selection voltage) is used to drive another pixel in the same column. A data pulse corresponding to image data is a voltage superimposed on the scanning signal SS. This non-selection voltage is the same as the non-selection potential VC2 of the scanning signal SS when the potential of the data signal SD is the reference potential VG. When the potential of the data signal SD becomes the potential of the data pulse, the non-selection potential V
The data pulse potential VS1, -VS1 or VS2, -V is applied to C2.
The voltage VC2 + VS1, VC2-VS1 or VC2 + on which S2 is superimposed
VS2, VC2-VS2.

The voltages VC2 + VS1, VC2-VS1,
VC2 + VS2, VC2-VS2 are all lower than the reference selection voltage VC1 of the selection voltage applied during the selection period TS, and the positive data pulse potentials VS1, VS2 are superimposed on the non-selection potential VC2 of the scanning signal SS. Voltage VC2 + VS1, VC2
+ VS2 is a voltage VC1−VS1, which is obtained by superimposing a negative data pulse potential −VS1, −VS2 on the selection potential VC1 of the scanning signal SS.
It is a voltage lower than VC1-VS2.

That is, the non-selection voltage is a voltage in which a positive data pulse and a negative data pulse corresponding to image data for driving another pixel in the same column are superimposed. SD indicates that the waveform for each selection period TS is the area A1 of the waveform on the positive side with respect to the reference potential VG.
And the area B1 of the negative side waveform is substantially equal, the non-selection voltage is equal to the area A2 of the positive side waveform around the non-selection potential VC2 of the scanning signal SS and the area of the negative side waveform B2. Are substantially equal to each other.

Then, the input terminal of the active element 2 and the counter electrode 4
When the selection voltage is applied between the pixel electrode 1 and the counter electrode 4, the voltage is applied between the pixel electrode 1 connected to the active element 2 and the counter electrode 4. That is, in FIG. 10, when a selection voltage is applied between a and c, the active element 2 composed of a diode ring
Is higher than the threshold voltage, the active element 2 is turned on, a current flows through the pixel electrode 1, and bc
A voltage is applied between them (between the pixel electrode 1 and the counter electrode 4).

As described above, when a voltage is applied between bc, charging of the pixel capacitor CLC formed by the pixel electrode 1, the counter electrode 4, and the liquid crystal therebetween is started. The charging of the pixel capacitance CLC is continued during the selection period TS.

When the non-selection period T0 elapses after the selection period Ts has elapsed, the charging of the pixel capacitor CLC proceeds, and the charge voltage increases.
Since the voltage applied to the input terminal of the active element 2 from the signal line 3 becomes low, the potential difference between both ends of the active element 2 becomes small, the active element 2 is turned off, and the charging of the pixel capacitance CLC is stopped. .

In this case, when the active element 2 is turned off, the active element 2 acts as a capacitor.
At 0, the voltage corresponding to the decrease of the voltage a-c (the voltage between the input terminal of the active element 2 and the counter electrode 4) Va-c (the difference between the voltage in the selection period TS and the voltage in the non-selection period TO) is The voltage is divided by the pixel capacitance CLC and the element capacitance CD of the active element 2 which are connected in series at a ratio opposite to the capacitance ratio.

Therefore, the voltage held in the pixel capacitor CLC during the non-selection period T0 is changed from the voltage charged during the selection period Ts to the pixel capacitance CLC out of the decrease in the a-c voltage Va-c. The voltage is reduced by the divided voltage value.

The liquid crystal is composed of a pixel electrode 1 and a counter electrode 4.
It operates by the voltage between. Due to its responsiveness, the liquid crystal does not operate in the extremely short selection period TS even when a high electric field is applied, and operates in response to the holding voltage of the pixel capacitor CLC during the non-selection period TO.

The pixel capacitor CLC is in a voltage holding state during the non-selection period To, and the voltage between the pixel electrode 1 and the counter electrode 4 is maintained at the holding voltage of the pixel capacitor CLC. The operation state is maintained during the non-selection period TO.

However, since the counter electrode 4 is supplied with a data signal SD having a waveform as shown in FIG. 1B having image data for driving the pixels in each row, the selection period T
Image data for driving other pixels in the same column is applied to the opposing electrode 4 of the pixel which has been deselected after passing S together with the data signal SD, and the potential of the opposing electrode 4 changes. Therefore, the voltage Va-c between a and c fluctuates, and the voltage between the electrodes of the pixel changes.

The change in the inter-electrode voltage of the pixel due to the change in the a-c voltage Va-c is the same as the voltage change when the selection period TS is changed to the non-selection period To as described above. This is the voltage that is divided by the pixel capacitance CLC out of the voltage obtained by dividing the variation of -c by the inverse of the capacitance ratio between the pixel capacitance CLC and the element capacitance CD.

However, in this driving method, the non-selection period T
The non-selection voltage applied between the input terminal of the active element 2 and the opposing electrode 4 during O is substantially equal to the area A2 of the waveform on the positive side and the area B2 of the waveform on the negative side with respect to the reference potential VG. Since the voltages are equal to each other, the fluctuation of the a-c voltage Va-c due to the influence of the image data for driving the other pixels is caused by the scanning signal S.
The fluctuation toward the positive side and the fluctuation toward the negative side around the non-selection potential VC2 of S are fluctuations substantially equal to each other. Therefore, the effective voltage of the pixel during the non-selection period does not change.

In the next selection period T S, at this time, a selection voltage having a polarity opposite to that of the previous selection period T S is applied as shown in FIG.
Since 0 is applied between a and c, the potential difference between both ends of the active element 2 becomes higher than the threshold voltage, the active element 2 is turned on, and the pixel capacitance CLC is charged to the opposite polarity. The following is the same as the above operation. Next, the gradation display by the above driving method will be described.

FIG. 2 is a waveform diagram of a selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the selection period T S, and (1) to (14) show image data of each gradation. It is a selection voltage according to.

Of the selection voltages (1) to (14), (1) to (14)
As for the selection voltage of (7), the voltage value is equal to the scanning signal S.
The low-level data pulse potential VS1,
−VS1 is the superposed voltage (VC1 + VS1, VC1−VS1), and only the pulse width is different. Each of the selection voltages (8) to (14) has a voltage value (VC1 + VS2, VC1-VS2) obtained by superimposing the high-level data pulse potentials VS2 and -VS2 on the selection potential VC1 of the scanning signal SS. Yes, only the pulse width is different. The pulse widths of the selection voltages of (8) to (14) are the same as the pulse widths of the selection voltages of (1) to (7), respectively, and the pulse widths of the selection voltages of (7) and (14) are The maximum pulse width is the same as 1/2 of the selection period TS.

FIG. 3 shows the input terminal of the active element 2 and the counter electrode 4.
Shows the voltage applied between the pixel electrode 1 and the counter electrode 4 when the above selection voltages (1) to (14) are applied. When the selection voltage is applied,
The voltage applied between the electrodes rises for the time corresponding to the pulse width of the selection voltage in the rise curve (b), and (8) to (14)
When the selection voltage is applied, the applied voltage between the electrodes becomes
In the rising curve (a), the signal rises for a time corresponding to the pulse width of the selection voltage.

In FIG. 3, (1) to (14) correspond to the above (1) to (14).
It shows the rising value of the applied voltage between electrodes when the selection voltage of (14) is applied.The selection voltages of (1) to (7) have the same voltage value, but have different pulse widths.
The rise value of the voltage applied between the electrodes when the selection voltages (1) to (7) are applied differs for each selection voltage. This is (8)
The same applies when the selection voltage of ~ (14) is applied.
The selection voltages (8) to (14) also have the same voltage value,
Since the pulse widths are different, the rising values of the voltage applied between the electrodes when the selection voltages (8) to (14) are applied also differ for each selection voltage.

The pulse widths of the selection voltages (8) to (14) are the same as the pulse widths of the selection voltages (2) to (7), respectively. And the selection voltage of (2) to (7) are different from each other, the rising value of the voltage applied between the electrodes when the selection voltage of (8) to (14) is applied is (2)
It becomes a value different from the rising value of the voltage applied between the electrodes when the selection voltage of (7) is applied. However, the rising value of the voltage applied between the electrodes when the selection voltage of (7) is applied and when the selection voltage of (8) is applied is almost the same.

FIGS. 4 to 8 show waveforms of the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4 and the voltage Vb applied between the pixel electrode 1 and the counter electrode 4. This shows the relationship with -c.

FIG. 4 shows the data pulse width of the data signal SD applied to the active element 2 during the selection period TS.
0/10 (no pulse), in this case, between the input terminal of the active element 2 and the counter electrode 4, (a)
Is applied.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
And the interelectrode voltage Vb-c applied between the counter electrode 4 and
As shown in (b), the voltage rises with a rising curve corresponding to the reference selection voltage VC1 over the entire period of the selection period TS.

Then, when the selection period TS elapses and the non-selection period TO is reached, and the active element 2 is turned off, the pixel capacitance CLC
From the voltage charged during the selection period TS, a-
The voltage V0 decreases by the voltage divided by the pixel capacitance CLC at a rate opposite to the capacitance ratio between the pixel capacitance CLC and the element capacitance CD in the decrease of the voltage Va-c, and this voltage V0 is the pixel electrode. 1 and the holding voltage between the counter electrode 4.

FIG. 5 shows the data pulse width of the data signal SD applied to the active element 2 during the selection period TS.
And the potentials are set to the low-level potentials VS1 and -VS1. In this case, a waveform like (a) between the input terminal of the active element 2 and the counter electrode 4 is formed. A selection voltage is applied. This selection voltage is the voltage (1) shown in FIG.

The waveform of the selection voltage is such that the data signal SD supplied to the common electrode has a data pulse of the potential VS1 having the same polarity as the scanning signal SS at the end of the first half of the selection period TS, and This is a waveform when a data pulse having a potential -VS1 having a polarity opposite to that of the scanning signal SS at the end of the latter half is applied between the input terminal of the active element 2 and the counter electrode 4 in the first half of the selection period TS. The selection voltage is the reference selection voltage VC1 from the beginning to the end of the first half period, and becomes the pulse superimposed voltage VC1−VS1 lower than the reference selection voltage VC1 at the end of the first half period. The selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 in the latter half of the selection period TS is the reference selection voltage VC1 from the beginning to the end of the latter half period, and is the end of the latter half period. , The pulse superimposed voltage VC1 + VS1 higher than the reference selection voltage VC1.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
And the interelectrode voltage Vb-c applied between the counter electrode 4 and
As shown in (b), from the beginning to the end of the first half of the selection period TS, it rises with a rising curve corresponding to the reference selection voltage VC1, and at the end of the first half, the low-voltage pulse superimposed voltage V
It rises with a gentle rising curve according to C1-VS1, and rises again with a rising curve according to the reference selection voltage VC1 from the beginning to the end of the latter half of the selection period TS, and at the end of the latter half, a high voltage pulse superimposed voltage VC1 + V
The voltage rises rapidly by the application of S1, and reaches the voltage value (1) in FIG.

In the non-selection period TO after the lapse of the selection period TS, the voltage of the pixel capacitor CLC becomes a voltage V1 which is reduced at a fixed rate, and this voltage V1 is applied between the pixel electrode 1 and the counter electrode 4. Between the holding voltages.

FIG. 6 shows a state where the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is the same as that of FIG. 5 and the potentials are set to the high level potentials VS2 and -VS2. At this time, a selection voltage having a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. This selection voltage is the voltage of (8) in FIG.

In this case, since the data pulse width of the selection voltage is the same as the data pulse width of the selection voltage in FIG. 5A, the inter-electrode voltage Vb applied between the pixel electrode 1 and the counter electrode 4 is set. As shown in FIG. 5B, -c rapidly rises for the same time at the same time as in FIG. 5B (the end of the latter half of the selection period TS), and the voltage value VC1 + VS2 of the selection voltage at this time is as shown in FIG. Since the selection voltage a) is higher than the voltage value VC1 + VS1, the rise of the inter-electrode voltage Vb-c is more rapid than in FIG. 5B.
It rises to the voltage value (8) in FIG.

In this case as well, when the selection period TS elapses and the non-selection period TO starts, the voltage of the pixel capacitor CLC becomes a voltage V8 which is reduced at a fixed rate, and this voltage V8 is applied to the pixel electrode 1 and the counter electrode. 4 and the holding voltage.

FIG. 7 shows that the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 2.5 / 10 of the selection period TS, and the potential is set to the high level potential VS2, -V.
VS2, in which case a selection voltage having a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. This selection voltage is the voltage (10) shown in FIG.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
And the interelectrode voltage Vb-c applied between the counter electrode 4 and
As shown in (b), in the first half of the selection period TS, a rising curve corresponding to the reference selection voltage VC1 and the reference selection voltage VC1
It rises with a rising curve according to the lower pulse superimposed voltage VC1−VS2, and rises in the latter half of the selection period TS with a rising curve according to the reference selection voltage VC1 and a rising curve according to the high voltage pulse superimposed voltage VC1 + VS2. At this time, since the voltage value of the selection voltage is the same as that of FIG. 6A, the selection voltage is a high voltage pulse superimposed voltage VC1.
The rising curve of the inter-electrode voltage Vb-c at the time of + VS2 is the same as that of FIG. 6B, but the data pulse width of the selection voltage is wider than that of FIG. Because of the length, the interelectrode voltage Vb-c is
Up to the voltage value.

When the non-selection period TO elapses after the selection period TS has elapsed, the voltage of the pixel capacitor CLC becomes a voltage V10 that is reduced at a fixed rate, and this voltage V10 is applied between the pixel electrode 1 and the counter electrode 4. Holding voltage.

FIG. 8 shows that the data pulse width of the data signal SD applied to the active element 2 during the selection period TS is set to 5/10 of the selection period TS (the maximum pulse width equal to 1/2 of the selection period TS). In this state, the potentials are set to the high-level potentials VS2 and -VS2. In this case, a selection voltage having a waveform as shown in (a) is applied between the input terminal of the active element 2 and the counter electrode 4. Is done. This selection voltage is the voltage (14) in FIG.

When a selection voltage having such a waveform is applied between the input terminal of the active element 2 and the counter electrode 4, the pixel electrode 1
And the voltage Vb-c applied between the counter electrode 4 and (b)
As shown in the above, the first half of the selection period TS rises with a rising curve corresponding to the pulse superimposed voltage VC1−VS2 lower than the reference selection voltage VC1, and rises with the rising curve according to the high voltage pulse superimposed voltage VC1 + VS2 in the latter half of the selection period TS. . At this time, since the voltage value of the selection voltage is the same as FIG. 6A and FIG. 7A, the rising curve of the inter-electrode voltage Vb-c when the selection voltage becomes the high voltage pulse superimposed voltage VC1 + VS2. Are the same, but the data pulse width of the selection voltage is wider than that of FIG. 7A, and therefore the application time of the pulse superposition voltage is longer,
The voltage Vb-c between the electrodes rises to the voltage value (14) in FIG.

In the non-selection period TO after the lapse of the selection period TS, the voltage of the pixel capacitor CLC becomes a voltage V14 which is reduced at a fixed rate, and this voltage V14 is applied between the pixel electrode 1 and the counter electrode 4. Holding voltage.

The voltage Vb- applied between the pixel electrode 1 and the counter electrode 4 during the selection period TS in FIGS.
The peak value of c (the voltage value at the end of the selection period TS) is determined by the waveform of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and the current-voltage of the diode ring as the active element 2. The characteristics and the time during which the selection voltage is applied (selection period T
S).

That is, the inter-electrode voltage Vb-c applied between the pixel electrode 1 and the opposing electrode 4 during the selection period TS is the voltage applied between the input terminal of the active element 2 and the opposing electrode 4. In response to the voltage value of Va-c, the voltage rises according to the rising curve determined by the current-voltage characteristic of the active element 2, and when the selection voltage is not applied after the selection period TS has elapsed.
The rising stops.

Therefore, when the selection period TS elapses and the non-selection period TO is reached, the voltage held in the pixel capacitor CCL (from the voltage charged during the selection period TS to the decrease in the voltage a-c). The voltage Vb-c, which is reduced by the divided voltage value to the pixel capacitor CLC, differs depending on the voltage value of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 and the data pulse width.

For example, when the selection voltage is a voltage having a data pulse width of 0 (no pulse), the pixel capacitance C
The voltage Vb-c held in CL becomes the lowest voltage V0 in the voltage control range as shown in FIG. Also, the selection voltage is
The maximum pulse width as shown in (14) of FIG.
When the data pulse of 2) is provided and the pulse voltage is the high voltage VS2, the voltage V held in the pixel capacitance CCL is applied.
bc becomes the highest voltage in the voltage control range as shown in FIG.

Further, even if the selection voltage is a voltage having a data pulse having a maximum pulse width as shown in FIG.
When the pulse voltage is the low voltage VS1, or when the selection voltage is a voltage having a data pulse having a width smaller than the maximum pulse width as shown in (1) to (6) and (8) to (13) in FIG. In some cases, the voltage Vb-c held in the pixel capacitor CCL is a voltage between the minimum value and the maximum value of the voltage control range, and this voltage depends on the data pulse width of the selection voltage and its pulse voltage. Change.

Note that (1)-(6) and (8)-
The selection voltage of (13) is a voltage having a waveform in which a data pulse is superimposed at the end of the first half and the end of the second half of the selection period TS.
This selection voltage may be a voltage having a waveform in which a data pulse is superimposed in the first half or the middle of the first half of the selection period TS, and in the first half or the middle of the second half of the selection period TS. Becomes a value corresponding to the voltage value of the selection voltage and the pulse width.

On the other hand, the rising angle of the liquid crystal depends on the pixel electrode 1.
The light transmittance of the pixel changes according to the rising angle of the liquid crystal, and the light transmittance of the pixel changes according to the value of the voltage (holding voltage of the pixel capacitance CCL) Vb-c applied between the pixel and the counter electrode 4.

Therefore, as described above, the selection period Ts
A selection voltage having a voltage value and a pulse width corresponding to the image data is applied between the input terminal of the active element 2 and the counter electrode 4 so that the pixel electrode 1 and the counter electrode 4 connected to the active element 2 If a voltage having a value according to the voltage value of the selection voltage and the data pulse width is applied in the meantime, the transmittance of the pixel can be controlled to realize a gray scale display.

Next, a description will be given of the number of gradations in the gradation display. The number of gradations is determined by the number of levels at which the value of the voltage Vb-c for charging the pixel capacitor CCL during the limited selection period TS can be selected. Depends on

Then, as described above, the voltage value and pulse width of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 are changed to change the applied voltage between the pixel electrode 1 and the counter electrode 4. In a gray scale display by a modulation method in which voltage modulation and pulse width modulation are combined, a change in the applied voltage between the pixel electrode 1 and the counter electrode 4 corresponding to the voltage value of the selection voltage and the pulse width is controlled. The liquid crystal display element using the active element 2 composed of a diode ring depends on the current-voltage characteristics of the active element. However, since the current-voltage characteristic of the active element 2 is rapid and the response is high, The applied voltage between the electrode 1 and the counter electrode 4 can be greatly changed.

FIG. 11 shows the active element 2 of the liquid crystal display element.
The current-voltage characteristic of the diode ring is compared with the current-voltage characteristic of the MIM using the tunnel effect. As shown in FIG.
Compared to IM, the current-voltage characteristics are sharper and the response is higher.

Therefore, the liquid crystal display element using the diode ring as the active element 2 can perform gradation display by high time division driving without increasing the applied voltage unlike the liquid crystal display element using the MIM as the active element. Is possible.

The current-voltage characteristics of the diode ring can be arbitrarily selected by changing the thickness of the I-type semiconductor layers of the thin film diodes 5 and 6, and the current-voltage characteristics between a and b in FIG. By changing the number of the thin film diodes 5 and 6, the current-voltage characteristics can be arbitrarily selected.

That is, the current-voltage characteristics of the diode ring become steeper as the thickness of the I-type semiconductor layers of the thin film diodes 5 and 6 becomes thinner. The lower the number, the steeper it becomes.

FIG. 12 shows that the diode ring is connected to the active element 2.
Of the liquid crystal display element to be applied to the pixel capacitance CLC with respect to the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4.
FIG. 7A is a graph showing a charging characteristic of a liquid crystal display element using a diode ring having a general current-voltage characteristic, and FIG. 7B is a graph showing a diode ring having a more rapid current-voltage characteristic. 2 shows the pixel capacitance charging characteristics of a liquid crystal display element using the method shown in FIG.

The pixel capacitance charging characteristic shown in FIG. 12A is a characteristic in which the charging voltage of the pixel capacitance CLC reaches a peak in a charging time of about 40 μsec. Approximately 40 times when the selection period TS is divided into two equal parts
.mu.sec (selection period TS is suitable for high time-division driving with a time-division number of about 80 .mu.sec.

Therefore, the gradation display of the liquid crystal display element may be performed by controlling the pulse width of the selection voltage within the range of 0 to about 40 μsec. In the case of a negative display type liquid crystal display element in which a pixel transmits light when a voltage is applied, the gradation of a display pixel is darkest when a selection voltage having a pulse width of 0 (no pulse) is applied. When a selection voltage having a pulse width of about 40 μsec is applied, the brightness becomes maximum, and when a selection voltage having a pulse width in a range of 0 to about 40 μs is applied, the brightness becomes in accordance with the pulse width.

As described above, the number of display gradations is determined by the number of levels of the voltage Vb-c for charging the pixel capacitance CCL during the selection period TS. To obtain a tone display, it is necessary to increase the difference between the charged voltages Vb-c of the pixel capacitors CCL, that is, the difference between the voltages applied between the pixel electrode 1 and the counter electrode 4 to some extent.

For this reason, the pulse width of the selection voltage is set to the voltage V of the voltage difference at which a clear gradation difference is obtained in the pixel capacitance CLC.
It is necessary to control the width Vc so that bc can be charged. However, the rising curve of the voltage Vb-c charged in the pixel capacitor CLC is given assuming that the current-voltage characteristic of the active element 2 is constant. Since the voltage Va-c applied between the input terminal of the active element 2 and the counter electrode 4 is determined, the applied voltage Va-c is increased to some extent so that the rising curve of the charging voltage Vb-c can be sharpened. For example, even if the difference between the pulse widths of the selection voltages is relatively small, the pixel capacitor CLC can be charged with the voltage Vb-c having a sufficient voltage difference.

When the applied voltage Va-c is increased,
During the selection period TS, the range of the voltage Vb-c charged to the pixel capacitor CCL increases according to the pulse width of the selection voltage. If the range of the charged voltage Vb-c is large, the pixel electrode 1
The number of steps of the voltage applied between the electrode and the counter electrode 4 can be increased.

Therefore, if the value of the reference selection voltage VC1 of the selection voltage is set to a somewhat high value, it is possible to increase the number of pulse widths of the selection voltage and to perform multi-stage gradation display. Note that the reference selection voltage VC1 of the selection voltage is
The voltage may be much lower than the voltage required to cause the liquid crystal display element using the MIM as an active element to perform gradation display.
This is the same in the liquid crystal display element having the pixel capacitance charging characteristics shown in FIG.

The pixel capacitance charging characteristic shown in FIG. 12B is a characteristic in which the charging voltage of the pixel capacitance CLC reaches a peak in a charging time of 10 to 15 μsec. Since the element can make the time obtained by dividing the selection period TS into two equal parts as very short as 10 to 15 microseconds (the selection period TS is 20 to 30 microseconds), the number of display gradations is as shown in FIG. Even if the liquid crystal display element has the same characteristics, time-division driving can be performed with a much larger number of time divisions.

In the above driving method, the liquid crystal display device using the active element 2 composed of a diode ring is driven by a modulation method in which the voltage value of the selection voltage and the data pulse width are changed according to image data. Therefore, even if the number of steps of the voltage value of the selection voltage is small, the voltage applied between the pixel electrode 1 and the counter electrode 4 can be changed in multiple steps by controlling the pulse width for each voltage value. Therefore, it is not necessary to use a drive signal of a multi-stage voltage level as in the voltage modulation method conventionally used as a method of driving the liquid crystal display element. The element can perform multi-gradation display.

On the other hand, during the non-selection period TO, the scanning signal SS supplied to the signal line 3 becomes the non-selection potential VC2. Since the data signal SD whose pulse width changes is supplied, the voltage Va− between the input terminal of the active element 2 and the counter electrode 4 is reduced.
c also varies in the non-selection period TO according to image data for driving other pixels in the same column.

For this reason, the inter-electrode voltage of the pixel during the non-selection period To is the same as the voltage fluctuation when the non-selection period To is changed from the above-described selection period TS to the change in the voltage Va between a and c. Of these, the voltage divided by the pixel capacitance CLC (the voltage divided by the pixel capacitance CLC of the voltage divided by the pixel capacitance CLC and the element capacitance CD at a ratio opposite to the capacitance ratio) fluctuates.

That is, the pixels during the non-selection period TO are:
The voltage value of the inter-electrode voltage VLC at the end of the selection period TS, such as the waveform of the non-selection period TO in FIGS. 2 to 8B (from the voltage applied during the selection period TS to the non-selection period TO). The voltage value which is reduced by the divided voltage value to the pixel capacitor CLC out of the reduced amount of the voltage Va between a and c at the time of To) V0-
A non-selection voltage is applied to V14 on which a variation due to the influence of image data for driving another pixel (a variation that is divided by the pixel capacitance CLC) is superimposed.

However, in the driving method described above, as shown in FIG. 1, the scanning signal SS supplied to the signal line 3 is kept at the selection potential VC1 of one of the positive and negative polarities during the selection period TS, and During TO, it is a signal of either one of positive and negative polarities and a non-selection potential VC2 lower than the selection potential VC1 during the selection period TS. The data signal SD supplied to the counter electrode 4 is a pulse having a width corresponding to image data. And a signal whose potential changes with substantially the same amplitude on the positive side and the negative side with respect to the reference potential VG in a cycle obtained by dividing the selection period TS into two equal parts, that is, the area of the waveform on the positive side with respect to the reference potential VG Since A1 is a signal having a waveform substantially equal to the area B1 of the negative waveform, the voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period To is, as described above, Non-selection potential VC2 of scanning signal SS is medium As a center, the voltage has a waveform in which the area A2 of the positive waveform and the area B2 of the negative waveform are substantially equal.

Therefore, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is, as shown in FIG. 4B to FIG. 8B, half the period of the selection period TS. At the end of the selection period TS, the voltage of the inter-electrode voltage VLC (hereinafter referred to as reference holding voltage) V0 to V14 has substantially the same amplitude on the positive side and the negative side (images for driving other pixels). This is a voltage at which the voltage value changes with the amplitude of the variation due to the influence of the data. That is, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is equal to the reference holding voltage V0 to
The waveform is such that the area A3 of the waveform on the positive side and the area B3 of the waveform on the negative side are substantially equal to each other with respect to V14.

Therefore, the non-selection voltage applied between the electrodes of the pixels during the non-selection period TO is substantially equal to the positive-side fluctuation and the negative-side fluctuation, and therefore the voltage fluctuation to the positive side is substantially equal. Minute and the voltage fluctuation to the negative side cancel each other,
The effective value of the inter-electrode voltage of the pixel during the non-selection period To, that is, the holding voltage, is kept at the above-mentioned reference holding voltages V1 to V14 and hardly fluctuates.

If the effective value of the inter-electrode voltage during the non-selection period TO hardly changes, the voltage-transmittance characteristic of the pixel during the non-selection period TO hardly changes. The voltage values V0 to V stored in the pixel capacitor CLC according to the pulse width of the selection voltage applied during the period TS.
Since the transmittance corresponding to 14 is maintained, the transmittance of the pixel hardly fluctuates during the non-selection period TO, and therefore, a display of a correct gradation according to the image data can be obtained.

That is, FIG. 13 shows the pulse width-transmittance characteristics of one pixel when the active matrix liquid crystal display device having the above-described configuration is time-divisionally driven by the driving method of the above embodiment. All of the pixels in one column corresponding to one counter electrode 4 except one measurement pixel are in a transmission state (a state in which a selection voltage is not applied).
The broken line indicates that all the pixels in the one row except for one measurement pixel are in the non-transmissive state (the voltage is high and the full width of 1/2 of the selection period TS is selected). (A state in which a selection voltage having a maximum pulse width corresponding to... Is applied).

In FIG. 13, the lower curve shows the characteristics when a low-voltage selection voltage (voltages of waveforms (1) to (7) in FIG. 2) is applied to the measurement pixel, and the upper curve shows the lower curve. Is a characteristic when a high selection voltage (voltages of waveforms (8) to (14) in FIG. 2) is applied to the measurement pixel.

As is clear from FIG. 13, the pulse width-transmittance characteristic (characteristic of the solid line) when all the other pixels are controlled to the transmission state, and all the other pixels are controlled to the non-transmission state. The pulse width-transmittance characteristics (characteristics indicated by a broken line) at the time are very close to each other, even when a low voltage selection voltage is applied to the measurement pixel and when a high voltage selection voltage is applied to the measurement pixel. Also, the variation width of the transmittance of the measurement pixel, which varies depending on the driving state of the other pixels in the same column, is within about 5%.

Therefore, the pulse width-transmittance characteristic is hardly affected by the driving state of the other pixels. Therefore, the transmittance of the pixel is correctly determined according to the pulse width of the selection voltage applied during the selection period TS. Can be controlled.

Further, in the driving method of the above embodiment, the data signal SD is a signal whose waveform in each selection period has positive and negative data pulses with respect to the reference potential VG, but is active during the selection period TS. The selection voltage applied between the input terminal of the element 2 and the counter electrode 4 is either positive or negative with respect to the non-selection potential VC2 of the scanning signal SS, regardless of whether the voltage on which the positive or negative data pulse is superimposed is applied. Therefore, during the selection period TS, the charge of the one polarity is accumulated between the pixel electrode 1 and the counter electrode 4.

That is, the charging between the electrodes of the pixel is performed by making full use of the selection period, and therefore, the charging time between the electrodes of the pixel can be sufficiently taken.
The voltage applied between the electrodes of the pixel can be made sufficiently high without being affected by the capability of the active element (the capability to allow a current to flow).

Further, in the conventional driving method, the voltage of the pixel
Since the driving state of other pixels greatly affects the transmittance characteristics, in order to reduce the fluctuation of the voltage-transmittance characteristics, the element capacitance of the active element with respect to the pixel capacitance is considerably reduced to drive the other pixels. Of the applied voltage between the input terminal of the active element and the opposing electrode due to the image data used in the operation, it is necessary to extremely reduce the voltage divided into the pixel capacitance.

For this reason, in a conventional liquid crystal display device using a diode ring as an active element, the diode constituting the diode ring is formed in an element area as small as possible to reduce the capacitance, or the diode ring is formed in a forward direction. The circuit and the reverse circuit are each configured by connecting a plurality of diodes in series to reduce the capacity of the diode ring.

However, in order to reduce the element area of the diode as described above, high-precision patterning is required in the manufacture thereof, and the number of diodes constituting the forward and reverse circuits of the diode ring is increased. In this case, the area occupied by the diode ring becomes large, and the area of the pixel electrode is limited accordingly.

On the other hand, in the driving method of the above embodiment, as described above, the fluctuation of the non-selection voltage to the positive side and the fluctuation to the negative side cancel each other out. Voltage fluctuations can be large to some extent, so
It is not necessary to extremely reduce the voltage divided by the pixel capacitance CLC among the fluctuations in the applied voltage between the input terminal of the active element 2 and the counter electrode 4.

Therefore, the ratio of the element capacitance CD to the pixel capacitance CLC is such that the voltage drop due to the capacitance ratio voltage division from the selection period TS to the non-selection period TO can be suppressed within a certain range (for example, 1/10). Degree).

Therefore, according to the driving method of the above embodiment, since the diodes constituting the diode ring can be formed with a relatively large element area, the diode ring can be easily manufactured without requiring high-precision patterning. In addition, the number of diodes constituting the forward and reverse circuits of the diode ring is reduced, the area occupied by the diode ring is reduced, and the area of the pixel electrode is increased accordingly, thereby increasing the aperture ratio of the liquid crystal display element. Can be higher.

In the above embodiment, the data signal is a signal whose potential changes to the positive side and the negative side with respect to the reference potential VG in a cycle obtained by dividing the selection period TS into two equal parts. If the signal is such that the potential changes to the positive side and the negative side with respect to the reference potential VG in a cycle obtained by dividing the period TS into a plurality,
A signal of any waveform may be used. In short, during the selection period TS, a voltage value according to the image data and one of the positive and negative polarities of the pulse width is provided between the input terminal of the active element 2 and the counter electrode 4. In the non-selection period To, the potential changes in a cycle shorter than the selection period TS, and the voltage of the waveform is substantially equal to the positive and negative areas around the non-selection potential VC2 of the scanning signal SS. Should be applied.

In the above-described embodiment, the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the selection period TS is the same as that of the waveforms (1) to (14) shown in FIG. The selection voltage is, for example, (1) to (1) shown in FIG.
The voltage of the waveform of 1) may be used. In this case, the voltage of 11 stages of (1) to (11) shown in FIG. It is possible to perform gradation display of the number of gradations (12 steps when the gradation when a pulse-free selection voltage is applied is added).

The reference selection voltage VC1 of the selection voltages shown in FIG. 15 and the data pulse superimposed voltages VC1 + VS1, VC1-VS.
1, VC1 + VS2, VC1-VS2, high-level potential VS
2, VC1 + VS with data pulse of -VS2 superimposed
2, VC1-VS2 are the same as the voltages VC1 + VS2, VC1-VS2 in FIG. Also, the potential VS of the low-level data pulse
1 and -VS1 are almost two thirds of the high-level potentials VS2 and -VS2. Therefore, the voltages VC1 + VS1 and VC1-VS1 on which the data pulses of the low-level potentials VS1 and -VS1 are superimposed are the voltages VC1 + VS1 of FIG. , VC1-VS1 are slightly higher in absolute value.

Even when the voltages having the waveforms (1) to (11) in FIG. 15 are used as the selection voltage, the voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period To is In the half cycle of the selection period TS, the same amplitude (other pixels) on the positive side and the negative side is centered on the voltage value (reference holding voltage) of the inter-electrode voltage VLC at the end of the selection period TS. Of the pixel during the non-selection period TO, that is, the holding voltage is held at the reference holding voltage. Since there is almost no fluctuation, it is possible to obtain a display of a correct gradation according to the image data. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. The description of the same items as in the first embodiment will be omitted.

The driving method of this embodiment will be described.
6 is a waveform diagram of a drive signal, and FIG. 6A shows a scanning signal S supplied to the signal line 3 of the first row of the liquid crystal display element shown in FIG.
The waveform of S, (b) is the waveform of the data signal SD supplied to one common electrode 4, and (c) is the drive signal input end of the active element 2 (connection end to the signal line 3) and the common electrode 4. 11 shows a waveform of a voltage Va-c applied between the points (between points a and c in FIG. 10).

The scanning signal SS is the same signal as in the first embodiment. The scanning signal SS has the selection potential VC1 during the selection period TS and the non-selection potential VC2 during the non-selection period TO, and its polarity is inverted every field TF. I do.

On the other hand, the data signal SD is a signal of a voltage value and a pulse number corresponding to image data supplied from the outside in synchronization with the selection period of the pixels of each row. Is a signal in which the potential changes with substantially the same amplitude on the positive side and the negative side with respect to the reference potential VG in a period obtained by equally dividing the selection period TS in each of the selection periods TS1, TS2, TS3.

In the figure, the number of divisions of the selection period TS is divided into ten equal parts in order to make the waveform easier to see. However, the number of divisions of the selection period T S is, for example, several tens, and the width of the data pulse is Is the same as the width of one divided period of the selection period TS.

The number of data pulses at the positive potential VS and the number of data pulses at the negative potential −VS in each selection period of the data signal SD are numbers corresponding to the same image data. The number of data pulses on the positive side and the number of data pulses on the negative side in each of the selection periods TS1, TS2, TS3... Are the same, and the absolute values of the potentials are also equal.

That is, the data signal SD is a signal whose waveform in each selection period TS has a waveform in which the area of the positive side waveform is substantially equal to the area of the negative side waveform centering on the reference potential VG.

In this embodiment, the potentials (absolute values) of the data pulses on the positive side and the negative side of the data signal SD are set to a low level potential VS1 and a double high level potential VS2 (VS2).
= 2 · VS1), and one of the two levels of potentials VS1 and VS2 is selected according to image data.

The data signal SD shown in FIG.
The number of pulses on the positive side and the negative side in the selection period TS1 of the pixels in the first row is 1, respectively. The number of pulses on the positive side and the negative side in the selection period TS2 of the pixels in the second row are 4, respectively. Although the number of pulses on the positive side and the number of negative sides in the selection period TS3 are 2 signals, each selection period T
The number of positive and negative data pulses for each of S1, TS2, TS3,.
In accordance with the image data, it changes in the range of 0 (no pulse) to n (the maximum allowable number of pulses that can be applied during the selection period TS determined by the pulse width).

When the scanning signal SS and the data signal SD having such waveforms are supplied to the signal line 3 and the counter electrode 4, the input terminal of the active element 2 connected to the signal line 3 and the counter electrode 4
Between them, a voltage Va-c having a waveform obtained by combining the scanning signal SS and the data signal SD as shown in FIG. 16C is applied.

Of the voltages Va-c applied between the input terminal of the active element 2 and the counter electrode 4, the selection voltage applied during the selection period TS is such that the potential of the data signal SD is equal to the reference potential VG. Is equal to the selection potential VC1 of the scanning signal SS, and when the potential of the data signal SD becomes the potential of the data pulse, the potential VS1, -VS1 or VS2, -VS1 of the data pulse is added to the selection potential VC1 of the scanning signal SS. Voltages VC1 + VS1, VC1-VS1 or VC1 + VS2, VC1-
VS2. Note that these voltages VC1 + VS1, VC1-VS
The values of 1, VC1 + VS2, VC1-VS2 are the same as in the first embodiment.

The non-selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period T0 is a data corresponding to image data for driving other pixels in the same column. The pulse is a voltage superimposed on the scanning signal SS. This non-selection voltage is the same as the non-selection potential VC2 of the scanning signal SS when the potential of the data signal SD is the reference potential VG, but the potential of the data signal SD Becomes the potential of the data pulse, the voltage VC2 obtained by superimposing the potential VS1, -VS1 or VS2, -VS2 of the data pulse on the non-select potential VC2 of the scanning signal SS.
+ VS1, VC2-VS1 or VC2 + VS2, VC2-VS2. These voltages VC2 + VS1, VC2-VS1, VC2 + VS2,
The value of VC2-VS2 is the same as in the first embodiment.

That is, the non-selection voltage is a voltage in which a positive data pulse and a negative data pulse corresponding to image data for driving other pixels in the same column are superimposed. The voltage is the non-selection potential VC2 of the scanning signal SS.
And the area of the waveform on the positive side is substantially equal to the area of the waveform on the negative side.

The input terminal of the active element 2 and the counter electrode 4
Is applied between the pixel electrode 1 connected to the active element 2 and the counter electrode 4,
Charging of the pixel capacitance CLC formed by the pixel electrode 1, the counter electrode 4, and the liquid crystal therebetween is started.

Further, the selection period TS elapses and the non-selection period T0 starts, and the voltage between the input terminal of the active element 2 and the counter electrode 4, that is, the voltage Va-c between ac in FIG. Then, the active element 2 is turned off and charging of the pixel capacitance CLC is stopped, and the voltage of the pixel capacitance CLC is changed from the voltage during the selection period TS to the pixel capacitance CLC of the decrease in the voltage a-c Va-c.
Divided voltage value to LC (pixel capacitance CLC and element capacitance C of active element 2)
D and the voltage divided by the pixel capacitance CLC of the voltage divided at a ratio opposite to the capacitance ratio). The gradation display by the driving method of this embodiment is also basically performed in the same manner as in the first embodiment.

That is, FIG. 17 to FIG.
2 shows the relationship between the waveform of the voltage Va-c applied between the input terminal and the counter electrode 4 and the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4.

FIG. 17 shows that the number of data pulses on the positive and negative sides of the data signal SD applied during the selection period TS is 0, respectively.
(No pulse), (a) shows a waveform of a selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) shows a state of the pixel electrode 1 and the counter electrode 4. Is a waveform of the voltage Vb-c applied during the period.

FIG. 18 shows that the number of data pulses on the positive and negative sides of the data signal SD applied during the selection period TS is 1 respectively.
(A) is a waveform of a selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is a state in which the potentials are set to the low level potentials VS1 and -VS1. 5 is a waveform of a voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4.

FIG. 19 shows a state in which the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is the same as in FIG. 18, and the potentials are set to the high level potentials VS2 and -VS2. (A) is a waveform of a selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is a voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4. It is a waveform of.

FIG. 20 shows that the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period Ts is the maximum allowable pulse number n, and the potential is the low level potential VS1,
(A) is a waveform of a selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is a state between the pixel electrode 1 and the counter electrode 4. 5 is a waveform of the voltage Vb-c applied to the power supply.

FIG. 21 shows that the number of data pulses on the positive side and the negative side of the data signal SD applied during the selection period TS is set to the maximum allowable pulse number n as in FIG.
(A) is a waveform of a selection voltage applied between the input terminal of the active element 2 and the counter electrode 4, and (b) is a state when the pixel electrode 1 and the counter electrode 4 are connected to each other. Is a waveform of the voltage Vb-c applied during the period.

Also in the driving method of this embodiment, the voltage Vb-c applied between the pixel electrode 1 and the counter electrode 4 is selected between the input terminal of the active element 2 and the counter electrode 4. When the voltage is the reference selection voltage VC1, the voltage rises according to a rising curve corresponding to the voltage VC1, and when the selection voltage becomes a pulse superimposed voltage VC1-VS1 or VC1-VS2 lower than the reference selection voltage VC1, the reference selection voltage. The pulse rises with a gentler rising curve than when VC1 is applied, and the selection voltage is higher than the reference selection voltage VC1.
When it becomes S1 or VC1 + VS2, it rises with a steep rising curve. The selection voltage is a voltage having a voltage value different from the number of data pulses according to image data, and therefore, the voltage V applied between the pixel electrode 1 and the counter electrode 4 is different.
bc is determined according to the number of data pulses of the selection voltage as shown in FIGS.
It rises stepwise as shown in FIG.

Therefore, when the selection period TS elapses and the non-selection period TO is reached, the voltage held in the pixel capacitor CCL (the voltage charged during the selection period TS by the decrease in the voltage a-c). The voltage Vb-c, which is reduced by the divided voltage value to the pixel capacitor CCL, differs depending on the voltage value of the selection voltage applied between the input terminal of the active element 2 and the counter electrode 4 and the number of data pulses.

For example, when the selection voltage is a voltage having a data pulse number of 0 (no pulse) as shown in FIG.
The voltage Vb-c held in the pixel capacitance CCL is the lowest voltage V0 in the control range, and the selection voltage is as shown in FIG.
In the case of a high-level voltage VC1 + VS2 such as 1 and a voltage having a data pulse of the maximum allowable pulse number n, the voltage Vb-c held in the pixel capacitor CCL is the highest voltage VnH in the control range. become.

Even if the selection voltage is a voltage having a data pulse of the maximum allowable pulse number n, the voltage value is not changed as shown in FIG.
In this case, the voltage Vb-c held in the pixel capacitor CCL is a voltage VnL between the minimum value and the maximum value of the control range.

Also, when the selection voltage is a voltage having a data pulse in a part of the selection period TS, the voltage Vb-c held in the pixel capacitor CCL is between the minimum value and the maximum value of the control range. The voltage changes according to the voltage value of the selection voltage and the number of data pulses. That is, for example, FIG.
When the number of data pulses is one as shown in FIG. 19 and the voltage is one, the voltage Vb-c held in the pixel capacitor CCL is V1L, V1H between the minimum value and the maximum value of the control range. . Since the voltage value VC1 + VS2 of the selection voltage in FIG. 19 is higher than the voltage value VC1 + VS1 of the selection voltage in FIG.
When the selection voltage shown in FIG.
The voltage held at CL is higher than the holding voltage V1L of FIG.
9, the holding voltage V1H is higher.

The selection voltage (voltage during the selection period TS of Va-c) shown in FIGS. 18 and 19A is a waveform in which a data pulse is superimposed at the end of the selection period TS. The data pulse of the selection voltage may be superimposed at the beginning or middle of the selection period TS.

The rising angle of the liquid crystal is determined by the voltage (pixel capacitance CLC) applied between the pixel electrode 1 and the counter electrode 4.
And the transmittance of the pixel changes according to the rising angle of the liquid crystal.

Therefore, as described above, the selection period Ts
A selection voltage of a voltage value and the number of pulses according to image data is applied between the input terminal of the active element 2 and the counter electrode 4, and the pixel electrode 1 connected to the active element 2 and the counter electrode 4 are connected to each other. If a voltage having a value corresponding to the voltage value of the selection voltage and the number of data pulses is applied in the meantime, the transmittance of the pixel can be controlled to realize a gray scale display.

The number of gradations in this gradation display is determined by the number of levels of the voltage Vb-c for charging the pixel capacitance CCL during the limited selection period TS. As described in the first embodiment, the liquid crystal display element using the active element 2 has an abrupt current-voltage characteristic and high responsiveness. By controlling the number of pulses of the selection voltage applied between the pixel electrode 1 and the counter electrode 4, the voltage applied between the pixel electrode 1 and the counter electrode 4 can be greatly changed.

In the above driving method, the liquid crystal display element using the active element 2 formed of a diode ring is driven by a modulation method in which the voltage value of the selection voltage and the number of data pulses are changed according to image data. Therefore, even if the number of steps of the voltage value of the selection voltage is small, the voltage applied between the pixel electrode 1 and the counter electrode 4 can be changed in multiple steps by controlling the number of pulses for each voltage value. Therefore, it is not necessary to use a drive signal of a multi-stage voltage level as in the voltage modulation method conventionally used as a method of driving the liquid crystal display element. The element can perform multi-gradation display.

In this embodiment, the current of the diode ring as the active element 2 is also used as the liquid crystal display element.
If a device having a sharp voltage characteristic (thin film thickness of the I-type semiconductor layers of the thin film diodes 5 and 6 or reduction of the number of the thin film diodes 5 and 6) is used, the selection period T
By shortening S, time division driving can be performed with a larger number of time divisions.

In the driving method of this embodiment, FIG.
As shown in the above, the scanning signal SS supplied to the signal line 3 is
During the selection period TS, the selection potential V of one of the positive and negative polarities
The data signal SD supplied to the counter electrode 4 is a signal that maintains C1 and maintains either the positive or negative polarity during the non-selection period To and the non-selection potential VC2 lower than the selection potential VC1 during the selection period TS. It has the number of pulses according to the data,
In addition, a signal whose potential changes with an amplitude substantially equal to the positive and negative sides with respect to the reference potential VG in a cycle obtained by dividing the selection period TS into two equal parts, that is, the area of the waveform on the positive side with respect to the reference potential VG and the negative side As described above, the voltage applied between the input terminal of the active element 2 and the counter electrode 4 during the non-selection period To is the same as that of the scanning signal SS. This is a voltage having a waveform in which the area of the waveform on the positive side and the area of the waveform on the negative side are substantially equal with respect to the selection potential VC2.

Accordingly, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is, as shown in FIGS. 17 to 21 (b), at a period obtained by equally dividing the selection period TS into even numbers. The voltage value of the inter-electrode voltage VLC at the end of the selection period TS (hereinafter referred to as the reference holding voltage) V0,
V1L, V1H... Are voltages whose voltage values change with substantially the same amplitude (amplitude due to the influence of image data applied to other pixels) on the positive side and the negative side centering on VnH. That is, the non-selection voltages applied between the electrodes of the pixels during the non-selection period TO are the reference holding voltages V0, V1L, V1H.
, The area of the positive side waveform and the area of the negative side waveform are substantially equal.

For this reason, the non-selection voltage applied between the electrodes of the pixel during the non-selection period TO is substantially equal to the positive-side fluctuation and the negative-side fluctuation. Since the fluctuations in the voltages cancel each other, the effective value of the inter-electrode voltage of the pixel during the non-selection period To is equal to the reference holding voltages V0 and V0.
1L, V1H: Maintained at VnH and hardly fluctuates.

Therefore, also in the driving method of this embodiment, the transmittance of the pixel is determined by the voltage value V0 stored in the pixel capacitor CLC according to the number of pulses of the selection voltage applied during the selection period TS.
, V1L, V1H... VnH, the transmittance of the pixels hardly fluctuates during the non-selection period TO, and a display of a correct gradation according to the image data can be obtained. . (Other application examples of the present invention)

In the first and second embodiments, the voltage value of the selection voltage is two-stage voltage. However, the voltage value of the selection voltage may be selected in three or more stages. By increasing the number of steps of the voltage value and controlling the pulse width or the number of pulses for each voltage value, it is possible to perform gray scale display with more gray scales. However, even in this case, the number of steps of the voltage value of the selection voltage may be much smaller than that in the case where multi-gradation display is performed only by voltage modulation.

Although each of the above embodiments is directed to a liquid crystal display element using a diode ring as the active element 2, the driving method of the present invention is applied to a liquid crystal display element using a diode ring as an active element. The present invention is not limited to this, and can be widely applied to active matrix liquid crystal display elements using active elements formed of non-linear resistance elements having a semiconductor, such as active elements having a back-to-back structure formed of thin film diodes.

[0174]

According to the present invention, a liquid crystal display element using an active element comprising a nonlinear resistance element having a semiconductor is driven by a modulation method in which modulation by voltage and modulation by pulse width or pulse number are combined. Therefore, the liquid crystal display element can perform a multi-gradation display without using a driving signal of a multi-step voltage level as in the conventional driving method.

Further, in the present invention, during the selection period, a selection voltage having either a positive or negative polarity of a pulse width or the number of pulses according to image data is applied between the drive signal input terminal of the active element and the counter electrode. In a non-selection period in which another pixel is selected, the potential changes in a cycle shorter than the selection period, and the area of the positive side and the negative side is substantially equal to the potential of the scanning signal in the non-selection period. Therefore, the fluctuation of the inter-electrode voltage of the pixel due to the influence of the image data for driving the other pixels during the non-selection period is shifted toward the positive side around the potential of the scan signal during the non-selection period. Since the fluctuation of the voltage of the pixel and the fluctuation of the voltage on the negative side are almost equal, and therefore the effective value of the voltage between the electrodes of the pixel during the non-selection period, that is, the holding voltage of the pixel hardly fluctuates, For driving With less variation in transmittance due to the influence of the image data, it is possible to obtain a display of the correct gradation corresponding to the image data.

[Brief description of the drawings]

FIG. 1 is a waveform diagram of a scanning signal, a data signal, and a voltage applied between a signal input terminal of an active element and a counter electrode according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of various selection voltages applied between an input terminal of an active element and a counter electrode.

FIG. 3 is a diagram showing an inter-electrode voltage applied between a pixel electrode and a counter electrode when the selection voltage of FIG. 2 is applied.

FIG. 4 shows a voltage applied between the input terminal of the active element and the counter electrode and a voltage applied between the pixel electrode and the counter electrode when the data signal applied during the selection period is a non-pulse signal. FIG.

FIG. 5 is a diagram showing a voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied in the selection period is 1/10 of the selection period and its potential is at a low level; FIG. 4 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 6 shows a voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied in the selection period is 1/10 of the selection period and its potential is at a high level; FIG. 4 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 7 shows a voltage applied between the input terminal of the active element and the counter electrode when the pulse width of the data signal applied in the selection period is 2.5 / 10 of the selection period and the potential is at a high level;
FIG. 4 is a waveform diagram of a voltage applied between a pixel electrode and a counter electrode.

FIG. 8 is a diagram showing a voltage applied between an input terminal of an active element and a counter electrode when a pulse width of a data signal applied in a selection period is a maximum width and a potential thereof is at a high level; FIG. 5 is a waveform diagram of a voltage applied between the counter electrode and the counter electrode.

FIG. 9 is a plan view of a part of a liquid crystal display element.

FIG. 10 is an equivalent circuit diagram of one pixel display element of a liquid crystal display element.

FIG. 11 is a current-voltage characteristic diagram of a diode ring and an MIM as active elements.

FIG. 12 is a graph showing a charging characteristic of a pixel capacitance with respect to an applied voltage of a liquid crystal display element having a diode ring as an active element.

FIG. 13 is a pulse width-transmittance characteristic diagram of one pixel of the liquid crystal display element when driven by the driving method according to the first embodiment of the present invention.

FIG. 14 is a waveform chart showing another example of various selection voltages applied between the input terminal of the active element and the counter electrode.

FIG. 15 is a view showing an inter-electrode voltage applied between a pixel electrode and a counter electrode when the selection voltage of FIG. 14 is applied.

FIG. 16 is a waveform diagram of a scanning signal, a data signal, and a voltage applied between a signal input terminal of an active element and a counter electrode according to a second embodiment of the present invention.

FIG. 17 illustrates a voltage applied between the input terminal of the active element and the counter electrode and a voltage applied between the pixel electrode and the counter electrode when the data signal applied during the selection period is a non-pulse signal. FIG.

FIG. 18 shows the voltage applied between the input terminal of the active element and the counter electrode when the number of pulses of the data signal applied during the selection period is 1 and the potential is low, and the pixel electrode and the counter electrode. FIG. 4 is a waveform diagram of a voltage applied between the circuit and FIG.

FIG. 19 shows the voltage applied between the input terminal of the active element and the counter electrode when the number of pulses of the data signal applied during the selection period is 1 and the potential is high, and the pixel electrode and the counter electrode. FIG. 4 is a waveform diagram of a voltage applied between the circuit and FIG.

FIG. 20 shows the relationship between the voltage applied between the input terminal of the active element and the counter electrode when the number of pulses of the data signal applied during the selection period is the maximum allowable number of pulses and the potential is low, and FIG. 4 is a waveform diagram of a voltage applied between an electrode and a counter electrode.

FIG. 21 shows the relationship between the voltage applied between the input terminal of the active element and the counter electrode when the number of pulses of the data signal applied in the selection period is the maximum allowable number of pulses and the potential is high, and FIG. 4 is a waveform diagram of a voltage applied between an electrode and a counter electrode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pixel electrode, 2 ... Active element, 3 ... Signal line, 4 ... Counter electrode, TS ... Selection period, TO ... Non-selection period, SS ... Scan signal, AD ... Data signal, Va-c ... Input terminal of active element , A voltage applied between the pixel electrode and the counter electrode, and a voltage applied between the pixel electrode and the counter electrode.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-74533 (JP, A) JP-A-1-251017 (JP, A) JP-A-57-179894 (JP, A) JP-A-2- 16596 (JP, A) JP-A-1-302395 (JP, A) JP-A-4-261516 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3 / 38 G02F 1/133 505-580

Claims (4)

(57) [Claims] A plurality of pixel electrodes arranged in a row direction and a column direction on one of a pair of transparent substrates opposed to each other with a liquid crystal layer therebetween, and a semiconductor connected to each of the pixel electrodes. An active element comprising a non-linear resistance element having
A signal line for supplying a drive signal to the active element is provided, and a liquid crystal display element provided with a counter electrode facing the pixel electrode on the other substrate is provided with an image on one of the signal line and the counter electrode. A liquid crystal display that supplies a data signal corresponding to data and supplies a scanning signal to the other, thereby sequentially selecting a plurality of pixels formed by the pixel electrode, the counter electrode, and the liquid crystal therebetween to perform time division driving. In the method for driving an element, a positive or negative data signal having a voltage value and a pulse width corresponding to image data and the scanning signal are superimposed between a driving signal input terminal of the active element and a counter electrode during a selection period. In a non-selection period in which a selection voltage of one polarity is applied and another pixel is selected, a data signal and a scanning signal for driving another pixel are superimposed, and the voltage is applied in a cycle shorter than the selection period. A liquid crystal display characterized by applying a voltage having a waveform that changes in position and has the same area on the positive side and the negative side around the potential in the non-selection period of the scanning signal supplied to one of the signal line and the counter electrode. Element driving method. 2. The method according to claim 1, wherein one of the signal line and the counter electrode is kept at one of the positive and negative polarities with respect to a reference potential which is a potential at the center of the potential change width during the selective period. Supplies a scanning signal that maintains one of the positive and negative polarities and a potential lower than the potential during the selection period, has a potential and a pulse width corresponding to the image data to the other, and has a period obtained by dividing the selection period into a plurality. 2. The method according to claim 1, wherein a data signal whose potential changes with an amplitude equal to the positive side and the negative side with respect to the reference potential is supplied. 3. A plurality of pixel electrodes arranged in a row direction and a column direction on one of a pair of transparent substrates opposed to each other with a liquid crystal layer therebetween, and a semiconductor connected to each of the pixel electrodes. An active element comprising a non-linear resistance element having
A signal line for supplying a drive signal to the active element is provided, and a liquid crystal display element provided with a counter electrode facing the pixel electrode on the other substrate is provided on one of the signal line and the counter electrode. A liquid crystal that supplies a data signal corresponding to image data and supplies a scanning signal to the other, thereby sequentially selecting a plurality of pixels formed by the pixel electrode, the counter electrode, and liquid crystal therebetween, and performing time-division driving. In the method of driving a display element, between a drive signal input terminal of the active element and a counter electrode, a positive signal and a negative signal in which a data signal having a voltage value and a pulse number according to image data and the scanning signal are superimposed during a selection period. In a non-selection period in which a selection voltage of one of the polarities is applied and another pixel is selected, a data signal and a scan signal are superimposed to drive another pixel, and the cycle is shorter than the selection period. A liquid crystal display characterized by applying a voltage whose potential changes and whose positive and negative areas are equal with respect to the potential of a scanning signal supplied to one of the signal line and the counter electrode during a non-selection period. Element driving method. 4. One of a signal line and a counter electrode maintains a potential of one of positive and negative polarities with respect to a reference potential, which is a potential at the center of a potential change width, during a selection period, during a non-selection period. Supplies a scanning signal that maintains one of the positive and negative polarities and a potential lower than the potential during the selection period, and has a potential and the number of pulses corresponding to image data, and a period obtained by dividing the selection period into a plurality. 4. The method of driving a liquid crystal display element according to claim 3, wherein a data signal whose potential changes with an amplitude equal to a positive side and a negative side with respect to the reference potential is supplied.