JP2008166306A - Inspection apparatus for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection apparatus for semiconductor device in which total inspection time can be reduced by performing inspection of a large number of semiconductor wafers in parallel. <P>SOLUTION: The inspection apparatus of a semiconductor device comprises a means R1 for holding and transferring a semiconductor wafer W on which a plurality of semiconductor devices D are formed in the directions of X axis, Y axis and Z axis, two or more wafer units 22 for storing semiconductor wafers W sequentially transferred by the wafer transfer means R1 one by one; a means arranged in each wafer unit 22 in order to inspect each semiconductor device D formed on each semiconductor wafer W; a means for detecting storage completion of semiconductor wafer W in the wafer unit 22, and a means 23 for controlling inspection start by the device inspection means, in the order of storage completion of semiconductor wafer W in the wafer unit 22, based on a detection signal from the housing detection means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device inspection apparatus.

  Semiconductor devices such as semiconductor memory ICs and system LSIs are manufactured using various processes (processes) such as oxidation, photolithography, diffusion sputtering, wafer testing, dicing, bonding, packaging, and final testing on the surface of a semiconductor wafer cut out from a bulk crystal. It is done through.

  Here, the wafer test checks the electrical characteristics of IC chips such as semiconductor memory ICs and system LSIs manufactured before cutting (dicing) many chips formed on a semiconductor wafer into several millimeters square. This refers to an inspection for determining whether a product is non-defective or defective.

  Specifically, using a tester equipped with a probe card, the probe (probe) of the probe card is brought into contact with the bonding pad of each IC chip formed on the semiconductor wafer, and various electrical characteristics are measured. I am testing. The test contents include disconnection / short circuit check, input / output voltage check, DC test to check output current, AC test to check output signal waveform, output pattern check, data writing availability, data holding time There is a function test that checks for the presence of measurement and data mutual interference.

  Here, a technique has been proposed in which the number of semiconductor devices formed on a wafer, such as LSIs, that can be simultaneously measured (the same number) is increased, thereby reducing the test cost of the semiconductor devices.

References describing techniques related to semiconductor device inspection apparatuses include, for example, Japanese Patent Laid-Open Nos. 2001-349925, 2003-315405, and 2004-045325.
JP 2001-349925 A JP 2003-315405 A JP 2004-045325 A

  However, since the conventional apparatus described above tests semiconductor wafers one by one, there is a limit to reducing the total inspection time and cost of a large number of semiconductor wafers even if the number of semiconductor devices is increased. It was.

  Therefore, the present invention can reduce the total inspection time by performing inspection of a large number of semiconductor wafers in parallel, and can reduce the cost required for a clean room by reducing the installation space of the apparatus. An object of the present invention is to provide an inspection apparatus for semiconductor devices in a space.

  In order to solve the above-described problem, the semiconductor device inspection apparatus according to the first aspect of the present invention can hold a semiconductor wafer on which a plurality of semiconductor devices are formed and transfer them in the three-dimensional directions of the X, Y, and Z axes. Wafer transfer means, two or more wafer units in which the semiconductor wafers transferred by the wafer transfer means are sequentially stored one by one, and each wafer unit is disposed on each of the semiconductor wafers. Device inspection means for inspecting each of the semiconductor devices, storage detection means for detecting completion of storage of the semiconductor wafer in the wafer unit, and the wafer of the semiconductor wafer based on a detection signal from the storage detection means And at least control means for controlling to start inspection by the device inspection means in the order in which the storage in the unit is completed. To.

  The semiconductor device inspection apparatus according to claim 2 further includes one or more cassette loaders / unloaders for receiving and storing a plurality of the semiconductor wafers, and the wafer transfer means includes A semiconductor wafer to be inspected is received from the cassette loader / unloader, and the semiconductor wafer which has been inspected by the device inspection means is delivered to the cassette loader / unloader and collected.

  According to a third aspect of the present invention, there is provided a semiconductor device inspection apparatus comprising: a plurality of device inspection means provided in a one-to-one relationship with the semiconductor devices formed on the semiconductor wafers; Device test means for inputting a predetermined test signal and inspecting the semiconductor device based on an output signal output from the semiconductor device in accordance with the test signal, electrodes formed on the semiconductor devices, and electrical A plurality of contact portions that can be contacted to each other, and connecting means for electrically connecting the semiconductor device and the corresponding device test means via the contact portions, the device test means, Waveform generating means for generating a waveform input to the semiconductor device.

  According to a fourth aspect of the present invention, there is provided a semiconductor device inspection apparatus which, in order from a wafer unit which has been inspected by the device inspection means, collects the semiconductor wafers by the wafer transfer means and removes the new semiconductor wafers from the wafers. Control is performed so as to be stored in the unit.

  According to a fifth aspect of the present invention, there is provided a semiconductor device inspection apparatus according to the first aspect, wherein the wafer transfer means includes an elevating means in the Z-axis direction and an arm that can move horizontally in the X-axis direction and the Y-axis direction. Alternatively, it is characterized by being composed of two or more articulated arm robots.

  According to a sixth aspect of the present invention, there is provided a semiconductor device inspection apparatus, wherein each of the wafer units includes a wafer stage on which the semiconductor wafer can be placed by the wafer transfer means, and the wafer stage is placed on the wafer transfer means. On the other hand, driving means for moving the wafer stage itself back and forth, alignment means for finely adjusting the position of the semiconductor wafer placed on the wafer stage in a state of being accommodated in each wafer unit, and placing the semiconductor wafer And a lifting / lowering means for raising / lowering the wafer stage itself with respect to the device test means.

  The semiconductor device inspection apparatus according to claim 7 is characterized in that at least one of a heat insulating means and a cooling means for preventing heat conduction to the elevating means is provided below the wafer stage. .

  The semiconductor device inspection apparatus according to claim 8 is characterized in that the heat insulating means is a ceramic plate, a fiber heat insulating material, and a foam material heat insulating material interposed between the lower part of the wafer stage and the lifting means. It is characterized by comprising.

  According to a ninth aspect of the present invention, there is provided the semiconductor device inspection apparatus, wherein the cooling means includes a thermal circuit substrate capable of supplying a refrigerant interposed between the lower part of the wafer stage and the elevating means. It is characterized by.

A semiconductor device inspection apparatus according to the invention of claim 10 comprises:
Each of the wafer units is provided with positioning imaging means for determining the mounting position of the semiconductor wafer outside the wafer unit in a state where the wafer stage has advanced.

  The semiconductor device inspection apparatus according to claim 11 is characterized in that the wafer stage is provided with temperature adjusting means capable of adjusting the semiconductor wafer placed on the wafer stage to a predetermined temperature. And

  The semiconductor device inspection apparatus according to claim 12 is characterized in that the waveform generating means is at least one of a pattern generator and a waveform generator.

  The semiconductor device inspection apparatus according to claim 13 is characterized in that the device test means further includes a driver for inputting the generated waveform to the semiconductor device.

  The semiconductor device inspection apparatus according to claim 14 is characterized in that the device test means is constituted by a single semiconductor device.

  According to the present invention, the following effects can be obtained.

  That is, according to the present invention, there are provided two or more wafer units including device inspection means controlled to start inspection by the device inspection means in the order in which the storage of the semiconductor wafers is completed, and each wafer unit includes Since the semiconductor wafer is supplied via the wafer transfer means, the wafer test can be executed efficiently in parallel, and the total inspection time and cost of many wafers can be reduced.

  Further, according to the present invention, since the device test means and the semiconductor device are provided in a one-to-one relationship, the number of measurements of the semiconductor device can be increased, and the apparatus can be reduced in size, thereby saving space. Cost reduction can be realized.

  Further, according to the present invention, a wafer that has been inspected can be recovered immediately, and a new wafer can be stored in the wafer unit to start the inspection, so that the inspection can be performed more efficiently.

  Furthermore, according to the present invention, an inspection apparatus in which a desired number of wafer units are mounted in the step direction or the horizontal direction can be easily manufactured. Therefore, an efficient and easy-to-use inspection apparatus that meets user needs can be provided. Can be provided.

  Further, according to the present invention, heat insulating means for preventing heat conduction to the elevating means below the wafer stage (for example, a ceramic plate interposed between the lower part of the wafer stage and the elevating means) Alternatively, a cooling means (for example, a thermal circuit substrate capable of supplying a refrigerant (including both gas and liquid) interposed between the lower part of the wafer stage and the elevating means) can be provided. It is possible to effectively prevent influences such as a decrease in accuracy due to heat of the X, Y, θ3-axis control means and deterioration due to heat of various mechanical parts and motors.

  According to the present invention, each of the wafer units is provided with positioning imaging means for determining the mounting position of the semiconductor wafer outside the wafer unit with the wafer stage advanced. Therefore, the degree of freedom in design is increased such that a sufficient installation space for the imaging means can be secured, and a relatively inexpensive CCD camera or the like can be employed. Therefore, the apparatus cost can be reduced as compared with a structure in which positioning is performed by arranging an ultra-small camera, a mirror, or the like in the wafer unit, thereby contributing to a reduction in test cost.

  For example, when all of the positioning imaging means are controlled by a single image processing apparatus, the apparatus configuration can be simplified to reduce the size and cost.

  Further, according to the present invention, the device test means provided in a one-to-one relationship with the semiconductor device includes the waveform generation means for generating the waveform input to the semiconductor device, so that the semiconductor device to be inspected is There is also a merit that the influence of the operation noise of the adjacent semiconductor devices which are isolated from each other is greatly reduced.

  Hereinafter, the best mode for carrying out the present invention will be described more specifically with reference to the drawings. Here, in the accompanying drawings, the same reference numerals are given to the same members, and duplicate descriptions are omitted. In addition, since description here is the best form by which this invention is implemented, this invention is not limited to the said form.

  FIG. 1A is a plan view schematically showing a semiconductor device inspection apparatus according to a first embodiment of the present invention, and FIG. 2B is a front view thereof. FIG. 2 is a configuration of a wafer unit of the semiconductor device inspection apparatus of FIG. FIG. 3 is a bottom view (A) and side view (B) showing the configuration of the prober unit provided in the wafer unit, and FIG. 4 is the configuration of the tester board provided in the prober unit. FIG. 5 is a partially cutaway perspective view showing the configuration of the wafer unit, FIG. 6 is a block diagram showing an outline of a control system of a semiconductor device inspection apparatus, and FIG. FIG. 8 is a perspective view showing a configuration example of a wafer handling robot included in a semiconductor device inspection apparatus, FIG. 8 is a block diagram showing a functional configuration of device test means (test circuit module) in the semiconductor device inspection apparatus, 9 is a flowchart showing a processing procedure of operation processing of the semiconductor device inspection apparatus, FIG. 10 is a flowchart showing a processing procedure of inspection processing of the semiconductor device inspection apparatus, and FIG. 11 is a semiconductor device according to the second embodiment of the present invention. FIG. 12A is a plan view showing the outline of the inspection apparatus, FIG. 12B is a front view thereof, and FIG. 12 is a schematic view showing an embodiment of the heat insulating structure of the wafer stage.

  As shown in FIG. 1, the semiconductor device inspection apparatus 10 according to the first embodiment includes an inspection apparatus body 20 and an attachment apparatus 30.

  Here, the accessory device 30 includes a chiller unit that supplies cooling water to the inspection apparatus main body 20, a system power supply apparatus that supplies driving power to each part of the inspection apparatus main body, and a unit power supply that supplies power to each wafer unit described later. An apparatus or the like is provided, and is connected to the inspection apparatus main body 20 via piping and wiring.

  The inspection apparatus main body 20 is a housing 21 and a wafer on which a semiconductor wafer W disposed in the housing 21 and on which a plurality of semiconductor devices D (see FIG. 2B) to be tested are formed is placed. A plurality of wafer units 22 each provided with a stage (also referred to as a wafer chuck) S and a prober unit 70 (details will be described later) as an inspection apparatus, as a main control unit for controlling the entire apparatus in the inspection of the semiconductor device D The host controller 23 holds the semiconductor wafer W and moves in a three-dimensional direction in the X-axis direction (left-right direction in the drawing), Y-axis direction (depth direction in the drawing), and Z-axis direction (up-down direction in the drawing). The wafer handling robot R1 as a transfer means for detaching / attaching the semiconductor wafer W to / from each wafer unit 22, and the semiconductor to the wafer handling robot R1 Supply of the wafer W, and a cassette loader and unloader 24 for recovery (one or two or more).

  Here, the host controller 23 has a central processing unit, an input / output device, and a storage device. The central processing unit manages software such as an inspection program, edits and translates a test program, controls execution of inspection, and peripherals. Performs device management and data processing of test results. The input / output devices include a keyboard, a printer, a display, and the like, and input control commands, input / output inspection programs, and output test results. The storage device includes a magnetic disk device, an optical disk device, a semiconductor storage device, and the like, and stores system software of the inspection device, inspection program, inspection result data, and the like.

  As shown in the block diagram of FIG. 6, the host controller 23 is connected to the cassette loader / unloader 24, the wafer handling robot R1, the wafer stage S, and the prober unit 70, and performs drive control of each device according to the inspection program. ing. The host controller 23 is connected to CCD cameras C1 and C2 for positioning, and each driving means of the wafer stage S is appropriately selected based on the alignment mark of the semiconductor wafer W imaged by the CCD cameras C1 and C2. By controlling, positioning of the semiconductor wafer W and positioning of the prober unit 70 and the semiconductor device D are performed.

  The wafer stage S is attached with a heater (temperature control means: not shown) that can heat the semiconductor wafer W mounted on the wafer mounting unit 40 provided in each wafer stage S to a predetermined temperature. . Therefore, the semiconductor wafer W is heated to a high temperature by increasing the temperature in the housing 21 or heating it through the wafer mounting unit 40 with a heater. In addition, when the semiconductor wafer W is cooled, the temperature inside the housing 21 is lowered. Alternatively, a flow path is formed in the wafer mounting section 40, and a liquid or gaseous refrigerant (temperature control means) is passed through the flow path to cool the wafer mounting section 40 itself.

  As shown in FIG. 2, the wafer unit 22 includes a box-shaped unit main body 60 having an opening 22a through which the wafer mounting unit 40 can advance and retreat on the front side, and the wafer mounting unit 40 with respect to the wafer handling robot R1. A wafer (with a ball screw feed mechanism, a linear motor, etc.) (not shown) that advances and retreats in the direction (depth direction in FIG. 1 and left-right direction in FIG. 2) and the wafer mounting portion 40 are accommodated. Vertical drive means (for example, a pusher mechanism P composed of a ball screw feed mechanism, an air cylinder, etc., which does not appear in the drawing) and the wafer mounting unit 40 itself are moved horizontally in a vertical direction with a stroke of, for example, 20 mm. A rotation mechanism (for example, a ball screw feed mechanism that does not appear in the figure) that performs positioning control (θ control) of the semiconductor wafer W by rotating it within a small angle is provided.

  As shown in FIG. 2, the unit main body 60 has a plate-like alignment stage base 61 processed with high accuracy, and a probe / tester fixed as a single frame having high rigidity installed on the alignment stage base 61. And a frame 62 for use.

  Above the fixing frame 62, a prober unit 70 (described later) is provided, and an opening (not shown in the figure) for exposing the probing contact 72 to the lower side is formed.

  A positioning camera (CCD camera or the like) C1 for positioning the wafer mounting portion 40 in the advanced state and the semiconductor wafer W is installed above the fixing frame 62 on the opening 22a side.

  Further, a camera for positioning the wafer stage S and the probe card 73 (ultra-miniature CCD camera or the like) C2 in a state where the wafer mounting portion 40 is accommodated inside the fixing frame 62 (that is, inside the wafer unit 22). Is installed.

  Here, since the wafer mounting unit 40 and the positioning camera C1 for the semiconductor wafer W are arranged outside the wafer unit 22 as described above, a sufficient installation space for the positioning camera C1 is provided. The degree of freedom of design can be increased, such as securing.

  Here, as shown in FIG. 2B, a semiconductor device D formed on each semiconductor wafer W to be inspected includes circuit elements such as transistors, capacitors, resistors, and wirings connecting these circuit elements. , And an electrode 50 for performing electrical input / output with the outside.

  The semiconductor wafer W is not particularly limited. For example, a semiconductor wafer W on which about 1000 dies of IC chips of 12 inches are formed can be an inspection object.

  Next, a prober unit 70 as an inspection apparatus will be described with reference to FIG.

  The prober unit 70 includes a rectangular high-rigidity frame 71 manufactured by casting or die-casting, a tester board 80 disposed on the upper side of the frame 71, and a number of probing probing contacts 72 on the lower surface. And a connector (for example, a ZIF connector) 74 that connects the tester board 80 and the probe card 73 so as to be able to exchange signals and is easy to insert and remove. Instead of the ZIF connector, a so-called pogo tower in which a number of probing pins (or pogo pins (POGO pin is a trademark of ETC)) are arranged in a ring shape or concentric shape may be used.

  In FIG. 3A, the probing contact 72 is fine and numerous and is not shown in the figure, but can actually face each electrode 50 of the semiconductor device D formed on each semiconductor wafer W. It is made with a simple pattern.

  As shown in FIG. 4, the tester board 80 has a large number of test circuit modules 82 mounted on the upper surface of a tester motherboard 81 composed of a laminated substrate of glass epoxy resin, and the ZIF disposed on the lower surface of the tester motherboard 81. A probe card 73 is connected via a connector 74.

  The test circuit module 82 is not particularly limited. For example, when the semiconductor wafer W on which the IC chip of about 1000 dies with 12 inches is formed as described above is to be inspected, the test circuit module 82 is a module corresponding to 1000 chips. Will be implemented.

  As shown in FIG. 1B, the wafer units 22 configured as described above are arranged in a total of eight, for example, four rows in the vertical direction and two rows in the horizontal direction. Note that the arrangement of the wafer units 22 is arbitrary, and it goes without saying that the number of vertical steps and the number of horizontal columns can be increased or decreased according to demands and conditions.

  Next, a wafer handling robot R1 as a wafer transfer means will be described with reference to FIGS.

  The wafer handling robot R1 in this embodiment is a so-called articulated double arm robot.

Specifically, as shown in FIG. 7, a robot main body 90 incorporating an electric motor, a speed change mechanism, and the like, and a first arm 91 connected to a rotary shaft (not shown) that pivotably protrudes from the upper end side. A second arm 92 rotatably connected to a small electric motor M provided at the tip of the first arm 91, and a wafer grip 93 provided on the tip of the second arm 92. I have.
The robot body 90 includes a lifting device (lifting means) 94 such as a telescopic type (a telescopic structure like a telescope barrel) as a lifting means for lifting the robot body 90 in the Z-axis direction. . With this lifting device, the robot body 90 is configured to be displaced in the Z-axis direction (vertical direction) with a stroke of, for example, about 1600 mm.

  The cassette loader / unloader 24 disposed in the vicinity of the wafer handling robot R <b> 1 includes a storage unit 24 a that stores a plurality of semiconductor wafers W, and faces the cassette loader / unloader 24 under the control of the host controller 23. The semiconductor wafer W to be inspected is supplied one by one to the wafer grip portion 93 of the wafer handling robot R1 that has arrived at the position, or the inspected semiconductor wafer W transferred by the grip portion 93 is recovered. To be operated.

  In this wafer handling robot R1, the host controller 23 controls the operation of the electric motor on the robot body 90 side and the electric motor M at the tip of the first arm, thereby controlling the semiconductor wafer W held on the wafer grip 93 by the X axis. And any position in the Y-axis direction. Further, the semiconductor wafer W held on the grip part 93 of the wafer can be transferred to an arbitrary position in the Z-axis direction by controlling the lifting device 94 and the like by the host controller 23.

  Thereby, the semiconductor wafer W supplied via the cassette loader / unloader 24 can be carried to an arbitrary wafer unit 22 or the inspected semiconductor wafer W can be recovered. That is, the semiconductor wafer W to be inspected is mounted on the wafer mounting portion 40 that has been advanced to the outside under the control of the host controller 23 in the arbitrary wafer unit 22 or the semiconductor wafer W that has been inspected is mounted on the wafer mounting portion. 40 can be recovered from above.

  From which wafer unit 22 the placement of the semiconductor wafer W is started or in what order the placement or collection is performed can be freely changed depending on the programming of the inspection program stored in the host controller 23. For example, in FIG. 1B, first, the semiconductor wafers W are placed on the left four-stage wafer units 22 in order from the top, and then on the right four-stage wafer units 22 in order from the top. An order in which the semiconductor wafer W is mounted is conceivable.

  Then, the wafer unit 22 on which the semiconductor wafer W is placed is detected by the CCD camera C1, the wafer stage 22 is based on the detection of the semiconductor wafer W or a wafer placement confirmation sensor that can be separately provided, or a time control based on the passage of a predetermined time. S is accommodated in the wafer unit 22, and the inspection of the semiconductor device D on the semiconductor wafer W is started by a procedure described later.

  As described above, according to the present embodiment, since the semiconductor devices D can be inspected in parallel in the respective wafer units 22 in the order in which the semiconductor wafers W are mounted, a large number of semiconductor wafers W can be inspected efficiently. This can be done, and thus the test cost can be reduced.

  Further, the semiconductor wafers W are collected from the wafer unit 22 in the order in which the inspections are completed, and the next semiconductor wafer W is immediately supplied to the wafer unit 22 so that the inspection can proceed with higher efficiency. It is.

  Next, the functional configuration of the test circuit module 82 will be described with reference to FIG.

  The test circuit module 82 as device test means inputs a predetermined test signal to the semiconductor device D on the semiconductor wafer W, and based on the output signal output from the semiconductor device according to the test signal, the test circuit module 82 Inspects, pattern generator 82-1, driver 82-2, comparator 82-3, waveform generator 82-4, interface unit 82-5, test engine 82-6, memory 82-7, voltage adjustment And a voltage / current application measuring unit 82-9.

  Here, a sub-controller 83 as a sub-control unit is provided corresponding to a plurality of (for example, 10 to 20) test circuit modules 82. This sub-controller 83 is under the control of the host controller 23, transmits a test program to each corresponding test circuit module 82, manages the test results of the semiconductor device D, performs log management, status management, etc. Execute.

  Further, power to the test circuit module 82 and the sub-controller 83 is supplied from the accessory device 30 adjacent to the inspection device 10.

  The test circuit module 82 is supplied with several types of voltages (± 15 V, +5 V, etc.) from the power supply 30, and the semiconductor device D on the semiconductor wafer W is supplied with the voltage supplied from the power supply 30 by the test circuit module 82. Supply with precision control. The test circuit module 82 may have a functional configuration other than these as long as it has a test function, and may have only a part of these functional configurations.

  Here, the pattern generator 82-1, which is one of the waveform generation means, extracts the waveform parameters from the tester language and inputs the waveform to the driver 82-2. The driver 82-2 buffers the waveform input from the pattern generator 82-1 at a predetermined voltage and inputs the buffered waveform to the semiconductor device D to be tested.

  The comparator 82-3 makes the output waveform from the semiconductor device D "high" or "low" based on a predetermined reference voltage, and sends it to the test engine 82-6. The test engine 82-6 compares the waveform from the comparator 82-3 with the expected value to determine the pass / fail (good / bad) of the semiconductor device D, and controls the sub controller 83 or the host controller 23 as an external controller. I do.

  The memory 82-7 stores the pass / fail information of the semiconductor device D determined by the test engine 82-6 in this way, the address position for each test pattern in which a defect has occurred, and the like. Further, when the semiconductor device D is a memory LSI, storage of defective bit positions, masking of defective bits, real-time counting of the number of defective bits, generation of ROM test patterns, and the like are performed.

  A waveform generator 82-4, which is another one of the waveform generating means, generates an arbitrary analog waveform such as a sine wave, a triangular wave, or a rectangular wave and inputs it to the semiconductor device D.

  The interface unit 82-5 is an interface between the host controller 23 and the test circuit module 82, specifically, a serial interface or a parallel interface. The voltage regulator 82-8 is an input power source for the driver 82-2 and an input power source for the semiconductor device D, and supplies a power source having a predetermined voltage.

  Then, the voltage / current application measuring unit 82-9 applies a voltage or current to the semiconductor device D to measure the operating current or operating voltage of the semiconductor device D, or opens / shorts the wiring formed in the semiconductor device D. Measure.

  Next, the processing procedure of the operation processing of the inspection apparatus according to the present embodiment will be described with reference to the flowchart shown in FIG.

  When this processing is started, initialization processing of the wafer handling robot R1 is first performed in step S1. Specifically, a process of checking the operation of the first arm 91 and the second arm 92 of the wafer handling robot R1 and stopping the wafer grip unit 93 at a predetermined position facing the cassette loader / unloader 24 is performed. Do.

  Next, the process proceeds to step S2, where it is determined whether or not the initialization process has been completed. If it has not been completed, the process is continued. If it is determined that the process has been completed, the process proceeds to step S3.

  In step S3, the cassette loader / unloader 24 is operated. Specifically, a process of sending only one semiconductor wafer W to be inspected onto the wafer grip portion 93 of the wafer handling robot R1 is performed. Next, the process proceeds to step S4, where the semiconductor wafer W is transferred by the wafer handling robot R1. Specifically, the electric motor included in the wafer handling robot R1 is controlled according to the control program to rotate the first arm and the second arm, and the wafer unit 22 (for example, as shown in FIG. 1B) at a predetermined position is rotated. The semiconductor wafer W is transferred to the uppermost wafer unit 22) on the left side, and the semiconductor wafer W is mounted on the wafer mounting portion 40 of the wafer stage S in the advanced state.

  Next, the process proceeds to step S5, and it is determined whether or not the placement of the semiconductor wafer W is confirmed by the positioning camera C1. If it is not detected yet, it waits. If it is determined that it has been detected, the process proceeds to step S6 to start a subroutine for inspection processing.

  Here, the inspection process will be described with reference to the flowchart of FIG.

  When the inspection process is started, first, in step S601, a positioning alignment mark formed on the semiconductor wafer W is captured by the positioning camera C1, and image processing software or the like is used based on the alignment mark captured in step S602. The position is grasped, and a positional deviation amount from a predetermined position is calculated.

  Next, the process proceeds to step S603, and θ (angle in the circumferential direction) of the semiconductor wafer W is corrected. Specifically, based on the positional deviation amount, the ball screw mechanism or the like provided in the wafer stage S is appropriately controlled to rotate the wafer mounting unit 40 by a slight angle to correct to an appropriate position. Here, since the positioning camera C1 is arranged outside the wafer unit 22 as described above, it is possible to increase the degree of design freedom, such as ensuring a sufficient installation space for the positioning camera C1. Can do.

  Next, the process proceeds to step S604, and a process of storing the wafer stage S in the wafer unit 22 is performed. Specifically, the wafer stage S itself is moved by driving a ball screw feeding mechanism or a linear motor provided in the wafer stage S. When a linear scale is used, setting with higher accuracy is possible.

  In step S605, the positioning alignment mark formed on the semiconductor wafer W is captured by the positioning camera C2, and the position is grasped by image processing software or the like based on the alignment mark captured in step S606. Then, the positional deviation amount from the predetermined position is calculated.

  In step S607, the X-axis direction, the Y-axis direction, and θ correction of the semiconductor wafer W are performed. Specifically, based on the positional deviation amount of the alignment mark, the pattern on the wafer, the wafer dicing line, etc., the ball screw mechanism provided in the wafer stage S is appropriately controlled to move the wafer mounting portion 40 by a small distance. Thus, each electrode 50 of the semiconductor device D fabricated on the semiconductor wafer W and each probing contact 72 on the prober unit 70 side are opposed to each other in a one-to-one relationship (for example, X, Y Alignment of axis <1μ, θ axis <1 degree).

Next, the process proceeds to step S608, and a process for raising the wafer stage S is performed. Specifically, it is raised by, for example, about 20 mm by the operation of a ball screw feed mechanism or an air cylinder provided in the wafer stage S. As a result, each electrode 50 of the semiconductor device D manufactured on the semiconductor wafer W and each probing contact 72 on the prober unit 70 side are in contact with each other in a one-to-one relationship so that a test signal can be transmitted and received. Become.
In addition, the contact check which a tester function has has confirmed whether the contact (contact) is possible.

  Next, the process proceeds to step S609, and various tests are executed based on a predetermined test program via the test circuit module 82 on the prober unit 70 side. Next, the process proceeds to step S610, where it is determined whether or not the inspection has been completed for all the semiconductor devices D on the semiconductor wafer W. If the inspection has not been completed, the processing is continued, and it is determined that the inspection has been completed. In this case, the process proceeds to step S611.

  In step S611, the wafer stage S is lowered to the original position, and the wafer stage S itself is moved out of the wafer unit 22 before returning to the operation process of FIG.

  In the operation process, the process proceeds to step S7, and it is determined whether or not the semiconductor wafers W are stored in all the wafer units 22. Specifically, the determination is made by managing in which wafer unit 22 the semiconductor wafer W has been stored by the host controller 23. If it is determined that all the wafer units 22 have not yet been stored, the process returns to step S3, and the processes from step S3 to step S7 are repeated. On the other hand, if it is determined in step S7 that the storage of the semiconductor wafers W in all the wafer units 22 has been completed, the process proceeds to step S8.

  In step S8, it is determined whether or not the inspection of the semiconductor device D is completed in any of the wafer units 22. Specifically, the determination is performed by monitoring the status of the inspection process performed through the test circuit module 82 of each prober unit 70 by the host controller 23. If it is determined that the inspection has not been completed for any of the wafer units 22, the process waits. If it is determined that the inspection has been completed for any of the wafer units 22, the process proceeds to step S 9. Recovery of the inspected semiconductor wafer W from the corresponding wafer unit 22 is performed by the operation of the wafer handling robot R1. Specifically, similarly to the operation in step S4, the electric motor included in the wafer handling robot R1 is controlled according to the control program to move to a desired height, and the first arm and the second arm are rotated to correspond to the corresponding positions. The inspected semiconductor wafer W placed on the wafer placement section 40 of the wafer stage S of the wafer unit 22 is placed on the wafer grip section 93 and transferred to a predetermined position on the cassette loader / unloader 24 side.

  Next, the process proceeds to step S10, where the inspected semiconductor wafer W held by the wafer grip portion 93 is collected by the cassette loader / unloader 24 into a predetermined storage portion. Then, the process proceeds to step S11, where it is determined whether or not the operation process is to be ended by program control or human operation. If it is determined that the operation process is to be ended, the process is ended. Returning to S3, the above processes are repeated.

  As described above, according to the inspection apparatus 10 according to the present embodiment, since the inspection by the prober unit 70 is controlled in order from the wafer unit 22 in which the storage of the semiconductor wafer W is completed, the wafer test is performed in parallel. Therefore, the total inspection time and cost of a large number of semiconductor wafers W can be reduced.

  Further, since the test circuit module 82 and the semiconductor device D are provided in a one-to-one relationship, the number of measurements of the semiconductor device D can be increased, and the cost of the inspection apparatus can be further reduced. it can.

  Further, the semiconductor wafer W that has been inspected can be recovered immediately, and the new semiconductor wafer W can be stored in the wafer unit 22 to start the inspection, so that the inspection can be performed more efficiently.

  In the inspection process, all test items of the characteristic test may be executed, but some test items such as an AC test may be performed by another inspection device.

  Further, the characteristic test may be performed by heating the semiconductor wafer W to about 85 ° C., or the characteristic test can be performed at room temperature or below.

  Further, the semiconductor wafer D is heated to a high temperature of about 125 ° C., and a high voltage is applied to the semiconductor device D to operate for a certain period of time to accelerate the occurrence of the initial failure. You may make it remove. That is, a burn-in test may be performed.

  Further, in the present embodiment, the test is performed by bringing the probing contact 72 into contact with the electrode 50 that performs electrical input / output with the outside in the semiconductor device D (that is, the diagnostic circuit of the semiconductor device D to be tested). Is a so-called BOST (Built-Out Self-Test), but a BIST (Built-In Self-Test) circuit having a self-diagnosis function is provided inside the semiconductor device D. The test may be performed by contacting the probing contact 72 with the electrode for the circuit, thereby reducing the number of electrodes, and as a result, the number of probing contacts 72 is reduced. The pitch can be increased and the reliability can be improved.

  One test circuit module 82 may be provided corresponding to a plurality of semiconductor devices D. Further, the test circuit module 82 may not be a single semiconductor device as illustrated, but may be configured by a plurality of electronic components having the functions of the semiconductor device.

  Next, a semiconductor device inspection apparatus 100 according to a second embodiment of the present invention will be described with reference to FIG.

  However, the difference between the present embodiment and the first embodiment is mainly the wafer handling robot that constitutes the transfer means for the semiconductor wafer W, and the other components are the same. Description is omitted.

  In this embodiment, as shown in FIGS. 11A and 11B, instead of the wafer handling robot R1 having a configuration in which the robot body 90 itself includes the lifting device 94 as shown in the first embodiment, a robot is used. A wafer handling robot R2 having moving means in the X-axis and Z-axis directions outside the main body 90 is employed.

  Specifically, Z-axis slide rails 101a and 101b are erected on both left and right ends in the casing 21 of the inspection apparatus 100, and an X-axis slide rail is provided between the Z-axis slide rails 101a and 101b. 102 is arranged to be slidable in the vertical direction. A robot body 90 of an articulated double arm robot is attached to the X-axis slide rail so as to be slidable in the horizontal direction. The X-axis slide rail 102 and the robot main body 90 are configured to be transferred in the vertical direction and the horizontal direction, respectively, by control of a ball screw feed mechanism or the like, for example.

  The basic configuration of the multi-joint type double arm robot is substantially the same as that shown in FIG. 7, and the semiconductor wafer W held on the grip portion 93 of the wafer by driving the first arm 91 and the second arm 92 is provided. The desired wafer unit 22 can be transferred.

  However, the wafer handling robot R2 does not require the robot body 90 itself to include the lifting device 94 as compared with R1, and thus it is possible to employ a lighter and cheaper arm robot.

  The operation similar to that of the first embodiment can also be performed by the inspection apparatus 100 including the wafer handling robot R2 configured as described above. More specifically, the semiconductor wafer W delivered from the cassette loader / unloader 24 is moved by moving the X-axis slide rail 102 and the robot main body 90 by a desired distance in the vertical and horizontal directions under the control of the host controller 23. It is possible to transfer to each wafer unit 22 or to collect the inspected semiconductor wafer W.

  In the first and second embodiments, the type of arm robot provided with the first arm 91 and the second arm 92 as shown in FIG. 7 is used, but the present invention is not limited to this. The type of arm robot may be one or three or more. The number of arm robots R1 and R2 installed is not limited to one, and two or more may be provided. Furthermore, two or more cassette loaders / unloaders 24 may be provided.

  For example, as shown in FIGS. 12A and 12B, in the first and second embodiments, two cassette loaders / unloaders 24A and B may be provided. In this case, in the configuration shown in FIGS. 12A and 12B, the wafer W is supplied and recovered by the cassette loader / unloader 24A to the wafer units 22 in the left column, and the wafer units 22 in the right column are supplied. On the other hand, the wafer W can be supplied and recovered by the cassette loader / unloader 24B, and the semiconductor device D can be inspected more efficiently.

  The means for moving the robot body 90 is not limited to the structure shown in the first embodiment and the second embodiment, and any structure can be used as long as the robot body 90 can be moved in the X-axis direction and the Y-axis direction. It is possible to adopt.

  Next, an embodiment of a pusher mechanism and a heat insulating structure that the wafer stage S can have will be described with reference to FIG. In addition, about the same structure as the above, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  In the heat insulating structure shown in this embodiment, first, a ceramic plate 200 having heat insulating properties is embedded at a position in the vicinity of the surface in a metal member constituting the wafer mounting portion 40. Thereby, it can suppress that the heat from the tester board 80 and the wafer stage S side is transmitted to the pusher mechanism P side via the wafer W as a test body.

  Instead of the ceramic plate 200, it is also conceivable to use a fiber-based heat insulating material (for example, glass fiber) or a foam material-based heat insulating material (foamed plastic, etc.).

  In this embodiment, the thermal circuit board 201 is installed below the wafer mounting unit 40, and a refrigerant (for example, a fluorine-based inert liquid) is supplied by a pump mechanism (not shown).

  Here, as the thermal circuit board, grooves are formed by half-etching in predetermined portions of the opposing surfaces of the two substrates on which the metal thermal conductor foils are stretched, and then these grooves are opposed to each other. Using the two substrates with an adhesive and using the groove as a coolant flow path, or using a chemical bond such as a hydrogen bond, ionic bond or van der Waals bond without using an adhesive Etc. are available. Thereby, the wafer mounting part 40 of the wafer stage S can be forcedly cooled, and it can suppress more effectively that the heat from the wafer stage S side is transmitted to the pusher mechanism P side.

Although the invention made by the present inventor has been specifically described based on the embodiments, the embodiments disclosed in the present specification are examples in all respects and are not limited to the disclosed technology. Should be considered. That is, the technical scope of the present invention should not be construed restrictively based on the description in the above embodiment, but should be construed according to the description of the claims to the last. All modifications within the scope of the claims and the equivalent technology are included.
For example, in the present embodiment, the case where both the heat insulating structure by the ceramic plate 200 and the cooling structure by the thermal circuit board 201 are provided has been described. Also good.

  The semiconductor device inspection apparatus according to the present invention can be applied to inspection of various semiconductor devices that require characteristic tests, and includes various semiconductor devices such as SDRAM, static RAM, flash memory, logic device, and logic / analog mixed device. Can be applied as a test target.

1A and 1B are a plan view and a front view showing an outline of a semiconductor device inspection apparatus according to a first embodiment of the present invention. FIGS. 2A and 2B are a side view and a plan view showing a configuration of a wafer unit of the semiconductor device inspection apparatus of FIG. They are the bottom view (A) and side view (B) which show the structure of the prober unit with which a wafer unit is provided. It is the top view (A) and side view (B) which show the structure of the tester board with which a prober unit is provided. It is a partially cutaway perspective view showing a configuration of a wafer unit. It is a block diagram which shows the outline of the control system of the test | inspection apparatus of a semiconductor device. It is a perspective view which shows the structural example of the wafer handling robot with which the inspection apparatus of a semiconductor device is provided. It is a block diagram which shows the function structure of the device test means (test circuit module) in the test | inspection apparatus of a semiconductor device. It is a flowchart which shows the process sequence of the operation | movement process of the test | inspection apparatus of a semiconductor device. It is a flowchart which shows the process sequence of the test | inspection process of the test | inspection apparatus of a semiconductor device. They are the top view (A) and front view (B) which show the outline of the inspection apparatus of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the other structural example of the test | inspection apparatus of a semiconductor device. It is the schematic which shows the Example of the heat insulation structure of a wafer stage.

Explanation of symbols

10. Semiconductor device inspection apparatus (first embodiment)
W Semiconductor wafer D Semiconductor device 21 Housing 22 Wafer unit 23 Host controller R1 Wafer handling robot (wafer transfer means)
24 (24A, B) Cassette loader / unloader C1, C2 Positioning camera 30 Attached device S Wafer stage 40 Wafer mounting part 50 Electrode 60 Unit body 61 Alignment stage base 62 Probe / tester fixing frame 70 Prober unit 71 Frame 72 Probing Contact 73 Probe card 74 ZIF connector 80 Tester board 81 Tester motherboard 82 Test circuit module (device inspection means)
DESCRIPTION OF SYMBOLS 90 Robot main body 91 1st arm M Electric motor 92 2nd arm 93 Wafer grip part 94 Lifting device (lifting means)
100 Semiconductor Device Inspection Apparatus (Second Embodiment)
R2 Wafer handling robot (wafer transfer means)
101a, 101b Z-axis slide rail 102 X-axis slide rail P Pusher mechanism 200 Ceramic plate 201 Thermal circuit board 202 Refrigerant

Claims (14)

A wafer transfer means capable of holding a semiconductor wafer on which a plurality of semiconductor devices are formed and transferring them in a three-dimensional direction of the X axis, Y axis, and Z axis;
Two or more wafer units in which the semiconductor wafers transferred by the wafer transfer means are sequentially stored one by one;
Device inspection means arranged for each of the wafer units and for inspecting the semiconductor devices formed on the semiconductor wafers;
Storage detecting means for detecting completion of storage of the semiconductor wafer in the wafer unit;
Control means for controlling to start inspection by the device inspection means in the order in which the storage of the semiconductor wafer into the wafer unit is completed based on a detection signal from the storage detection means;
An inspection apparatus for semiconductor devices, comprising:   The apparatus further comprises one or more cassette loaders / unloaders for receiving and storing a plurality of the semiconductor wafers, and the wafer transfer means receives the semiconductor wafers to be inspected from the cassette loaders / unloaders, and 2. The semiconductor device inspection apparatus according to claim 1, wherein the semiconductor wafer inspection apparatus is configured to deliver and recover a semiconductor wafer that has been inspected by the device inspection means to a cassette loader / unloader. The device inspection means includes
A plurality of semiconductor devices formed in a one-to-one relationship with each of the semiconductor devices formed on each of the semiconductor wafers, and a predetermined test signal is input to each of the semiconductor devices and output from the semiconductor device according to the test signal Device test means for inspecting the semiconductor device based on an output signal;
A plurality of contact portions that can be electrically contacted with the electrodes formed in each semiconductor device, and a connection means that electrically connects the semiconductor device and the corresponding device test means via the contact portions And
The device test means includes waveform generation means for generating a waveform input to the semiconductor device;
The semiconductor device inspection apparatus according to claim 1, further comprising:   The control means performs control so that the semiconductor wafers are collected by the wafer transfer means in order from the wafer units that have been inspected by the device inspection means, and new semiconductor wafers are stored in the wafer units. An inspection apparatus for a semiconductor device according to any one of claims 1 to 3.   The wafer transfer means is composed of one or two or more articulated arm robots including an elevating means in the Z-axis direction and an arm that can move horizontally in the X-axis direction and the Y-axis direction. The semiconductor device inspection apparatus according to claim 1, wherein the inspection apparatus is a semiconductor device inspection device. Each wafer unit includes a wafer stage on which the semiconductor wafer can be placed by the wafer transfer means,
The wafer stage is
Drive means for advancing and retracting the wafer stage itself relative to the wafer transfer means;
Alignment means for finely adjusting the position of the semiconductor wafer placed on the wafer stage in a state of being accommodated in each wafer unit;
Elevating means for elevating and lowering the wafer stage itself relative to the device test means with the semiconductor wafer mounted thereon,
The semiconductor device inspection apparatus according to claim 1, further comprising:   The semiconductor device according to claim 1, wherein at least one of a heat insulating unit and a cooling unit for preventing heat conduction to the elevating unit is provided below the wafer stage. Inspection device.   The semiconductor according to claim 7, wherein the heat insulating means includes a ceramic plate, a fiber heat insulating material, and a foam material heat insulating material interposed between the lower part of the wafer stage and the lifting / lowering means. Device inspection equipment.   The semiconductor device inspection apparatus according to claim 7, wherein the cooling unit includes a thermal circuit substrate capable of supplying a coolant interposed between the lower part of the wafer stage and the elevating unit. Each wafer unit is
The positioning imaging means for determining the mounting position of the semiconductor wafer in a state where the wafer stage has advanced is provided outside the wafer unit. Inspection device for semiconductor devices.   11. The semiconductor device according to claim 1, wherein the wafer stage is provided with temperature adjusting means capable of adjusting a semiconductor wafer placed on the wafer stage to a predetermined temperature. Inspection device.   12. The semiconductor device inspection apparatus according to claim 1, wherein the waveform generating means is at least one of a pattern generator and a waveform generator.   The semiconductor device inspection apparatus according to claim 1, wherein the device test unit further includes a driver that inputs a generated waveform to the semiconductor device.   14. The semiconductor device inspection apparatus according to claim 1, wherein the device test means is constituted by a single semiconductor device.

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