JP2011080960A - Semiconductor inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor inspection device with high spatial resolution which can shorten the time required to inspection and identifying abnormal places of the semiconductor device with a simple constitution. <P>SOLUTION: The semiconductor inspection device 1A includes: a stress applying device 22 applying stress voltage Vs to a terminal electrode of a DUT 17; a light source 11 emitting light of wavelength transmitting a silicon substrate 17a; an interference optical system irradiating light received from the light source 11 to the silicon substrate 17a to form an interference figure of light transmitted the silicon substrate 17a; an IR camera 19 imaging the interference figure to form the data imaged; and an operation part 21 calculating information for identifying exothermic parts of the DUT 17 as a failure generation part based on the data imaged. A temporal waveform of the stress voltage Vs is an iterative waveform with a constant period and the temporal waveform assuming temporal variation of optical distance as a sinusoidal undulance inside the silicon substrate 17a due to exothermic heat of the DUT 17. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor inspection apparatus.

  A semiconductor inspection apparatus is required to identify an extremely small abnormality occurrence location such as several micrometers or a submicron in a device under test (DUT) in a short time. There is a thermal lock-in measurement method as one method for specifying a DUT abnormality occurrence location. In this method, radiant heat generated from heat generation due to current concentration accompanying abnormality of the DUT is captured by an infrared camera (for example, an InSb camera). However, the wavelength of such radiant heat is as long as 3.5 [μm] to 5.2 [μm], and a high spatial resolution is required with the recent miniaturization of semiconductor devices. The spatial resolution is suppressed to about half the wavelength of radiant heat (1 [μm] to 2 [μm]).

  On the other hand, when the DUT is irradiated with light having a wavelength that passes through the substrate material (for example, silicon) (for example, light having a wavelength of 1.3 [μm]), optical properties such as expansion of the substrate and a change in refractive index due to heat generation at the location where an abnormality has occurred. Due to the change in the target distance, the reflected light from the abnormal location causes a phase lag with respect to the reflected light from the normal location. By measuring this phase delay with high accuracy using optical interference measurement technology, not only the location of the heat generation (abnormality occurrence location) but also the phenomenon can be observed in real time.

  However, in the method of measuring the change in the optical distance on the substrate using the optical interferometer, the phase difference between the reference light and the sample light in the optical interferometer and the phase lag of the thermal expansion waveform with respect to the voltage waveform applied to the DUT Is a problem. As a method for avoiding this interference, in Non-Patent Document 1, in the zero-dimensional measurement (point sensing), the optical path length difference between the reference light and the sample light or the phase of the electrical signal is adjusted in advance, so that the optical phase difference is zero or π / 2 is adopted.

  In addition, in order to specify a DUT abnormality occurrence location, it is necessary to inspect the DUT two-dimensionally instead of one point. Non-Patent Document 2 proposes a method of two-dimensionally scanning light by placing a DUT on an XY stage in the one-point sensing mechanism shown in Non-Patent Document 1.

  Further, Patent Document 1 uses a photothermal displacement effect in which light energy is converted into heat energy, and irradiates a portion of the DUT where light whose intensity is modulated in a sine wave shape is to be measured, and sets the temperature of the portion. A method is described in which the amplitude and phase of the thermal expansion waveform at that time are obtained by synchronous detection with an optical interferometer.

  The method described in Patent Document 2 uses a Michelson-type interference microscope, applies a long stress pulse of 10 nanoseconds to 500 nanoseconds or more to the DUT, and applies the stress pulse and after the stress pulse is applied. By acquiring interference images in two different states and creating a difference image, a heat generation location is to be specified.

  Further, the method described in Non-Patent Document 3 is an improvement of the method described in Patent Document 2, and modulates light in a pulse form using an acousto-optic device (AOM: Acoustic-Optical Modulator). The optical phase is estimated by approximation.

Japanese Patent No. 3203936 US Patent Application Publication No. 2005/0036151

M. Goldstein, “Heterodyn interferometer for the detection of electric and thermal signals in integrated circuits through the substrate”, Review of Scientific Instruments, American Institute of Physics, 64 (10), pp. 3009-3013 (1993) C. Furbock, “Thermal and free carrier concentration mapping during ESDevent in Smart Power ESD protection devices using an inproved laserinterferometric technique”, Microelectronics Reliability, elsevier, 40, pp.1365-1370 (2000) V.Dubec, “Backside interferometric methods for localization of ESD-induced leakage current and metal shorts”, Microelectronics Reliability, elsevier, 47, pp.1549-1554 (2007)

  However, the method described in Non-Patent Document 1 is limited to one-point sensing, and is difficult to apply to two-dimensional measurement in a certain area such as abnormality detection of a semiconductor device. If the method described in Non-Patent Document 2 is used, the method described in Non-Patent Document 1 can be applied to two-dimensional measurement. However, in order to maintain the optical phase φ at 0 or π / 2, the DUT itself is used as an XY stage. Since the scanning is carried on, the measurement time becomes long and the apparatus configuration becomes complicated. As a method for scanning the irradiation light, a method of providing a scanning mechanism such as a galvanometer mirror is conceivable. However, the phase difference between the reference light and the sample light in the optical interferometer and the phase of the thermal expansion waveform with respect to the voltage waveform applied to the DUT. In order to prevent interference with delay, it is necessary to measure phase differences in all measurement regions in advance or adjust them to a predetermined value. Therefore, it takes time and labor to detect the abnormality of the semiconductor device.

  Further, in Patent Document 1, light that is intensity-modulated in a sine wave shape is irradiated onto the DUT, and thermal expansion in the DUT is also sinusoidally modulated at the same frequency as this light. It is disclosed that the amplitude A and the phase delay Φ of the thermal expansion waveform can be directly measured from the interference image by performing synchronous detection. However, since the excitation light is required in addition to the irradiation light to the DUT, the structure becomes complicated. In addition, since the temperature change of the thermal conductivity and the linear expansion coefficient, which is less sensitive to temperature than the optical distance change of the sample, is detected as the amount of thermal expansion displacement, the accuracy of the detected temperature change is ± 10 ° C. It is not so expensive and it is considered difficult to identify an abnormal part of a semiconductor device.

  The present invention has been made in view of the above-described problems, has a high spatial resolution, can reduce the time required for inspection, and can identify an abnormal portion of a semiconductor device with a simple configuration. An object is to provide an apparatus.

  In order to solve the above-described problems, a semiconductor inspection apparatus according to the present invention is a semiconductor inspection apparatus for specifying an abnormality occurrence location of a device under test having a substrate, and applies a stress voltage to a terminal electrode of the device under inspection. A stress applying means, a light source that generates light having a wavelength that passes through the substrate, an interference optical system that irradiates the substrate with light provided from the light source, and generates an interference image related to the light transmitted through the substrate, and an interference image. An imaging unit that captures an image and generates imaging data, and an arithmetic unit that calculates information for specifying a heat generation location of the device to be inspected as an abnormality occurrence location based on the imaging data. In this semiconductor inspection apparatus, the time waveform of the stress voltage is a repetitive waveform of a constant period, and the time waveform is a time waveform in which the time change of the optical distance inside the substrate due to heat generation of the device under test is sinusoidal. To do.

  The semiconductor inspection apparatus may be characterized in that the calculation means calculates the distribution of the phase delay of the light transmitted through the substrate included in the interference image as information for specifying the heat generation location of the device to be inspected.

  The semiconductor inspection apparatus may be characterized in that the time waveform of the stress voltage is sinusoidal.

  The semiconductor inspection apparatus may be characterized in that the time waveform of the stress voltage is a waveform in which a harmonic is superimposed on a fundamental wave having a constant period. In this case, the time waveform of the stress voltage may be a rectangular wave repeated at a constant period.

  Further, the semiconductor inspection apparatus may be characterized in that the terminal electrode of the device under test is a power supply terminal. In this case, the stress applying means may input a signal during normal operation to the signal terminal of the device under test.

  The semiconductor inspection apparatus may be characterized in that the terminal electrode of the device under test is a signal terminal. In this case, the stress applying means may supply a power supply voltage during normal operation to the power supply terminal of the device under test.

  The semiconductor inspection apparatus further includes a mechanism for performing imaging a plurality of times while moving the visual field, and the computing means performs computation by connecting a plurality of imaging data obtained by the imaging a plurality of times. This may be a feature.

  According to the present invention, it is possible to realize a semiconductor inspection apparatus that has a high spatial resolution, can reduce the time required for inspection, and can identify an abnormal portion of a semiconductor device with a simple configuration.

It is a figure showing composition of semiconductor inspection device 1A concerning a 1st embodiment of the present invention. It is sectional drawing which expands and shows the structure of the to-be-inspected device (DUT) 17 vicinity of 1 A of semiconductor inspection apparatuses. 4 is a diagram for explaining the principle when the semiconductor inspection apparatus 1A detects a minute heat generation point of the DUT 17. FIG. 2 is a diagram showing an interferometer including a beam splitter BS, a mirror M, and a camera C. FIG. It is an example of the imaging data in the camera C of FIG. It is a thermal frequency response curve just under the exothermic point when the silicon thickness d is 400 [μm]. Reference signal SP1 (FIG. 7A), trigger signal of IR camera 19 (FIG. 7B), trigger signal of stress applying device 22 (FIG. 7C), and thermal expansion waveform of silicon substrate 17a (FIG. 7). 7 (d)) is a timing chart showing the relationship. It is a diagram showing an example of the distribution of the Fourier coefficients a ₁ of the fundamental wave shows the calculation result of equation (7). It is a diagram showing an example of the distribution of the Fourier coefficients b ₁ of the fundamental wave shows the calculation result of equation (8). (A) is a diagram showing an example of the distribution of the Fourier coefficients a _1, b ₁ thermal phase Φ calculated from, shows the calculation result of Equation (9). (B) It is the figure which expanded a part of (a). FIG. 11 is a diagram illustrating an example of a distribution of thermal amplitude A obtained by Expression (14) in the examples illustrated in FIGS. 8, 9, and 10. It is a block diagram which shows the structural example of the semiconductor inspection apparatus 100 using the conventional one point measurement method (optical heterodyne interferometry) and a phase shift method. It is a block diagram which shows simply the structure of 1 A of semiconductor inspection apparatuses. It is a figure which shows the structure of the semiconductor inspection apparatus 1B which concerns on 2nd Embodiment of this invention. It is a figure which shows the structure of 1C of semiconductor inspection apparatuses which concern on 3rd Embodiment of this invention.

  Embodiments of a semiconductor inspection apparatus according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a semiconductor inspection apparatus 1A according to the first embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing the structure near the DUT 17 of the semiconductor inspection apparatus 1A. The semiconductor inspection apparatus 1A according to the present embodiment is an apparatus for identifying an abnormality occurrence location of the DUT 17 by detecting a minute heat generation location of the DUT 17 to be inspected.

  As shown in FIG. 2, the DUT 17 includes a silicon substrate 17a, a circuit layer 17b provided on the lower surface of the silicon substrate 17a, and a resin mold 17c that covers the silicon substrate 17a and the circuit layer 17b. Originally, the silicon substrate 17a and the circuit layer 17b are completely covered with the resin mold 17c, but in this DUT 17, a part of the resin mold 17c is removed so that the upper surface of the silicon substrate 17a is exposed for inspection. . The circuit layer 17b is formed with a semiconductor circuit and gives a temperature change to the silicon substrate 17a.

Here, FIG. 3 is a diagram for explaining the principle when the semiconductor inspection apparatus 1 </ b> A detects a minute heat generation location of the DUT 17. As shown in FIG. 3A, the optical thickness of the silicon substrate 17a of the DUT 17 is expressed as nL using the substrate thickness as L and the refractive index n. Note that the refractive index n of silicon is 3.5. When the temperature of the silicon substrate 17a rises by T [K], the optical thickness of the silicon substrate 17a changes to (nL + ΔnTL + αLTn) as shown in FIG. 3B. Δn is a refractive index change coefficient with respect to temperature change, and in the case of silicon, it is 5 × 10 ⁻⁵ [K ⁻¹ ]. α is a linear expansion coefficient due to temperature change, and in the case of silicon, it is 3.5 × 10 ⁻⁶ [K ⁻¹ ].

  Therefore, when the DUT 17 is irradiated with light having a wavelength that passes through the silicon substrate 17a (for example, light having a wavelength of 1.3 [μm]), the reflected light from the heat generation point is caused by expansion of the silicon substrate 17a accompanying the heat generation or change in refractive index. Causes a phase lag with respect to the reflected light from a normal location or a state before a heat generation phenomenon occurs. Therefore, as shown in FIG. 4, when an interferometer including a beam splitter BS, a mirror M, and a camera C is configured and light La having a wavelength that passes through the silicon substrate 17a is incident on the interferometer, the interferometer is caused by this phase delay. Interference fringe changes can be observed. FIG. 5 shows an example of imaging data in the camera C, and it can be seen that the phase of the interference fringes is partially delayed from the original phase (line PH1 in the figure) (line PH2 in the figure). When the thickness of the silicon substrate 17a is 400 [μm], the amount of change in the optical thickness of the silicon substrate 17a per 1 [K] of temperature change is 75 [nm / K]. In the interferometer shown in FIG. 4 that measures the interference, the distance is 150 [nm / K] for the round-trip optical path. When the wavelength of light is 1.3 [μm], a phase delay of 1/9 of the bright-to-bright interval of the interference fringes, that is, 40 ° occurs.

  The semiconductor inspection apparatus 1A irradiates the DUT 17 with light having a wavelength that passes through the silicon substrate 17a, and measures the phase lag with high accuracy using an optical interference measurement technique. Detecting a change in refractive index, etc., and specifying a heat generation location.

  In order to accurately detect the heat generation point described above, the semiconductor inspection apparatus 1A according to the present embodiment is a Linnik interferometer in which an objective lens is disposed on both of two optical paths branched in the Michelson interferometer. The device configuration is based on the above. As shown in FIG. 1, the semiconductor inspection apparatus 1A includes a low coherence light source 11, lenses 12a and 12b, a beam splitter 13, an objective lens 14, a mirror 15, an objective lens 16, an IR camera 19, and a frame memory 20.

  The low-coherence light source 11 includes a so-called super luminescence diode (SLD), and includes light including a wavelength that passes through the silicon substrate 17a of the DUT 17, for example, a center wavelength of 1.3 [μm] and a wavelength width of 20 [nm. ] Is output. As the low-coherence light source 11, for example, a fiber output type manufactured by FiberLab, such as model number SLD-131-04 (center wavelength 1.3 [μm], wavelength half width 20 [nm], maximum power 4 [mW]) Can be used. The reason why the SLD is used as the light source is to suitably distinguish the reflected light from the upper surface of the silicon substrate 17a and the light reflected from the lower surface through the inside of the silicon substrate 17a by using the coherence distance. Because it can.

  The lenses 12a and 12b, the beam splitter 13, the objective lens 14, the mirror 15, and the objective lens 16 irradiate the silicon substrate 17a with the light beam L1 provided from the low-coherence light source 11, and the interference image related to the light transmitted through the silicon substrate 17a. An interference optical system for generating

  The lens 12 a is optically coupled to the low coherence light source 11 and collimates the light beam L <b> 1 emitted from the optical fiber output end of the low coherence light source 11. The lens 12b condenses the light beam L1 that has passed through the lens 12a. The beam splitter 13 is optically coupled to the low coherence light source 11 via lenses 12a and 12b, and the light beam L1 that has passed through the lenses 12a and 12b is converted into two light beams L2 (reference light) and L3 (sample light). Branch. The objective lens 14 is disposed between one reflecting surface of the beam splitter 13 and the mirror 15, and focuses one light beam L <b> 2 (reference light) branched from the beam splitter 13 on the surface of the mirror 15. The magnification of the objective lens 14 is, for example, 5 times. The mirror 15 reflects the light beam L2 (reference light) and returns it to the beam splitter 13 again.

  The objective lens 16 is disposed between the other reflecting surface of the beam splitter 13 and the DUT 17, and focuses the other light beam L3 (sample light) branched from the beam splitter 13 on the silicon substrate 17a of the DUT 17 and the circuit layer. Match with the interface with 17b. The magnification of the objective lens 16 is, for example, 5 times, and is equal to the magnification of the objective lens 14. The light beam L3 that reaches the DUT 17 passes through the silicon substrate 17a, is reflected at the interface between the silicon substrate 17a and the circuit layer 17b, returns to the beam splitter 13 again, and is combined with the return light of the light beam L2 to be an interference image. Configure.

  The IR camera 19 is an image pickup unit in the present embodiment, and includes an image pickup device having sensitivity in a wavelength region near 1.3 [μm] that is an output wavelength of the low coherence light source 11. The IR camera 19 is optically coupled to the beam splitter 13 via the lens 18, and images the combined light L4 obtained by combining the return light of the light beam L2 and the return light of the light beam L3. The lens 18 forms the combined light L4 (interference image) on the imaging device surface of the IR camera 19. That is, the lens 18 forms the pattern image of the circuit layer 17b included in the return light of the light beam L3 and the image of the mirror 15 included in the return light of the light beam L2 on the imaging element surface of the IR camera 19. As a result, an interference fringe of the combined light L4 (interference image) formed by the light beam L3 (sample light) reflected by the circuit layer 17b and the light beam L2 (reference light) reflected by the mirror 15 inevitably. The maximum contrast.

  The frame memory 20 stores imaging data of the combined light L4 (interference image) captured by the IR camera 19. The computing unit 21 is computing means in the present embodiment. The calculation unit 21 performs a predetermined analysis calculation based on the imaging data stored in the frame memory 20 and outputs information for specifying a heat generation point (that is, an abnormality occurrence point) of the DUT 17. The computing unit 21 is realized by an information processing apparatus configured to include a CPU and a memory, for example.

  The semiconductor inspection apparatus 1A further includes a stress applying device 22, a Peltier element 23, and a temperature control controller 24. The stress applying device 22 is a stress applying means for applying stress to the DUT 17, and specifically, by applying a predetermined stress voltage Vs to a terminal electrode (power supply terminal or signal terminal) of the DUT 17, A current is passed through the circuit layer 17b of the DUT 17. In addition, when applying the stress voltage Vs to the power supply terminal of DUT17, it is preferable that the stress application apparatus 22 inputs the signal at the time of normal operation to a signal terminal. When applying the stress voltage Vs to the signal terminal of the DUT 17, it is preferable that the stress applying device 22 inputs the power supply voltage during normal operation to the power supply terminal.

The stress voltage Vs is a repetitive waveform with a constant period, and has a time waveform that makes the time change of the optical distance inside the silicon substrate 17a due to heat generation of the DUT 17 a smooth change of a sine wave. The stress voltage Vs has, for example, a voltage waveform that is a periodic sinusoidal time waveform. Alternatively, the stress voltage Vs may have a voltage waveform that is a waveform in which a harmonic is superimposed on a fundamental wave having a constant period, typically a periodic rectangular wave-like time waveform. In one embodiment, when the normal operating voltage of the DUT 17 is 5 [V], the voltage waveform of the stress voltage Vs is a waveform that repeats an ON voltage of 5 [V] and an OFF voltage of 0 [V] at a constant cycle. The duty ratio is 50%, for example. In the DUT 17, due to the application of the stress voltage Vs, heat proportional to the power P of the stress voltage Vs (= Vs ² / R, R is the resistance value of the abnormality occurrence location) is generated at the abnormality occurrence location such as disconnection. The silicon substrate 17a at the location expands.

  Further, the repetition frequency of the stress voltage Vs is determined as follows. When light passes through the silicon substrate 17a in the thickness direction, the optical distance changes due to thermal expansion of silicon. Further, the thermal expansion reaction of silicon occurs with a certain time constant with respect to heat generation from an abnormality occurrence site such as disconnection. That is, when the repetition period of the stress voltage Vs is relatively short with respect to the response speed of the thermal expansion reaction on the silicon substrate 17a side, the change in the optical distance in the silicon substrate 17a follows the change in the stress voltage Vs with a delay. At the same time, the thermal amplitude is also attenuated. Therefore, when the repetition period of the stress voltage Vs is appropriately determined, the change in the optical distance in the silicon substrate 17a becomes a time function (that is, a sine wave) including only the fundamental frequency. In the present embodiment, the repetition frequency of the stress voltage Vs is determined so that the change in the optical distance in the silicon substrate 17a becomes a sinusoidal time function.

  When the stress voltage Vs having a constant period is applied by the stress applying device 22, heat is accumulated in the entire DUT 17. The Peltier element 23 has the DUT 17 mounted on one surface (heat absorbing surface), and the other surface (heat radiating surface) is in contact with a heat radiating member (not shown). The Peltier element 23 absorbs heat accumulated in the DUT 17 from the heat absorbing surface and releases it from the heat radiating surface. The temperature controller 24 is an electric circuit that gives a drive current Id to the Peltier element 23, and generates the drive current Id so that the DUT 17 has a constant temperature. The Peltier element 23 and the temperature controller 24 realize the thermal equilibrium state of the DUT 17 in a short time. The set temperature of the DUT 17 is 25 ° C., for example.

Here, a method for determining the repetition frequency of the stress voltage Vs will be further described. The thermal conductivity of silicon constituting the silicon substrate 17a kappa, specific heat c and density [rho, the thermal resistance R _h and the heat capacity C _h of the silicon substrate 17a is calculated by the following equation (1) and (2).

Thus the thermal resistance _{R h} and the heat capacity _{C h} of the silicon substrate 17a obtained, the time constant of the expansion reaction of the silicon substrate 17a with respect to heat input τ when seeking _{(= C h · R h)} ,

It becomes. Here, d [cm] is the thickness of silicon. Therefore, the thermal cutoff frequency fc is given by the following equation (4).

  Here, d is also called a thermal diffusion length, and corresponds to the thickness of the silicon substrate 17a of the DUT 17. For example, when the silicon thickness d is 400 [μm], the thermal cutoff frequency fc is about 180 [Hz] according to the above equation (4). FIG. 6 is a thermal frequency response curve immediately below the heating point when the silicon thickness d is 400 [μm]. Here, a case where a rectangular wave stress voltage Vs is input to the DUT 17 is considered. The rectangular wave of the stress voltage Vs includes a harmonic component having a frequency (3Ω, 5Ω, 7Ω,...) That is an odd multiple of the basic frequency Ω in addition to the basic wave (frequency Ω). If the frequency Ω of the wave is set to 180 [Hz], the thermal amplitude of the third harmonic (3Ω = 540 [Hz]) component is attenuated to about one third of the thermal amplitude of the fundamental wave. Considering that the ratio of the 3rd harmonic contained in the rectangular wave of the stress voltage Vs is 1/3 of the fundamental wave, the magnitude of the thermal amplitude of the 3rd harmonic component is 9 minutes of the amplitude of the fundamental wave. 1 is about 11%. Thus, even when a waveform including harmonics (for example, a rectangular wave) is input as the stress voltage Vs, a component having higher frequency than the fundamental wave (harmonic component) due to the thermal frequency response in the silicon substrate 17a. Is greatly attenuated. As a result, the optical thickness of the silicon substrate 17a is modulated with a sinusoidal waveform having the same frequency as the fundamental frequency Ω.

Similarly, consider a case where the stress voltage Vs to be applied is input to the DUT 17 as a sine wave. When a sine wave of the stress voltage Vs is applied to the terminal electrode, heat is generated in the square due to thermal resistance. That is, when Vs is represented by the formula (4a),

The amount of heat generated by the heat source can be expressed by equation (4b). That is, in addition to the fundamental wave Ω, the frequency component of the second harmonic is diffused as heat in the DUT 17.

In this case, the ratio between the fundamental wave and the second harmonic is m / 4. For example, if the degree of modulation m is 0.25, the second harmonic is attenuated to 1/16 of the thermal amplitude of the fundamental wave. Thus, even when a sine wave is input as the stress voltage Vs, the second harmonic is greatly attenuated by the thermal frequency response in the silicon substrate 17a. As a result, the optical thickness of the silicon substrate 17a is modulated with a sinusoidal waveform having the same frequency as the fundamental frequency Ω.

  Strictly speaking, since the thickness d of the silicon substrate 17a depends on the internal structure of the DUT 17, the theoretical thermal cutoff frequency fc described above cannot be obtained. As a result of actual measurement by the present inventor, when the repetition frequency of the stress voltage Vs is set to several hertz to several tens of hertz, a favorable result is obtained in which the change in the optical distance in the silicon substrate 17a becomes a sinusoidal time function. It has been.

Table 1 below shows physical property values such as thermal conductivity κ, specific heat c, and density ρ of silicon.

Then, by applying the stress voltage Vs having the repetition frequency as described above to the DUT 17, the combined light L 4 (interference image) incident on the IR camera 19 becomes the interference intensity I (t expressed by the following equation (5). , X, y). In equation (5), Ir is the light intensity of the light beam L2 (reference light), Is is the light intensity of the light beam L3 (sample light), φ is the optical phase difference, m is the modulation factor, and Ω is the basic stress voltage Vs. The frequency, Φ, is the initial phase of the stress voltage Vs.

Further, the stress voltage Vs may have a voltage waveform such as a square root of a sine wave represented by the following formula (6). However, _{V 0} is an arbitrary coefficient.

Since the power energy of the stress voltage Vs (that is, the amount of generated heat) is proportional to the square of Vs, by applying the stress voltage Vs represented by the above equation (6) to the DUT 17, {1 + sin (Ωt )} In proportion to the heat generated. Therefore, an interference image as shown in Expression (5), that is, an interference image in which the optical distance is modulated in a sine wave shape can be suitably obtained.

  Note that the IR camera 19 preferably performs imaging at least twice within a period (2π / Ω) corresponding to the fundamental frequency Ω of the stress voltage Vs applied to the DUT 17.

  The semiconductor inspection apparatus 1A preferably further includes a feedback mechanism for reducing the phase noise of the interferometer. The semiconductor inspection apparatus 1A of this embodiment includes a light source 32, dichroic mirrors 33 and 34, a piezoelectric element 36, a modulator 37, a photodiode 38, a multiplier 39, and a feedback circuit 40 as such a feedback mechanism.

  The light source 32 outputs a light beam L5 having a wavelength different from that of the light beam L1. The wavelength of the light beam L5 is a wavelength that does not transmit through the silicon substrate 17a of the DUT 17, and is a wavelength that is reflected at the interface between the upper surface (exposed surface) of the silicon substrate 17a and air (for example, 633 [nm]). The light beam L5 output from the light source 32 is collimated by the lens 12c.

  The dichroic mirror 33 is an optical component for coaxially multiplexing the light beam L5 emitted from the light source 32 and the light beam L1 emitted from the low coherence light source 11. The dichroic mirror 33 of the present embodiment transmits light in the wavelength region including the light beam L1 and reflects light in the wavelength region including the light beam L5. The dichroic mirror 33 transmits the light beam L1 incident on one surface from the lens 12a toward the lens 12b, and transmits the light beam L5 incident on the other surface from the lens 12c to the lens 12b with the same optical axis as the light beam L1. Reflect toward you. The light beam L5 enters the beam splitter 13 together with the light beam L1, and is branched into two light beams L6 and L7 in the same manner as the light beam L1. The light beam L6 passes through the objective lens 14 together with the light beam L2 (reference light), reaches the mirror 15, and is reflected by the mirror 15. The light beam L7 passes through the objective lens 16 together with the light beam L3 (sample light), reaches the DUT 17, and is reflected by the upper surface (exposed surface) of the silicon substrate 17a.

  The reflected lights of these light beams L6 and L7 are combined at the beam splitter 13 and pass through the lens 18 as combined light L8. Here, a dichroic mirror 34 is provided between the lens 18 and the IR camera 19. The dichroic mirror 34 is an optical component for separating the combined light L8 having a wavelength different from that of the combined light L4 from the combined light L4. The dichroic mirror 34 of the present embodiment transmits light in the wavelength region including the combined light L4 and reflects light in the wavelength region including the combined light L8. The dichroic mirror 34 transmits the combined light L4 incident on one surface from the lens 18 toward the IR camera 19, and optically couples the combined light L8 incident on the one surface from the lens 18 to the one surface. Reflected toward the light receiving surface of the photodiode 38.

  In the photodiode 38, an electric signal S1 corresponding to the light intensity of the combined light L8 is generated. The electrical signal S1 is sent from the photodiode 38 to the multiplier 39. Further, the multiplier 39 further receives a sinusoidal electric signal (frequency ω) S 2 output from the modulator 37. The multiplier 39 provides an electric signal S3 obtained by multiplying the electric signals S1 and S2 to the feedback circuit 40.

  The feedback circuit 40 is a circuit for driving the piezoelectric element 36 fixed to the mirror 15. The feedback circuit 40 determines the distance Ls between the beam splitter 13 and the upper surface (exposed surface) of the silicon substrate 17a based on the electric signal S3 provided from the multiplier 39 and the electric signal S2 provided from the modulator 37. The piezoelectric element 36 is driven so that the difference (Ls−Lr) between the beam splitter 13 and the mirror 15 from the distance Lr is kept constant.

  Note that the feedback system for reducing the phase noise of the interferometer is not limited to the above-described one, and various other systems can be applied.

  Next, the relationship between the imaging timing in the IR camera 19 and the stress voltage Vs will be described. The semiconductor inspection apparatus 1A of the present embodiment further includes a reference signal generator 54 and a frequency divider 55 in order to appropriately adjust the imaging timing in the IR camera 19 and the phase of the stress voltage Vs.

  The reference signal generator 54 is a device that generates a reference signal SP1 that is a periodic pulse signal. The reference signal SP1 is provided to the IR camera 19 as a reference of a trigger signal indicating the photographing timing of the IR camera 19, and is also provided to the frequency divider 55. The frequency divider 55 divides the reference signal SP1 by at least two. The frequency-divided signal SP2 is provided from the frequency divider 55 to the stress applying device 22. The stress applying device 22 generates the stress voltage Vs with the frequency of the signal SP2 as the fundamental frequency Ω.

  FIGS. 7A to 7D show the reference signal SP1 (FIG. 7A), the trigger signal of the IR camera 19 (FIG. 7B), the trigger signal of the stress applying device 22 (ie, the signal SP2, FIG. 7C is a timing chart showing the relationship between the thermal expansion waveform (FIG. 7D) of the silicon substrate 17a. The trigger signal of the IR camera 19 indicates both the exposure timing and the exposure time of the IR camera 19. The exposure time of the IR camera 19 is preferably set to a time that does not impair the modulation of the combined light L4 (interference image).

  Imaging data photographed and generated by the IR camera 19 at the timing indicated by the reference signal SP1 is stored in the frame memory 20. The computing unit 21 takes out this imaging data, analyzes it by the method described below, and determines the phase lag (hereinafter referred to as the thermal phase) of the thermal expansion waveform and the amplitude of the thermal expansion waveform as information for identifying the location where the abnormality has occurred. (Hereinafter referred to as thermal amplitude) is calculated.

In the calculation unit 21, the interference light intensity I (t, x, y) shown in the above equation (5) is obtained as time series data for each pixel of the IR camera 19. The computing unit 21 performs Fourier analysis shown in the following equations (7) and (8) on the time series data of each pixel, thereby obtaining Fourier coefficients a ₁ and b ₁ for the fundamental wave (frequency Ω). calculate. The symbol A represents 2√ (IsIr) in the formula (5). J ₁ (m) is a first-order first-order Bessel function with respect to the modulation degree m.

Then, the arithmetic unit 21, the thermal phase Φ in each pixel, obtained by equation (9) below using the Fourier coefficients a ₁ and b ₁ of the fundamental wave.

FIG. 8 is a diagram showing an example of the distribution of the Fourier coefficient a ₁ of the fundamental wave, and shows the calculation result of the above equation (7). FIG. 9 is a diagram showing an example of the distribution of the Fourier coefficient b ₁ of the fundamental wave, and shows the calculation result of the above equation (8). FIG. 10A is an example of the distribution of the thermal phase Φ calculated from these Fourier coefficients a ₁ and b _1. FIG. 10B is an enlarged view of a part of FIG. It is. FIG. 10A and FIG. 10B show the calculation result of the above equation (9). 8, 9, and 10, the vertical axis and the horizontal axis indicate the pixel numbers in the vertical direction and the horizontal direction, respectively, and the actual size of the entire field of view is 3 [mm] × 2.5 [mm]. It is. In FIG. 10, the unit of the thermal phase Φ is radians.

  In the embodiments shown in FIGS. 8, 9, and 10, the ON voltage 5 [V] and the OFF voltage 0 [] are applied to the power supply voltage terminal of the DUT 17 whose silicon substrate 17a has a thickness of 400 [μm] as the stress voltage Vs. V], a rectangular wave with a duty ratio of 50% was applied. In addition, objective lenses 14 and 16 having a magnification of 5 times were used.

  Referring to FIG. 10A, a region having a relatively small thermal phase Φ exists in the upper right region from the center of the image. That is, it shows that heat is generated in this region, and this region can be specified as an abnormality occurrence location in the DUT 17. FIG. 10B shows this area in an enlarged manner, and the display range of the thermal phase Φ is narrowed to increase the contrast. The calculation unit 21 calculates and outputs such distribution data or distribution image of the thermal phase Φ as information for specifying the heat generation location of the DUT 17.

The thermal phase Φ can be converted into time by the following relational expression (10).

Further, if the number of samplings (that is, the number of times of imaging by the IR camera 19) is 4 or more within one cycle (2π / Ω), Fourier coefficients a ₂ and b ₂ corresponding to the second harmonic are expressed by the equations (11) and ( 12).

The thermal phase Φ in each pixel of the imaging data is expressed by the following equation (13) using the Fourier coefficients a ₂ and b ₂ of the second harmonic obtained by equations (11) and (12). .

The calculation unit 21 obtains the thermal amplitude A in each pixel by the following formula (14) based on the Fourier coefficients a ₁ and b ₁ of the fundamental wave and the Fourier coefficients a ₂ and b ₂ of the second harmonic wave.

Here, J ₁ and J ₂ in the equation (14) are first-type Bessel functions for the modulation degree m. In practice, since J ₂ is about one-tenth of J _1, when S / N in the second harmonic wave is low, the same measurements by shifting the phase of light 90 degrees, with zero phase difference Using the Fourier coefficients a ₁ (0), b ₁ (0) of the fundamental wave and the Fourier coefficients a ₁ (π / 2), b ₂ (π / 2) of the fundamental wave at a phase difference of 90 °. The phase Φ may be obtained.

  FIG. 11 is a diagram showing an example of the distribution of the thermal amplitude A obtained by the equation (14) in the embodiments shown in FIGS. 8, 9, and 10. In FIG. 11, the vertical axis and the horizontal axis indicate the pixel numbers in the vertical direction and the horizontal direction, respectively, and the actual size of the entire visual field is 3 [mm] × 2.5 [mm]. In FIG. 11, the unit of the thermal amplitude A is an arbitrary unit. In FIG. 11, the method in the case where the S / N at the second harmonic as described in paragraph [0067] is low is not used.

  Referring to FIG. 11, it can be seen that the thermal amplitude A becomes smaller as the pixel is farther from the heat generation point (point P in the figure). This is due to the thermal frequency characteristics of silicon shown in FIG. Therefore, a location where the thermal amplitude A is large can be identified as a location where an abnormality has occurred in the DUT 17. In this example, the abnormality occurrence location specified by the image of the thermal amplitude A shown in FIG. 11 coincides with the abnormality occurrence location specified by the image of the thermal phase Φ shown in FIG.

In addition, when S / N is sufficiently secured, as indicated by the equation (5), since many harmonic components are included, the thermal phase in each pixel of the imaging data with respect to the harmonic frequencies mΩ and nΩ. Φ and thermal amplitude A are also expressed by the following equations (15) and (16). However, in formulas (15) and (16), i and j are integers.


Further, the ratio (J _j / J _i ) of the Bessel functions of the orders i and j is calculated by the following equation (17).

  The operational effects of the semiconductor inspection apparatus 1A according to the present embodiment described above will be described.

  As described above, when the DUT is irradiated with light having a wavelength that passes through the substrate material (for example, silicon), the reflected light from the abnormality occurrence point is normal due to the expansion of the substrate and the change in refractive index caused by the heat generation at the abnormality occurrence point. A phase delay φ occurs with respect to the reflected light from the location. By measuring this phase delay φ with high accuracy using an optical interference measurement technique, it is possible not only to identify a heat generation location (abnormality occurrence location) but also to observe the phenomenon in real time. However, when an abnormality occurrence location of several micrometers is specified from an area of several hundred millimeters square of the DUT (about 6 digits drop in terms of area), it is not always necessary to observe a phenomenon related to the occurrence of the abnormality in real time.

  Therefore, in the semiconductor inspection apparatus 1A of the present embodiment, the stress voltage Vs having a constant period is applied so that the change in the optical distance inside the silicon substrate 17a due to the heat generated by the DUT 17 becomes sinusoidal, and the silicon substrate 17a is transmitted. By observing the intensity of the interference light accompanying the change in the phase of the detected light and detecting the phase lag and attenuation of the change in the optical distance inside the silicon substrate 17a, the location where the abnormality occurs in the DUT 17 is specified. Thereby, compared with the conventional thermal lock-in measuring method, spatial resolution can be improved.

More specifically, in the conventional thermal lock-in measurement method, a stress voltage having a time waveform such as a rectangular wave is applied to the DUT, and the radiant heat accompanying the heat generation from the location where the abnormality has occurred is imaged with an InSb camera. At that time, photographing is performed at a frequency at least twice the frequency of the stress voltage. Thereafter, Fourier analysis is performed on each pixel of the imaging data acquired as time series data, and a heat generation location (abnormality occurrence location) is specified from the amplitude and phase characteristics of the radiant heat. That is, in the thermal lock-in measurement method, measurement is performed according to the following procedure.
(1) A stress voltage having a constant frequency is applied to the DUT.
(2) Heat generation changes according to the modulation frequency of the stress voltage.
(3) Continuous imaging is performed at a sampling frequency higher than the modulation frequency of the stress voltage.
(4) Acquire amplitude and phase components based on the imaging data.

  However, it is difficult to apply such a procedure of the thermal lock-in measurement method to the interference image (the combined light L4 shown in FIG. 1) due to the light transmitted through the substrate. This is because the light intensity of the interference image and the change in phase of transmitted light due to heat generation of the DUT are non-linear with each other. For this reason, various methods for extracting the phase difference from the light intensity of the interference image (referred to as phase demodulation) have been studied in consideration of the fact that the light intensity and the phase difference of the interference image are nonlinear with each other.

For example, as a method for measuring a local site (one point), there is an optical heterodyne method. In principle, in the optical heterodyne method, the sum (φ + φ _m ) of the phase φ of the light and the phase φ _m of the modulated wave for modulating the light is obtained. In such one-point measurement, the time change of the optical phase φ in the local region is measured with time 0 as a reference, that is, (φ ₀ + φ _m ) as the initial phase φ ₀ . Therefore, it is not necessary to consider the initial phase φ ₀ at time 0 at all. Although this initial phase φ ₀ depends on the surface accuracy (flatness) of the DUT upper surface, in many cases, the DUT upper surface has irregularities on the order of nanometers, so the initial phase φ ₀ is in the plane of the DUT. Not uniform.

What is required of the semiconductor inspection apparatus is to specify the location where an abnormality has occurred in the semiconductor device, and therefore the relationship with other normal points is important. That is, the non-uniform initial phase φ ₀ within the plane of the DUT means that there is an offset at each point. In a state including such an offset, it is difficult to specify a heat generation location (abnormality occurrence location) by comparison with other normal points. For this reason, in the method based on one-point measurement such as the optical heterodyne method, it is necessary to measure the distribution of the initial phase φ ₀ in advance using some means in order to accurately identify the abnormality occurrence location. Therefore, it is difficult to apply the one-point measurement technique to measurement in the plane of the DUT (that is, two-dimensional) to specify the location where an abnormality has occurred in the semiconductor device.

  As a method for demodulating the optical phase φ from the optical interference image obtained in two dimensions, there are a Fourier transform method and a phase shift method. If the optical phase φ (t, x, y) is obtained from the two-dimensional interference image using these methods, and the procedure similar to the thermal lock-in measurement method is used for the obtained optical phase φ (t, x, y), The thermal phase Φ and the thermal amplitude A can be calculated. This is because the optical phase φ and the thermal expansion are in a linear relationship with each other. However, in the Fourier transform method, a carrier signal is generated by creating a large number of spatial fringes in an interference image. Therefore, when the Fourier transform method is used, for example, the feedback mechanism (the light source 32, the dichroic mirrors 33 and 34, the piezoelectric element 36, the modulator 37, the photodiode 38, the multiplier 39, and the feedback circuit 40) of the present embodiment. It is difficult to provide a simple mechanism, and it is difficult to remove noise from the interferometer. Alternatively, if there is a location in the observation field where it is known that there is no thermal expansion, there is a method of canceling phase noise using it as a reference point. However, when measuring a sample with an unknown heat generation location, provide that reference point. It is difficult. Further, in the phase shift method, it is possible to provide the feedback mechanism of the present embodiment, but since at least three interference images having different optical phases φ and known optical phases φ are required, There is a problem that the measurement time becomes long. In addition, since it is necessary to intermittently control the reference mirror on the nanometer order, there is a problem that the apparatus configuration becomes complicated.

  On the other hand, in the semiconductor inspection apparatus 1A of the present embodiment, the optical phase φ is not demodulated based on the optical interference image, but the temporal change in the optical distance inside the silicon substrate 17a due to the heat generated by the DUT 17 is sinusoidal. By applying the stress voltage Vs having a constant period in such a manner, the thermal phase Φ and the thermal amplitude A can be directly obtained from the optical interference image (the combined light L4). Therefore, as compared with the conventional apparatus using the Fourier transform method, it is possible to remove the noise of the interferometer by providing a feedback mechanism, and it is possible to specify the abnormality occurrence location more accurately. That is, since the semiconductor inspection apparatus 1A does not use the Fourier transform method, the light beam L5 from the light source 32 is guided on the optical path coaxial with the light beam L1 from the low-coherence light source 11 to cancel the phase noise in the interferometer. It is easy to introduce the Fordback mechanism.

  Further, according to the semiconductor inspection apparatus 1A, the measurement time can be shortened as compared with the conventional apparatus using the phase shift method (for example, a time of one third or less compared with the case of using the π / 2 phase shift method). In addition, a mechanism for modulating the reference mirror is unnecessary, and the apparatus configuration can be simplified.

  Further, according to the semiconductor inspection apparatus 1A of the present embodiment, the state of attenuation of the thermal amplitude A due to thermal diffusion and the delay of the thermal phase Φ can be observed without quantifying the optical phase φ from the optical interference image (the combined light L4). Since it can be obtained as quantitative information, the mechanism can be simplified. The attenuation amount of the thermal amplitude represents a temperature difference (° C.), and the thermal phase Φ represents a time delay of heat conduction.

  In the present embodiment, an example in which the heat generation location of the DUT 17 is measured two-dimensionally is shown, but the configuration of the semiconductor inspection apparatus 1A can also be applied to one-point measurement.

  A difference between the configuration of the semiconductor inspection apparatus 1A of the present embodiment and the configuration of the semiconductor inspection apparatus using the conventional one-point measurement or phase shift method will be illustrated and described. FIG. 12 is a block diagram showing a configuration example of a semiconductor inspection apparatus 100 using a conventional one-point measurement or phase shift method. FIG. 13 is a block diagram schematically showing the configuration of the semiconductor inspection apparatus 1A of the present embodiment. As shown in FIG. 12, in the conventional semiconductor inspection apparatus 100, the signal generator 101 controls the modulator 102 to modulate the reference light LR, while applying a stress voltage to the DUT 103 from the stress applying apparatus 104. Then, the sample light LS transmitted through the DUT 103 and the reference light LR are combined to form an interference image, and the interference image is captured by the camera 105. Thereafter, synchronous detection is performed, and the optical phase and the optical amplitude are demodulated by one-point measurement or a phase shift method, and then the thermal phase Φ and the thermal amplitude A are calculated based on the optical phase and the optical amplitude.

  On the other hand, as shown in FIG. 13, in the semiconductor inspection apparatus 1 </ b> A of the present embodiment, the thermal phase Φ and the thermal amplitude A are calculated directly from the imaging data (interference image) acquired by the camera 19. The method for directly obtaining the thermal phase Φ and the thermal amplitude A is described in Non-Patent Document 1 and Patent Document 1 described above, but Non-Patent Document 1 and Patent Document 1 describe one-point measurement. It cannot be simply expanded to two-dimensional measurement.

(Second Embodiment)
FIG. 14 is a diagram showing a configuration of a semiconductor inspection apparatus 1B according to the second embodiment of the present invention. Similar to the semiconductor inspection apparatus 1A of the first embodiment described above, the semiconductor inspection apparatus 1B irradiates the DUT 17 with light having a wavelength that passes through the silicon substrate 17a (see FIG. 2), and this phase delay is measured by an optical interference measurement technique. Is used to detect the expansion of the silicon substrate 17a due to heat generation, a change in refractive index, and the like, and identify the heat generation location.

  The semiconductor inspection apparatus 1B of the present embodiment has an apparatus configuration based on a coaxial optical path type interferometer (Mirau interferometer) in order to eliminate the need for phase stabilization in the interferometer. As shown in FIG. 14, the semiconductor inspection apparatus 1B includes a halogen light source 25, a filter 26, a lens 27, a half mirror 28, and an objective lens 29. These constitute the interference optical system in the present embodiment for generating an interference image related to the light transmitted through the silicon substrate 17a. Similarly to the first embodiment, the semiconductor inspection apparatus 1B includes a lens 18, an IR camera 19, a frame memory 20, a calculation unit 21, a stress application device 22, a Peltier element 23, a temperature controller 24, and a reference signal generator 54. , And the frequency divider 55, the configuration and function (action) thereof are the same as those of the first embodiment, and thus detailed description thereof is omitted.

  The broadband light output from the halogen light source 25 passes through the filter 26. At that time, only the light beam L 11 including a wavelength that transmits the silicon substrate 17 a of the DUT 17 passes through the filter 26. The light beam L11 realizes so-called Keller illumination on the sample surface by the lens 27. Thereafter, the light beam L11 is reflected by the half mirror 28. The objective lens 29 is a so-called Mirau-type objective lens, and the light beam L11 passes through the objective lens 29 and reaches the DUT 17. The light beam L11 that has reached the DUT 17 passes through the silicon substrate 17a, is reflected at the interface between the silicon substrate 17a and the circuit layer 17b, and then returns to the objective lens 29 again. Then, an interference image is generated in the objective lens 29, and the light beam L12 including the interference image passes through the half mirror 28 and the lens 18 and enters the IR camera 19.

  The semiconductor inspection apparatus according to the present invention may have an optical system like the semiconductor inspection apparatus 1B, and can exhibit the same effects as the semiconductor inspection apparatus 1A of the first embodiment. That is, according to the semiconductor inspection apparatus 1B, by using a Mirau-type interference microscope with less phase noise, a mechanism for modulating the reference mirror becomes unnecessary, and the apparatus configuration can be simplified.

  In addition, according to the semiconductor inspection apparatus 1B, the attenuation of the thermal amplitude A due to thermal diffusion and the state of the thermal phase Φ can be obtained as quantitative information without quantifying the optical phase φ from the optical interference image. Can be simplified.

(Third embodiment)
FIG. 15 is a diagram showing a configuration of a semiconductor inspection apparatus 1C according to the third embodiment of the present invention. Similar to the semiconductor inspection apparatus 1A of the first embodiment described above, the semiconductor inspection apparatus 1C irradiates the DUT 17 with light having a wavelength that passes through the silicon substrate 17a (see FIG. 2), and this phase delay is measured by an optical interference measurement technique. Is used to detect the expansion of the silicon substrate 17a due to heat generation, a change in refractive index, and the like, and identify the heat generation location.

  In the semiconductor inspection apparatus 1C of the present embodiment, the reflected light from the upper surface (light incident surface) of the silicon substrate 17a and the reflected light from the lower surface (interface with the circuit layer 17b) interfere with each other, so An interferometer having an optical path is realized.

  Specifically, as illustrated in FIG. 15, the semiconductor inspection apparatus 1 </ b> C includes an IR camera 19, a frame memory 20, and a calculation unit 21 having the same functions as those in the first embodiment. The semiconductor inspection apparatus 1C includes an illumination light source 61, a laser light source 62, beam splitters 63 to 65, an objective lens 66, a movable mirror 67, a mirror 68, optical path length correction members 69 and 70, a photodiode 71, an imaging lens 72, In addition, a filter 73 is provided. Among these optical members, the beam splitters 63 to 65, the objective lens 66, the movable mirror 67, the fixed mirror 68, the optical path length correction members 69 and 70, the photodiode 71, the imaging lens 72, and the filter 73 are the silicon substrate 17a. The interference optical system in the present embodiment for generating an interference image related to the light transmitted through is constructed.

  The light beam L21 output from the illumination light source 61 includes a wavelength that passes through the silicon substrate 17a of the DUT 17. The light beam L21 is reflected by the beam splitter 63, passes through the objective lens 66, and reaches the DUT 17. A part of the light beam L21 reaching the DUT 17 is reflected on the silicon substrate 17a (see FIG. 2), and the other part is reflected on the boundary surface between the silicon substrate 17a and the circuit layer 17b. Then, the light beam L 22 including these reflected lights passes through the objective lens 66 and the beam splitter 63 and reaches the beam splitter 64.

  In the beam splitter 64, the light beam L22 is branched into two light beams L23 and L24. One light beam L 23 is reflected by the movable mirror 67 and then passes through the optical path length correction member 69. The other light beam L 24 is reflected by the mirror 68 after passing through the optical path length correction member 70. These optical members (movable mirror 67, mirror 68, and optical path length correction members 69 and 70) adjust the optical path difference between the reflected light from the upper surface of the silicon substrate 17a and the reflected light from the lower surface to suitably interfere with each other. The optical delay circuit is configured. The light beams L23 and L24 are combined again by the beam splitter 65, pass through the imaging lens 72 and the filter 73, and enter the IR camera 19.

  The laser beam L25 emitted from the laser light source 62 is incident on the beam splitter 64. The laser beam L25 is branched into two laser beams L26 and L27 by the beam splitter 64. One laser beam L26 reaches the beam splitter 65 with the same optical axis as the light beam L23. The other laser beam L27 reaches the beam splitter 65 with the same optical axis as the light beam L24. The laser beams L26 and L27 are combined in the beam splitter 65, and the light intensity is detected by the photodiode 71. The detection signal in the photodiode 71 is fed back to the piezoelectric element 68a in order to cancel the phase noise in the optical delay circuit. The mirror 68 is driven by a piezoelectric element 68a fixed to the mirror 68 so that the difference in optical path length between the two lights L26 and L27 traveling from the beam splitter 64 to the beam splitter 65 is kept constant.

  Also in this embodiment, the configurations and functions of the IR camera 19, the frame memory 20, and the calculation unit 21 are the same as those in the first embodiment.

  The semiconductor inspection apparatus according to the present invention may have an optical system like the semiconductor inspection apparatus 1C, and can exhibit the same operational effects as the semiconductor inspection apparatus 1A of the first embodiment. That is, according to the semiconductor inspection apparatus 1C, the measurement time can be shortened, and a mechanism for modulating the reference mirror is not necessary, and the apparatus configuration can be simplified.

  Further, according to the semiconductor inspection apparatus 1C, the attenuation of the thermal amplitude A due to thermal diffusion and the state of the thermal phase Φ can be obtained as quantitative information without quantifying the optical phase φ from the optical interference image. Can be simplified.

  The semiconductor inspection apparatus according to the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, although the silicon substrate is exemplified as the substrate included in the DUT in the above embodiment, the semiconductor inspection apparatus according to the present invention is not limited to this, and can inspect the DUT including substrates made of various materials.

  The semiconductor inspection apparatus according to the present invention may further include a mechanism for performing imaging a plurality of times while moving the visual field. In this case, it is preferable that the calculation means (calculation unit 21) performs calculation by connecting a plurality of imaging data obtained by a plurality of imaging operations.

  DESCRIPTION OF SYMBOLS 1A, 1B, 1C ... Semiconductor inspection apparatus, 11 ... Low-coherence light source, 12a, 12b, 12c, 18, 27 ... Lens, 13 ... Beam splitter, 14, 16, 29, 66 ... Objective lens, 15 ... Mirror, 17 ... Device under test (DUT), 17a ... silicon substrate, 17b ... circuit layer, 17c ... resin mold, 19 ... camera, 20 ... frame memory, 21 ... calculation unit, 22 ... stress application device, 23 ... Peltier element, 24 ... temperature Control controller, 25 ... halogen light source, 26, 73 ... filter, 28 ... half mirror, 32 ... light source, 33, 34 ... dichroic mirror, 36 ... piezoelectric element, 37 ... modulator, 38, 71 ... photodiode, 39 ... multiplication 40 ... feedback circuit 54 ... reference signal generator 55 ... frequency divider 61 ... illumination light source 62 ... laser Sources, 63-65 ... beam splitter, 67 ... movable mirror, 68 ... fixed mirror, 68a ... piezoelectric elements, 69, 70 ... optical path length correction member, 72 ... imaging lens, Vs ... stress voltage.

Claims (10)

A semiconductor inspection apparatus for specifying an abnormality occurrence location of a device to be inspected having a substrate,
Stress applying means for applying a stress voltage to the terminal electrode of the device under test;
A light source that generates light of a wavelength that passes through the substrate;
An interference optical system that irradiates a substrate with light provided from a light source and generates an interference image related to the light transmitted through the substrate;
Imaging means for capturing an interference image and generating imaging data;
Computation means for computing information for identifying the heat generation location of the device under test as an abnormality occurrence location based on the imaging data,
A semiconductor inspection apparatus characterized in that the time waveform of the stress voltage is a repetitive waveform of a constant period, and is a time waveform in which the temporal change of the optical distance inside the substrate due to heat generation of the device under test is sinusoidal.   2. The semiconductor inspection according to claim 1, wherein the calculation unit calculates a distribution of phase delay of light transmitted through the substrate included in the interference image as information for specifying a heat generation location of the device to be inspected. apparatus.   3. The semiconductor inspection apparatus according to claim 1, wherein a time waveform of the stress voltage is a sine wave.   3. The semiconductor inspection apparatus according to claim 1, wherein the time waveform of the stress voltage is a waveform in which a harmonic is superimposed on a fundamental wave having a constant period.   The semiconductor inspection apparatus according to claim 4, wherein the time waveform of the stress voltage is a rectangular wave repeated at a constant period.   6. The semiconductor inspection apparatus according to claim 1, wherein the terminal electrode of the device to be inspected is a power supply terminal.   7. The semiconductor inspection apparatus according to claim 6, wherein the stress applying means inputs a signal during normal operation to a signal terminal of the device to be inspected.   6. The semiconductor inspection apparatus according to claim 1, wherein the terminal electrode of the device to be inspected is a signal terminal.   9. The semiconductor inspection apparatus according to claim 8, wherein the stress applying means supplies a power supply voltage during normal operation to a power supply terminal of the device to be inspected. It further comprises a mechanism for performing multiple imaging while moving the field of view,
The semiconductor inspection apparatus according to claim 1, wherein the calculation unit performs calculation by connecting a plurality of pieces of imaging data obtained by a plurality of times of imaging.