JP2008158338A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image liquid crystal display device capable of erasing an image in an early stage even when a power-OFF sequence can not be performed. <P>SOLUTION: If, for example, a battery or a power cable is removed unexpectedly, a power-OFF notice signal OEVE of a panel driving circuit 2 which has been at H gradually begins to fall at time t0, but the power-OFF notice signal OEVE quickly falls because of a resistance 161 which pulls it down (Fig. 9 (a)). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device that can erase an image at an early stage even if a power-off sequence cannot be executed.

In a liquid crystal display device, for example, when an off operation (power off) of a power switch is detected, an image is erased, and then a power off sequence in which power supply to a circuit is cut off may be executed (see Patent Document 1). reference).
Japanese Patent Laid-Open No. 2000-2866

  However, the liquid crystal display device may be used for a digital still camera, a digital video camera, or the like that is often handled by a user who is not familiar with the operation. If the power cable is disconnected, the power off sequence may not be executed.

  FIG. 10 is a diagram illustrating a state in which a power supply is unexpectedly turned off in a liquid crystal display device displaying normally white and grayscale.

  As shown in the figure, the image is gradually erased, but since it is normally white, the time to erase is longer for pixels closer to black.

  Also, depending on the liquid crystal display device, when so-called horizontal line inversion display is performed, an image cannot be erased early on a line with a negative pixel polarity with respect to a line with a positive pixel polarity, which is recognized as a horizontal stripe pattern. May end up.

  FIG. 11 is a waveform diagram according to an example of the liquid crystal display device when the power is unexpectedly turned off.

  Originally, the power supply voltage VDD is maintained at the power-on voltage until a predetermined time length elapses after the power is turned off, and the power-off notification signal OEVE is at a low voltage level (L) during that time. However, the power supply voltage VDD and the power supply OFF notification signal OEVE both start to decrease at time t0 when the power supply is unexpectedly cut off, so that the image cannot be erased in the power supply OFF sequence.

  Even if the image cannot be erased due to the power-off sequence, if the negative power supply voltage YVSS decreases, for example, early, the image may be erased early on the negative line. However, in practice, the power supply voltage YVSS does not drop early, so that the image cannot be erased early on the negative line.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an image liquid crystal display device capable of erasing an image at an early stage even if the power-off sequence cannot be executed.

  In order to solve the above-described problem, in the liquid crystal display device according to the first aspect of the present invention, a plurality of signal lines and a plurality of scanning lines intersect with each other, and the intersections are made conductive by driving the scanning lines at the intersections. An array substrate having a pixel transistor, a pixel electrode in which the potential of the signal line at the intersection is set by the conductive pixel transistor, a counter substrate having a counter electrode facing each pixel electrode through a liquid crystal layer, A power-off notification signal having a predetermined voltage level and a positive power supply voltage are supplied to the liquid crystal panel, and the power-off notification signal is supplied from the voltage level before the supply of the positive power supply voltage is stopped. A panel driving circuit for lowering the voltage level, and the liquid crystal panel has a voltage level lower than the voltage level when the power-off notification signal is lower than the voltage level. A power-off sequence of erasing the image using a source voltage is executed, and an afterimage countermeasure circuit having a resistor is provided, and the resistor pulls down the power-off notification signal to a circuit below the low voltage level It is characterized by being.

  In this liquid crystal display device, by pulling down the power-off notification signal to a circuit below a low voltage level, for example, when a battery or a power cable is unexpectedly pulled out in the panel drive circuit, the power-off notification signal is early due to the pulled-down resistance. The same sequence as the power-off sequence is executed. Therefore, the image can be erased early even if the power-off sequence cannot be executed.

  A liquid crystal display device according to a second aspect of the present invention includes a pixel transistor in which a plurality of signal lines and a plurality of scanning lines cross each other, and is made conductive by driving the scanning lines at the intersections. A liquid crystal panel comprising: an array substrate having a pixel electrode in which the potential of the signal line at the intersection is set; and a counter substrate provided with a counter electrode facing each pixel electrode through a liquid crystal layer, and the liquid crystal panel A panel drive that supplies a power-off notification signal having a predetermined voltage level and a positive and negative power supply voltage and sets the power-off notification signal to a voltage level lower than the voltage level before the supply of the positive power supply voltage is stopped. And the liquid crystal panel uses a power supply voltage before the supply stop, so that the power-off notification signal is set to a voltage level lower than the voltage level. A protection circuit having a rectifier provided to execute a power-off sequence of erasing an image and to be connected to the signal line so as to limit the potential of the signal line with the negative power supply voltage; and a resistor An afterimage countermeasure circuit is provided, and a negative voltage remaining on the pixel electrode when the power-off sequence cannot be executed is applied to a signal line, and the resistor is the rectifier element The negative power supply voltage is pulled up with respect to a circuit having a voltage level higher than a voltage level obtained by adding a threshold voltage necessary for conduction to the negative voltage.

  In this liquid crystal display device, the rectifier element is made conductive by pulling up a negative power supply voltage with respect to a circuit having a voltage level higher than a voltage level obtained by adding a threshold voltage necessary for conduction of the rectifier element to the negative voltage. As a result, an image at a pixel having a negative pixel polarity is erased early. Therefore, the image can be erased early even if the power-off sequence cannot be executed.

  According to the liquid crystal display device of the first aspect of the present invention, the power-off notification signal is pulled down to a circuit having a low voltage level or lower, so that the panel drive circuit pulls down the battery or the power cable when it is unexpectedly removed. The power-off notification signal is lowered early due to the resistance, and the same sequence as the power-off sequence is executed. Therefore, the image can be erased early even if the power-off sequence cannot be executed.

  According to the liquid crystal display device of the second aspect of the present invention, the negative power supply voltage is pulled up with respect to a circuit having a voltage level higher than the voltage level obtained by adding the threshold voltage necessary for the conduction of the rectifying element to the negative voltage. By doing so, the rectifying element becomes conductive, and as a result, an image at a pixel having a negative pixel polarity is quickly erased. Therefore, the image can be erased early even if the power-off sequence cannot be executed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the numerical value in description is an example and this invention is not limited to this numerical value.

  FIG. 1 is a configuration diagram of a liquid crystal display device according to the present embodiment.

  The liquid crystal display device includes a liquid crystal panel 1 and a panel drive circuit 2. Although not shown, the liquid crystal panel 1 includes a liquid crystal layer between an array substrate such as glass and a counter substrate.

  In the array substrate, a plurality of signal lines X1, X2,... And a plurality of scanning lines Y1, Y2,. At the intersection, a pixel transistor Q, which is an N-type MOSFET, and a pixel electrode P made of ITO (Indium Tin Oxide) are formed here. The source of the pixel transistor Q is a signal line, and the drain is a pixel electrode P. The gates are connected to the scanning lines, respectively. In the counter substrate, a single counter electrode Pcom is formed so as to face all of the crossing portions, and in each crossing portion, a liquid crystal capacitance Clc is configured by the counter electrode Pcom, the pixel electrode P, and the liquid crystal. In each intersection, a storage capacitor (not shown) for holding the potential of the pixel electrode P is configured.

  Thus, a pixel is formed at each intersection, and a display area A is formed by the pixel.

  The pixel transistor is formed by, for example, a p-Si (polysilicon) process. In the same process, the array substrate includes a precharge control circuit 11, a precharge voltage common voltage selection circuit 12, a precharge circuit 13, and a scanning line drive. A circuit 14, a signal line driving circuit 15, and an afterimage countermeasure circuit 16 are formed.

  The panel drive circuit 2 supplies the liquid crystal panel 1 with a power supply voltage VDD (8.5 V) and a power supply voltage YVSS (−8.5 V) based on the power supply voltage VSS (0 V: ground). Note that the power supply voltage YVSS may be generated from the power supply voltage VDD in the liquid crystal panel 1.

  The panel drive circuit 2 supplies the liquid crystal panel 1 with clock signals XCK +, XCK-, YCK, start signals XST, YST, data signal Data, precharge signal PCG, power-off notification signal OEVE, common voltage Vcom (2.55 V), A precharge voltage Vpre (2.5 V) is supplied.

  FIG. 2A is a detailed diagram of the precharge control circuit 11.

  The precharge control circuit 11 generates a circuit 111 for generating signals PCG + and PCG− to the precharge circuit 13 from the precharge signal PCG and the power-off notification signal OEVE, and the signal OEVE to the precharge voltage common voltage selection circuit 12. Signal OEVEUU +, its inverted signal OEVEUU−, and a circuit 112 for generating a signal OEVEU to the scanning line driving circuit 14.

  The circuit 111 includes a level shifter (L / S) that boosts the precharge signal PCG and a logic circuit.

  The circuit 112 includes a level shifter (L / S) that boosts the power-off notification signal OEVE, a logic circuit, and a level shifter (L / S) that outputs the signals OEVEUU + and OEVEUU−.

  FIG. 2B is a diagram showing a sequence when these signals are powered off.

  The panel drive circuit 2 detects, for example, a power switch off operation (referred to as power off).

  As a result, the power-off notification signal OEVE, which was +3 V until the power is turned off (power on), becomes 0 V after the power is turned off.

  In the following description, not only the power-off notification signal OEVE but also the higher binary level is H and the lower one is L (0 V).

  The precharge signal PCG is H during the horizontal blanking period, and is L otherwise.

  The signal PCG + is H when the power-off notification signal OEVE is H and the precharge signal PCG is H or when the power-off notification signal OEVE is L, and is L otherwise. The signal PCG− is inverted with respect to the signal PCG +.

  The signals OEVEU and OEVEUU + are H when the power-off notification signal OEVE is H and L when the power-off notification signal OEVE is L. Although not shown, the signal OEVEUU− is inverted with respect to the signal OEVEUU +.

  FIG. 3 is a diagram illustrating a sequence when the power is turned off.

  The power supply voltage VDD, the common voltage Vcom, and the precharge voltage Vpre are maintained at the power-on voltage until a predetermined time length T has elapsed from the power-off, and then approach 0V.

  Each signal XCK +, YCK, Data, XST, YST stops when the power is turned off. Similarly, the signal XCK−, which is an inverted signal of the signal XCK +, is stopped when the power is turned off.

  The power-off notification signal OEVE is H until the power is turned off and then L.

  FIG. 4 is a detailed diagram of the precharge voltage common voltage selection circuit 12.

  In the precharge voltage common voltage selection circuit 12, when the signal OEVEUU + is H and the signal OEVEUU− is L, the analog switch 121 is turned on, and the signal Vpc to the precharge circuit 13 is set to the precharge voltage Vpre.

  In the precharge voltage common voltage selection circuit 12, on the other hand, when the signal OEVEUU + is L and the signal OEVEUU− is H, the analog switch 122 is turned on, and the signal Vpc to the precharge circuit 13 is set to the common voltage Vcom.

  FIG. 5A is a detailed diagram of the precharge circuit 13.

  In the precharge circuit 13, when the signal PCG + is H and the signal PCG- is L, all the analog switches 131 provided on the signal lines X1, X2,... Are turned on, and signals are sent to all the signal lines X1, X2,. Vpc is supplied.

  In the horizontal blanking period in which the signal PCG + is H and the signal PCG− is L, the pixel transistor Q is turned on, and the precharge voltage Vpre set to the signal Vpc at that time passes through the signal line and the pixel transistor Q. Applied to the pixel electrode P. By such precharging, the time until a desired pixel potential is obtained is shortened.

  A protection circuit 132 that protects the signal line driving circuit 15 is connected to each of the signal lines X1, X2,.

  FIG. 5B is a detailed diagram of the protection circuit 132.

  In the protection circuit 132, the N-type MOSFET 1321 and the P-type MOSFET 1322 are each configured to operate as a rectifying element.

  In the protection circuit 132, first, the power supply voltage YVSS is supplied to the short-circuited gate-drain of the N-type MOSFET 1321, and the source is connected to the signal line (X1 in the figure). As a result, the lower limit of the potential of the signal line is limited by the power supply voltage YVSS (−8.5 V), thereby protecting the signal line driving circuit 15.

  In the protection circuit 132, the power supply voltage VDD is supplied to the shorted gate-drain of the P-type MOSFET 1322, and the source is connected to the signal line (X1 in the figure). As a result, the upper limit of the potential of the signal line is limited by the power supply voltage VDD (8.5 V), thereby protecting the signal line driving circuit 15.

  FIG. 6A is a detailed diagram of the scanning line driving circuit 14.

  Each scanning line Y1, Y2, Y3,... Includes a shift register (S / R) and a logic circuit.

  FIG. 6B is a diagram illustrating a sequence during power-on in the scanning line driving circuit 14.

  In the scanning line driving circuit 14, when the power-on signal OEVEU is H and the start signal YST is input, the scanning lines Y1, Y2, Y3,... Are sequentially set to H in synchronization with the clock signal YCK. Become. In addition, the signal line driving circuit 15 when the power is turned on supplies a video signal based on the data signal Data to the signal line, thereby displaying an image.

  FIG. 6C is a diagram showing a sequence after the power is turned off.

  In the scanning line driving circuit 14, the signal OEVEU after power-off is L, and all the scanning lines Y1, Y2, Y3,. In addition, since the signal line driving circuit 15 after the power is turned off is set to the common voltage Vcom (2.55 V) on the signal line, no image is erased.

  FIG. 7 is a diagram illustrating the voltage range of the video signal supplied to each signal line by the signal line driving circuit 15 and the range of the pixel electrode voltage (pixel potential). As described above, the numerical value is an example.

  The voltage range of the video signal is 0.6 V to 4.5 V, and the voltage in this range is once applied to the pixel electrode P. The potential of the pixel electrode P is then applied by so-called capacitor coupling driving (CC driving). Is shifted.

  When the potential of the pixel electrode P (pixel potential) with respect to the common voltage Vcom (2.55 V) is made positive (the pixel polarity is made positive) after the shift, the range of the pixel potential is 2.55 V to 7.1 V. is there. In normally white, it is 2.55V (white)-7.1V (black).

  After shifting, when the potential of the pixel electrode P (pixel potential) with respect to the common voltage Vcom (2.55 V) is made negative (pixel polarity is made negative), the range of the pixel potential is −2 V to 2.55 V. . In normally white, it is -2V (black)-2.55V (white).

  FIG. 8A is a detailed diagram of an example of the afterimage countermeasure circuit 16.

  In the afterimage countermeasure circuit 16, the power-off notification signal OEVE is pulled down to the power supply voltage VSS (ground) by the resistor 161.

  FIG. 8B is a detailed diagram of an example of the afterimage countermeasure circuit 16.

  In the afterimage countermeasure circuit 16 according to another example, the power-off notification signal OEVE is pulled down to the power supply voltage YVSS by the resistor 162.

  FIG. 8C is a detailed diagram of an example of the afterimage countermeasure circuit 16.

  In the afterimage countermeasure circuit 16 according to another example, the power supply voltage YVSS is pulled up to the power supply voltage VDD by the resistor 163.

  When the circuit of FIG. 8A is employed, when the power supply is unexpectedly cut off in the panel drive circuit 2, the waveform diagram of FIG.

  In the panel drive circuit 2 at time t0, for example, when a battery or a power cable is unexpectedly removed, the power supply voltage VDD cannot maintain the voltage when the power is turned on, and therefore the power off sequence cannot be executed.

  However, since the power-off notification signal OEVE is pulled down by the resistor 161, the power-off notification signal OEVE after time t0 is lowered early, and the same sequence as the power-off sequence is executed. Therefore, an image can be erased early even if the power-off sequence cannot be executed.

  Here, since the voltage level when the power-off notification signal OEVE is L is 0 V, the power-off notification signal OEVE is pulled down to the power supply voltage VSS. However, the power-off notification signal OEVE may be lowered early. Therefore, if the power-off notification signal OEVE is pulled down with respect to a circuit below the voltage level when the power-off notification signal OEVE is L (for example, the power supply voltage YVSS), the same effect can be expected, and such a configuration is adopted. May be.

  When the circuit shown in FIG. 8B is employed, when the panel drive circuit 2 is unexpectedly powered off, the waveform diagram of FIG. 9B is obtained.

  In the panel drive circuit 2 at time t0, for example, when a battery or a power cable is unexpectedly removed, the power voltage YVSS (−8.5 V) is changed to a positive voltage by the resistor 162, and the power-off notification signal OEVE is changed to the positive voltage side. It gradually approaches 0V while showing the same value as.

  Even when the circuit of FIG. 8C is employed, the same waveform as in FIG. 9B is observed by the resistor 163.

  Here, the effect of the change in the power supply voltage YVSS as shown in FIGS. 9A and 9B will be described.

  In the example of FIG. 7, when all pixels are displayed in black with normally white, the pixel potential of a pixel having a positive pixel polarity is 7.1V, and the pixel potential of a pixel having a negative pixel polarity is −2V.

  In this state, when the power supply is unexpectedly cut off and the common voltage Vcom is changed from 2.55V to 0V, the pixel potential with a positive pixel polarity is approximately 4.5V, and the pixel potential with a negative pixel polarity is approximately -4. .5V.

  In addition, when the signal line driving circuit 15 opens the signal line and the scanning line driving circuit 14 operates for a while when the power is cut off, the signal line has a positive pixel potential of 4.5V, -4.5V, which is a pixel potential having a negative pixel polarity, is applied alternately. That is, the positive and negative voltages remaining on the pixel electrode P are applied to the signal line.

  After the power supply is unexpectedly cut off, the power supply VDD changes as shown in FIGS. 9A, 9B, and 11, so that the potential difference from 4.5 V applied to the signal line is relatively large. Therefore, in many cases, the P-type MOSFET 1322 becomes conductive, and an image at a pixel having a positive pixel polarity is erased.

  On the other hand, if the power supply voltage YVSS changes as shown in FIG. 11 after an unexpected power failure, the potential difference from −4.5 V applied to the signal line is relatively small. Therefore, in many cases, the N-type MOSFET 1321 does not conduct, and an image at a pixel having a negative pixel polarity cannot be erased early.

  Therefore, in the present embodiment, after the power supply is unexpectedly cut off, the power supply voltage YVSS is changed as shown in FIGS. 9A and 9B so that the potential difference from −4.5 V applied to the signal line is increased. It becomes larger than the case of FIG. As a result, the N-type MOSFET 1321 becomes conductive, and an image at a pixel having a negative pixel polarity is quickly erased. Therefore, the image can be erased early even if the power-off sequence cannot be executed.

  Here, considering a voltage level obtained by adding a threshold voltage necessary for conduction of the N-type MOSFET 1321 that is a rectifying element to −4.5 V (−3.5 V if the threshold voltage is 1 V), the power-off notification signal OEVE and the power source The voltage VDD has a voltage level higher than the voltage level. By pulling up the power supply voltage YVSS to a circuit having such a voltage level, the N-type MOSFET 1321 becomes conductive, and as a result, the pixel polarity is increased. Images with negative pixels can be erased early.

  Therefore, if the power supply voltage YVSS is pulled up with respect to another circuit having a voltage level obtained by adding the threshold voltage of the N-type MOSFET 1321 to −4.5 V, a similar effect can be expected. It may be adopted.

It is a block diagram of the liquid crystal display device which concerns on this Embodiment. FIG. 2A is a detailed diagram of the precharge control circuit 11, and FIG. 2B is a diagram showing a sequence when the power is turned off. It is a figure which shows the sequence at the time of power-off. 3 is a detailed diagram of a precharge voltage common voltage selection circuit 12. FIG. FIG. 5A is a detailed diagram of the precharge circuit 13 and FIG. 5B is a detailed diagram of the protection circuit 132 thereof. 6A is a detailed diagram of the scanning line driving circuit 14, FIG. 6B is a diagram showing a sequence during power-on, and FIG. 6C is a sequence after power-off. FIG. It is a figure which shows the voltage range of a video signal, and the range of pixel electric potential. 3 is a detailed diagram of an example of an afterimage countermeasure circuit 16. FIG. It is a wave form diagram when there is an unexpected power failure in the panel drive circuit. It is a figure which shows a mode when the power supply is unexpectedly cut off with the liquid crystal display device which is displaying the gray scale by normally white. It is a wave form diagram which concerns on an example at the time of the unexpected power failure in a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Panel drive circuit 11 Precharge control circuit 12 Precharge voltage common voltage selection circuit 13 Precharge circuit 14 Scan line drive circuit 15 Signal line drive circuit 16 Residual image countermeasure circuit 121,122, ..., 131 Analog switch 132 Protection circuit 161, 162, 163 Resistance 1321 N-type MOSFET
1322 P-type MOSFET
A Display area Clc Liquid crystal capacitance Data Data signal OEVE Power off notification signal P Pixel electrode PCG Precharge signal Pcom Counter electrode Q Pixel transistor VDD, VSS, YVSS Power supply voltage Vcom Common voltage Vpre Precharge voltage X1, X2, ... Signal line XST, YST start signal XCK +, XCK-, YCK clock signal Y1, Y2,... Scanning line

Claims (6)

A plurality of signal lines and a plurality of scanning lines intersect with each other, and pixel transistors that are made conductive by driving the scanning lines at the intersections at each intersection, and the potentials of the signal lines at the intersections are set by the conductive pixel transistors. A liquid crystal panel comprising: an array substrate having a pixel electrode; and a counter substrate having a counter electrode facing each pixel electrode through a liquid crystal layer;
A panel that supplies a power-off notification signal having a predetermined voltage level and a positive power supply voltage to the liquid crystal panel, and sets the power-off notification signal to a voltage level lower than the voltage level before the supply of the positive power supply voltage is stopped. A drive circuit,
The liquid crystal panel performs a power-off sequence of erasing the image using the power supply voltage before the supply is stopped when the power-off notification signal is set to a voltage level lower than the voltage level, and It has an afterimage countermeasure circuit with resistance,
The liquid crystal display device according to claim 1, wherein the resistor pulls down the power-off notification signal to a circuit below the low voltage level.   The liquid crystal display device according to claim 1, wherein the resistor pulls down the power-off notification signal with respect to the ground. The panel drive circuit supplies a negative power supply voltage to the liquid crystal panel,
The liquid crystal display device according to claim 1, wherein the resistor pulls down the power-off notification signal with respect to the negative power supply voltage. A plurality of signal lines and a plurality of scanning lines intersect with each other, and pixel transistors that are turned on by driving the scanning lines at the intersections are set at the respective intersections, and the potentials of the signal lines at the intersections are set by the turned-on pixel transistors. A liquid crystal panel comprising: an array substrate having a pixel electrode; and a counter substrate having a counter electrode facing each pixel electrode through a liquid crystal layer;
A power-off notification signal having a predetermined voltage level and positive and negative power supply voltages are supplied to the liquid crystal panel, and the power-off notification signal is set to a voltage level lower than the voltage level before the supply of the positive power supply voltage is stopped. A panel drive circuit that
The liquid crystal panel performs a power-off sequence of erasing the image using the power supply voltage before the supply is stopped when the power-off notification signal is set to a voltage level lower than the voltage level, and A protection circuit having a rectifying element connected to the signal line and configured to limit the potential of the signal line with the negative power supply voltage, and an afterimage countermeasure circuit having a resistor, and the power off sequence can be executed. The negative voltage remaining on the pixel electrode when not present is configured to be applied to the signal line,
The resistor pulls up the negative power supply voltage to a circuit having a voltage level higher than a voltage level obtained by adding a threshold voltage necessary for conduction of the rectifying element to the negative voltage. A liquid crystal display device.   The liquid crystal display device according to claim 4, wherein the resistor pulls up the negative power supply voltage with respect to the power-off notification signal.   The liquid crystal display device according to claim 4, wherein the resistor pulls up the negative power supply voltage with respect to the positive power supply voltage.

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