CN111341282B - Pixel circuit - Google Patents
Pixel circuit Download PDFInfo
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- CN111341282B CN111341282B CN202010311206.1A CN202010311206A CN111341282B CN 111341282 B CN111341282 B CN 111341282B CN 202010311206 A CN202010311206 A CN 202010311206A CN 111341282 B CN111341282 B CN 111341282B
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- type transistor
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- pixel circuit
- transistor
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- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 29
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
A pixel circuit comprises a data transistor, a first P-type transistor, a first N-type transistor, a liquid crystal capacitor, a second P-type transistor and a second N-type transistor. The data transistor is coupled to the first node and receives a data voltage and a gate signal. The first P-type transistor and the first N-type transistor are coupled in series between the first pulse signal and the second pulse signal and are commonly coupled to a first node and a second node. The liquid crystal capacitor is coupled between the second node and the common voltage signal. The second P-type transistor and the second N-type transistor are coupled in series between the first pulse signal and the second pulse signal and are commonly coupled to the first node and the second node.
Description
Technical Field
The present invention relates to a pixel circuit, and more particularly, to a liquid crystal pixel circuit.
Background
Memory In Pixel (MIP) technology is a high-level display technology, one of the main objectives of which is to reduce the power consumption of the panel, and the technical effect is similar to the bistable state of an electrophoretic display (EPD), that is, the display with very low or lowest power consumption can be achieved without changing the picture or with only a small amount of changes. However, in the MIP pixel, the energy consumption during voltage conversion is reduced by the memory unit in the pixel itself, and the liquid crystal is driven by polarity inversion, so that the pixel needs to be designed according to the driving requirement.
Disclosure of Invention
The present invention provides a pixel circuit which can maintain the voltage at both ends of the liquid crystal in a polarity inversion manner even without an inverter circuit, thereby maintaining the normal operation of the pixel circuit when data writing is not performed.
The pixel circuit comprises a data transistor, a first P-type transistor, a first N-type transistor, a liquid crystal capacitor, a second P-type transistor and a second N-type transistor. The data transistor has a first terminal for receiving a data voltage, a second terminal coupled to the first node, and a control terminal for receiving a gate signal. The first P-type transistor has a first terminal for receiving the first pulse signal, a second terminal coupled to the second node, and a control terminal coupled to the first node. The first N-type transistor has a first terminal coupled to the second node, a second terminal receiving the second pulse signal, and a control terminal coupled to the first node. The liquid crystal capacitor is coupled between the second node and the common voltage signal. The second P-type transistor has a first terminal for receiving the first pulse signal, a second terminal coupled to the first node, and a control terminal coupled to the second node. The second N-type transistor has a first terminal coupled to the first node, a second terminal receiving the second pulse signal, and a control terminal coupled to the second node.
In view of the above, the pixel circuit according to the embodiment of the invention alternately transmits the first pulse signal and the second pulse signal to the first node through the second P-type transistor and the second N-type transistor to maintain the voltage of the first node. Therefore, even if data is not written, the logic level of the first node is maintained, thereby maintaining the color displayed by the pixel circuit. Furthermore, when the pixel circuit is composed of the first node, the second node, the data transistor, the first P-type transistor, the first N-type transistor, the liquid crystal capacitor, the second P-type transistor and the second N-type transistor, the circuit area of the pixel circuit can be reduced, so that the pixel circuit can be applied to a display panel with higher pixel Per Inch (pixel Per Inch, PPI) unit area.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a circuit diagram of a pixel circuit according to an embodiment of the invention.
Fig. 2 is a schematic diagram of driving waveforms of a pixel circuit according to an embodiment of the invention.
Description of reference numerals:
100: pixel circuit
Clc: liquid crystal capacitor
D: first node
Data: data voltage
DP 1-DP 3: during the display period
And (3) Gate: grid signal
P: second node
TD: data transistor
TN 1: a first N-type transistor
TN 2: second N-type transistor
TP 1: a first P type transistor
TP 2: second P type transistor
Vb: first pulse signal
VCOM: common voltage signal
Vd, Vp: voltage of
Vw: second pulse signal
Detailed Description
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a circuit diagram of a pixel circuit according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, a pixel circuit 100 includes a first node D, a second node P, a data transistor TD, a first P-type transistor TP1, a first N-type transistor TN1, and a liquid crystal capacitor ClcA second P-type transistor TP2 and a second N-type transistor TN 2. The data transistor TD, the first P-type transistor TP1, the first N-type transistor TN1, the second P-type transistor TP2 and the second N-type transistor TN2 may be Low Temperature Polysilicon (LTPS) transistors, respectively. In an embodiment of the invention, the pixel circuit 100 may include a first node D, a second node P, a data transistor TD, a first P-type transistor TP1, a first N-type transistor TN1, and a liquid crystal capacitor ClcA second P-type transistor TP2 and a second N-type transistor TN 2.
The Data transistor TD has a first terminal for receiving the Data voltage Data, a second terminal coupled to the first node D, and a control terminal for receiving the Gate signal Gate. The first P-type transistor TP1 has a first terminal for receiving the first pulse signal Vb, a second terminal coupled to the second node P, and a control terminal coupled to the first node D. The first N-type transistor TN1 has a first terminal coupled to the second node P, a second terminal receiving the second pulse signal Vw, and a control terminal coupled to the first node D. The first pulse signal Vb and the second pulse signal Vw are opposite phases.
Liquid crystal capacitor ClcCoupled between the second node P and a common voltage signal VCOM, wherein a liquid crystal capacitor C is formedlcThe liquid crystal material of the liquid crystal layer can be operated in a normally black mode (normal black mode) or a normally white mode (normal white mode), and the common voltage signal VCOM is the same as one of the first pulse signal Vb and the second pulse signal Vw. The second P-type transistor TP2 has a first terminal for receiving the first pulse signal Vb, a second terminal coupled to the first node D, and a control terminal coupled to the second node P. The second N-type transistor TN2 hasThere are a first terminal coupled to the first node D, a second terminal receiving the second pulse signal Vw, and a control terminal coupled to the second node P.
In an embodiment of the present invention, the turn-on threshold voltage of the first P-type transistor TP1 may be different from the turn-on threshold voltage of the second P-type transistor TP2, and the turn-on threshold voltage of the first N-type transistor TN1 may be different from the turn-on threshold voltage of the second N-type transistor TN 2. For example, the turn-on threshold voltage of the first P-type transistor TP1 may be less than the turn-on threshold voltage of the second P-type transistor TP2, and the turn-on threshold voltage of the first N-type transistor TN1 may be less than the turn-on threshold voltage of the second N-type transistor TN 2.
In an embodiment of the present invention, the size of the first P-type transistor TP1 may be different from the size of the second P-type transistor TP2, and the size of the first N-type transistor TN1 may be different from the size of the second N-type transistor TN 2. For example, the size of the first P-type transistor TP1 may be larger than the size of the second P-type transistor TP2, and the size of the first N-type transistor TN1 may be larger than the size of the second N-type transistor TN 2.
When the turn-on threshold voltage of the first P-type transistor TP1 is less than the turn-on threshold voltage of the second P-type transistor TP2 and the turn-on threshold voltage of the first N-type transistor TN1 is less than the turn-on threshold voltage of the second N-type transistor TN2, the first P-type transistor TP1 and the first N-type transistor TN1 can quickly reflect the change of the voltage Vd at the first node D to quickly change the voltage Vp at the second node P.
When the size of the first P-type transistor TP1 is larger than that of the second P-type transistor TP2 and the size of the first N-type transistor TN1 is larger than that of the second N-type transistor TN2, the first P-type transistor TP1 and the first N-type transistor TN1 can rapidly change the voltage Vp of the second node P by a higher current.
Fig. 2 is a schematic diagram of driving waveforms of a pixel circuit according to an embodiment of the invention. Referring to fig. 1 and 2, the time lengths of the display periods DP 1-DP 3 may be the same or different, and each of the display periods DP 1-DP 3 at least includes one frame period, i.e., the pixel circuit 100 can update (or write data in) only once in a plurality of frame periods. In this embodiment, a liquid crystal capacitor C is formedlcThe liquid crystal material of the liquid crystal layer(s) is operated in a normally black mode (normal black mode), for example, and the common voltage signal VCOM is the same as the first pulse signal Vb, for example.
Taking the display period PD1 as an example, the Data voltage Data is at a low voltage level when the Gate signal Gate is enabled, i.e., the voltage Vd at the first node D is set (or written) to a low voltage level. At this time, the first P-type transistor TP1 is turned on, and the first N-type transistor TN1 is turned off, so that the voltage Vp at the second node P is the same as the first pulse signal Vb. Since the common voltage signal VCOM is the same as the first pulse signal Vb, the liquid crystal capacitor ClcThere is no voltage difference across, i.e., the liquid crystal in the liquid crystal layer is not twisted, so the pixel circuit 100 appears black (or darker color).
And, when the first pulse signal Vb is at a high voltage level, the second P-type transistor TP2 is turned off, the second N-type transistor TN2 is turned on, and the second pulse signal Vw at a low voltage level is transferred to the first node D, so that the voltage Vd at the first node D is continuously set to a low voltage level; when the first pulse signal Vb is at a low voltage level, the second P-type transistor TP2 is turned on, the second N-type transistor TN2 is turned off, and the first pulse signal Vb at the low voltage level is transferred to the first node D such that the voltage Vd at the first node D is still set to the low voltage level.
Taking the display period PD2 as an example, the Data voltage Data is at a high voltage level when the Gate signal Gate is enabled, i.e., the voltage Vd at the first node D is set (or written) to the high voltage level. At this time, the first P-type transistor TP1 is turned off, and the first N-type transistor TN1 is turned on, so that the voltage Vp of the second node P is the same as the second pulse signal Vw. Since the common voltage signal VCOM is the same as the first pulse signal Vb, the liquid crystal capacitor ClcThere is a voltage difference between the two ends, that is, the liquid crystal in the liquid crystal layer is twisted, so that the pixel circuit 100 appears white (or brighter).
And, when the second pulse signal Vw is at a high voltage level, the second P-type transistor TP2 is turned off, the second N-type transistor TN2 is turned on, and the second pulse signal Vw at the high voltage level is transferred to the first node D, so that the voltage Vd at the first node D is continuously set to the high voltage level; when the second pulse signal Vw is at a low voltage level, the second P-type transistor TP2 is turned on, the second N-type transistor TN2 is turned off, and the first pulse signal Vb at a high voltage level is transferred to the first node D such that the voltage Vd at the first node D is still set to a high voltage level. In addition, the operation of the display period PD3 is the same as the display period DP1, which is not described herein again.
In summary, the pixel circuit according to the embodiments of the invention alternately transmits the first pulse signal and the second pulse signal to the first node through the second P-type transistor and the second N-type transistor to maintain the voltage of the first node. Therefore, even if data is not written, the logic level of the first node is maintained, thereby maintaining the color displayed by the pixel circuit. Furthermore, when the pixel circuit is composed of the first node, the second node, the data transistor, the first P-type transistor, the first N-type transistor, the liquid crystal capacitor, the second P-type transistor and the second N-type transistor, the circuit area of the pixel circuit can be reduced, so that the pixel circuit can be applied to a display panel with Pixels Per Inch (PPI) with higher unit area resolution.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (7)
1. A pixel circuit, comprising:
a data transistor having a first terminal for receiving a data voltage, a second terminal coupled to a first node, and a control terminal for receiving a gate signal;
a first P-type transistor having a first terminal for receiving a first pulse signal, a second terminal coupled to a second node, and a control terminal coupled to the first node;
a first N-type transistor having a first terminal coupled to the second node, a second terminal receiving a second pulse signal, and a control terminal coupled to the first node;
a liquid crystal capacitor coupled between the second node and a common voltage signal;
a second P-type transistor having a first terminal for receiving the first pulse signal, a second terminal coupled to the first node, and a control terminal coupled to the second node; and
a second N-type transistor having a first terminal coupled to the first node, a second terminal receiving the second pulse signal, and a control terminal coupled to the second node,
wherein the liquid crystal layer forming the liquid crystal capacitor is operated in a normally black display mode or a normally white display mode,
wherein the pixel circuit is composed of the first node, the second node, the data transistor, the first P-type transistor, the first N-type transistor, the liquid crystal capacitor, the second P-type transistor and the second N-type transistor,
wherein the common voltage signal is identical to one of the first pulse signal and the second pulse signal.
2. The pixel circuit of claim 1, wherein the first pulse signal and the second pulse signal are inverse to each other.
3. The pixel circuit of claim 1, wherein the first P-type transistor has a turn-on threshold voltage different from the turn-on threshold voltage of the second P-type transistor, and the first N-type transistor has a turn-on threshold voltage different from the turn-on threshold voltage of the second N-type transistor.
4. The pixel circuit of claim 3, wherein the turn-on threshold voltage of the first P-type transistor is less than the turn-on threshold voltage of the second P-type transistor, and the turn-on threshold voltage of the first N-type transistor is less than the turn-on threshold voltage of the second N-type transistor.
5. The pixel circuit of claim 1, wherein the first P-type transistor has a different size than the second P-type transistor, and the first N-type transistor has a different size than the second N-type transistor.
6. A pixel circuit as claimed in claim 5, wherein the first P-type transistor is larger in size than the second P-type transistor, and the first N-type transistor is larger in size than the second N-type transistor.
7. The pixel circuit of claim 1, wherein the data transistor, the first P-type transistor, the first N-type transistor, the second P-type transistor, and the second N-type transistor are each a low temperature polysilicon transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108138304 | 2019-10-23 | ||
| TW108138304A TWI706394B (en) | 2019-10-23 | 2019-10-23 | Pixel circuit |
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| Publication Number | Publication Date |
|---|---|
| CN111341282A CN111341282A (en) | 2020-06-26 |
| CN111341282B true CN111341282B (en) | 2022-05-03 |
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| CN202010311206.1A Active CN111341282B (en) | 2019-10-23 | 2020-04-20 | Pixel circuit |
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| CN (1) | CN111341282B (en) |
| TW (1) | TWI706394B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101071246A (en) * | 2007-06-28 | 2007-11-14 | 友达光电股份有限公司 | Liquid crystal display devic,e grid driving circuit and its driving circuit unit |
| CN102930822A (en) * | 2012-11-12 | 2013-02-13 | 京东方科技集团股份有限公司 | Pixel circuit and display device and driving method of pixel circuit |
| CN103021339A (en) * | 2012-12-31 | 2013-04-03 | 昆山工研院新型平板显示技术中心有限公司 | Pixel circuit, display device and drive method of pixel circuit |
| CN103035201A (en) * | 2012-12-19 | 2013-04-10 | 昆山工研院新型平板显示技术中心有限公司 | Organic light-emitting diode pixel circuit, driving method thereof and display panel thereof |
| KR101404549B1 (en) * | 2008-02-15 | 2014-06-10 | 삼성디스플레이 주식회사 | Display device and driving method thereof |
| CN110060646A (en) * | 2019-05-08 | 2019-07-26 | 京东方科技集团股份有限公司 | Data-latching circuit, pixel circuit, array substrate and liquid crystal display panel |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI352234B (en) * | 2007-08-29 | 2011-11-11 | Au Optronics Corp | Liquid crystal display device |
| KR102006672B1 (en) * | 2017-09-05 | 2019-08-02 | 주식회사 라온텍 | Display apparatus and method for generating enable signal for the same |
| CN109935218B (en) * | 2019-01-21 | 2020-12-01 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof, display panel and display device |
-
2019
- 2019-10-23 TW TW108138304A patent/TWI706394B/en active
-
2020
- 2020-04-20 CN CN202010311206.1A patent/CN111341282B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101071246A (en) * | 2007-06-28 | 2007-11-14 | 友达光电股份有限公司 | Liquid crystal display devic,e grid driving circuit and its driving circuit unit |
| KR101404549B1 (en) * | 2008-02-15 | 2014-06-10 | 삼성디스플레이 주식회사 | Display device and driving method thereof |
| CN102930822A (en) * | 2012-11-12 | 2013-02-13 | 京东方科技集团股份有限公司 | Pixel circuit and display device and driving method of pixel circuit |
| CN103035201A (en) * | 2012-12-19 | 2013-04-10 | 昆山工研院新型平板显示技术中心有限公司 | Organic light-emitting diode pixel circuit, driving method thereof and display panel thereof |
| CN103021339A (en) * | 2012-12-31 | 2013-04-03 | 昆山工研院新型平板显示技术中心有限公司 | Pixel circuit, display device and drive method of pixel circuit |
| CN110060646A (en) * | 2019-05-08 | 2019-07-26 | 京东方科技集团股份有限公司 | Data-latching circuit, pixel circuit, array substrate and liquid crystal display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI706394B (en) | 2020-10-01 |
| TW202117690A (en) | 2021-05-01 |
| CN111341282A (en) | 2020-06-26 |
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