JP2008155558A - Misregistration compensation circuit, image formation device, and misregistration correction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compensate an image formation misregistration extending over a plurality of lines by replacing in order of gradation data to be supplied to an optical head while an operation frequency is suppressed to low. <P>SOLUTION: An image formation device 100 is provided which has misregistration compensation circuits 30 (K, C, M, Y). The misregistration compensation circuits 30 (K, C, M, Y) respectively have line buffers 31 (K, C, M, Y) which can simultaneously execute writing and reading, a write address generator 50 for executing buffer write address processing (S3) of repeating the write address processing for generating the write address to supply it to the line buffers 31 (K, C, M, Y), and a read address generator 60 for executing buffer read processing (S4) of repeating the read address processing for generating the read address and supplying it to the line buffers 31 (K, C, M, Y) in parallel with the buffer write processing (S3). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a position shift correction circuit that corrects a shift in image formation position across a plurality of lines by changing the order of gradation data supplied to the optical head, an image forming apparatus including the position shift correction circuit, and a position The present invention relates to a deviation correction method.

  2. Description of the Related Art An electrophotographic image forming apparatus in which an electrostatic latent image is written for each line on an image carrier (for example, a photosensitive drum) with an optical head having electro-optical elements such as LEDs arranged in one direction has become widespread. In such an image forming apparatus, the optical head should be mounted so that the arrangement direction of the electro-optical elements and the reference position which is an ideal exposure position of the image carrier are parallel to each other.

  However, in reality, since there is an attachment error, it is difficult to attach the optical head so that they are parallel to each other. For this reason, there is a possibility that a deviation of the image forming position across a plurality of lines due to a deviation between the arrangement direction of the electro-optic elements and the reference position (a deviation between the position of the actually formed image and the ideal image position) may occur. There is. In the image forming apparatus, when the image forming position shifts over a plurality of lines, the quality of the formed image is greatly deteriorated. In particular, in a tandem type color image forming apparatus that requires four optical heads, since the mounting errors of the optical heads are different, significant color misregistration occurs.

In view of this, a technique has been developed for correcting a shift in image forming position across a plurality of lines by changing the order of gradation data supplied to an optical head (see Patent Documents 1 to 7). These technologies require the use of a line buffer that can hold gradation data for multiple lines. The technique for changing the order of gradation data when writing to the line buffer and the gradation data when reading from the line buffer are required. It is roughly divided into technologies that change the order of
Japanese Patent No. 2980391 Japanese Patent No. 3399350 Japanese Patent No. 3381582 Japanese Patent No. 3684226 Japanese Patent No. 34200003 JP-A-10-315545 JP 2000-229442 A

  However, in the conventional technique, the gradation data is read from the line buffer after the gradation data has been written to the line buffer. Therefore, the operating frequency must be at least twice that when a memory capable of executing writing and reading simultaneously is used as a line buffer. That is, the conventional technique is a technique that requires high-speed memory and high-speed signal transmission. This is disadvantageous in terms of both cost and reliability.

  Therefore, the present invention provides a positional deviation correction circuit capable of correcting the deviation of the image forming position across a plurality of lines by changing the order of the gradation data supplied to the optical head while keeping the operating frequency low. An image forming apparatus using a positional deviation correction circuit and a positional deviation correction method are provided.

The positional deviation correction circuit according to the present invention receives a plurality of electro-optical elements arranged in one direction and whose light emission characteristics are changed by applied electric energy and image formation data in which gradation data is connected, and A drive unit that applies a plurality of electrical energies respectively corresponding to the gradation data for one line to each of the plurality of electro-optic elements for each gradation data of the same number as that of the optical element; The electro-optical element is used in an image forming apparatus including an optical head that irradiates a charged surface passing through a linear reference position and writes a latent image for each line. Receives image data in which gradation data is linked from a higher-level circuit, and shifts the order of gradation data in the image data, with respect to the deviation of the image forming position across multiple lines due to the deviation from the position. In the positional deviation correction circuit that generates the image formation data and corrects it by supplying it to the optical head, it has a storage area capable of storing the gradation data for the plurality of lines, and the supplied gradation data A line buffer capable of simultaneously executing data write processing for writing to the storage area of the supplied write address and data read processing for reading out and outputting gradation data from the storage area of the supplied read address, and generating the write address A write address generation unit that executes buffer write processing that is repetition of write address processing that is supplied to the line buffer, and buffer read processing that is repetition of read address processing that generates the read address and supplies the read line to the line buffer Is executed in parallel with the buffer write process. Characterized in that it comprises a less generating unit.
According to the position shift correction circuit, in the position shift correction circuit that corrects the shift of the image forming position across a plurality of lines by changing the order of the gradation data supplied to the optical head, the buffer write process and the buffer for the line buffer are performed. Since the read process is executed in parallel (simultaneously), the operating frequency can be kept low.

  In the positional deviation correction circuit, the line buffer has a storage area for the number of lines that is one line more than the plurality of lines, and the read address generation unit includes the read address process in each of the read address processes. The read address corresponding to a line different from the line corresponding to the write address generated by the write address process executed at the same time may be generated and supplied to the line buffer. According to this aspect, it is possible to reliably avoid a situation in which writing and reading to the same address are performed simultaneously.

In the positional deviation correction circuit, the read address generation unit may start the buffer read process when the write address is first generated in the buffer write process. In this aspect, the buffer read process starts immediately after the buffer write process starts. Therefore, complicated timing control is unnecessary and a simple circuit configuration is obtained.
By the way, in the conventional technique, when the gray scale data is first read from the line buffer, the gray scale data must be written in all the storage areas of the line buffer. Therefore, the gray scale data is first written in the line buffer. After that, the time from when the gradation data is first read out from the line buffer differs depending on the storage capacity of the line buffer, that is, the number of lines over which the deviation of the image forming position to be corrected extends. Therefore, the timing adjustment between the parts is complicated. In particular, in a tandem type color image forming apparatus, the number of lines across which the deviation of the image forming position to be corrected is different, and thus the above adjustment is extremely complicated. On the other hand, in this form, since said time becomes fixed, said adjustment becomes easy.

  The positional deviation correction circuit may include an initialization unit that initializes the line buffer with gradation data having the lowest gradation value. The gradation data having the lowest gradation value is gradation data corresponding to zero electric energy. At the start of the operation of the misregistration correction circuit, dummy data is required to fill a gap between a series of gradation data whose order has been changed. According to this aspect, complicated processing for inserting dummy data into the gap is performed. Therefore, the circuit configuration is simple.

  The positional deviation correction circuit may include the upper circuit, and the upper circuit may supply gradation data having the lowest gradation value for the plurality of lines following the image data. When the operation of the position misalignment correction circuit is stopped, dummy data for filling a gap between a series of gradation data whose order has been changed is required. According to this aspect, complicated processing for inserting dummy data into the gap is performed. Therefore, the circuit configuration is simple.

  An image forming apparatus according to the present invention includes any one of the above-described various misalignment correction circuits, an image carrier having a surface to be the charging surface, and a charger that charges the surface to form the charging surface. And a developing device for forming a visible image on the image carrier by attaching toner to the latent image, and a transfer device for transferring the visible image to a transfer target. According to this image forming apparatus, since the operating frequency of the positional deviation correction circuit can be kept low, it is possible to reduce the probability of occurrence of a problem due to a malfunction of the positional deviation correction circuit.

The positional deviation correction method according to the present invention receives a plurality of electro-optic elements arranged in one direction and whose light emission characteristics are changed by applied electric energy and image formation data obtained by connecting gradation data, and A drive unit that applies a plurality of electrical energies respectively corresponding to the gradation data for one line to each of the plurality of electro-optic elements for each gradation data of the same number as that of the optical element; In the image forming apparatus including an optical head that irradiates a charged surface passing through a linear reference position with light from each of the electro-optic elements and writes a latent image for each line, the one direction and the reference position The image formation position shift across multiple lines due to the shift of the image data is received from the upper circuit, and the order of the gradation data in the image data is received. In the positional deviation correction method for correcting by generating the image formation data and supplying it to the optical head, the storage device is provided with a storage area capable of storing the gradation data for the plurality of lines, and the supplied gradation data is supplied. Write to supply the write address to a line buffer capable of simultaneously executing data write processing for writing to the storage area of the written write address and data read processing for reading and outputting gradation data from the storage area of the supplied read address While performing buffer write processing which is repetition of address processing, in parallel with the buffer write processing, buffer read processing which is repetition of read address processing for supplying the read address to the line buffer is performed. To do.
According to the position shift correction circuit, in the position shift correction circuit that corrects the shift of the image forming position across a plurality of lines by changing the order of the gradation data supplied to the optical head, the buffer write process and the buffer for the line buffer are performed. Since the read process is executed in parallel (simultaneously), the operating frequency can be kept low.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The scope of the present invention includes modifications obtained by modifying the embodiment. In the drawings, the ratio of dimensions of each part is appropriately changed from the actual one.

  FIG. 1 is a longitudinal sectional view of an image forming apparatus 100 according to an embodiment of the present invention. The image forming apparatus 100 is a tandem type full-color image forming apparatus using a belt intermediate transfer body method. In the image forming apparatus 100, four optical heads 10K, 10C, 10M, and 10Y having the same configuration are associated with four photosensitive drums (image carriers) 110K, 110C, 110M, and 110Y having the same configuration. Are arranged respectively.

  As shown in the figure, the image forming apparatus 100 is provided with a driving roller 121 and a driven roller 122, and an endless intermediate transfer belt (transfer body) 120 is wound around these rollers 121 and 122. The rollers 121 and 122 are rotated as indicated by arrows. Although not shown, tension applying means such as a tension roller that applies tension to the intermediate transfer belt 120 may be provided.

  Around the intermediate transfer belt 120, photosensitive drums 110K, 110C, 110M, and 110Y having photosensitive layers on four outer peripheral surfaces are arranged at predetermined intervals. The photosensitive drums 110K, 110C, 110M, and 110Y are rotationally driven in synchronization with the driving of the intermediate transfer belt 120. The subscripts K, C, M, and Y mean that they are used to form black, cyan, magenta, and yellow visible images, respectively. The same applies to other members. By the rotational drive described above, the outer peripheral surface of the photosensitive drum 110 (K, C, M, Y) passes through a reference position (ideal exposure position) determined for itself.

  Around each photosensitive drum 110 (K, C, M, Y), there is a corona charger 111 (K, C, M, Y), an optical head 10 (K, C, M, Y), and a developing unit. 114 (K, C, M, Y) are arranged. The corona charger 111 (K, C, M, Y) uniformly charges the outer peripheral surface of the corresponding photosensitive drum 110 (K, C, M, Y). The optical head 10 (K, C, M, Y) writes an electrostatic latent image on the charged outer peripheral surface of the photosensitive drum. The developing device 114 (K, C, M, Y) forms a visible image, that is, a visible image on the photosensitive drum by attaching toner as a developer to the electrostatic latent image.

  The black, cyan, magenta, and yellow developed images formed by the four-color single-color image forming station are intermediate transfer that proceeds so as to pass through these transfer positions cyclically at the transfer positions of the respective colors. By being sequentially primary-transferred onto the belt 120, it is superimposed on the intermediate transfer belt 120, and as a result, a full-color visible image is obtained. That is, an image is formed on the intermediate transfer belt 120.

  Four primary transfer corotrons (transfer devices) 112 (K, C, M, Y) are arranged inside the intermediate transfer belt 120. The primary transfer corotron 112 (K, C, M, Y) is disposed in the vicinity of the photosensitive drum 110 (K, C, M, Y), and the photosensitive drum 110 (K, C, M, Y). The electrostatic image is electrostatically attracted from the toner image to transfer the visible image to the intermediate transfer belt 120 passing between the photosensitive drum and the primary transfer corotron.

  A sheet 102 as an object on which an image is to be finally formed is fed one by one from the sheet feeding cassette 101 by the pickup roller 103, and between the intermediate transfer belt 120 and the secondary transfer roller 126 in contact with the driving roller 121. To the nip (secondary transfer position). The full-color visible image on the intermediate transfer belt 120 is secondarily transferred to one side of the sheet 102 by the secondary transfer roller 126 and fixed on the sheet 102 through the fixing roller pair 127 as a fixing unit. . That is, an image is formed on the sheet 102. Thereafter, the sheet 102 is discharged onto a paper discharge cassette formed in the upper part of the apparatus by a paper discharge roller pair 128.

  As is apparent from the above description, the image forming apparatus 100 includes the photosensitive drum 110 having a surface that passes through the linear reference position, the corona charger 111 that charges the surface, and the photosensitive drum 110 being charged. An optical head 10 that writes an electrostatic latent image on the surface, a developer 114 that forms a visible image on the photosensitive drum 110 by attaching toner to the electrostatic latent image, and an intermediate portion that has advanced to the secondary transfer position. A primary transfer corotron 112 for transferring the visible image to the transfer belt 120 is provided, and an image is formed on the intermediate transfer belt 120 (finally the sheet 102).

  FIG. 2 is a perspective view illustrating a schematic configuration in the vicinity of the photosensitive drum 110 </ b> Y in the image forming apparatus 100. In this figure, the Y direction is the traveling direction of the intermediate transfer belt 120, and the X1 direction is a direction perpendicular to the intermediate transfer belt 120 and substantially parallel to the bus line of the photosensitive drum 110Y. Further, the reference symbol PY in the drawing indicates a reference position determined for the photosensitive drum 110Y. The reference position PY is parallel to the bus line of the photosensitive drum 110Y. Further, in this drawing, the sheet 102 is virtually shown in a portion on the intermediate transfer belt 120 that will come into contact with the sheet 102 later.

  As shown in FIG. 2, the optical head 10Y includes an electro-optical panel 1Y and a converging lens array 2Y. Specifically, the converging lens array 2Y is SLA (Selfoc Lens Array) available from Nippon Sheet Glass Co., Ltd. (Selfoc \ SELFOC is a registered trademark of Nippon Sheet Glass Co., Ltd.). It should be noted that the present embodiment may be modified so that the converging lens array 2Y is omitted, or a microlens array may be employed instead of the converging lens array 2Y.

  FIG. 3 is a plan view schematically showing the configuration of the optical head 10Y. As shown in FIGS. 2 and 3, the electro-optical panel 1Y has an array part 11Y extending in the A direction. In the array unit 11Y, a plurality of electro-optical elements whose light emission characteristics are changed by the applied electric energy are arranged in a line in the A direction. The light from each electro-optic element travels in the front direction of the paper in FIG. 3, and passes through the converging lens array 2Y to reach the photosensitive drum 110Y.

  As the electro-optic element, an organic EL (Electro Luminescent) element that requires excitation by recombination of carriers is employed. Note that a modification of the present embodiment may employ a light emitting element that does not require carrier recombination (for example, an inorganic EL element) or a light emitting element that does not require excitation (for example, an inorganic LED) as an electro-optical element. Good.

  On the other hand, the converging lens array 2Y extends in the A direction, is disposed between the electro-optical panel 1Y and the photosensitive drum 110Y, and overlaps the entire area of the array unit 11Y. The relative position between the electro-optical panel 1Y and the converging lens array 2Y is fixed by a case (not shown), and the relative position between the optical head 10Y and the photosensitive drum 110Y is fixed by the casing of the image forming apparatus 100.

  As shown in FIG. 3, the optical head 10 </ b> Y is provided with fifteen driving units 12 </ b> Y <b> 0 to 12 </ b> Y <b> 14 that sequentially drive m electro-optic elements, arranged in order in the A direction. In other words, the array unit 11Y is provided with 15m electro-optic elements, and these electro-optic elements are driven by the drive unit 12Y (0 to 14). The drive units 12Y (0 to 14) have m-stage shift registers 13Y0 to 13Y14 and latch circuits 14Y0 to 14Y14, respectively. Each stage of the shift register 13Y (0 to 14) has a one-to-one correspondence with the electro-optic element in the array unit 11Y. The latch circuit 14Y (0 to 14) includes m latches corresponding one-to-one to the electro-optic elements in the array unit 11Y.

  Each of the shift registers 13Y (0 to 13) has a final stage preceding the next shift register 13Y (1 to 14), and the first stage of the shift register 13Y (0) includes image formation data from the upper circuit. D2Y is input. The image formation data D2Y is data in which gradation data indicating gradation is connected. Therefore, the gradation data input to the first stage of the shift register 13Y (0) is sequentially shifted and finally reaches the last stage of the shift register 13Y (14). That is, the shift register 13Y (0 to 13) constitutes one shift register that can hold gradation data for one line.

  Each latch of the latch circuit 14Y (0 to 14) latches the gradation data held in the corresponding stage every time the gradation data D2Y for one line is held in the shift register 13Y (0 to 13). To do. The drive unit 12Y (0 to 14) supplies electric energy corresponding to the gradation data latched in each latch to the electro-optical element corresponding to the latch. In other words, the drive unit 12Y (0 to 14) outputs a plurality of electric energies corresponding to the gradation data for one line for each of the same number of gradation data for one line as the plurality of electro-optic elements. To the electro-optic element. Accordingly, the electrostatic latent image is written for each line.

  As described above, it is difficult to attach the optical head 10Y to the housing of the image forming apparatus 100 so that the reference position PY and the A direction are parallel, and the A direction and the reference position PY may not be parallel. Is expensive. That is, in FIG. 2, when attention is paid to the visible image IM for one line on the intermediate transfer belt 120 (finally the sheet 102), the extending direction X2M and the reference position PY may not be parallel, that is, There is a high possibility that a deviation between an actual image formation position and an ideal image formation position (hereinafter referred to as “position deviation”) will occur.

  FIG. 4 is a diagram illustrating an example of positional deviation. In the example of FIG. 4A, the extending direction X2Y of the visible image IM for one line is inclined upward to the X1 direction. In the example of FIG. 4B, the extending direction X2Y is inclined upward to the X1 direction. In the drawing, the line number is shown in the vicinity of each line when the printable area of the sheet 102 is divided into the 0th line to the nth line extending in the X1 direction and arranged in the Y direction. As is apparent, in any example, the visible image IM for one line extends over a plurality of lines. As mentioned above, this is a situation to avoid. For this reason, the image forming apparatus 100 includes position shift correction circuits 30K, 30C, 30M, and 30Y.

  FIG. 5 is a block diagram illustrating an outline of the electrical configuration of the image forming apparatus 100. As shown in this figure, the image forming apparatus 100 includes a positional deviation correction circuit 30 (K) for supplying image forming data D2 (K, C, M, Y) to the optical head 10 (K, C, M, Y), respectively. , C, M, Y) and an upper circuit 20 that supplies the image data D1 (K, C, M, Y) to the positional deviation correction circuit 30 (K, C, M, Y). The image data D1Y (K, C, M, Y) and the image formation data D2 (K, C, M, Y) are data obtained by connecting gradation data.

  The positional deviation correction circuit 30 (K, C, M, Y) has a line buffer 31 (K, C, M, Y), receives image data D1Y (K, C, M, Y), and receives the received image. A circuit that corrects misregistration by generating the image formation data D2 (K, C, M, Y) by changing the order of gradation data in the data using the line buffer 31 (K, C, M, Y). It is. Since the configuration of the positional deviation correction circuit 30 (K, C, M, Y) is the same, only the configuration of the positional deviation correction circuit 30Y will be described below.

  FIG. 6 is a diagram schematically showing an example of the structure of the image data D1Y supplied from the upper circuit 20 to the positional deviation correction circuit 30Y. The image data D1Y is data in which gradation data is connected. As shown in this figure, the gradation data constituting the image data D1Y is sequentially supplied to the positional deviation correction circuit 30Y for each block in which each line is equally divided. Is done. When i, j is an integer greater than or equal to 0, the gradation data of the image to be formed in the region having the row number i and the block number j is included in the block L (i, j). The size of each block is the same.

  The number of blocks per line is the same as the number of rows (to be referred to as “corrected row numbers” hereinafter) over which the positional deviation to be corrected extends. FIG. 6 shows an example in which the number of corrected rows is 8. Specifically, the gradation data of the block L (0, 0) is first supplied to the positional deviation correction circuit 30Y, then the gradation data of the block L (0, 1) is supplied, and then the block L The gradation data of (0, 2) is supplied,..., The gradation data of block L (0, 7) is then supplied, the gradation data of block L (1, 0) is then supplied, and the next Is supplied with gradation data of the block L (1, 1), and eventually the gradation data of the block L (n, 7) is supplied.

  When the A direction and the reference position PY are not parallel, and there is a relationship that causes a positional shift extending over a plurality of rows, if the image data D1Y in which the gradation data is arranged in the above order is supplied to the optical head 10Y as it is, For example, as shown in FIG. 4, a positional shift over a plurality of lines occurs. 7 and 9 show examples of image formation data D2Y to be generated by the position shift correction circuit 30Y in order to avoid such position shift.

  FIG. 7 is a diagram showing an example of grayscale data to be latched by the latch circuit 14Y (0 to 14) in the example of the upward right side of FIG. In this example, the number of corrected rows is 8. In this example, the gradation data for one line on which an image is to be formed in the row whose row number is 0 is composed of gradation data indicating 0 (gradation data having the lowest gradation value) for 7 blocks, Next, the gradation data of the block L (0, 0) is connected, and the gradation data for one line on which an image is to be formed in the row with the row number 1 is the gradation data with a gradation value of 0. (Minimum gradation data: gradation data with the lowest gradation value) is connected for 7 blocks, and then the gradation data of block L (0, 0) is connected. As for the gradation data for one line to be formed, the minimum gradation data is continued for 6 blocks, then the gradation data of the block L (0,1) is connected, and then the block L (1,0) ..., the gradation data for one line on which an image is to be formed in the row whose row number is n-1, Next to the lock L (n-1, 7), the block L (n, 6) is connected, and then the lowest gradation data is connected by 6 blocks, and an image is formed in the row with the row number n. The gradation data for one power line is obtained by connecting the lowest gradation data for 7 blocks next to the block L (n, 7). From this example, it can be seen that, in order to correct the right-up position shift, the image formation data D2Y should be generated so that the formed image is left-up.

  FIG. 8 is a diagram illustrating an example of grayscale data to be latched by the latch circuit 14Y (0 to 14) in the example of the upward left in FIG. 4B. In this example, the number of corrected rows is 8. In this example, the gradation data for one line in which an image is to be formed in the row whose row number is 0 is the block L (0, 7) followed by the minimum gradation data for 7 blocks. For the gradation data for one line in which an image is to be formed in the row with the row number 2, the block L (1, 7) is followed by the block L (0, 6), and then the lowest gradation data is 6. The gradation data for one line in which an image is to be formed in the row whose row number is n-1 is continuous with the minimum gradation data for 6 blocks, and then the block L ( n, 1) gradation data, followed by a block L (n-1,0), and the gradation data for one line in which an image is to be formed in a row with row number n is The minimum gradation data is connected for 7 blocks, and then the gradation data for block L (n, 0) is connected. To become. From this example, it can be seen that, in order to correct the leftward misalignment, the image formation data D2Y should be generated so that the formed image is rightward.

  FIG. 9 is a diagram schematically illustrating an example of how to use the line buffer 31Y in the example of the correction of the position shift to the right in FIG. FIG. 10 is a diagram schematically illustrating an example of how to use the line buffer 31Y in the example of the correction of the leftward positional deviation of FIG. FIG. 11 is a memory map of the line buffer 31Y. In these drawings, a solid arrow indicates a region where gradation data is written and its transition direction, and a dotted arrow indicates a region where gradation data is read and its transition direction.

  9 and 10, the storage area of the line buffer 31Y is divided into nine line areas L0 to L9, which is one more than the number of corrected lines, and each of the line areas L0 to L9 is divided into 8 by dividing points dp1 to dp7. It is divided into block areas B0 to B7. Each of the row areas L0 to L9 can hold gradation data for one row, and each of the block areas B0 to B7 can hold gradation data for one block. The leading addresses (offsets: L0S to L8S) of the row areas L0 to L8 have a relationship of L0S <L1S <L2S <... <L7S <L8S <L9S. In each of the row areas L0 to L9, the head addresses (divided addresses: B0S to B7S) of the block areas B0 to B7 have a relationship of B0S <B1S <B2S <... <L5S <L6S <L7S. B0S to B7S are local addresses. Also, assuming that the length of one row (the number of gradation data for one row: the number of electro-optic elements) is len, L0S = 0, L1S = len, L2S = 2len,..., L7S = 7len, L8S = 8len Thus, the start address of the block B6 in the row area L5 is 5len + 6 (len / 8).

  In the writing (writing) of the gradation data to the line buffer 31Y, as is clear from FIG. 11, the process of sequentially changing the write address from the start address of the row area L0 to the final address of the row area L8 is repeated. On the other hand, the transition of the read address in the reading (reading) of the gradation data from the line buffer 31Y differs depending on whether the correction is performed for a right-up position shift or the left-up position shift.

  In the case of correcting the position shift to the right, first, as shown in FIG. 9 (a1), the write address sequentially changes from the head address (B0S) of the block B0 in the row area L0 to the last address of the block. In the meantime, the read address is sequentially shifted from the last address of the block B7 in the next area L1 of the area L0 to the head address (B7S) of the block. Next, as shown in FIG. 9 (a2), while the write address transitions sequentially from the head address (B1S) of the block B1 in the row area L0 to the last address of the block, the read address is changed to the next of the row area L1. The transition is made in order from the last address of the block B6 before the block B7 to the head address (B6S) of the block in the row area L2.

  Such processing is repeated, and as shown in FIG. 9A3, the write address reaches the final address of the block B7 in the area L0, and the read address is the head of the block B0 in the area L8 before the area L0. When the address (B0S) is reached, as shown in FIG. 9 (a4), while the write address transitions sequentially from the head address (B0S) of the block B0 in the area L1 to the final address of the block, The transition is made sequentially from the last address of the block B7 in the next area L2 to the head address (B7S) of the block. Thereafter, the same processing as described above is repeated. However, the line area next to the line area L8 is the line area L0, and the line area before the line area L0 is the line area L8.

  Then, as shown in FIG. 9 (a5), the write address reaches the final address of the block B7 in the row area L8, and the read address becomes the head address (B0S) of the block B0 in the row area L8 before the row area L8. When it reaches, the process described above is repeated. The same processing is performed when correcting the upward leftward misalignment. However, in this case, as shown in FIG. 10, the transition of the read address between the row areas is performed in the order of the row area L8, the row area L7,..., The row area L1, the row area L0,. Transition between these blocks is performed in the order of block B0, block B1,..., Block B6, block B7,.

  If the address control described above can be realized, the image forming data D2Y that can obtain the results shown in FIGS. 7 to 8 can be generated. Next, a flowchart showing a flow of processing capable of realizing the address control shown in FIGS. 9 to 11 will be described.

  FIG. 12 is a flowchart showing the operation of the positional deviation correction circuit 30Y. As shown in this figure, when the power is turned on, the positional deviation correction circuit 30Y repeats the process of determining whether or not to start the operation (step S1) until the determination result is “YES”. This determination is “YES”, for example, when a signal (start) described later is supplied from the higher-level circuit 20. In parallel with the above repetitive processing, the positional deviation correction circuit 30Y initializes itself (step S2). Specifically, the line buffer 31Y is initialized and various parameters are loaded from the upper circuit 20.

  By the initialization, the lowest gradation data is written in all the storage areas of the line buffer 31Y. Various parameters loaded from the upper circuit 20 include, for example, the final address (adrs_max) of the storage area used for correction of positional deviation, the len, the number of corrected rows (NOL), the division among the storage areas of the line buffer 31Y. A parameter indicating an address and an offset indicating a head address of a row area are given. When the initialization is completed and the determination result in step S1 is “YES”, the positional deviation correction circuit 30Y executes the buffer write process (step S3) and the buffer read process (step S4) in parallel.

  FIG. 13 is a flowchart of the buffer write process. In the buffer write process, the positional deviation correction circuit 30Y first sets the write address (adrs_w) to 0 (step S31). Next, adrs_w is supplied to the line buffer 31Y, and a data write process (step S33) is performed. Further, in parallel with steps S32 and S33, the positional deviation correction circuit 30Y determines whether adrs_w and adrs_max are equal (step S34). If the determination result is “NO”, 1 is set to adrs_w. Addition is performed (step S35), and the process returns to steps S32 and S34. If the determination result of step S34 is “YES”, the positional deviation correction circuit 30Y returns the process to step S31. That is, the buffer write process is a repetition of the write address process that generates a write address and supplies it to the line buffer 31Y, and the positional deviation correction circuit 30Y functions as a write address generation unit.

  FIG. 14 is a flowchart of the buffer read process. This buffer read process is premised on loading of the various parameters described above, and can be appropriately modified according to the parameters to be loaded. In the buffer read process of FIG. 14, the positional deviation correction circuit 30Y first selects the first offset (step S31). The offsets are arranged cyclically, and the positional deviation correction circuit 30Y selects one offset (for example, L1S) from these offsets (step S41). Next, the line address (adrs_L) indicating the storage area in the row area is set to len-1 (step S42).

  Next, the positional deviation correction circuit 30Y selects the first division address (step S43). The division addresses are arranged cyclically, and the positional deviation correction circuit 30Y selects one division address (for example, B7S) from these division addresses (step S43). Next, the positional deviation correction circuit 30Y generates adrs_r based on the selected offset and adrs_L (step S44), supplies the generated adrs_r to the line buffer 31Y (step S45), and performs data read processing (step S46). .

  On the other hand, the position misalignment correction circuit 30Y determines whether or not adrs_L is equal to the selected divided address after the completion of step S43 (step S47). If the determination result is “NO”, 1 is set to adrs_L. Addition is performed (step S48), and the process returns to steps S44 and S47. If the determination result in step S47 is “YES”, the positional deviation correction circuit 30Y determines whether drs_L is equal to the selected offset (step S49), and if the determination result is “NO”. Then, the next offset and the next divided address are selected (step S50), 1 is added to adrs_L (step S48), and the process returns to steps S44 and S47. If the determination result in step S49 is “YES”, the positional deviation correction circuit 30Y selects the next offset (step S51), and returns the process to steps S44 and S47.

That is, the buffer read process is a repetition of the read address process that generates a read address and supplies the read address to the line buffer 31Y. The positional deviation correction circuit 30Y performs a read address process that executes the read address process in parallel with the buffer write process. It functions as a part.
If the processing described above can be realized, the address control shown in FIGS. 9 to 11 can be realized. Here, two types of circuit configurations capable of realizing the address control shown in FIGS. 12 to 14 will be described.

<First Embodiment>
FIG. 15 is a block diagram showing a configuration of a positional deviation correction circuit according to the first embodiment. The positional deviation correction circuit includes a DPRAM (Dual Port RAM) 40, a write address generation unit 50, and a read address generation unit 60. The DPRAM 40 is used as a line buffer and has a storage area capable of storing gradation data for a plurality of lines. When gradation data and a write address are supplied, the gradation data is stored in the write address. A data write process for writing to an area and a data read process for reading out and outputting gradation data from the storage area of the read address when a read address is supplied can be executed simultaneously. The write address generation unit 50 generates adrs_w that changes cyclically for each clock from the reception of the signal (start) indicating the start of operation from the upper circuit 20 until the signal (end) indicating the stop of the operation. . The adrs_w is supplied to the DPRAM 40 and is supplied to the read address generation unit 60.

  FIG. 16 is a circuit diagram showing a configuration of the read address generation unit 60. The read address generation unit 60 includes a line address counter 61, an offset counter 62, a clock counter 63, a divided address register 64, an offset register 65, a data selector 66, a comparator 67, a data selector 68, and an OR circuit 69.

  The line address counter 61 is a down counter that generates adrs_L. The line address counter 61 receives adrs_r as a clock, and len−1 (for example, 15m−1) is set as an initial value. The value of the line address counter 61 returns to len−1 after 0. The offset counter 62 is a down counter that outputs data for selecting an offset. In the offset counter 62, the number of corrected rows (NOL (for example, 8)) is set as an initial value. The value of the line address counter 61 returns to len−1 after 0. The block counter 63 is a down counter that outputs data for selecting a division address. In the block counter 63, a value (for example, 7) obtained by subtracting 1 from the number of corrected rows (NOL) is set as an initial value. The value of the block counter 63 returns to NOL-1 after 0.

  The number of division address registers 64 and the number of data input terminals of the data selector 65 are each NOL. Divided addresses (for example, B0S to B7S) are loaded into the divided address registers 64, respectively. Each divided address is input to the data input terminal of the data selector 65. The output data of the block counter 63 is input to the SEL terminal of the data selector 65. Therefore, the data selector 65 selects and outputs one divided address corresponding to the output data of the block counter 63 from the divided addresses of NOL.

  The comparator 67 receives adrs_L and the output data of the data selector 65. The comparator 67 inputs a clock to the offset counter 62 and the block counter 63 only when the two match. Only when this clock is input, the offset counter 62 and the block counter 63 count down.

  The number of offset registers 65 and the number of data input terminals of the data selector 68 are each NOL + 1. Each offset register 65 is loaded with an offset (for example, L0S to L8S). Each offset is input to the data input terminal of the data selector 68. The output data of the offset counter 62 is input to the SEL terminal of the data selector 68. Therefore, the data selector 68 selects and outputs one offset corresponding to the output data of the offset counter 62 from the offset of NOL + 1.

  The output data (upper address) and adrs_L (lower address) of the offset counter 62 are combined by the OR circuit 69 to become adrs_r and are supplied to the DPRAM 40.

<Second Embodiment>
FIG. 17 is a block diagram showing a configuration of a positional deviation correction circuit according to the second embodiment. The positional deviation correction circuit includes a write address generation unit 50, a read address generation unit 60, an address decoder 70, and a latch circuit 80. The latch circuit 80 has a plurality of D flip-flops 81. Image data D1Y is input to the data input terminal D of each D flip-flop 81.

  The address decoder 70 is connected to an address line connected to the clock input terminal C of all the D flip-flops 81, and supplies a clock to one address line corresponding to adrs_w supplied from the write address generator 50. Then, the corresponding D flip-flop 81 is asserted. As a result, gradation data is written in the D flip-flop 81. The address decoder 70 is connected to an address line connected to the output control terminal OC of all the D flip-flops 81, and is connected to one address line corresponding to adrs_w supplied from the read address generation unit 60. A clock is supplied and the corresponding D flip-flop 81 is asserted. As a result, gradation data is read from the D flip-flop 81.

  In each of the above-described embodiments, the higher-order circuit 20 follows the image data D1 (K, C, M, Y) and adrs_max + 1 for each positional deviation correction circuit 30 (K, C, M, Y). After supplying the lowest gradation data (gradation data corresponding to the number of correction rows), a signal (end) indicating operation stop is supplied. As shown in FIGS. 7 and 8, when the position shift correction circuit 30 (K, C, M, Y) is stopped, the gap between the gradation data contained in the image data D1 (K, C, M, Y) However, in each of the above embodiments, since the upper circuit 20 performs the above processing, a complicated process for inserting the dummy data into the gap is unnecessary, and simple processing is performed. It has a circuit configuration.

<Modification>

  FIG. 18 is a longitudinal sectional view of an image forming apparatus according to a modification of the embodiment of the present invention. This image forming apparatus is a rotary developing type full-color image forming apparatus using a belt intermediate transfer body system, and the same positional deviation as the above-described positional deviation correction circuit 30 (C, M, Y, K) and the upper circuit 20. A correction circuit and an upper circuit are provided. In the image forming apparatus shown in FIG. 18, a corona charger 168, a rotary developing unit 161, an optical head 167, and an intermediate transfer belt 169 are provided around a photosensitive drum (image carrier) 165. The optical head 167 has the same configuration as the optical head 10 described above.

  The corona charger 168 uniformly charges the outer peripheral surface of the photosensitive drum 165. The optical head 167 writes an electrostatic latent image on the charged outer peripheral surface of the photosensitive drum 165. The optical head 167 is an electro-optical device or an electro-optical device according to a modification thereof, and is installed such that the arrangement direction of the plurality of light emitting elements 14 is along the bus line (main scanning direction) of the photosensitive drum 165. The electrostatic latent image is written by irradiating the photosensitive drum with light by the plurality of light emitting elements 14 described above.

  The developing unit 161 is a drum in which four developing units 163Y, 163C, 163M, and 163K are arranged at an angular interval of 90 °, and can rotate counterclockwise about the shaft 161a. The developing units 163Y, 163C, 163M, and 163K supply yellow, cyan, magenta, and black toners to the photosensitive drum 165, respectively, and attach the toner as a developer to the electrostatic latent image, thereby the photosensitive drum 165. A visible image, that is, a visible image is formed.

  The endless intermediate transfer belt 169 is wound around a driving roller 170a, a driven roller 170b, a primary transfer roller 166, and a tension roller, and is rotated around these rollers in a direction indicated by an arrow. The primary transfer roller 166 transfers the visible image to the intermediate transfer belt 169 that passes between the photosensitive drum and the primary transfer roller 166 by electrostatically attracting the visible image from the photosensitive drum 165.

  Specifically, in the first rotation of the photosensitive drum 165, an electrostatic latent image for a yellow (Y) image is written by the optical head 167, and a developed image of the same color is formed by the developing device 163Y. The image is transferred to the transfer belt 169. Further, in the next rotation, an electrostatic latent image for a cyan (C) image is written by the optical head 167, and a developed image of the same color is formed by the developing device 163C, and an intermediate transfer is performed so as to overlap the yellow developed image. Transferred to the belt 169. In this way, the yellow, cyan, magenta, and black visible images are sequentially superimposed on the intermediate transfer belt 169 while the photosensitive drum 9 rotates four times. As a result, a full-color visible image is formed on the transfer belt 169. It is formed. When images are finally formed on both sides of a sheet as an object on which an image is to be formed, the same color images of the front and back surfaces are transferred to the intermediate transfer belt 169, and then the front and back surfaces are transferred to the intermediate transfer belt 169. A full-color visible image is obtained on the intermediate transfer belt 169 by transferring the visible image of the next color.

  The image forming apparatus is provided with a sheet conveyance path 174 through which a sheet passes. The sheets are picked up one by one from the paper feed cassette 178 by the pick-up roller 179, advanced through the sheet transport path 174 by the transport roller, and between the intermediate transfer belt 169 and the secondary transfer roller 171 in contact with the drive roller 170a. Pass through the nip. The secondary transfer roller 171 transfers the developed image to one side of the sheet by electrostatically attracting a full-color developed image from the intermediate transfer belt 169 collectively. The secondary transfer roller 171 can be moved closer to and away from the intermediate transfer belt 169 by a clutch (not shown). The secondary transfer roller 171 is brought into contact with the intermediate transfer belt 169 when a full-color visible image is transferred onto the sheet, and is separated from the secondary transfer roller 171 while the visible image is superimposed on the intermediate transfer belt 169.

  The sheet on which the image has been transferred as described above is conveyed to the fixing device 172 and is passed between the heating roller 172a and the pressure roller 172b of the fixing device 172, whereby the visible image on the sheet is fixed. The sheet after the fixing process is drawn into the discharge roller pair 176 and proceeds in the direction of arrow F. In the case of double-sided printing, after most of the sheet passes through the paper discharge roller pair 176, the paper discharge roller pair 176 is rotated in the reverse direction and introduced into the double-sided printing conveyance path 175 as indicated by an arrow G. The Then, the visible image is transferred to the other surface of the sheet by the secondary transfer roller 171, the fixing process is performed again by the fixing device 172, and then the sheet is discharged by the discharge roller pair 176.

  Note that the above-described embodiment may be modified to be an image forming apparatus of a type that directly transfers a visible image from a photosensitive drum to a sheet without using an intermediate transfer belt, or an image forming apparatus that forms a monochrome image. . Further, the arrangement pattern of the electro-optic elements in the optical heads 10 and 167 may be a plurality of rows and a staggered pattern.

1 is a longitudinal sectional view of an image forming apparatus 100 according to an embodiment of the present invention. 2 is a perspective view showing an outline of a configuration in the vicinity of a photosensitive drum 110Y in the image forming apparatus 100. FIG. 2 is a plan view illustrating an outline of a configuration of an optical head 10Y in the image forming apparatus 100. FIG. It is a figure which shows the example of position shift. 2 is a block diagram illustrating an outline of an electrical configuration of the image forming apparatus 100. FIG. 3 is a diagram schematically showing an example of the structure of image data D1Y supplied to a positional deviation correction circuit 30Y in the image forming apparatus 100. FIG. 3 is a diagram illustrating an example of gradation data to be latched by a latch circuit 14Y (0 to 14) in the image forming apparatus 100. FIG. It is a figure which shows another example of the gradation data which should be latched by the latch circuit 14Y (0-14). It is a figure which shows typically an example of the usage method of the line buffer 31Y in the position shift correction circuit 30Y. It is a figure which shows typically another example of the usage method of the line buffer 31Y in the position shift correction circuit 30Y. It is a memory map of the line buffer 31Y. It is a flowchart which shows operation | movement of the position shift correction circuit 30Y. It is a flowchart of a buffer write process in the positional deviation correction circuit 30Y. It is a flowchart of a buffer read process in the positional deviation correction circuit 30Y. It is a block diagram which shows the structure of the position shift correction circuit which concerns on the 1st Embodiment of this invention. FIG. 16 is a circuit diagram showing a configuration of a read address generation unit 60 in the positional deviation correction circuit of FIG. 15. It is a block diagram which shows the structure of the position shift correction circuit which concerns on the 2nd Embodiment of this invention. It is a longitudinal cross-sectional view of the image forming apparatus which concerns on the modification of embodiment of this invention.

Explanation of symbols

  10 (K, C, M, Y), 167 ... optical head, 20 ... upper circuit, 30 (K, C, M, Y) ... position shift correction circuit, 31 (K, C, M, Y) ... line buffer 50, write address generation unit, 60, read address generation unit, 110, 165, photosensitive drum (image carrier), 111, 168, corona charger (charger), 114, 163, developing unit, 112, primary Transfer corotron (transfer device), 166... Primary transfer roller (transfer device).

Claims (7)

A plurality of electro-optical elements that are arranged in one direction and whose light emission characteristics are changed by the applied electric energy and image formation data including gradation data are received, and the same number of floors as one line as the plurality of electro-optical elements. A drive unit that applies a plurality of electric energy corresponding to the gradation data for one line to each of the plurality of electro-optic elements for each tone data, and receives light from each of the plurality of electro-optic elements , Used in an image forming apparatus including an optical head that irradiates a charged surface passing through a linear reference position and writes a latent image for each line;
An image forming position shift across a plurality of lines due to a shift between the one direction and the reference position is received from the upper circuit, and image data including gradation data is received, and the order of the gradation data in the image data is changed. In a positional deviation correction circuit that corrects by generating the image formation data and supplying it to the optical head,
A storage area capable of storing gradation data for a plurality of lines; a data write process for writing the supplied gradation data into a storage area for the supplied write address; and a storage area for the supplied read address. A line buffer capable of simultaneously executing data read processing for reading out and outputting adjustment data;
A write address generation unit that executes a buffer write process that is a repetition of a write address process that generates the write address and supplies it to the line buffer;
A read address generation unit that executes a buffer read process that is a repetition of a read address process that generates the read address and supplies the read address to the line buffer, in parallel with the buffer write process;
A positional deviation correction circuit characterized by that. The line buffer has a storage area for the number of lines one line more than the plurality of lines,
In each of the read address processing, the read address generation unit is configured to read the read address corresponding to a line different from the line corresponding to the write address generated in the write address processing executed simultaneously with the read address processing. And supply to the line buffer,
The position shift correction circuit according to claim 1. The read address generation unit starts the buffer read process when the write address is first generated in the buffer write process.
The position shift correction circuit according to claim 1. An initialization unit that initializes the line buffer with gradation data having a lowest gradation value;
The position shift correction circuit according to claim 1. Comprising the upper circuit,
The upper circuit supplies gradation data having the lowest gradation value for the plurality of lines following the image data.
The position shift correction circuit according to claim 1. A positional deviation correction circuit according to any one of claims 1 to 5,
An image carrier having a surface to be the charging surface;
A charger that charges the surface to form the charging surface;
The optical head;
A developing unit that forms a visible image on the image carrier by attaching toner to the latent image; and
An image forming apparatus comprising: a transfer device that transfers the visible image to a transfer target. A plurality of electro-optical elements that are arranged in one direction and whose light emission characteristics are changed by the applied electric energy and image formation data including gradation data are received, and the same number of floors as one line as the plurality of electro-optical elements. A drive unit that applies a plurality of electric energy corresponding to the gradation data for one line to each of the plurality of electro-optic elements for each tone data, and receives light from each of the plurality of electro-optic elements In an image forming apparatus including an optical head that irradiates a charged surface passing through a linear reference position and writes a latent image for each line, an image extending over a plurality of lines due to a deviation between the one direction and the reference position The image forming data is generated by receiving the image data in which the gradation data is linked from the upper circuit and generating the image forming data by changing the order of the gradation data in the image data. In the position shift correction method for correcting by supplying to the optical head,
A storage area capable of storing gradation data for a plurality of lines; a data write process for writing the supplied gradation data into a storage area for the supplied write address; and a storage area for the supplied read address. While performing the buffer write process, which is a repetition of the write address process for supplying the write address to the line buffer capable of simultaneously executing the data read process for reading out and outputting the adjustment data, in parallel with the buffer write process, Performing buffer read processing that is a repetition of read address processing for supplying the read address to the line buffer;
A positional deviation correction method characterized by that.

Images