JP4513493B2 - Printer head, image forming apparatus including the same, and printer head drive circuit - Google Patents

Description

  The present invention relates to a printer head or line such as an organic EL (Electro-luminescence) printer head used to form an electrostatic latent image by exposing a photosensitive member in an image forming apparatus such as a printer, a copy, and a facsimile. The present invention relates to a technical field of a head, an image forming apparatus including the head, and a printer head driving circuit.

  In this type of organic EL printer head, in many cases, lighting / non-lighting according to data signals in a plurality of organic EL light emitting elements arranged in a line is sequentially performed at a timing according to a line scanning signal. Here, each pixel circuit is provided with an organic EL light emitting element and a driving transistor for causing a driving current to flow therethrough. The driving transistor is turned on according to a data signal, and the driving current is supplied to the organic EL light emitting element. The light emission according to the data signal is performed (see Patent Document 1).

JP 11-27469 A

  However, in an ordinary organic EL panel, each stage included in the shift register has several tens of stages. Therefore, when clock wiring is arranged in the vicinity of the logic circuit, clock signal wiring and power supply wiring intersect at many places. In such a case, the parasitic capacitance of the clock signal wiring generated when the clock signal is supplied via the clock signal wiring is increased, which may hinder high-speed operation particularly in the printer head. In particular, when a plurality of clock signal wirings are provided to supply multiphase clock signals in the printer head, the parasitic capacitance of the clock signal wirings increases and signal delay becomes remarkable. Further, in the printer head, when a large number of wirings are arranged in a narrow area for the purpose of downsizing the printer head, the parasitic capacitance caused by the wirings crossing each other due to restrictions on the layout of these wirings. It may increase and cause signal delay. For example, when a relatively high-frequency clock signal intersects with another wiring such as a power supply line, signal delay is further noticeable, making it difficult to drive the line scanning circuit and the like at high speed and normally. In some cases. Further, when a multiphase clock signal is supplied via a plurality of clock wirings, for example, jitter caused by a deviation of rising or falling of each clock signal waveform occurs, and the printer head can be driven normally. It may be difficult.

  Accordingly, the present invention has been made in view of the above problems and the like, and provides a printer head capable of high-speed and normal driving, an image forming apparatus including the printer head, and a printer head drive circuit. And

In order to solve the above problems, a printer head according to the present invention is arranged in a line on a substrate, includes current-driven light emitting elements for exposing a photoconductor, and is sequentially supplied. A plurality of pixel circuits configured to write a data signal defining a drive current flowing through the light emitting element in accordance with a scanning signal; and a line scanning circuit for sequentially supplying the line scanning signal to the plurality of pixel circuits; A clock signal supplied via a clock signal supply line including a portion extending along the arrangement direction of the plurality of pixel circuits is selectively transmitted to the line scanning circuit via a clock signal output line. A clock signal supply means for supplying the power supply to the line scanning circuit, and the clock signal supply means and the line scanning circuit in plan view on the substrate to supply power to the line scanning circuit; Is provided between the, and a power supply line, wherein the clock signal output lines includes a portion that intersects with extending linearly along the arrangement direction of the plurality of pixel circuits are arranged, the clock signal The supply means includes a plurality of first unit circuits that are electrically connected in parallel to the clock signal supply line and selectively supply the single-phase clock signal to the line scanning circuit, respectively. The line scanning circuit includes a plurality of second unit circuits that are arranged in correspondence with the plurality of first unit circuits along the arrangement direction of the plurality of pixel circuits, respectively, and that output the clock signals, respectively. Each of the plurality of second unit circuits supplies a clock supply control signal for controlling the supply of the clock signal to the clock signal supply unit, and the clock signal supply unit includes the plurality of second unit circuits. Counts each clock supply control signal supplied from the circuit, by selecting the second unit circuit that requires the clock signal to selectively supply the clock signal to the line scanning circuit.

  According to the printer head of the present invention, for example, a plurality of pixel circuits including organic EL light emitting elements are arranged in a line on a substrate. Here, “arranged in a line” according to the present invention refers to a case in which a plurality of pixel circuits extend in one line along the line direction in which the plurality of pixel circuits are arranged, a case in which two or more lines extend, or a staggered pattern. Including the case of extension. Such a line-shaped printer head can emit line-shaped light sequentially from the light-emitting element array along the line direction in which the plurality of pixel circuits are arranged with respect to the photoconductor. Alternatively, it is possible to emit line-shaped light from the light-emitting element array at the same time or a part of the light.

  According to the printer head of the present invention, the parasitic capacitance generated in the clock signal supply line can be reduced by selectively supplying the clock signal from the clock signal supply means to the line scanning circuit. The plurality of pixel circuits, the line scanning circuit, the clock signal supply means, and the power supply line are provided on the same substrate. For example, the branch line branched from the clock signal supply line intersects the power supply line. However, according to the printer head of the present invention, it is possible to reduce the parasitic capacitance generated in the branch line and the clock signal supply line. More specifically, for example, when a clock signal is supplied to the line scanning circuit via a clock signal supply line that partially intersects the power supply line, a parasitic capacitance is generated in the clock signal supply line. By selectively supplying the clock signal to the line scanning circuit via the line, the number of times that the clock signal crosses the power supply line can be substantially reduced, and the parasitic capacitance generated in the clock signal supply line or the like is reduced. can do. Further, by selectively supplying the clock signal to the line scanning circuit, the chance that a useless clock signal among the clock signals supplied via the clock signal supply line crosses the power supply line can be reduced. Therefore, for example, even when the clock signal is supplied so as to cross the power supply line in a state where the clock signal supply line, the power supply line, the line scanning circuit, etc. are arranged on the same substrate, the line scanning circuit, etc. The clock signal can be supplied to the logic circuit at high speed. Here, “selectively” according to the present invention does not always supply a clock signal to the line scanning circuit, for example, when the printer head operates, but a logic circuit such as a line scanning circuit requires the clock signal. This means that the clock signal is supplied only when

  The power supply line is provided between the clock signal supply means and the line scanning circuit when viewed in plan on the substrate, and extends in a line along the arrangement direction in which a plurality of pixel circuits are arranged. Therefore, the power supply line must have a portion that intersects with the clock signal output line. However, as described above, the clock signal is selectively supplied to the line scanning circuit. Thus, the parasitic capacitance of the clock signal supply line can be reduced without changing the layout or the like of the power supply line. In particular, in the printer head, there is a demand for downsizing in accordance with the size of the printer along with improvement in the number of pixels, and various wirings arranged in the printer head are arranged so as to intersect with each other in an electrically insulated state. There are many cases. For example, the power supply line and the clock signal are often arranged so as to intersect each other. Even in such a case, it is possible to supply the clock signal at a higher speed so that the high-speed driving of the printer head is not impaired by reducing the chance that the clock signal crosses the power supply line. The term “on the substrate” according to the present invention is not limited to the meaning on the surface of the substrate. For example, the meaning is on the same plane inside the substrate or the same laminated structure formed on the substrate. Including. That is, “on the substrate” according to the present invention means directly or indirectly above the substrate. For example, the power supply line and the clock signal supply line are formed on the same plane inside the substrate. After that, a case where a protective film or the like is formed thereon is also included. The term “on the substrate” according to the present invention means that, for example, wiring and circuits that process various signals such as a clock signal supply line, a power supply line, and a line scanning circuit to drive a pixel circuit include an insulating film or the like. It also includes the case where they are arranged on different layers on the substrate.

  As described above, according to the printer head of the present invention, the parasitic capacitance of the clock signal supply line and the like can be reduced, and the clock signal can be supplied to the line scanning circuit at high speed. In particular, in a printer head that may require a high frequency for a line scanning signal, for example, the line scanning circuit can be driven at high speed and normally by reducing the parasitic capacitance generated in the clock signal supply line.

  In one aspect of the printer head according to the present invention, the line scanning circuit includes the power supply line and a portion extending in a line along the arrangement direction when viewed in plan on the substrate. You may arrange | position between wiring.

  According to this aspect, since the clock signal does not cross the ground-side wiring during the operation of the printer head, it is possible to reduce the chance that parasitic capacitance occurs in the clock signal supply line.

In order to solve the above problems, a printer head drive circuit according to the present invention is arranged in a line on a substrate and includes current-driven light-emitting elements for exposing a photosensitive member, and sequentially supplies them. A printer head drive circuit for driving a printer head having a plurality of pixel circuits configured to write a data signal defining a drive current flowing in the light emitting element in accordance with a line scan signal to be written. And a line scanning circuit for sequentially supplying the line scanning signals to the plurality of pixel circuits on the substrate, and a clock signal supply line including a portion extending along an arrangement direction of the plurality of pixel circuits. Clock signal supply means for selectively supplying the clock signal supplied to the line scanning circuit via a clock signal output line, and the line scanning circuit In order to supply power, it is provided between the clock signal supply means and the line scanning circuit in plan view on the substrate, and is line-shaped along the arrangement direction in which the plurality of pixel circuits are arranged. And a power supply line including a portion where the clock signal output line intersects , and the clock signal supply means is electrically connected in parallel to the clock signal supply line, and the single phase A plurality of first unit circuits for selectively supplying the clock signal to the line scanning circuit, and the line scanning circuit is arranged along the arrangement direction of the plurality of pixel circuits. And a plurality of second unit circuits that respectively output the clock signal, and each of the plurality of second unit circuits is connected to the clock signal supply means. The clock signal supply means counts the clock supply control signal supplied from each of the plurality of second unit circuits, and requires the clock signal. By selecting a 2-unit circuit, the clock signal is selectively supplied to the line scanning circuit .

  According to the printer head drive circuit of the present invention, like the printer head described above, the parasitic capacitance of the clock signal supply line and the like is reduced, and the line scan circuit for supplying the line scan signal is driven while being driven at high speed. It is possible to expose the body.

  In order to solve the above problems, the image forming apparatus according to the present invention can develop the electrostatic latent image formed on the photoconductor by the above-described printer head, the photoconductor, and exposure by the printer head. Developing means for forming a visual image and transfer means for transferring the formed visible image onto a recording medium.

  According to the image forming apparatus of the present invention, since the printer head according to the present invention described above is provided, a photosensitive member such as a photosensitive drum is exposed at high speed and with high resolution. Accordingly, through subsequent development and transfer, a high-speed and high-quality color image or black-and-white image can be formed on a recording medium such as copy paper. In addition, the size of the image forming apparatus can be reduced by downsizing the printer head.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, the printer head according to the present embodiment will be described in detail with reference to FIGS. 1 to 6. Thereafter, a printer as an example of an image forming apparatus according to the present invention will be described with reference to FIG. In the following embodiments, a printer head on which an organic EL light emitting element (hereinafter referred to as an EL element), which is an example of a current driven light emitting element, is described as an example.

(Printer head)
First, a schematic configuration of a printer head according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a perspective view schematically showing a configuration of a printer head according to the present embodiment, and FIG. 2 is a schematic diagram of the printer head showing various specific examples relating to a planar layout of a light emitting unit and a pixel circuit. It is a partial enlarged plan view.

  In FIG. 1, a printer head 1 is connected to a substrate 10, a plurality of light emitting units 11 arranged in a line on the substrate 10, an external circuit connection terminal 12 to which a data signal is supplied, and an external circuit connection terminal 12. A data line unit 13, a scanning circuit 17, a clock signal supply line 30, a power supply line 40, and a ground wiring 50 are provided.

  The substrate 10 is composed of a glass substrate, a quartz substrate, a semiconductor substrate, or the like that extends in the longitudinal direction with the left-right direction in the figure as the “longitudinal direction”. The substrate 10 has a size in which a line-shaped region in which a plurality of light emitting units 11 are arranged can be printed on printing paper of various sizes by a printer including the printer head 1. The substrate 10 has a length in the longitudinal direction of 20 cm to 30 cm so that it can be printed on, for example, A size printing paper. The substrate 10 has a length of, for example, 10 mm in its short direction. Short in the short direction is very advantageous because a wide space for arranging various elements other than the printer head 1 can be secured in the printer including the printer head 1.

  The external circuit connection terminals 12 are arranged along the edge of the substrate 10. A part of the plurality of external circuit connection terminals 12 provided as a data signal source is a binary data signal from a printer engine or the like, that is, whether it is lit (on) or not lit (off) for each pixel. A data signal indicating is supplied.

  One or a plurality of data line portions 13 are wired so as to extend along the longitudinal direction of the substrate 10. A data signal is supplied from the data signal source to the data line unit 13 via the external circuit connection terminal 12.

  The scanning circuit 17 is retrofitted or built in the substrate 10. As will be described later, the scanning circuit 17 is configured to sequentially supply a line scanning signal for controlling the timing of light emission in each light emitting unit 11 to each pixel circuit 201.

  The clock signal supply line 30 is arranged on the substrate 10 so as to extend along the horizontal direction in the drawing, that is, the arrangement direction in which the light emitting units 11 are arranged. The clock signal supply line 30 supplies a clock signal supplied from, for example, a timing generator (not shown) to the scanning circuit 17.

  Similar to the clock signal supply line 30, the power supply line 40 and the ground wiring 50 are arranged on the substrate 10 so as to extend along the arrangement direction of the light emitting units 11. The clock signal supply line 30, the power supply line 40, and the ground wiring 50 are not limited to the case where they are disposed on the substrate 10, but are disposed on the same plane together with the light emitting unit 11 and the scanning circuit 17. If so, it may be arranged inside the substrate 10. For example, the power supply line 40 supplies power for driving various elements included in the scanning circuit 17, and the ground wiring 50 grounds various elements included in the scanning circuit 17. The printer head 1 has a configuration in which the scanning circuit 17 is disposed between the power supply line 40 and the ground wiring 50 on the substrate 10, and more specifically, outside the power supply line 40, more specifically, the substrate 10. The clock signal supply line 30 is arranged above the power supply line 40 in the drawing. Therefore, when the clock signal is supplied from the clock signal supply line 30 to the scanning circuit 17, the clock signal intersects with the power supply line 40.

  In FIG. 2, the plurality of light emitting units 11 are arranged along a line direction that coincides with the longitudinal direction of the substrate 10. The light emitting unit 11 may be provided with only one line (FIG. 2A), may be provided with a plurality of lines in a staggered pattern (FIG. 2B), or may be provided with a plurality of lines in a matrix. Good (FIG. 2 (c)). In any specific example, one light emitting unit 11 is provided for each pixel circuit 201 and is arranged at a pitch of about 10 μm, for example. Each pixel circuit 201 is supplied with a line scanning signal from the line scanning circuit 17 shown in FIG. 1 via a line scanning signal line 141, and a data signal via a lead line portion 13 c of the data line portion 13. Supplied. Further, the pixel circuit 201 is configured such that a high potential power source and a low potential power source are respectively supplied from the high potential wiring 116 and the low potential wiring 118.

  Next, a specific example of the pixel circuit 201 and various wirings connected to the pixel circuit 201 will be described with reference to FIG. FIG. 3 is a block diagram illustrating a specific example of an electrical schematic configuration of the printer head 1. In FIG. 3, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In FIG. 3, the data line unit 13 includes a data signal supply line 13a and an input buffer DINV. In addition, pixel circuit groups B1, B2,..., Bn including a plurality of pixel circuits 201 are electrically connected to the ends of the leader line portion 13c, which is a branch line branched from the data signal supply line 13a. Yes. In FIG. 3, the pixel circuits 201 are arranged in a horizontal row, but as the actual planar layout, various layouts are adopted as shown in FIGS. 2 (a) to 2 (c). Is possible. In particular in the specific example of FIG. 3, the input buffer DINV generates a binary voltage corresponding to the binary data signal supplied from the data signal supply line 13a and supplies it to the pixel circuit 201 via the lead line portion 13c. To do. The input buffer DINV and the electrostatic protection circuits 226 and 228 can protect each part of the printer head 1 from abnormal voltage such as static electricity. Further, using a separately supplied power supply voltage, the binary voltage in the data signal supply line 13a and the lead-out line portion 13c is firmly held at any one of the binary voltages corresponding to ON / OFF of the binary data signal. can do. As a result, the pixel circuit 201 can be driven via the data line unit 13. In the present embodiment, the voltage program method is adopted as the driving method of the pixel circuit 201 included in the printer head 1, but the driving method of the pixel circuit 201 is not limited to the voltage program method, and for example, a traditional method It is also possible to employ a current program method that is a driving method of the organic EL display device.

  The scanning circuit 17 includes a shift register circuit SR which is an example of a “line scanning circuit” according to the present invention, and a transmission gate group TG which is an example of a “clock signal supply unit” according to the present invention. The shift register circuit SR sequentially supplies line scanning signals S1, S2,..., S4 to the line scanning signal line 141 in accordance with a clock signal supplied from the clock signal supply line 30 via the transmission gate group TG. It is configured as follows.

  The transmission gate group TG includes transmission gates TG01, TG02,..., TGm1, which are examples of the “first unit circuit” according to the present invention. Each of the transmission gates TG01, TG02,..., TGm1 is electrically connected in parallel to the clock signal supply line 30 and electrically connected to each stage SRi of the shift register circuit SR. That is, m of the transmission gate TGm1 matches n of the shift register SRn. Each of the transmission gates TG01, TG11,... TGm1 sequentially supplies a clock signal to each stage SRi of the shift register circuit SR. Each of the transmission gates TG10, TG11,..., TGm1 is electrically connected to each stage SRi of the shift register circuit SR via a clock signal output line 241. The clock signal output line 241 is disposed between the power supply line 40 and an insulating film, for example, and extends in the vertical direction in the figure so as to intersect the power supply line 40. Therefore, the power supply line 40 includes a portion intersecting with each clock signal output line 241, and the clock signal supplied to each stage SRi of the shift register circuit SR from the transmission gates TG01, TG11,. Crosses with the power supply line 40.

  The shift register circuit SR includes each stage SRi (i = 0, 1, 2,..., N) of the shift register circuit SR. In the following description, the stage SR0 to which the start pulse SP is first input only transfers the start pulse to the next stage SR1, and each stage SR1, SR2,..., SRn after the stage SR1. Supplies the line scanning signal Si to the pixel circuit 201.

  Each of the stages SRi of the shift register circuit SR is an example of the “second unit circuit” according to the present invention, and the stage SR0, which is the first stage of the shift register circuit SR, is included in the operation of the printer head 1. A start pulse SP and a clock signal CLK are input. The stage SR0 latches the start pulse SP in accordance with the clock signal CLK and outputs a sampling control signal, supplies a transfer signal to the next stage SR1 by this sampling control signal, and each stage SR1 sequentially transfers the transfer signal to the next stage. Supply. Thereby, each stage SRi of the shift register circuit SR samples the start pulse SP according to the sampling control signal and supplies it to the line scanning signal line 141 as the line scanning signal Si. More specifically, the stage SRi includes a flip-flop circuit unit FFi (i = 0, 1, 2,..., N) and an OR logic circuit unit ORi (i = 1, 2,..., N), inverter INVi (i = 0, 1, 2,..., N) and transmission gate TGi2 (i = 0, 1, 2,. , N), and each stage SRi processes the start pulse SP described above by these elements and supplies line scanning signals S1, S2,..., Sn to the pixel circuit 201. The second and subsequent stages SRi (i = 1, 2,..., N) are further provided with a NAND circuit section Ni (i = 1, 2,..., N), via the NAND circuit section Ni. The line scanning signal Si is supplied to the pixel circuit 201. The stage SRn which is the final stage of the shift register circuit SR outputs the start pulse SP as the end pulse EP.

  Each of the transmission gates TG01, TG11,... TGm1 selectively supplies the clock signal supplied from the clock signal supply line 30 to each stage SRi of the shift register circuit SR, so that the clock signal is supplied to the power supply line. Reduce the chance to cross 40. More specifically, for example, by counting the clock supply control signal supplied from each stage of the shift register circuit SR, the stage where the clock signal is required is selected and the clock signal is supplied. As a result, it is possible to reduce the parasitic capacitance generated in the clock signal supply line 30 and the clock signal output line 241 when the clock signal crosses the power supply line 40, and to supply the clock signal at high speed. Become.

  The pixel circuit 201 includes a control transistor TR1, a driving transistor TR2, and an EL element OLED. The EL element OLED functions as the light emitting unit 11 shown in FIGS. The detailed configuration of the EL element OLED is the same as or similar to that of the EL element in the existing organic EL display panel. A line scanning signal Si (i = 1, 2,..., N) is supplied to the gate of the control transistor TR1. Then, the binary voltage of the data signal supplied from the leader line portion 13c to the source is supplied to the gate of the driving transistor TR2 via the source and drain at the timing when the corresponding line scanning signal Si is supplied. It is configured as follows. The driving transistor TR2 is turned on when one value (for example, high level voltage) of the binary voltage of the data signal is applied to its gate. Therefore, at this time, a driving current flows between the cathode and the anode of the EL element to which a predetermined potential is supplied. As a result, the EL element OLED emits light, that is, lights up. Conversely, the driving transistor TR2 is turned off when the other value (for example, a low level voltage) of the binary voltage of the data signal is applied to its gate. Therefore, at this time, the driving current does not flow between the cathode and the anode supplied with the predetermined potential.

  The pixel circuit 201 is grouped into pixel blocks Bi (i = 0, 1,..., N) each including four light emitting units 11 (see FIGS. 1 and 2). The pixel block Bi includes a predetermined number of pixel circuits 201 (that is, four here). In the pixel block Bi, one line scanning signal line 141 is electrically connected to each other, and the plurality of light emitting units 11 included in the pixel block Bi are collectively fed from the line scanning signal line 141 to the same line scanning. A signal Si is supplied. In the present embodiment, the case where there are four data signal supply lines 13a will be described as an example. However, the number of data line signal supply lines included in the data line unit 13 is not limited to four. For example, when the number of data signal supply lines is 128, 128 different data signals can be simultaneously supplied from the data line unit 13 to each of 128 pixel circuits belonging to the same pixel block. Is possible. Each of the four data signal supply lines 13a is electrically connected to the light emitting unit 11 included in the pixel block Bi. One data signal supply line 13a is electrically connected to each of the four pixel circuits 201 included in the pixel block Bi. Furthermore, each of the data signal supply lines 13a is also electrically connected to the pixel circuit 201 included in another pixel block Bi. Therefore, each of the data signal supply lines 13a included in the data line unit 13 is shared by the pixel circuits 201 included in each pixel block Bi. Thereby, the pixel circuits 201 arranged in a straight line can be operated for each pixel block Bi.

  Next, the configuration of the printer head 1 will be described in more detail with reference to FIGS. 4 and 5. 4 is an enlarged plan view showing a part of the printer head 1, and FIG. 5 is a cross-sectional view taken along the line V-V 'in FIG. , TGm1, TG02, TG12,..., TGn2, each stage of the shift register circuit SR, SR0, SR1,... SRn, and each stage of the shift register circuit SR. The wirings and the like that are electrically connected have a configuration in which required electrical connections are made to each other and are repeated along the left-right direction in FIG. 3, so in FIG. 4 and FIG. This will be described while showing the configuration in the vicinity of the TG 11.

  In FIG. 4, a clock signal supply line 30, a transmission gate TG11, a power supply line 40, a transmission gate TG12, one stage SR1 of the shift register circuit SR, and a ground wiring 50 are arranged on the substrate 10 in order from the upper side in the drawing. .

  The clock signal supply line 30, the power supply line 40, and the ground wiring 50 extend along the horizontal direction in the drawing along the scanning circuit 17 arranged along the plurality of pixel circuits 201. The transmission gate TG11 is disposed between the clock signal supply line 30 and the power supply line 40 along the vertical direction in the drawing. The output side of the transmission gate TG11 is electrically connected to the input side of the transmission gate TG12. More specifically, the output side of the transmission gate TG11 is electrically connected to the input side of the transmission gate TG12 via a clock signal output line 241 extending in the vertical direction in the drawing. The clock signal output line 241 is insulated from the power supply line 40 in the state of being insulated from the power supply line 40 through an insulating film. Therefore, the clock signal output line 241 is insulated from the power supply line 40. It will intersect in the state. Therefore, when the clock signal is supplied from the transmission gate TG11 to the transmission gate TG12, the clock signal crosses the power supply line 40.

  The shift register circuit SR is disposed between the power supply line 40 and the ground wiring 50 along the vertical direction in the drawing. In the drawing, the transistor TR50 included in one stage SR1 of the shift register circuit SR and a part of the transistor TR60 included in the NAND circuit N1 are shown. The NAND circuit N1 collectively supplies the line scanning signal output from one stage SR1 of the shift register circuit SR to the pixel circuit group B1 electrically connected to the NAND circuit N1.

  In FIG. 5, a clock signal supply line 30, a transmission gate TG11, a power supply line 40, one stage SR1 of the shift register circuit SR, and a ground wiring 50 are formed of insulating films 122, 124, 125 formed on the substrate 10, The gate insulating film 123 is disposed on or in the film. The transmission gate TG11 includes a transistor TR60. In the transistor TR60, contact holes 501 and 502 penetrating the gate insulating film 124 and reaching the semiconductor layer 105 of the transistor TR60 are formed. The conductive film constituting the drain electrode 101 and the source electrode 103 of the transistor TR60 is continuously formed so as to reach the surface of the semiconductor layer 105 along the inner walls of the contact holes 501 and 502, respectively. The drain electrode 101 is electrically connected to the clock signal output line 241, and the source electrode 103 is electrically connected to the clock signal supply line 30. The gate electrode 102 is formed so as to face the semiconductor layer 105 with the gate insulating film 123 interposed therebetween, and is embedded in the insulating film 124 so as to be electrically isolated from the drain electrode 101 and the source electrode 103. . The clock signal output line 241 is embedded in the insulating film 124 so as to cross the power supply line 40 below the power supply line 40 formed on the insulating film 124, and is one stage SR1 of the shift register circuit SR. Has been extended to. Similarly to the transmission gate TR11, the transistor TR50 included in one stage SR1 of the shift register circuit SR has contact holes 601 and 602 that penetrate the insulating film 124 and reach the semiconductor layer 205 of the transistor TR50. The conductive film constituting the drain electrode 201 and the source electrode 203 of the transistor TR50 is continuously formed so as to reach the surface of the semiconductor layer 205 along the inner walls of the contact holes 601 and 602, respectively. Although the gate electrode 202 of the transistor TR50 has a double gate structure, it goes without saying that it may have a single gate structure. The ground wiring 50 is formed on the gate insulating film 124, and the line signal output line 141 is embedded in the insulating film 124 so as to intersect the ground wiring 50 below the ground wiring 50.

  As described above, when the clock signal output line 241 is arranged so as to cross the power supply line 40, the transmission gate TG11 selectively supplies the clock signal to the shift register circuit SR as described above. The parasitic capacitance generated in the signal output line 241 and the clock signal supply line 30 can be reduced, and the clock signal can be supplied to the shift register circuit SR at high speed. In particular, when the thickness of the insulating film 124 interposed between the clock signal supply line 241 and the power supply line 40 is thin, the parasitic capacitance generated by supplying the clock signal increases, but the clock signal is connected to the power supply line. If the chance of dating is reduced, the parasitic capacitance generated can be reduced.

  Next, another embodiment of a printer head according to the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a specific example of the electrical schematic configuration of the printer head according to the present embodiment. In FIG. 6, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The printer head 100 includes a clock control circuit unit 20, a line scanning circuit 17, a data line unit 13, a pixel circuit unit 80, a clock signal supply line 30, and a power supply line 40 which are examples of the “clock signal supply unit” according to the invention. , And ground wiring 50 as main components.

  In FIG. 6, the clock signal control unit 20 includes a plurality of clock control circuits 21 which are examples of the “first unit circuit” according to the present invention. The clock control circuit 21 is electrically connected in parallel to a clock signal supply line 30 that extends along the longitudinal direction of the printer head 100. The clock control circuit 21 is provided for each of a plurality of clock recovery circuits 41 to be described later. The clock signal is supplied to the clock control circuit 21 via a clock signal supply line 30 including a portion extending in a line shape along the horizontal direction in the drawing, that is, the arrangement direction in which the pixel circuits 201 are arranged. The clock signal supplied via the clock signal supply line 30 is a single-phase clock signal that is input from the input side on the left side in the figure by a timing generator (not shown).

  Each of the clock control circuits 21 includes four input / output terminals. More specifically, the clock control circuit 21 includes a clock signal input terminal CLKINa, a fixed potential input terminal VINa, a clock signal output terminal CLKOUTa, and a clock supply control signal input terminal CNTINa. The clock control circuit 21 is electrically connected in parallel to a clock signal supply line 30 in which a buffer 32 is electrically inserted on the input side of the clock signal. Since the input impedance of the buffer 32 is large and the output impedance is small, the absolute value of the binary voltage of the clock signal indicating 1 (high level) or 0 (low level) hardly varies between input and output. Therefore, the buffer 32 can stably supply the clock signal to each of the clock control circuits 21 while maintaining the absolute value of the binary voltage of the clock signal at the time of input. In particular, in the present embodiment, it is possible to obtain a special effect that the clock signal can be stably supplied after the wiring capacity is suppressed by using one clock signal supply line 30.

  A low potential (LO) power supply is input to the first clock control circuit 21 closest to the input side of the clock signal, that is, the fixed potential input terminal VINa of the clock control circuit 21 arranged on the left side in the drawing. A high potential (HIGH) power source is input to the fixed potential input terminal VINa of the clock control circuit 21. A low potential (LO) power source is input to the fixed potential input terminal VINa of the third clock control circuit 21, and a high potential (HIGH) power source is input to the fixed potential input terminal VINa of the fourth clock control circuit 21. Is done. Low-potential and high-potential power supplies are alternately input to the fixed potential input terminals VINa of the plurality of clock control circuits 21 in order from the clock signal input side.

  The clock supply control signal input terminal CNTINa of the clock control circuit 21 receives a clock supply control signal output from a clock recovery circuit 41 described later. The clock control circuit 21 takes in the clock signal from the clock input terminal CLKINa in accordance with the power supply and clock supply control signal input from the fixed potential input terminal VINa and the clock supply control signal input terminal CNTINa, and outputs the clock signal output terminal CLKOUTa. Output to. It is an example of “selectively” according to the present invention that the clock control circuit 21 supplies a clock signal to the clock recovery circuit 41 described later in accordance with the power supply and the clock supply control signal. That is, the clock control circuit 21 does not always supply the clock signal to the clock recovery circuit 41 while the clock signal is supplied, but only supplies the clock signal for a predetermined period according to the clock supply control signal and the power source. This is supplied to the clock recovery circuit 41.

  Thus, the clock control circuit 21 does not always supply the clock signal to the clock recovery circuit 41 described later, but both the clock supply control signal and the clock signal are signals indicating 1 (high level). Only when the clock signal is supplied to the clock recovery circuit 41. More specifically, the clock control circuit 21 can supply a clock signal to the clock recovery circuit 41 only when a clock recovery circuit 41 (to be described later) generates a positive-phase clock signal and a reverse-phase clock signal. That is, the clock control circuit 21 selectively supplies a clock signal only to a clock reproduction circuit 41 that generates a normal phase and a reverse phase clock signal for a predetermined period.

  Therefore, the clock signal is supplied only to the clock recovery circuit 41 that requires the clock signal, and even if the clock signal output line 241 is arranged to intersect the power supply line 40, the clock signal is supplied. The chance that the signal crosses the power supply line 40 can be reduced. As a result, the generation of parasitic capacitance in the clock signal supply line 30 and the clock signal output line 241 can be reduced, the delay of the clock signal due to the parasitic capacitance can be suppressed, and the printer head can be driven at high speed.

  The clock generation unit 40 is an example of the “clock waveform generation unit” according to the present invention, and includes a plurality of clock recovery circuits 41 electrically connected to each of the clock control circuits 21. The clock recovery circuit 41 is an example of a “second unit circuit” according to the present invention, and generates a positive-phase clock signal and a reverse-phase clock signal from a single-phase clock signal supplied from the clock control circuit 21. Here, the anti-phase clock signal is a signal having a waveform obtained by inverting the normal phase clock signal with respect to a reference potential. The clock recovery circuit 41 includes a clock supply control signal output terminal CNTOUTb, a clock input terminal CLKINb, a first input terminal OR1b and a second input terminal OR2, a normal phase clock signal output terminal OUTb, and a negative phase clock signal output terminal OUTBb. Yes. The clock recovery circuit 41 generates a positive phase clock signal and a negative phase clock signal from the single phase clock signal input from the clock signal input terminal CLKINb, and each of the positive phase clock signal output terminal OUTb and the negative phase clock signal output terminal OUTBb. The normal phase and reverse phase clock signals are supplied to one stage of the shift register circuit SR corresponding to the clock recovery circuit 41. In this way, each stage of the shift register circuit SR, which will be described later, sequentially transfers the transfer signal to the next stage of the shift register by the normal phase and reverse phase clock signals generated from the single-phase clock signal, and the pixel circuit, which will be described later A line scanning signal is supplied to 201 via a logic element or the like. For example, the clock recovery circuit 41 processes a single-phase clock signal with a plurality of logic elements and inverters that are electrically connected to each other to generate a normal-phase clock signal and a reverse-phase clock signal.

  Each stage of the shift register circuit SR is electrically connected to an input terminal IN to which a start pulse or a transfer signal output from the previous stage is input, an output terminal OUT to output a transfer signal, and a reverse-phase clock signal output terminal OUTB of the clock recovery circuit 41. And a clock signal input terminal CL1 electrically connected to the positive-phase clock signal output terminal OUT. Here, the shift register SR0, which is the leftmost stage of the shift register circuit SR, only transfers the start pulse SP to the next stage as a transfer signal, and each stage SR1, SR2 of the shift register circuit SR. ,..., SRn are sequentially transferred from the transfer signal SRn + 1, which is the final stage of the shift register circuit SR arranged on the rightmost side in the drawing. The shift register circuit SR is provided with a NAND logic element 60 corresponding to each stage SR1, SR2,..., SRn of the shift register. Each of the stages SR0, SR1,..., SRn of the shift register circuit SR has a NAND logic element 60 using a transfer signal indicating 1 (high level) sequentially as a line scanning signal in accordance with a normal phase clock signal and a reverse phase clock signal. To supply. The NAND logic element 60 supplies line scanning signals to pixel circuit groups B1, B2,. According to the buffer 33 electrically inserted in the middle of the wiring 31 for supplying the start pulse to the shift register circuit SR, the start pulse or the transfer signal can be stably supplied as in the buffer 32. Each stage can be supplied. According to each stage SRi of the shift register circuit SR, when a normal phase clock signal and a reverse phase clock signal are input from the clock signal input terminals CL1 and CL2, the transfer signal is transferred to the next stage.

  As described above, according to the printer head 100, not only can the parasitic capacitance generated when the clock signal is supplied from the clock signal supply line 30 to the scanning circuit 17, but also the shift register included in the scanning circuit 17 can be reduced. It is also possible to reduce the load on the circuit SR. Therefore, not only can the clock signal be transmitted in the printer head 100 at high speed, but also the reliability of the printer head can be improved.

(Printer)
Next, an embodiment related to a printer including the above-described printer head 1 will be described in detail with reference to FIG. FIG. 7 is a schematic sectional view showing the main configuration of the printer according to this embodiment. In the following embodiment, a color printer having four printer heads 1 for YMCK will be described as an example.

  In FIG. 7, the printer 1000 includes four image forming units 1001Y, 1001M, 100C, and 1001K for YMCK, each of which includes a photosensitive drum 1002 as an example of the “photosensitive member” according to the present invention and its surroundings. And a developing device 1013 which is an example of the “developing unit” according to the present invention.

  Next, the configuration of the printer 1 according to the present embodiment will be described together with its operation.

  In FIG. 7, after the toner remaining on the surface of the photosensitive drum 1002 in the previous cycle is removed by the cleaner 1011, the surface of the photosensitive drum 1002 is charged by corona discharge or the like by the charger 1012 for the current cycle. . Subsequently, an electrostatic latent image corresponding to the data signal is formed on the surface of the photosensitive drum 1002 by exposure corresponding to the data signal by the printer head 1 of the above-described embodiment. Subsequently, by using toner of a color corresponding to each unit among Y (yellow), M (magenta), C (cyan), and K (black), development is performed by the developing device 1021, and the photosensitive drum 1002 is developed. A toner image that is a visible image by toner adhesion is formed on the surface. On the other hand, the transfer belt 1020 is rotated by rollers 1021, 1022, and the like. Then, the toner image on the photosensitive drum 1002 is transferred onto the transfer belt 1020 while being pressed from the back side by the transfer roller 1014 at the transfer position facing each photosensitive drum 1002. The transferred toner image is further transferred onto a sheet such as a copy sheet conveyed by the conveying device 1030. Then, the image-formed paper is discharged onto a discharge tray via a fixing device (not shown).

  As described above, the printer 1000 according to this embodiment includes the above-described printer head 1 or 100, so that the photosensitive drum 1002 can be exposed at high speed and with high resolution. In addition, the size of the printer can be reduced by downsizing the printer head 1. In particular, in FIG. 7, the printer head 1 can be easily formed in a desired length as the longitudinal direction in the direction of the rotation axis of the photosensitive drum 1002, and further along the circumferential direction of the photosensitive drum 1002. The length of the printer head 1 in this direction is nothing but the length in the short direction, and can be very short. Therefore, it is very advantageous to apply the printer head 1 as in this embodiment to a printer having a configuration in which various devices are arranged around the photosensitive drum 1002 as shown in FIG. Also in such a printer 100, the printer head 1 or 100 can be miniaturized to a required size and can transmit a clock signal or the like at high speed.

  The present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. A printer provided with this is also included in the technical scope of the present invention.

1 is a perspective view schematically showing a configuration of a printer head according to an embodiment of the present invention. FIG. 2 is a schematic partial enlarged plan view of a printer head according to the present embodiment. FIG. 3 is a block diagram illustrating an electrical connection state of the printer head according to the embodiment. FIG. 2 is an enlarged plan view illustrating a part of the printer head according to the embodiment. It is the VV 'sectional view taken on the line of FIG. It is the block diagram which showed the electrical connection state of the printer head concerning other this embodiment of this invention. 1 is a schematic cross-sectional view showing a main configuration of a printer according to an embodiment of the present invention.

Explanation of symbols

1,100 Printer head, TR1 control transistor, TR2 drive transistor, 201 pixel unit, 11 light emitting unit, 17 scanning circuit, 21 clock control circuit, 40 power supply line, 30 clock signal supply line, 50 ground wiring, OLED EL Device 101, 201 drain electrode, 102, 202 gate electrode, 103, 203 source electrode, 1000 printer,

Claims (4)

On the board
A line-shaped array includes current-driven light-emitting elements for exposing the photosensitive member, and a data signal for defining a drive current flowing through the light-emitting elements is written in accordance with sequentially supplied line scanning signals. A plurality of pixel circuits configured to be
A line scanning circuit for sequentially supplying the line scanning signals to the plurality of pixel circuits;
A clock signal supplied via a clock signal supply line including a portion extending in the arrangement direction of the plurality of pixel circuits is selectively supplied to the line scanning circuit via a clock signal output line. Clock signal supply means for
In order to supply power to the line scanning circuit, it is provided between the clock signal supply means and the line scanning circuit as viewed in plan on the substrate, and the arrangement direction in which the plurality of pixel circuits are arranged And a power supply line including a portion extending in a line along the clock signal output line and crossing the clock signal output line ,
The clock signal supply means includes a plurality of first unit circuits that are electrically connected in parallel to the clock signal supply line and selectively supply the single-phase clock signal to the line scanning circuit. And
The line scanning circuit includes a plurality of second unit circuits arranged in correspondence with the plurality of first unit circuits along the arrangement direction of the plurality of pixel circuits, respectively, and outputting the clock signal, respectively.
Each of the plurality of second unit circuits supplies a clock supply control signal for controlling the supply of the clock signal to the clock signal supply means,
The clock signal supply means counts the clock supply control signal supplied from each of the plurality of second unit circuits, and selects the second unit circuit that requires the clock signal, thereby the line scanning circuit. Selectively supplying the clock signal to
A printer head characterized by that. The line scanning circuit is disposed between the power supply line and a ground-side wiring including a portion extending in a line along the arrangement direction when viewed in plan on the substrate. The printer head according to claim 1. The substrate is arranged in a line on the substrate and includes current-driven light-emitting elements for exposing the photosensitive member, and defines a drive current that flows through the light-emitting elements in accordance with sequentially supplied line scanning signals. A printer head drive circuit for driving a printer head comprising a plurality of pixel circuits configured to write data signals,
On the substrate,
A line scanning circuit for sequentially supplying the line scanning signals to the plurality of pixel circuits;
A clock signal supplied via a clock signal supply line including a portion extending in the arrangement direction of the plurality of pixel circuits is selectively supplied to the line scanning circuit via a clock signal output line. Clock signal supply means for
In order to supply power to the line scanning circuit, it is provided between the clock signal supply means and the line scanning circuit as viewed in plan on the substrate, and the arrangement direction in which the plurality of pixel circuits are arranged And a power supply line including a portion extending in a line along the clock signal output line and crossing the clock signal output line ,
The clock signal supply means includes a plurality of first unit circuits that are electrically connected in parallel to the clock signal supply line and selectively supply the single-phase clock signal to the line scanning circuit. And
The line scanning circuit includes a plurality of second unit circuits arranged in correspondence with the plurality of first unit circuits along the arrangement direction of the plurality of pixel circuits, respectively, and outputting the clock signal, respectively.
Each of the plurality of second unit circuits supplies a clock supply control signal for controlling the supply of the clock signal to the clock signal supply means,
The clock signal supply means counts the clock supply control signal supplied from each of the plurality of second unit circuits, and selects the second unit circuit that requires the clock signal, thereby the line scanning circuit. Selectively supplying the clock signal to
A printer head drive circuit. A printer head according to claim 1 or 2 ,
The photoreceptor;
Developing means for forming a visible image by developing an electrostatic latent image formed on the photoreceptor by exposure by the printer head;
An image forming apparatus comprising: transfer means for transferring the formed visible image onto a recording medium.

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