JP2008147298A - Semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor memory device which suppresses the etching of an element isolation insulating film when an insulating film formed between a control gate and a floating gate is etched. <P>SOLUTION: The method includes a step of forming a tunnel insulating film TI, polysilicon film 13, and an insulating film IN on a memory cell formation region, forming a gate insulating film GI on a peripheral circuit formation region, and forming a polysilicon film 14 on the above two regions, a step of etching the polysilicon film 14 on the memory cell formation region and peripheral circuit formation region until the gate insulating film GI on the peripheral circuit formation region is exposed, using a predetermined shape of hard mask pattern 51 formed on the polysilicon film 14, and a step of covering the peripheral circuit formation region with a resist 52, etching the surface-exposed insulating film IN on the memory cell formation region, and then etching the surface-exposed polysilicon films 13 and 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a field effect transistor having a stack gate type structure and a manufacturing method thereof.

  A so-called flash memory is known as a device capable of batch erasing among non-volatile semiconductor memory devices capable of electrically rewriting data. Since flash memory has excellent portability and shock resistance and can be erased electrically, the demand for flash memory has rapidly expanded in recent years as a storage device for small portable information devices such as portable personal computers and digital still cameras. Yes.

  This flash memory has a memory cell portion in which a plurality of flash memory cells are arranged in a matrix and a peripheral circuit portion in which a peripheral circuit for controlling the operation of the flash memory cells is formed. As each flash memory cell in the memory cell portion, there is one in which a stack gate type field effect transistor is formed. This stacked gate type field effect transistor has a gate structure in which a tunnel insulating film, a floating gate, an insulating film, and a control gate are stacked in order on a well surface in a semiconductor substrate, and the line width of the gate structure. Source / drain regions formed on well surfaces on both sides in the direction. Here, as the insulating film in the gate structure, an ONO (Oxide-Nitride-Oxide) film having a laminated structure of a first oxide film, a nitride film, and a second oxide film in order from the bottom is generally used. It is. In one peripheral circuit portion, a gate structure in which a gate insulating film and a gate electrode are sequentially stacked at a predetermined position on the well surface in the semiconductor substrate, and a well structure on both sides of the gate structure in the line width direction are formed. A field effect transistor having source / drain regions is formed.

  In the manufacture of such a flash memory, conventionally, the control gate and the peripheral gate are patterned by simultaneously etching the control gate of the memory cell portion and the gate electrode (hereinafter also referred to as the peripheral gate) of the peripheral circuit portion. The method was adopted.

  By the way, with the recent progress of miniaturization of semiconductor memory devices, the peripheral gate insulating film tends to be thinned in order to improve the transistor performance (current drive capability) of the peripheral circuit portion. Also, with respect to the flash memory cell in the memory cell portion, the ONO film, which is an insulating film formed between the control gate and the floating gate, cannot be thinned in order to improve the coupling ratio. It is necessary to increase the thickness.

  In such a situation, if the control gate of the flash memory cell of the memory cell portion and the peripheral gate of the peripheral circuit portion are to be etched simultaneously, the etching of the polysilicon on the peripheral gate insulating film of the peripheral circuit portion is stopped simultaneously. There is a problem in that it is difficult to achieve a sufficient etching amount at a deep location of the control gate in the memory cell portion (between the floating gate and the floating gate). That is, it is difficult to suppress both penetration of the peripheral gate insulating film and control gate etching residue. Therefore, conventionally, the peripheral gate of the peripheral circuit portion and the control gate of the flash memory cell of the memory cell portion are separately etched.

  10-1 to 16-5 are diagrams showing a conventional example of a method for manufacturing a general flash memory as a semiconductor memory device. 10-1 to 10-5 are top views showing a conventional example of a method for manufacturing a memory cell portion, and FIGS. 11-1 to 11-5 are shown in FIGS. 10-1 to 10-5, respectively. FIGS. 12-1 to 12-5 are cross-sectional views taken along line BB in the memory cell portion shown in FIGS. 10-1 to 10-5, respectively. 13-1 to 13-5 are CC cross-sectional views in the memory cell portion shown in FIGS. 10-1 to 10-5, respectively. FIGS. 14-1 to 14-5 are FIGS. 1 to 10-5 are DD cross-sectional views in the memory cell portion, and FIGS. 15-1 to 15-5 are top views showing a conventional example of a method for manufacturing a peripheral circuit portion. -1 to 16-5 are EE breaks in the peripheral circuit portions shown in FIGS. 15-1 to 15-5, respectively. It is a diagram.

  First, a flash memory is formed in a memory cell formation region on a semiconductor substrate 1 such as silicon on which an element isolation insulating film 2 is formed by a known method, and a peripheral circuit is formed in a peripheral circuit formation region. In the memory cell formation region, for example, a polysilicon film 13 to be a tunnel insulating film TI and a floating gate FG is deposited on the semiconductor substrate 1, and the polysilicon film 13 is separated between adjacent regions separated by the element isolation insulating film 2. Patterning into a predetermined shape so as not to contact. An insulating film IN such as an ONO film and, for example, a polysilicon film 14 that becomes the control gate CG are formed thereon. Then, a hard mask pattern 51 is formed at a position where the control gate CG is to be formed (FIGS. 10-1, 11-1, 12-1, and 13-1 to 14-1). Further, in the peripheral circuit formation region, as shown in FIG. 16A, the gate insulating film GI and the polysilicon film 14 are sequentially formed on the semiconductor substrate 1, and the hard mask pattern 51 is formed at the position where the peripheral gate is formed. (FIGS. 15-1 and 16-1). Here, the polysilicon film 14 and the hard mask pattern 51 are formed simultaneously in the memory cell formation region and the peripheral circuit region.

  Next, a resist 53 is applied to the entire surface of the semiconductor substrate 1 on which the hard mask pattern 51 is formed, and the resist 53 is etched so that only the peripheral circuit formation region is exposed (FIGS. 10-2, 11-2, FIG. 12-2, FIG. 13-2, FIG. 14-2). That is, the memory cell formation region is covered with the resist 53. In this state, using the hard mask pattern 51 in the peripheral circuit formation region as a mask, the polysilicon film 14 is etched until the gate insulating film GI is exposed (FIGS. 15-2 and 16-2). As a result, the gate electrode GE is patterned in the peripheral circuit formation region.

  After removing the resist 53 in the memory cell formation region, a resist 54 is applied again on the entire surface of the semiconductor substrate 1 on which the hard mask pattern 51 is formed, and the resist 54 is etched so that only the memory cell formation region is exposed ( FIGS. 15-3 and 16-3). That is, the peripheral circuit formation region is covered with the resist 54. In this state, using the hard mask pattern 51 in the memory cell formation region as a mask, the polysilicon film 14 is etched until the insulating film IN is exposed (FIGS. 10-3, 11-3, 12-3, and 13). -3, Fig. 14-3). As a result, a control gate CG is formed in the memory cell formation region.

  Subsequently, the insulating film IN is etched in the memory cell formation region (FIGS. 10-4, 11-4, 12-4, 13-4, 14-4, 15-4, and 16-4). ). At this time, the etching is performed under the condition that the insulating film IN is etched but the polysilicon film 13 is not etched. Therefore, the insulating film IN formed on the element isolation insulating film 2 is also removed. Subsequently, the polysilicon film 13 is etched at a position where the flash memory cell is not formed in the memory cell formation region (FIGS. 10-5, 11-5, 12-5, 13-5, 14-5, FIG. 15-5 and FIG. 16-5). As a result, the floating gate FG is formed in the memory cell formation region. Thereafter, by removing the resist 54 in the peripheral circuit formation region, the gate processing of the flash memory cell is completed. A flash memory is manufactured by forming diffusion layers and sidewalls by a conventionally known method.

  With the miniaturization of the semiconductor memory device, in the stacked gate flash memory, simultaneous etching of the control gate CG of the memory cell portion and the peripheral gate of the peripheral circuit portion becomes difficult, and the above-described FIGS. As shown in FIG. 5, the photolithography process must be divided and etched separately. As a result, since the photolithography process and the resist removal process are increased, there is a problem that the process cost is increased, and at the same time, the foreign matter is increased and the process yield is decreased.

  When the insulating film IN is etched in the memory cell portion, as shown in FIGS. 11-4, 12-4, 13-4, and 14-4, the polysilicon film 13 at the position where the flash memory cell is not formed and The element isolation insulating film 2 between the polysilicon film 13 has also been etched. When the amount of etching of the element isolation insulating film 2 increases, there is a possibility that the implantation type penetrates the thinned element isolation insulating film 2 in an ion implantation step for forming a source / drain region (diffusion layer) in a later step. As a result, the isolation breakdown voltage due to the element isolation insulating film 2 decreases. As a result, a pair bit failure or a pair bit line failure occurs, which causes a problem of reducing the yield of the flash memory.

  The present invention has been made in view of the above, and has a memory cell portion formed of a stack gate type field effect transistor, which has been miniaturized, and a peripheral circuit portion that controls the operation of the memory cell portion. In a semiconductor memory device, simultaneous etching of a control gate of a memory cell portion and a peripheral gate of a peripheral circuit portion is realized, and an element isolation insulating film at the time of etching an insulating film formed between the control gate and the floating gate is realized. It is an object of the present invention to obtain a semiconductor memory device and a manufacturing method thereof that can suppress etching.

  In order to achieve the above object, according to a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, a tunnel insulating film and an element are first formed on a memory cell formation region of a semiconductor substrate on which an element isolation insulating film is formed. A first polysilicon film patterned so as to sandwich the element isolation insulating film along the extending direction of the isolation insulating film, and an insulating film, and a peripheral circuit adjacent to the memory cell formation region of the semiconductor substrate A gate insulating film is formed over the formation region. Then, a second polysilicon film is formed on the memory cell formation region and the peripheral circuit formation region. Next, using the mask of a predetermined shape formed on the second polysilicon film in the memory cell formation region and the peripheral circuit formation region, the memory cell formation region and the peripheral region are exposed until the gate insulating film in the peripheral circuit formation region is exposed. The second polysilicon film in the circuit formation region is etched. Next, the peripheral circuit formation region is covered with a resist, the insulating film exposed on the surface is etched on the memory cell formation region, and then the first and second polysilicon films exposed on the surface are etched on the memory cell formation region. Thus, a floating gate and a control gate are formed.

  According to one embodiment of the present invention, the etching condition for forming the gate electrode in the peripheral circuit formation region can be set to a condition that the gate insulating film does not penetrate. In addition, since the etching of the gate electrode in the peripheral circuit formation region and the control gate in the memory cell formation region can be performed in the same process, a photolithography process is not added as in the conventional manufacturing method. The yield is improved. Further, since the second polysilicon film left between the first polysilicon films serving as floating gates functions as a mask during etching of the insulating film, etching of the element isolation insulating film under the adjacent floating gates is performed. It has the effect that can be prevented. As a result, in the ion implantation process of the memory cell formation region in a later process, impurity atoms can penetrate the element isolation insulating film, and a reduction in breakdown voltage between the isolation of the element isolation insulating film can be suppressed.

  Exemplary embodiments of a semiconductor memory device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to the embodiments. The cross-sectional views of the semiconductor memory device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones.

  In the following description, as a semiconductor memory device, a memory cell portion in which a plurality of flash memory cells made up of stacked gate type field effect transistors are arranged in a matrix, and a peripheral circuit that controls the operation of the flash memory cell An example of a flash memory having a peripheral circuit portion in which is formed will be described. There are various types of flash memory, such as NOR type and NAND type, but any type of flash memory can be used as long as a stack gate type field effect transistor is used in the memory cell portion. Embodiments can be applied.

  FIGS. 1-1 to 1-3 are diagrams schematically showing a configuration of a memory cell portion of a semiconductor memory device according to the present invention, and FIGS. 2-1 to 2-2 are semiconductor memory devices according to the present invention. It is a figure which shows typically the structure of the peripheral circuit part of an apparatus. 1-1 is a top view of the memory cell portion of the semiconductor memory device, FIG. 1-2 is a cross-sectional view taken along the line AA in FIG. 1-1, and FIG. It is -C sectional drawing. FIG. 2A is a top view of the peripheral circuit portion of the semiconductor memory device, and FIG. 2B is a cross-sectional view taken along line E-E in FIG. More specifically, FIGS. 1-2 and 2-1 schematically show the state of the cross section in the direction perpendicular to the word line, and FIG. 1-3 shows the cross section in the direction parallel to the word line. The state is shown schematically.

In the semiconductor memory device, a memory cell portion 10 and a peripheral circuit portion 30 are formed on a semiconductor substrate 1 such as silicon. As shown in FIGS. 1A to 1C, a stacked gate field effect transistor is formed in the memory cell unit 10. That is, the tunnel insulating film TI, the floating gate FG, the insulating film IN, and the control gate CG are sequentially stacked at a predetermined position on the well surface in the semiconductor substrate 1 separated by the element isolation insulating film 2 such as a SiO ₂ film. A stacked gate structure, sidewalls SW made of silicon nitride films or the like formed on both side surfaces of the floating gate FG, the insulating film IN, and the control gate CG in the line width direction; A stack gate type field effect transistor having source / drain regions formed on the well surface is formed as a flash memory cell. Here, the tunnel insulating film TI is made of a SiO ₂ film or the like, and the floating gate FG and the control gate CG are made of a polysilicon film or the like. The insulating film IN, and the first oxide film made of SiO ₂ film, a nitride film made of the Si ₃ N ₄ film, ONO film having a stacked structure of a second oxide film made of SiO ₂ film, etc. Consists of.

  Here, as shown in FIG. 1C, in the cross section of the flash memory cell in the direction parallel to the word line, the position of the surface of the element isolation insulating film 2 is the position where the insulating film IN is formed and the other positions. It is characterized by substantially the same at the position of.

Further, as shown in FIGS. 2-1 to 2-2, a normal field effect transistor is formed in the peripheral circuit unit 30. That is, a predetermined gate insulating film GI made of SiO ₂ film in the position of the well surface in the semiconductor substrate 1 with element separation realized by the element isolation insulating film 2 such as SiO ₂ film, a gate electrode GE made of polysilicon or the like in order Peripheral gate structure formed by stacking, sidewalls made of silicon nitride films or the like formed on both side surfaces in the line width direction of the gate electrode GE, and sources formed on well surfaces on both sides in the line width direction of the peripheral gate structure A field effect transistor having a / drain region is formed.

  Such a semiconductor memory device has a structure in which the thickness of the gate insulating film GI in the peripheral circuit section 30 is 30 mm or less and the thickness of the floating gate FG in the memory cell section 10 is 1,200 mm or more. Effective for storage devices.

  Next, a method for manufacturing a semiconductor memory device having such a configuration will be described. FIGS. 3A to 9D are diagrams schematically showing the procedure of the method of manufacturing the semiconductor memory device according to the present invention. FIGS. 3-1 to 3-4 are top views showing the procedure according to this embodiment of the method of manufacturing the memory cell portion, and FIGS. 4-1 to 4-4 are FIGS. 3-1 to 3 respectively. 4 is a cross-sectional view taken along line AA in the memory cell portion shown in FIG. 4, and FIGS. 5A to 5D are cross-sectional views taken along line BB in the memory cell portion shown in FIGS. FIGS. 6-1 to 6-4 are cross-sectional views taken along the line CC in the memory cell portion shown in FIGS. 3-1 to 3-4, respectively, and FIGS. FIG. 4 is a DD cross-sectional view of the memory cell portion shown in FIGS. 3-1 to 3-4, respectively. FIGS. 8-1 to 8-4 are top views showing the procedure according to this embodiment of the method for manufacturing the peripheral circuit portion, and FIGS. 9-1 to 9-4 are FIGS. It is EE sectional drawing in the peripheral circuit part shown by FIGS. 8-4. In the following description, a region on the semiconductor substrate 1 where the memory cell portion 10 is formed is referred to as a memory cell formation region, and a region on the semiconductor substrate 1 where the peripheral circuit portion 30 is formed is referred to as a peripheral circuit formation region.

  First, in a memory cell formation region, a polysilicon film 13 formed on the tunnel insulating film TI is patterned into a predetermined shape by a conventionally known method, and a polysilicon film serving as the insulating film IN and the control gate CG is formed thereon. 14 is formed. Further, a hard mask pattern 51 patterned in a predetermined (word line) shape is formed on the polysilicon film 14 (FIGS. 3-1, 4-1, 5-1 and 6-1, Fig. 7-1). In the peripheral circuit formation region, a polysilicon film 14 is formed on the gate insulating film GI, and a hard mask pattern 51 patterned into a predetermined (word line) shape is further formed thereon (FIG. 8- 1, FIG. 9-1). The polysilicon film 14 and the hard mask pattern 51 are formed simultaneously in the memory cell formation region and the peripheral circuit formation region.

  Specifically, the states shown in FIG. 3-1, FIG. 4-1, FIG. 5-1, FIG. 6-1, FIG. 7-1, FIG. Get. First, an element isolation insulating film 2 is formed in a predetermined region on the semiconductor substrate 1 by a method such as STI (Shallow Trench Isolation), and a predetermined conductivity type is formed in a region partitioned by the element isolation insulating film 2 by ion implantation. Forming wells. Next, the peripheral circuit formation region is masked with a resist, and a tunnel insulating film TI is formed on the well surface of the memory cell formation region by, eg, thermal oxidation. A polysilicon film 13 is deposited on the tunnel insulating film TI and the element isolation insulating film 2, and the polysilicon film 13 is not contacted between adjacent wells via the element isolation insulating film 2 by photolithography technique and etching technique. Perform patterning. Thereafter, an insulating film IN made of an ONO film is formed on the semiconductor substrate 1 on which the polysilicon film 13 is patterned.

  After the mask on the peripheral circuit formation region is removed, the memory cell formation region is masked with a resist, and a gate insulating film GI is formed on the well surface of the peripheral circuit formation region, for example, by thermal oxidation. After removing the mask in the memory cell formation region, a polysilicon film 14 is formed on the insulating film IN in the memory cell formation region, on the gate insulating film GI in the peripheral circuit formation region, and on the element isolation insulating film 2. Further, a TEOS (TetraEthyl OrthoSilicate) oxide film is formed on the polysilicon film 14, and the TEOS oxide film is patterned into a predetermined (word line) shape by a photolithography technique and dry etching to form a hard mask pattern 51. . As a result, the structures shown in FIGS. 3-1, 4-1, 5-1, 6-1, 7-1, 8-1 and 9-1 are obtained.

  Next, using the hard mask pattern 51 as a mask, the polysilicon film 14 in the memory cell formation region and the polysilicon film 14 in the peripheral circuit formation region are simultaneously etched by dry etching (FIGS. 3-2, 4-2, and 5). -2, Fig. 6-2, Fig. 7-2, Fig. 8-2, Fig. 9-2). At this time, the etching is performed until the gate insulating film GI in the peripheral circuit formation region is exposed. In this state, the polysilicon film 14 sandwiched between adjacent stack gate structures in the memory cell formation region is in a half-etched state (FIG. 5-2). Here, overetching is performed so that the film thickness of the half-etched polysilicon film 14 remaining between the stack gates becomes thinner than the thickness of the polysilicon film 13 to be the floating gate FG. Further, since the etching at this time is performed under the condition that the selection ratio of the polysilicon film is larger than that of the silicon oxide film or the silicon nitride film, as shown in FIGS. 4-2 and 7-2. The insulating film IN functions as an etching stopper film. As a result, the gate electrode GE is formed in the peripheral circuit formation region.

  Thereafter, a resist is applied to the entire surface of the semiconductor substrate 1, and patterning is performed so that only the memory cell formation region is covered with the resist. Then, impurity atoms of a predetermined conductivity type are ion-implanted into the peripheral circuit formation region. As a result, diffusion layers to be the source / drain regions 12 are formed on the well surfaces on both sides in the line width direction of the gate electrode GE using the gate electrode GE and the hard mask pattern 51 in the peripheral circuit formation region as a mask.

  Next, after removing the resist on the memory cell formation region, a resist 52 is applied to the entire surface of the semiconductor substrate 1, and patterning is performed so that only the peripheral circuit formation region is covered with the resist 52 (FIGS. 8-3 and 8-3). Fig. 9-3). Thereafter, the insulating film IN is etched by dry etching using the control gate CG and the hard mask pattern 51 formed in FIGS. 3-2, 4-2, 5-2, 6-2, and 7-2 as a mask. (FIGS. 3-3, 4-3, 5-3, 6-3, and 7-3). Since the etching at this time is performed under the condition that the selection ratio of the silicon oxide film and the silicon nitride film is larger than that of the polysilicon film, only the portion where the insulating film IN (ONO film) is exposed on the surface is etched. Is done. That is, only the insulating film IN exposed between the stacked gate structures of FIG. 4B and the insulating film IN exposed on the polysilicon film 13 at the position where the flash memory cell of FIG. 3 and FIG. 7-3. On the other hand, a portion where the half-etched polysilicon film 14 between the stacked gate structures in FIG. 5-2 is exposed, or a polysilicon film 14 between the polysilicon film 13 and the polysilicon film 13 in FIG. In such a portion, the etching hardly progresses and remains as it is as shown in FIGS. 5-3 and 7-3.

  As shown in FIG. 7C, the polysilicon film 14 between the polysilicon film 13 and the polysilicon film 13 at the position where the polysilicon film 14 where the flash memory cell is not formed is removed is formed of the insulating film IN. Since it is not removed by etching, the element isolation insulating film 2 existing under the polysilicon film 14 is not removed (etched). That is, the polysilicon film 14 serves as a mask.

  Next, without removing the resist 52 formed on the peripheral circuit formation region, the polysilicon film 13 is subsequently etched at the position where the flash memory cell is not formed in the memory cell formation region (FIGS. 3-4 and 4-). 4, Fig. 5-4, Fig. 6-4, Fig. 7-4, Fig. 8-4, Fig. 9-4). Since the etching at this time is performed under the condition that the selection ratio of the polysilicon film is larger than that of the silicon oxide film or the silicon nitride film, only the polysilicon films 13 and 14 whose surfaces are exposed are removed. Thereby, the floating gate FG is formed. The thickness of the polysilicon film 14 between the floating gate FG (polysilicon film 13) and the floating gate FG (polysilicon film 13) is smaller than the thickness of the polysilicon film 13 to be etched. The polysilicon film 13 is simultaneously removed in a self-aligning manner when the polysilicon film 13 is etched.

  Specifically, the polysilicon film 13 whose surface is exposed between the stack gate structures as shown in FIG. 4-3 is etched until the tunnel insulating film TI is exposed as shown in FIG. 4-4. The Further, as shown in FIG. 5-3, the polysilicon film 14 whose surface is exposed between the stacked gate structures is etched until the insulating film IN is exposed as shown in FIG. 5-4. Further, as shown in FIG. 7-3, in the portion where the surfaces of the polysilicon films 13 and 14 are exposed at the position where the flash memory cell is not formed, as shown in FIG. Etching is performed until the TI and the element isolation insulating film 2 are exposed. Thereby, a stack gate structure is formed in the memory cell formation region.

  Thereafter, impurity atoms of a predetermined conductivity type are ion-implanted into the well surfaces on both sides in the line width direction of the stack gate structure in the memory cell formation region by a conventionally known method to form a diffusion layer to be a source / drain region. Further, sidewalls SW are formed on both sides in the line width direction of the stack gate structure in the memory cell formation region and the peripheral gate structure in the peripheral circuit formation region. Then, a multi-layer wiring process necessary for functioning as a flash memory is performed by a known technique to manufacture a flash memory. 3-4, FIG. 4-4, FIG. 5-4, FIG. 6-4, FIG. 7-4, FIG. 8-4, and FIG. 9-4 are processed by a conventionally known method. The description is omitted.

  According to this embodiment, when the polysilicon film 14 is etched to form the gate electrode of the field effect transistor in the peripheral circuit formation region, the polysilicon film 14 that simultaneously becomes the control gate CG in the memory cell formation region. Also etched. At this time, the etching was performed so that the polysilicon film 14 was left thinner than the polysilicon film 13 between the adjacent polysilicon films 13 to be the floating gates FG. As a result, the etching condition for forming the gate electrode GE in this peripheral circuit formation region can be set to a condition that the gate insulating film GI does not penetrate.

  Conventionally, the etching of the gate electrode GE in the peripheral circuit formation region and the etching of the control gate CG in the memory cell formation region are performed in separate steps, but in this embodiment, both are performed in the same step. Therefore, a photolithography process is not added as in the conventional manufacturing method. As a result, the process yield is improved.

  Further, since the polysilicon film 14 left between the polysilicon films 13 to be adjacent floating gates FG functions as a mask when the insulating film IN is etched, it is in a lower layer between the floating gates FG and FG. Etching of the element isolation insulating film 2 can be prevented. In addition, when the polysilicon film 13 is etched when forming the floating gate FG, the etching stops at the insulating film IN immediately below the remaining portion of the polysilicon film 14, and the lower layer between the floating gate FG and the floating gate FG. Etching of the element isolation insulating film 2 can be prevented. As a result, the element isolation insulating film 2 is prevented from being removed. Thereby, in the ion implantation process of the memory cell formation region in the subsequent process, the impurity atoms can penetrate the element isolation insulating film 2, and a decrease in breakdown voltage between the isolation of the element isolation insulating film 2 can be suppressed. And it has the effect that the yield of manufacture of flash memory improves.

  As described above, the method of manufacturing a semiconductor memory device according to the present invention is useful for a semiconductor memory device having a stack gate type field effect transistor in a memory cell portion and a normal field effect transistor in a peripheral circuit portion. It is.

1 is a top view of a memory cell portion of a semiconductor memory device according to the present invention. It is AA sectional drawing of FIGS. 1-1. It is BB sectional drawing of FIGS. 1-1. It is a top view of the peripheral circuit part of the semiconductor device concerning this invention. It is CC sectional drawing of FIGS. It is a top view which shows the procedure by this embodiment of the manufacturing method of a memory cell part (the 1). It is a top view which shows the procedure by this embodiment of the manufacturing method of a memory cell part (the 2). It is a top view which shows the procedure by this embodiment of the manufacturing method of a memory cell part (the 3). It is a top view which shows the procedure by this embodiment of the manufacturing method of a memory cell part (the 4). FIG. 3 is a cross-sectional view taken along the line AA in the memory cell portion shown in FIG. FIG. 3 is a cross-sectional view taken along line AA in the memory cell portion illustrated in FIG. 3-2 (part 2); FIG. 3 is a cross-sectional view taken along the line AA in the memory cell portion shown in FIG. FIG. 4 is an AA cross-sectional view of the memory cell portion shown in FIG. 3-4 (part 4); FIG. 3 is a BB cross-sectional view of the memory cell portion shown in FIG. FIG. 3B is a BB cross-sectional view of the memory cell portion illustrated in FIG. 3-2 (part 2). FIG. 3B is a BB cross-sectional view of the memory cell portion shown in FIG. FIG. 4B is a BB sectional view of the memory cell portion shown in FIG. 3-4 (part 4). FIG. 3 is a cross-sectional view taken along the line CC of the memory cell portion illustrated in FIG. FIG. 3 is a CC cross-sectional view of the memory cell portion shown in FIG. 3-2 (part 2); FIG. 3C is a cross-sectional view taken along the line CC in the memory cell portion illustrated in FIG. FIG. 4C is a cross-sectional view taken along the line CC in the memory cell portion illustrated in FIG. 3-4 (part 4). FIG. 3 is a DD cross-sectional view of the memory cell portion shown in FIG. FIG. 3 is a DD cross-sectional view of the memory cell portion shown in FIG. 3-2 (part 2); FIG. 4 is a DD cross-sectional view of the memory cell portion shown in FIG. FIG. 4D is a DD sectional view of the memory cell portion shown in FIG. 3-4 (part 4); It is a top view which shows the procedure by this embodiment of the manufacturing method of a peripheral circuit part (the 1). It is a top view which shows the procedure by this embodiment of the manufacturing method of a peripheral circuit part (the 2). It is a top view which shows the procedure by this embodiment of the manufacturing method of a peripheral circuit part (the 3). It is a top view which shows the procedure by this embodiment of the manufacturing method of a peripheral circuit part (the 4). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 8-1 (the 1). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 8-2 (the 2). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 8-3 (the 3). FIG. 8E is a cross-sectional view taken along line EE in the peripheral circuit portion illustrated in FIG. 8-4 (part 4). It is a top view which shows the prior art example of the manufacturing method of a memory cell part (the 1). It is a top view which shows the prior art example of the manufacturing method of a memory cell part (the 2). It is a top view which shows the prior art example of the manufacturing method of a memory cell part (the 3). It is a top view which shows the prior art example of the manufacturing method of a memory cell part (the 4). It is a top view which shows the prior art example of the manufacturing method of a memory cell part (the 5). It is AA sectional drawing in the memory cell part shown by FIGS. 10-1 (the 1). FIG. 10B is a cross-sectional view taken along the line AA in the memory cell portion illustrated in FIG. FIG. 10 is a cross-sectional view taken along line AA in the memory cell portion illustrated in FIG. FIG. 10B is a cross-sectional view taken along the line AA in the memory cell portion illustrated in FIG. 10-4 (part 4). FIG. 10A is a cross-sectional view along the line AA in the memory cell portion shown in FIG. 10-5 (part 5); FIG. 10B is a BB cross-sectional view of the memory cell portion illustrated in FIG. FIG. 10B is a BB sectional view of the memory cell portion shown in FIG. FIG. 10 is a BB sectional view of the memory cell portion shown in FIG. 10-3 (part 3); FIG. 10B is a BB sectional view of the memory cell portion shown in FIG. 10-4 (part 4). FIG. 10B is a BB sectional view of the memory cell portion shown in FIG. 10-5 (part 5); FIG. 10C is a cross-sectional view taken along the line CC in the memory cell portion illustrated in FIG. FIG. 10B is a cross-sectional view taken along the line CC in the memory cell portion illustrated in FIG. FIG. 10C is a cross-sectional view taken along the line CC in the memory cell portion illustrated in FIG. FIG. 10C is a CC cross-sectional view of the memory cell portion shown in FIG. 10-4 (part 4). FIG. 10C is a CC cross-sectional view of the memory cell portion shown in FIG. 10-5 (part 5); FIG. 10 is a DD cross-sectional view of the memory cell portion shown in FIG. FIG. 10D is a DD cross-sectional view of the memory cell portion shown in FIG. 10-2 (part 2); FIG. 10 is a DD cross-sectional view of the memory cell portion shown in FIG. 10-3 (part 3); FIG. 10D is a DD cross-sectional view of the memory cell portion shown in FIG. 10-4 (part 4); FIG. 10D is a DD sectional view of the memory cell portion shown in FIG. 10-5 (part 5); It is a top view which shows the prior art example of the manufacturing method of a peripheral circuit part (the 1). It is a top view which shows the prior art example of the manufacturing method of a peripheral circuit part (the 2). It is a top view which shows the prior art example of the manufacturing method of a peripheral circuit part (the 3). It is a top view which shows the prior art example of the manufacturing method of a peripheral circuit part (the 4). It is a top view which shows the prior art example of the manufacturing method of a peripheral circuit part (the 5). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 15-1 (the 1). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 15-2 (the 2). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 15-3 (the 3). It is EE sectional drawing in the peripheral circuit part shown by FIGS. 15-4 (the 4). FIG. 15E is a cross-sectional view taken along the line E-E in the peripheral circuit section illustrated in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation insulating film 10 Memory cell part 11 Stack gate structure 12, 32 Source / drain region 13, 14 Polysilicon film 30 Peripheral circuit part 31 Gate structure CG Control gate GE Gate electrode GI Gate insulating film FG Floating gate IN Insulating film SW Side wall TI Tunnel insulating film

Claims (6)

A stack gate structure composed of a stack of a tunnel insulating film, a floating gate, an insulating film, and a control gate is formed at a predetermined position on the semiconductor substrate partitioned by the element isolation insulating film. A memory cell portion in which stacked gate field effect transistors having source / drain regions formed on the surface of the semiconductor substrate are arranged as a flash memory cell in a matrix on the semiconductor substrate;
A peripheral gate structure composed of a laminate of a gate insulating film and a gate electrode is formed at a predetermined position on the semiconductor substrate partitioned by an element isolation insulating film, and the peripheral gate structure is formed on the surface of the semiconductor substrate on both sides in the line width direction. A peripheral circuit portion formed adjacent to the memory cell portion, including a field effect transistor in which a source / drain region is formed;
With
The upper surface of the element isolation insulating film of the memory cell portion has substantially the same height in the element isolation insulating film, and is formed on the element isolation insulating film with the element isolation insulating film interposed therebetween. A semiconductor memory device, wherein the insulating film having a stack gate structure is formed. A first polycrystal patterned so as to sandwich the element isolation insulating film along the extending direction of the element isolation insulating film on the memory cell formation region of the semiconductor substrate on which the element isolation insulating film is formed. Forming a silicon film and an insulating film; forming a gate insulating film on a peripheral circuit forming region adjacent to the memory cell forming region of the semiconductor substrate; and further forming a gate insulating film on the memory cell forming region and the peripheral circuit forming region. A first step of forming two polysilicon films;
A second step of forming a mask having a predetermined shape on the second polysilicon film in the memory cell formation region and the peripheral circuit formation region;
Etching the memory cell formation region and the second polysilicon film in the peripheral circuit formation region until the gate insulating film in the peripheral circuit formation region is exposed using the mask;
A fourth step of covering the peripheral circuit formation region with a resist;
A fifth step of etching the insulating film exposed on the surface of the memory cell formation region;
A sixth step of etching the first and second polysilicon films exposed on the surface of the memory cell formation region to form a floating gate and a control gate;
A method for manufacturing a semiconductor memory device, comprising:   In the third step, the first polysilicon film is left under a condition that the second polysilicon film remains on the insulating film between the adjacent second polysilicon films etched on the memory cell formation region. The method of manufacturing a semiconductor memory device according to claim 2, wherein the polysilicon film is etched.   In the fifth step, the second polysilicon film remaining on the insulating film between the adjacent second polysilicon films etched on the memory cell formation region is exposed to the surface using the second polysilicon film as a mask. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein the insulating film is etched.   In the third step, the film thickness of the second polysilicon film remaining on the insulating film between the adjacent second polysilicon films etched on the memory cell formation region is set to be the first thickness. 5. The method of manufacturing a semiconductor memory device according to claim 2, wherein the etching is performed so as to be smaller than the thickness of the polysilicon film.   In the sixth step, the first and second polysilicon films exposed on the surface are etched using the insulating film formed on the element isolation insulating film as an etching stopper film. Item 6. A method for manufacturing a semiconductor memory device according to Item 5.

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