JP2008146205A - Control signal arbitration method in digital voice signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control signal arbitration method in a digital voice signal processor which can perform the bi-directional communication of a control signal between boards having digital voice processing circuits, is small in the number of wiring and is free from problem due to interference with a voice signal. <P>SOLUTION: The control signal arbitration method in the digital voice signal processor which is equipped with at least two modules 20 and in which a word clock with frequency being the same as the sampling frequency of a voice signal is distributed to each module 20 and a voice signal is serially transferred between those modules 20 synchronously with the word clock, includes: counting the word clock; performing a predetermined arithmetic operation with the counting result; acquiring a transmission right to a shared bus line La when the arithmetic result by the predetermined arithmetic operation is matched with the unique value of the module and transmitting a control signal to the shared bus line La with the same transfer clock as the serial transfer clock of the voice signal; and receiving the control signal only when acquiring reception authority. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to transmission / reception of control signals between modules mounted on a digital audio signal processing apparatus, and to a control signal arbitration method in a digital audio signal processing apparatus having an arbitration function for the control signals.

  A digital audio signal processing device such as an audio digital mixer has a plurality of substrates having various roles such as decoding of input / output audio signals, encoding processing, digital signal processing such as equalizer and compressor, or communication processing with an operation panel. It is necessary to transmit and receive information other than audio signals (hereinafter referred to as control signals) between the mounted substrates. As a specific example, a control signal from an operation panel such as a volume position is first received by a communication processing board in the apparatus, and the communication processing board changes another parameter such as a filter coefficient according to the control content. Send new parameters to the signal processing board. In addition, since the status of the device is displayed on the operation panel in real time on an LED or display, each board in the device needs to transmit its status to the communication processing board, and moreover, multiple signal processing Some parameters may be shared between substrates.

  Conventionally, control signal communication between boards in the apparatus uses a CPU data bus, or uses a one-to-one serial communication represented by a 4-wire SPI (Serial Peripheral Interface) or RS422, Alternatively, communication is performed using a general protocol such as Ethernet (registered trademark) or Arcnet that can transmit and receive data to and from a plurality of nodes.

  In an apparatus in which a plurality of CPU boards are mounted, when accessing a shared memory, arbitration for determining and accessing the transmission and reception right order is necessary to avoid data collision, and FIG. 8 shows conventional shared bus arbitration. Shows the system. In this shared bus arbitration system, CPUs 1 to 3 that perform predetermined arithmetic processing according to tasks performed by the shared bus arbitration system, a RAM (Random Access Memory) 4 made of a semiconductor memory, and external data are input. The data can be output (transmitted) to the CPUs 1 to 3 via the input / output buses 1b to 3b, and the data output from the CPUs 1 to 3 can be input via the input / output buses 1b to 3b An input / output port 5 capable of outputting data via the input / output buses 1b to 3b, a system clock is input, a system clock generation circuit 15 is input, the system clock is input, and a counter is synchronized with the system clock. The counter 14 that updates the value and the signals shared by the CPUs 1 to 3 and sent from the RAM 4 and the input / output port 5 are input to the CPUs 1 to 3. And it conveyed, the shared bus 16 for transmitting an output signal to RAM4 and output port 5 from CPU1～3, an arbitration circuit 11 to 13 are schematic configuration from the register 7-9 Prefecture as. The registers 7 to 9 store the drive numbers of the CPUs 1 to 3, give the drive numbers to the arbitration circuits 11 to 13, and the arbitration circuits 11 to 13 are predetermined based on the counter value and the drive number supplied from the counter 14. The operation clocks 1 a to 3 a are supplied to the CPUs 1 to 3. That is, the predetermined CPUs 1 to 3 are given transmission and reception rights for processing using the shared bus, and can operate without collision between the control signals.

  In this shared bus arbitration system, shared bus arbitration is achieved with a relatively small circuit configuration, and the capacity of the shared memory, which is often used in a conventional method in which a plurality of CPUs access a shared memory using a dedicated bus, is used. The shared bus arbitration system is disclosed which can eliminate the increase in the number of CPUs, contribute to the reduction of the chip size, and can easily cope with the change in the number of CPUs sharing the shared bus. (For example, see Patent Document 1)

Japanese Patent Laying-Open No. 2006-31426 (Description [0029] to [0040], Drawing 1)

  Conventionally, in a communication method between substrates in an apparatus, when a CPU bus (internal bus) is used, the number of signal lines used in the apparatus for parallel transfer is very large. Similarly, in the case of a 4-wire SPI or RS422 interface, the number of signal lines increases as the number of substrates increases in order to connect substrates (nodes) one-to-one.

  On the other hand, in an interface using serial communication that can be connected in a bus format such as Ethernet (registered trademark) or Arcnet, the number of signal lines to be wired in the apparatus is small. However, there are the following problems. It is necessary to wire not only the control signal line but also the audio signal line in the apparatus. In the case of a general protocol such as Ethernet (registered trademark) or Arcnet, the data transfer speed cannot be freely changed, and cannot be synchronized with an audio signal. Therefore, when these protocols are used, there arises a problem of malfunction due to interference with the audio signal. In such a case, it is necessary to take measures such as separating the wiring board.

  As a method for communicating control signals between substrates, a method of interrupting a control signal into a part of an audio signal, such as the channel status of AES / EBU (Audio Engineering Society / European Broadcast Union), is conceivable. Not all have audio signal input and output. There are boards that have no input / output of audio signals, such as boards that have only input, boards that have only output, and communication processing boards. In the end, if control signals are transmitted bidirectionally between arbitrary boards, a new audio signal line dedicated to control signal communication is required. Accordingly, since the audio signal lines are connected one-to-one, the number of wirings becomes enormous as the number of substrates increases as in the SPI and RS422.

  The present invention has been made in view of the above problems, and can perform two-way communication of control signals between arbitrary boards in the apparatus, has a small number of wires, and has no problems due to interference with audio signals. It is an object to provide a control signal arbitration method in an apparatus.

The present invention achieves the above-mentioned object, and the invention of claim 1 has at least two modules, and a word clock having the same frequency as the sampling frequency of the audio signal is distributed to each module. In the control signal arbitration method in the digital audio signal processing apparatus that serially transfers the audio signal between the modules in synchronization with the word clock,
Counting the word clock, performing a predetermined calculation with the counting result, obtaining a transmission right to the shared bus line when the calculation result by the predetermined calculation matches the eigenvalue of the module, and a serial transfer clock of the audio signal A control signal is transmitted to the shared bus line with the same transfer clock, and the control signal is arbitrated so that the control signal is received only when a reception right is obtained from the shared bus line. This is a control signal arbitration method.

The invention of claim 2 is the control signal arbitration method in the digital audio signal processing device of claim 1,
The word lock is a control signal arbitration method that synchronizes serial transfer of the audio signal and sets the sampling period by pulses having different duty ratios.

The invention of claim 3 is the control signal arbitration method in the digital audio signal processing device of claim 1,
In the control signal arbitration method, the word lock is counted based on a word clock having a specific duty ratio among the word clocks including the different duty ratios.

According to a fourth aspect of the present invention, in the control signal arbitration method in the digital audio signal processing device according to the first aspect,
The control signal arbitration method is characterized in that the predetermined calculation is a modular calculation of the count result and a value related to the number of modules.

In the first aspect of the present invention, a word clock having at least two modules and having the same frequency as the sampling frequency of the audio signal is distributed to each module, and the audio signal is transmitted between the modules in synchronization with the word clock. In the control signal arbitration method in the digital audio signal processing apparatus for serial transfer,
Counting the word clock, performing a predetermined calculation with the counting result, obtaining a transmission right to the shared bus line when the calculation result by the predetermined calculation matches the eigenvalue of the module, and a serial transfer clock of the audio signal A control signal is transmitted to the shared bus line with the same transfer clock, and the control signal is arbitrated so that the control signal is received only when a reception right is obtained from the shared bus line. Since the control signal arbitration method is used, wiring for control signal communication can be reduced because only one shared bus line is required regardless of the number of substrates. Therefore, downsizing is facilitated and man-made costs can be reduced. Therefore, there is an advantage that an apparatus or a system can be provided at a low cost. Furthermore, since each module is connected to the shared bus line, one-to-one communication as well as one-to-many communication is possible, and there is an advantage that flexible communication is possible. Further, since the transfer clock to the shared bus line is the same as the transfer clock of the audio signal, interference between the audio signal and the control signal is eliminated. Therefore, it is possible to send and receive stable audio signals, and there is an advantage that the quality as an audio processing circuit is improved.

According to a second aspect of the present invention, in the control signal arbitration method in the digital audio signal processing device according to the first aspect,
Since the word lock is a control signal arbitration method that synchronizes serial transfer of the audio signal and sets the sampling period by pulses having different duty ratios, a word clock having a specific duty ratio is detected. This makes it possible to synchronize a long cycle exceeding the sampling cycle on all the substrates in the apparatus. For example, it is possible to switch parameters in a plurality of substrates within the same sampling period. This eliminates the need for a dedicated signal line to synchronize the control, facilitates downsizing, and reduces the cost.

According to a third aspect of the present invention, in the control signal arbitration method in the digital audio signal processing device according to the first aspect,
The word lock count is a control signal arbitration method characterized in that the count is based on a word clock having a specific duty ratio among the word clocks including the different duty ratios. Since it is possible to determine which board has the transmission right depending on the number of word clocks counted from the number, it is possible to connect the shared bus line, and wiring of a synchronization signal for avoiding transmission collision Therefore, it is possible to avoid a collision in transmission / reception of a control signal or the like.

According to a fourth aspect of the present invention, in the control signal arbitration method in the digital audio signal processing device according to the first aspect,
The control signal arbitration method is characterized in that the predetermined calculation is a modular calculation of the count result and a value related to the number of modules, so that a count value from a word clock having a specific duty ratio is a fixed value. Therefore, even when the period of arrival of a word clock having a specific duty ratio is very long, the transmission or reception right of each board is given at a predetermined period.

  Hereinafter, an embodiment of a digital audio signal processing apparatus and a control signal arbitration method according to the present invention will be described with reference to FIGS. 1 is a block diagram showing an embodiment of a digital audio signal processing apparatus according to the present invention. FIG. 2 shows the phase relationship between the audio signal and the word clock, and FIG. 3 explains the word clock. FIG. 4 is a diagram showing the phase relationship between the word clock as a reference signal and the output to the shared bus line of the substrate. FIG. 5 shows a control flow in which one board in this embodiment controls On / Off of output to the shared bus line, and FIG. 6 shows On / Off timing of output to the shared bus line of each board in this embodiment. FIG. 7 is a diagram showing a data format of output data of the shared bus line in the present embodiment.

  In the present embodiment, as shown in FIG. 1, a plurality of substrates 20 are incorporated in a digital audio signal processing apparatus, and each substrate 20 includes a shared bus transmission circuit 21, a shared bus reception circuit 22, and control signal transmission / reception. It is comprised from the host 23 which requires. A bus line 24 for connecting each substrate 20 is provided in the apparatus. The bus line 24 has a signal line (hereinafter referred to as a shared bus line) La for transmitting a control signal and the like, a signal line Lb for transmitting a transfer clock, There is a signal line Lc for transmitting the word clock, and the word clock, the transfer clock, and the shared bus line are distributed to each substrate 20, and further, the shared bus transmission circuit 21, the shared bus reception circuit 22, and the host on each substrate 20. 23.

  The host 23 performs processing according to the role of the substrate. For example, if the board is a board that performs signal processing, such as an equalizer, the host 23 receives an audio signal from the host 23 of another board, performs a corresponding operation such as a digital filter, and the resulting audio signal. Is transmitted to the host 23 of another board. At that time, parameters such as a filter coefficient are obtained from a control signal received from the host 23 of another board such as a board that communicates with the operation panel. As described above, it is assumed that the host 23 needs to transmit and receive control signals to and from the host 23 on another board in addition to the audio signal.

  Further, the audio signal is transferred between the hosts 23 using a word clock and a transfer clock in a phase relationship as shown in the timing charts of FIGS. 2 (A), (B), (a) to (c). Shall. 2A and 2B show the relationship between the word clock and the audio signal in one cycle of the word clock. The period of the rising edge of the word clock is constant, the period is a sampling period, and the audio signal is composed of 32 words (words 0 to 31) having a word length of 32 bits per sampling period. 2A to 2C are waveform diagrams showing in detail the phase relationship at the rising edge to the word clock. FIG. 2A shows the waveform of the rising edge of the word clock, and FIG. ) Shows the waveform of the transfer clock for transmitting the audio signal, and FIG. 8C shows the audio data (D31 to D0) synchronized with the transfer clock. One word data of 32 bits is transferred MSB first, and the leading bit D32 of the word is transferred so that it is latched at the rising edge of the transfer clock immediately after the rising edge of the word clock.

  Note that the frequency of the transfer clock in FIG. 2B is set to sampling frequency × 1024 because 32-bit audio data is composed of one word in one sampling period and is composed of 32 words.

  Next, a method for transmitting and receiving control signals between the hosts 23 will be described. First, the word clock has a constant rising edge period (sampling period), but, as shown in FIG. 3, the pulse duty ratio has two pulses of 1/2 and 1/4. The pulses having a duty ratio of 1/4 appear once every fixed period, and all other pulses have a duty ratio of 1/2.

  Control signal transmission / reception between the hosts 23 is performed using the shared bus line La via the shared bus transmission circuit 21 and the shared bus reception circuit 22. The shared bus transmission circuit 21 has an on / off switching control of output to the shared bus line La and a function of receiving a control signal to be output from the host and sending it to the shared bus line La. First, output On / Off switching control to the shared bus line La will be described. On / Off switching to the shared bus line La is synchronized with the word clock, and at any given time, the board 20 that is On, that is, the board 20 to which the transmission right is granted is always shared, so that only one board is shared. Avoid output collisions on the bus line. In addition, the timing at which the output of the shared bus transmission circuit 21 is switched from Off to On is the rising edge of the word clock. However, the timing at which the output is switched from On to Off takes a switching margin, so 8 clocks before the transfer clock from the edge. In addition, it is assumed that one board 20 does not continuously turn on the word clock for two cycles or more, that is, does not continuously give a transmission right.

  The output On / Off timing in the shared bus transmission circuit 21 is illustrated in FIGS. 4A to 4C show the phase relationship when switching the shared bus transmission circuit 21 when the transmission right is transferred from the board 1 to the board 2, and FIG. 4A shows the waveform of the word clock. 4B shows a waveform diagram of an On / Off signal A output to the shared bus line La on the substrate 1 side, and FIG. 4C shows On waveform of the output to the shared bus line La on the substrate 2 side. The waveform diagram by the / Off signal A is shown.

  Next, the logic for giving the transmission right to each board 20 in order will be described. First, each board 20 has a unique node number, and the shared bus transmission circuit 21 of each board 20 has a processing function of sampling a word clock with a transfer clock. Furthermore, each shared bus transmission circuit 21 counts the transfer clock from the timing at which the duty ratio of the pulse of the word clock can be determined to be 1/2 or 1/4, that is, from the rising edge of the word clock. At the timing of 1024 = 384 clocks, a determination is made as to whether the condition is On or Off, and the determination is reflected in the transmission right switching at the next rising edge of the word clock.

  The condition determination at the timing of the 38th clock by the shared bus transmission circuit 21 will be described in detail with reference to the flowchart of FIG. In FIG. 5, step S1 determines whether the sampling value of the word clock pulse is high or low. This value is 3/8 of one cycle of the word clock because the condition judgment timing is low when a pulse with a duty ratio of 1/4 is detected, and the process proceeds to step S2 where a pulse with a duty ratio of 1/2 Is detected, it goes high, and the process proceeds to step S3. In step S2, the word clock count is cleared to zero. If the result of step S1 is high, the process proceeds to step S3, and the count number is incremented by one. After performing the processes of steps S2 and S3, the process proceeds to step S4, the modular calculation represented by [Equation 1] is performed on the count number, and the process proceeds to step S5. In step S5, the calculation result a of [Equation 1] is compared with its own node number. If they match, the process proceeds to step S6, and it is determined as output On. If they do not match, the process proceeds to step S7. to decide. Since the same word clock is distributed to all the boards 20, the calculation result a of [Equation 1] has the same value for all the boards 20. Accordingly, since all the node numbers to be compared with the value a are different for each substrate, the plurality of substrates 20 are not judged as output On. In this way, the shared bus transmission circuit 21 is provided with arbitration means for determining the transmission right by counting the transfer clock and the word clock, and the collision of outputs on the shared bus line La can be avoided.

  Next, a specific example of the modular calculation will be described. When the count number of word clock pulses is 200, the maximum node number is 15, and these values are substituted into the modular calculation formula of [Equation 1], the count is calculated. Since the remainder obtained by dividing the number 200 by the node number 16 is the operation result a, the operation result a is 8. For example, the number of substrates 20 is 4 and the number of substrates 2 is assigned node numbers 0 to 3, and the output On / Off timing of each substrate 20 to the shared bus line La is shown in FIGS. Shown in f). 6A to 6F, FIG. 6A shows the count number, FIG. 6B shows the word clock waveform, and FIGS. 6C to 6F show each node ( The On / Off timing for outputting the output of the substrate 20 to the shared bus line La is shown, and the outputs of the respective substrates 20 are never output to the shared bus line La at the same time during one sampling period. A transmission right is given to each board so that the shared bus line La can be used preferentially. The shared bus transmission circuit 21 to which the transmission right is given can transmit a control signal or the like from the host 23 via the shared bus line La.

  Next, the output function of the control signal from the host 23 to the shared bus line La of the shared bus transmission circuit 21 will be described. The control signal from the host 23 in the shared gas transmission circuit 21 is output to the shared bus line La only during the transmission right, that is, the word clock period when the output is On. When the control signal to be output from the host 23 is received when there is no transmission right, the shared bus transmission circuit 21 stores the control signal in the internal buffer and outputs it when the transmission right is next turned around. When the shared bus transmission circuit 21 outputs a control signal from the host 23 during the period of the output On when the transmission right is given, a transmission flag indicating to which board is transmitted is added before the control signal. For example, if a maximum of 16 boards 20 are provided and the node numbers 0 to 15 are set, the transmission flag is 16 bits, the first bit is the transmission flag to node number 0, and 2 from the top. The 16th bit from the head is given a transmission flag to the node number 15 as the transmission flag for the node number 1, and the 16th bit from the beginning. The logic of each transmission flag indicates that 0 is transmission to the board and 1 is not transmission to the board. For example, when the 16 bits are “0xFFFD”, the node number 14 is the reception board. It is also possible to transmit a plurality of transmission flags with 0 simultaneously, and distribute the same data to a plurality of substrates.

  The control signal requested to be transmitted from the host 23 is output from the 17th bit immediately after the 16-bit transmission flag. Accordingly, considering that the 8 bits immediately before the rising edge of the word clock are output off, the control signal that can be output during one clock of the word clock is 1024-16-8 = 1000 bits. 7A and 7B show data formats of output data output from the shared bus transmission circuit 21 to the shared bus line La. FIG. 4A is a waveform diagram of the word clock, and FIG. 4B shows the data format of the output output to the common bus line La corresponding to the word clock, and the output to the common bus line La. The data format is composed of a 16-bit transmission flag and a control signal from the host 23 consisting of 1000 bits. Output data to the common bus line La including the transmission flag is output in synchronism with the transfer clock by combining the leading bit of the rising edge of the word clock simultaneously with the transfer of the audio signal.

  The transmission right comes periodically regardless of whether or not there is a transmission request from the host 23. However, if there is no transmission request from the host 23, meaningless data is transmitted to other boards even if the transmission right arrives. In order to prevent reception, the shared bus transmission circuit 21 outputs all the transmission flags of the first 16 bits set to 1.

  The shared bus reception circuit 22 monitors the data output to the shared bus line La, and passes the subsequent 1000-bit control signal to the host 23 only when the transmission flag indicates transmission to itself. The transmission flag is checked by counting the transfer clock from the rising edge of the word clock. The transfer clock immediately after the rising edge of the word clock is the 0th clock, and only when the value from the shared bus of the clock number equal to its own node number is 0, the value of the shared bus after the 16th clock is hosted as received data. 23.

  Note that the shared bus line La is fixed to 1 while no substrate 20 outputs on. By setting in this way, even if there is a period in which no board 20 is turned on due to a missing node number, the transmission flags are all set to 1, so that any board 20 is in that period. Since the value from the shared bus line La is ignored, it is possible to prevent receiving meaningless data.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, although the transmission flag is 16 bits, if the number of nodes is not 16, the transmission flag may be increased. Conversely, if the number of nodes is small, the transmission flag is decreased. The control signal length may be increased. Also, the frequency of the transfer clock is set to sampling frequency × 1024, the word length of the audio signal is 32 bits, and 32 words are transferred in one sampling period, but this value is not essential. Depending on the capability of the transfer media used (TTL, RS485, LVDS, etc.), the transfer speed may be increased or decreased. The word length of the audio signal may be a smaller number of bits depending on the number of quantization bits when the analog audio signal is AD-converted. In addition, it is conceivable that the transfer capability of the shared bus line is inferior to the audio signal of one-to-one connection, but in such a case, the transfer clock is set to be faster according to the audio signal, It is also conceivable to reduce the transfer rate by thinning out the transfer clock. Further, although the On / Off switching margin is 8 transfer clocks, this length is not essential and may be changed according to the output buffer switching characteristics.

  The present invention is effective for an apparatus having a digital audio processing circuit and receiving complicated control from an operation panel or the like. In particular, since an audio adjustment console used in a studio of a broadcasting station has a multi-channel audio processing circuit, the present invention is suitable for an audio signal that does not interfere with a control signal. Moreover, even if it is a household acoustic product, when it uses for what has a several audio | voice processing board | substrate, since an audio | voice signal does not interfere with a control signal, the quality of an audio | voice signal improves and it becomes suitable as an audio equipment. .

It is a block diagram which shows one Embodiment of the audio | voice signal processing apparatus which concerns on this invention. (A), (B), (a)-(c) is the figure which showed the phase relationship of the audio | voice signal corresponding to the sampling period in this embodiment. It is explanatory drawing of the word clock in this embodiment. (A)-(c) is a figure which shows the phase relationship of the word clock and board | substrate output in this embodiment. It is a figure which shows the flowchart for setting a transmission or reception right by On / Off switching in this embodiment. (A)-(f) is a figure which shows the output On / Off timing of each board | substrate in this embodiment. (A), (b) is a figure which shows the data format of the data bus sent to the shared bus line in this embodiment. It is a block diagram which shows one Embodiment of the conventional audio | voice signal processing apparatus.

Explanation of symbols

20 module 21 shared bus transmission circuit 22 shared bus reception circuit 23 host 24 bus line La signal line (shared bus line)
Lb Signal line for transmitting transfer clock Lc Signal line for transmitting word clock Ld Signal line for audio signal

Claims (4)

Digital audio signal processing that has at least two modules, a word clock having the same frequency as the sampling frequency of the audio signal is distributed to each module, and the audio signal is serially transferred between the modules in synchronization with the word clock In the control signal arbitration method in the apparatus,
Counting the word clock, performing a predetermined calculation with the counting result, obtaining a transmission right to the shared bus line when the calculation result by the predetermined calculation matches the eigenvalue of the module, and a serial transfer clock of the audio signal A control signal is transmitted to the shared bus line with the same transfer clock, and the control signal is arbitrated so that the control signal is received only when a reception right is obtained from the shared bus line. Control signal arbitration method. The control signal arbitration method in the digital audio signal processing device according to claim 1,
A control signal arbitration method characterized in that the word lock synchronizes serial transfer of the audio signal and sets the sampling period by pulses having different duty ratios. The control signal arbitration method in the digital audio signal processing device according to claim 1,
The word lock count is based on a word clock having a specific duty ratio among the word clocks including the different duty ratios. The control signal arbitration method in the digital audio signal processing device according to claim 1,
The control signal arbitration method, wherein the predetermined calculation is a modular calculation of the counting result and a value related to the number of modules.

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