JPH0514416A - Data transmission system - Google Patents

Abstract

PURPOSE:To provide a transmission system in which the number of control lines between a CPU and each device is reduced. CONSTITUTION:A data line, a clock line and a write line are connected respectively between a parallel interface IC22 and serial parallel conversion ICs (23-1)-(23-n), an identification data to designate a reception destination is added to a data to be sent from a CPU 21 and the result is sent to each serial/parallel conversion IC, each serial conversion IC compares the data with an identification data allocated respectively thereto, a coincident serial/parallel conversion IC only is activated, the stored data is converted into a parallel data and it is sent to relating devices (24-1)-(24-n), and when a stored data is sent from the devices (26-1)-(26-n) and sent, an identification data designating a specific parallel/serial conversion IC is sent from the CPU, only the parallel serial conversion IC having an identification data allocated to itself is activated and the stored data is converted into a serial data and the result is sent to the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a data transmission system, especially C
The parallel data output from the PU is converted into serial data by the parallel interface IC and transmitted to a large number of serial-parallel conversion ICs, which are converted into parallel data by these serial-parallel conversion ICs and transmitted to peripheral devices. The present invention relates to a method in which parallel data from a large number of peripheral devices is converted into serial data by a parallel / serial conversion IC and transmitted to a parallel interface IC, where it is converted into parallel data and transmitted to a CPU.

[0002]

2. Description of the Related Art For example, in a camera for television broadcasting, various items such as pedestal level, gamma amplifier gain, flare, white clip, knee point, knee level, etc. are controlled, and auto iris on / off and flare on / off are controlled. Control of operations such as gamma switching and filter switching, and reading and displaying of aperture value, filter position, positions of various switches, and the like are performed.

In order to control and read or display the operating state, data is transmitted between the CPU provided in the camera and various equipment. Serial data from the CPU is transmitted to the equipment as parallel data. Alternatively, it is necessary to transmit parallel data from the device as serial data to the CPU. Therefore, conventionally, a parallel interface IC provided in the CPU board is used.

FIG. 1 shows a conventional configuration for outputting parallel data from a CPU as serial data to various devices. The CPU 1 is connected to a parallel interface IC 3 provided in a CPU board 2, and the parallel interface is connected to this parallel interface. , Serial-parallel conversion IC (hereinafter S
/ P conversion IC may be abbreviated) 4-1 to 4-n, and these S / P conversion ICs are connected to respective devices 5
1-5-n. Between the parallel interface IC3 and the S / P conversion ICs 4-1 to 4-n, the data line 6 and the clock line 7 are connected to the respective S / P conversion I.
The write lines 8-1 to 8-n are connected in parallel to the C data terminal and the clock terminal and the S / P conversion I
It is connected to the write terminal of C. The CPU 1 and the parallel interface IC 3 provided in the CPU substrate 2 may be housed in one package and used, but can be considered separately in terms of functionality.

The parallel interface IC 3 transfers all data and clocks via the data line 6 and the clock line 7 into S / P conversion ICs 4-1 and 4-.
n in parallel, then parallel interface IC
A specific S / P conversion IC selected by
A write signal is output to the write line 8-2 connected to the P conversion IC 4-2, only this S / P conversion IC 4-2 is activated, and the previously transmitted data is transmitted to the related device 5-2. To do.

FIG. 2 shows a conventional transmission system for inputting parallel data from various devices 15-1 to 15-n to the CPU 1 as serial data.
It is connected to a parallel interface 13 provided in the board 2, and this parallel interface is connected to each device 15-1.
Parallel-serial conversion IC (P
/ S conversion IC) 14-1 to 14-n. The mode of this connection is the data line 16 and the clock line 1.
7 is connected in parallel to the P / S conversion ICs 14-1 to 14-n and the chip select lines 18-1 to 18-n are respectively connected to the chip select terminals of the P / S conversion ICs 14-1 to 14-n. Connecting.

The parallel data output from each of the devices 15-1 to 15-n is the P / S conversion IC 14-1 to 14-n.
To be temporarily stored there. After that, the parallel interface IC 13 transmits a chip select signal to a specific chip select line, for example, 18-2, and the P / S connected to this chip select line.
This P / S conversion IC is activated by activating only the conversion IC 14-2.
The data stored in C is converted into serial data under the control of the clock transmitted from the CPU 1 via the clock line 17 and read via the data line 16,
It is transmitted to PU1.

[0008]

As described above, in the conventional camera, the parallel interface ICs 3 and 13 provided in the CPU board 2 and the various devices 5-1 to 5 are used.
-N and 15-1 to 15-n are connected to separate write lines 8-1 to 8-n and chip select lines 18-1 to 18-n, respectively.
There is a problem that the number of various control lines output from U becomes very large, which hinders downsizing of the camera. That is, the data lines 6, 16 and the clock lines 7, 17 are all S
/ P conversion ICs 4-1 to 4-n and P / S conversion IC 14
-1 to 14-n can be shared, but since the write lines 8-1 to 8-n and the chip select lines 18-1 to 18-n must be provided for each device, a parallel interface 3,13 and S / P conversion I
C4-1 to 4-n and P / S conversion ICs 14-1 to 14
The number of control lines connected to −n is extremely large, and reaches 80 or more, for example.

As described above, all the control lines are parallel interface ICs 3 and 13 provided in the CPU board.
Since it is connected to the pin, the number of this pin becomes very large, and there is a problem that the size cannot be reduced. Also, if you change the specifications of the camera or try to upgrade,
There is also a problem that there are not enough pins to connect the control lines, and it is difficult to deal with them.

The present invention solves the above-mentioned problems, remarkably reduces the number of control lines between the CPU and each device, can be downsized, and can easily cope with specification changes and version upgrades. It is intended to provide a transmission method.

[0011]

The data transmission system according to the first invention of the present application is such that a parallel interface IC is connected to a CPU, and the parallel interface IC is connected to the CPU.
Is connected to a plurality of serial / parallel conversion ICs connected to each of a plurality of devices, parallel data output from the CPU is converted to serial data by a parallel interface IC, and the serial data is transmitted to the plurality of serial / parallel conversion ICs. In converting the parallel data to the plurality of devices by using these serial-parallel conversion ICs, the data line, clock line and write line connected to the parallel interface IC are parallel to the plurality of serial-parallel conversion ICs. Connected, the data output from the CPU via the parallel interface IC is transmitted together with the identification data designating the receiving destination of the data, and this data is transmitted via the clock line in all serial-parallel conversion ICs. Under control of clock supplied Receives and accumulates, C in all of the serial-parallel conversion IC in response to a write signal to be transmitted through the write line at the end of the data transmission
Identification data for specifying the recipient transmitted from the PU,
The serial / parallel conversion ICs are compared with the identification data assigned in advance, and only the serial / parallel conversion ICs that match with each other are activated to convert the serial data transmitted from the CPU into parallel data and convert the serial data. -Transmission to a device connected to the parallel conversion IC is a feature.

Further, in the data transmission system according to the second invention of the present application, parallel data output from a plurality of devices is converted into serial data by a plurality of parallel-serial conversion ICs connected to each device, respectively. When the data is transmitted to the interface IC, converted into parallel data by the parallel interface IC and transmitted to the CPU, the data line, clock line and write line connected to the parallel interface IC are parallel to the plurality of parallel / serial conversion ICs. , Parallel data output from the plurality of devices are accumulated in respective parallel-serial conversion ICs, and CP
The identification data for designating the parallel-serial conversion IC from which data should be sent from the U to the CPU via the parallel interface IC and the data line is transferred to all parallel
The identification data is transmitted to the serial conversion ICs, and in each parallel / serial conversion IC, the identification data is received and accumulated under the control of the clock supplied via the clock line, and at the end of the identification data transmission, the parallel interface IC and the CPU All parallel-serial conversion ICs in response to a write signal supplied via a write line
In the above, the identification data transmitted from the CPU is compared with the identification data previously assigned to each parallel-serial conversion IC, and the parallel data
Only the serial conversion IC is activated, the parallel data output from the device connected to the parallel / serial conversion IC and accumulated therein is converted into serial data, and the data line and parallel interface I
It is characterized in that it is transmitted to the CPU via C.

In the data transmission method according to the third invention of the present application, a parallel interface IC is connected to the CPU, and the parallel interface IC is connected to a plurality of serial / parallel conversion ICs connected to each of a plurality of devices. The parallel data output from the CPU is converted into serial data by a parallel interface IC and transmitted to a plurality of serial / parallel conversion ICs, which are converted into parallel data by these serial / parallel conversion ICs and transmitted to a plurality of devices. , Parallel data output from a plurality of devices is converted into serial data by a plurality of parallel / serial conversion ICs connected to each device, transmitted to the parallel interface IC, and converted into parallel data by the parallel interface IC. To transmit to the CPU Or, wherein the plurality of parallel with connecting the connected data lines in parallel interface IC, a clock line and write line in parallel to the plurality of serial-parallel conversion IC
It is connected in parallel to the serial conversion IC, and the data output from the CPU via the parallel interface IC is transmitted together with the identification data designating the recipient of the data, and this data is transmitted in all the serial / parallel conversion ICs. Is received and stored under the control of the clock supplied via the clock line, and transmitted from the CPU in all serial-parallel conversion ICs in response to the write signal transmitted via the write line at the end of data transmission. The received identification data for designating the recipient is compared with the identification data previously assigned to the respective serial / parallel conversion ICs, and only the serial / parallel conversion ICs that match the two are activated and transmitted from the CPU. Convert the received serial data to parallel data and perform the serial-parallel conversion I Transmitted to the device connected to,
All the parallel data output from the plurality of devices are stored in the respective parallel / serial conversion ICs, and the identification data for designating the parallel / serial conversion ICs to which the data should be sent from the CPU via the parallel interface IC and the data line are all stored. Parallel / serial conversion IC
To each parallel-serial conversion IC, the identification data is received and stored under the control of the clock supplied via the clock line, and at the end of the identification data transmission, the parallel interface IC and the write line are transmitted from the CPU. The identification data transmitted from the CPUs in all the parallel / serial conversion ICs in response to the write signal supplied via the comparison are compared with the identification data previously assigned to the respective parallel / serial conversion ICs. Only the matched parallel-serial conversion IC is activated, and the parallel data supplied from the device connected to the parallel-serial conversion IC and accumulated in the device is converted into serial data, and the data line and the parallel interface IC are set. Specially for transmission to the CPU via It is an.

[0014]

According to the data transmission methods according to the above-mentioned first to third inventions, the parallel interface IC provided in the CPU board and the plurality of serial / parallel conversion ICs respectively connected to the plurality of devices. and/
Alternatively, since only one data line, one clock line, and one write line need only be connected to the parallel-serial conversion IC, the number of control lines between them can be significantly reduced compared to the conventional one. Therefore, the number of pins of the parallel interface IC can be correspondingly reduced, downsizing can be achieved, and specification changes and version upgrades can be easily dealt with.

In a preferred embodiment of the data transmission system according to the present invention, a busy line connected to the parallel interface IC is connected in parallel to the plurality of parallel / serial conversion ICs, and any one of the parallel / serial conversion ICs is connected. , When the data supplied from the device changes, the busy signal is transmitted to the CPU through this busy line and parallel interface IC, and CP
The U transmits the identification signal to all the parallel-serial conversion ICs only when it receives the busy signal. With such a configuration, the CPU only needs to read the data stored in the parallel-serial conversion IC only when the data from the device changes, so that the load on the CPU can be reduced.

[0016]

FIG. 3 is a block diagram showing the configuration of an embodiment of a data transmission system according to the present invention. In this example, various devices provided in the television camera are controlled, and the operation state is read and displayed. However, the present invention is not limited to such an application, and for example, a VTR or a television monitor. It can be applied to any device as long as it has a built-in microcomputer. When applied to a television camera, it can be roughly divided into two ways. One of them is for inputting / outputting data between the TV camera and the outside. It has a gain selector switch, color bar on / off switch, auto white balance channel selector switch, auto white balance start switch, filter selector switch. It controls the state of external switches such as a shutter changeover switch and a monitor select switch, and controls blinking of various lamps such as a tally lamp, a filter position indicator lamp, and a shutter position indicator lamp. The other is to read the control and operation state inside the camera, for example, control of a preamplifier and a process amplifier for processing an image and the state of these amplifiers. For example, in automatic white balance switching, when multiple sets are assembled in one studio, the white balance state is stored in advance for each set and the camera is moved between the sets. By occasionally switching the switches, it is possible to save the trouble of finely adjusting the white balance each time.

As shown in FIG. 3, a CPU 21 is connected to a parallel interface IC 22 provided in its substrate.
The parallel interface IC is connected to a plurality of serial / parallel conversion ICs 23-1 to 23-n, and these serial / parallel conversion ICs are connected to the respective devices 24-1 to 24-n. Further, the parallel interface IC 22 is further connected to a plurality of parallel / serial conversion ICs 25-1 to 25-n, and these parallel / serial conversion ICs are connected to the respective devices 26-1 to 26-1.
26-n.

In the present invention, the data line 27 for outputting data, the clock line 28, and the write line 29 connected to the parallel interface IC 22 are connected to the plurality of serial-parallel conversion ICs 23-1 to 23-n.
The data line 30, the clock line 31, and the write line 32 for data input connected to the parallel interface IC 22 are connected in parallel to the plurality of parallel-serial conversion ICs 25-1 to 25-n. The data line 27 for data output may be one for transmitting data in one direction from the parallel interface IC 22 to the plurality of serial / parallel conversion ICs 23-1 to 23-n, but the data line 30 for data input is a parallel interface. Data can be transmitted in both directions between the IC and the plurality of parallel-serial conversion ICs 25-1 to 25-n. Further, in this example, the busy line 33 connected to the parallel interface IC 22 is connected to a plurality of parallel / serial conversion I.
C25-1 to 25-n are connected in parallel.

Next, the operation of the data transmission system shown in FIG. 3 will be described. First, the CPU 21 to the devices 24-1 to 24-1.
The case of transmitting data to 24-n will be described with reference to the signal waveform diagram shown in FIG. First, the CPU 21 transmits the data shown in FIG. 4A to all the serial / parallel conversion ICs 23-1 to 23-n via the parallel interface IC 22 and the data line 27. This data is composed of m-bit transmission data DT and k-bit identification data ID. The identification data ID is
The destination of the transmission data DT is designated, and specific identification data is given to each of the serial / parallel conversion ICs 23-1 to 23-n.

FIG. 5 shows a serial / parallel conversion IC 23--
It is a block diagram which shows each detailed structure of 1-23-n. Each of the serial / parallel conversion ICs 23-1 to 23-n includes a shift register 41, a comparator 42, a latch 43, and an identification data setting unit 44,
The data line 27 and the clock line 28 are connected to the data and clock input terminals of the shift register 41, respectively, and the write line 29 is connected to the control terminal of the comparator 42. The identification data setting unit 44 is set so as to generate the identification data pre-assigned to each of the serial-parallel conversion ICs 23-1 to 23-n.

As shown in FIG. 4A, the transmission data DT (D1 to Dm) and the identification data ID (CS1 to CSk) output from the CPU 21 to the data line 27 via the parallel interface IC 22 are as shown in FIG. 4B. In addition, all the serial / parallel conversions I are synchronized with the clock supplied from the CPU through the parallel interface IC 22 and the clock line 28 at the same time.
It is supplied to C23-1 to C23-n and is temporarily stored in each shift register 41. Transmission data DT (D
1 to Dm) and the identification data ID (CS1 to CSk) are not output, the clock is not supplied. After the completion of the data transmission, the write signal is simultaneously supplied to all the serial / parallel conversion ICs 23-1 to 23-n via the write line 29 as shown in FIG. 4C.

Each serial / parallel conversion IC 23-1.
In 23-n, the number of bits of the identification data ID is known in advance among the transmission data DT and the identification data ID stored in the shift register 41 in response to the write signal, so only the identification data ID is separated. Read to one input terminal of the comparator 42. The other input terminal of the comparator 42 is supplied with the identification data previously assigned to the respective serial / parallel conversion ICs from the identification data setting unit 44, and the comparator receives the identification data supplied to these input terminals. To compare. As a result of this comparison, any one of the serial / parallel conversion ICs, for example, the serial / parallel conversion IC 23-
2 the identification data I transmitted from the CPU 21
D matches the preset identification data, the comparator 42 sends a signal to the latch 43, and the transmission data DT stored in the shift register 41 is latched. The shift register 41 and the latch 43 respond to this signal by transmitting the transmission data D stored in the shift register.
The T is read into the latch and transmitted as m-bit parallel data to the device 24-2 connected to the serial-parallel conversion IC 23-2.

As described above, in the first invention of the present application, all the serial-parallel conversion ICs 23-by adding the identification data ID designating the receiving destination of this data to the transmission data DT output from the CPU 21. 1-23-n
To the serial-parallel conversion IC, and the identification data ID added to the received data is compared with the identification data pre-assigned to each serial-parallel conversion IC. However, since only the serial / parallel conversion ICs that match with each other are activated and the accumulated transmission data DT is transmitted to the related device as parallel data, the parallel interface IC 22 and a plurality of parallel / serial conversions are performed. It is only necessary to connect one data line 27, one clock line 28 and one write line 29 to each of the ICs 23-1 to 23-n, and it is possible to reduce the number of pins of the parallel interface IC and to reduce the size. Can be achieved.

Next, the operation of transmitting data from each of the devices 26-1 to 26-n to the CPU 21 via the parallel interface IC 22 will be described. The signal waveform diagram shown in FIG. 6 and the parallel-serial conversion IC 25 shown in FIG. -1-
25-n will also be described with reference to the detailed block diagram.

Parallel-serial conversion IC 25 of FIG.
Each of 1 to 25-n is, as shown in FIG. 7, an input / output control circuit 51, a first shift register 52, a second shift register 53, a first comparator 54, an identification data setting unit 55, a latch 56 and a second. It comprises a comparator 57. The data line 30 is connected to the data output terminal of the input / output control circuit 51 and the data input terminal of the second shift register 53, and the clock line 31 is connected to the clock input terminals of the first and second shift registers 52 and 53. And the write line 32 is connected to the control terminal of the first comparator 54. The busy line 33 is connected to the output terminal of the second comparator 57.

Parallel / serial conversion ICs 25-1 and 25-2
Devices 26-1 to 26-n connected to each of 5-n
The parallel data output from is supplied to the latch 56 and the second comparator 57 via the data bus 58. When the CPU 21 reads the data of a predetermined device, first, as shown in FIG. 6A, the parallel / serial conversion I connected to the predetermined device via the data line 30.
C, for example, the k-bit identification data ID previously assigned to the parallel-serial conversion IC 25-2 is transmitted. Since the data line 30 is connected in parallel to all the parallel-serial conversion ICs 25-1 to 25-n,
This identification data ID is used for all parallel / serial conversion I.
Supplied to C. In this case, the input / output control circuits 51 of all the parallel-serial conversion ICs 25-1 to 25-n are
Since the input mode is set by the signal from the first comparator 54, the identification data ID is from the CPU 21 to the parallel interface IC2 as shown in FIG. 6B.
The second shift register 53 of all the parallel-serial conversion ICs 25-1 to 25-n in synchronization with the clock simultaneously transmitted via the clock line 31
Accumulated in.

As shown in FIG. 6C, when the write signal is transmitted through the write line 32 after the transmission of the identification data ID, all the parallel-serial conversion ICs 25 are transmitted.
1 to 25-n, the identification data ID stored in the second shift register 53 and constantly supplied to one input terminal of the first comparator 54 is constantly supplied from the identification data setting unit 55 to the other input terminal. Compare with the identification data provided. As a result of this comparison, any one of the parallel / serial conversion ICs, in this example, the first comparator 54 of the parallel / serial conversion IC 25-2 outputs a coincidence signal and activates only this parallel / serial conversion IC. At the rising edge of the clock shown in FIG. 6B, the CPU
Identification data ID (CS1 to CSk) output from 21
Is read by the first shift register 53, and the rising position of this clock may be any time during the period when CS2 is being output, for example, if attention is paid to the second bit CS2 of the identification data, it is normally the output of CS2. The clock is started in the middle of the period. When the output of the last bit CSk of the identification data ID is completed, the clock maintains the H level, falls with a 1/2 cycle delay from the rising of the write signal shown in FIG. 6C, and the clock is output again. The first bit D1 of the transmission data DT shown in FIG. 6D is output from the input / output control circuit 51 at the rising edge of the write signal, and the second and subsequent bits D1.
2 to Dm are output at the rising edge of the clock. When the write signal falls, the input / output control circuit 51 becomes high impedance and data is no longer output. For example, when the second bit D2 is focused on, the clock may fall at any time during the period in which this bit is output, but normally it falls at the center of the output period. That is, the clock in the period of bits D2 to Dm is a pulse with a duty of 50%.

When the coincidence signal is output from the first comparator 54 in the parallel-serial conversion IC 25-2, the latch 56 latches the parallel data supplied from the device 26-2 at that time. The parallel data is further supplied from the latch 56 to the first shift register 52 and temporarily stored therein. When the coincidence signal is output from the first comparator 54, the signal supplied to the input / output control circuit 51 also changes, and this input / output control circuit is switched to the output mode. Therefore, as shown in FIG. 6D, the parallel data stored in the first shift register 52 is converted into m-bit serial transmission data DT, and is transmitted through the data line 30 in synchronization with the clock supplied through the clock line 31. It is transmitted to the CPU 21. As shown in FIG. 6C, when the write signal falls from the H level to the L level, the input / output control circuit 51 returns to the input mode. The output control circuit 51 has a high impedance in the input mode, and is in a state capable of outputting a signal in the output mode.

As described above, in the second invention of the present application, the identification data ID transmitted from the CPU 21 via the data line 30 is converted into the parallel / serial conversion IC 2 by each parallel / serial conversion IC 2.
5-1 to 25-n is compared with the identification data assigned to itself, and only the parallel / serial conversion IC that matches the two is activated and supplied from the device connected to the parallel / serial conversion IC. The parallel data is converted into serial data and transmitted by the CPU. Control between the parallel interface IC 22 provided in the substrate of the CPU 21 and the plurality of parallel-serial conversion ICs 25-1 to 25-n. The lines can be only one data line 30, clock line 31, and write line 32, respectively, and the number of pins of the parallel interface IC can be reduced.

In this embodiment, the parallel interface IC 22 and the plurality of parallel / serial conversion ICs 2 are used.
A busy line 33 is provided between the device 5-1 and 25-n, and when the data supplied from any of the devices 26-1 to 26-n changes, a busy signal is transmitted to the CPU 21 via this busy line. In response to this, the CPU responds to the above-mentioned parallel-serial conversion ICs 25-1 to 25-1.
The load of the CPU is reduced by reading 25-n sequentially.

That is, as shown in FIG.
In the serial conversion ICs 25-1 to 25-n, the data taken in the latch 56 is supplied to one input terminal of the second comparator 57, and the devices 26-1 to 26-n are supplied to the other input terminal of the second comparator 57. I am trying to supply the parallel data supplied from. The second comparator 57 constantly compares these data,
When they match, the output of the second comparator is set to high impedance. Since the busy line 33 is pulled up, it is at the H level. When the data from the device changes and the data latched in the latch 56 and the parallel data from the device do not match, the L level busy signal is output. In this case, since the output of the second comparator 57 is an open drain type output, all the parallel-serial conversion ICs 2
The busy signals from 5-1 to 25-n can be transmitted to the parallel interface IC 22 via one busy line 33.

Therefore, the CPU 21 monitors the level of the busy signal appearing on the busy line 33, and when the level of this busy signal changes from H level to L level,
As described above, the CPU transmits the identification data ID to the data line 30, and the parallel / serial conversion IC 25
By reading the data from the -1 to 25-n, the parallel-serial conversion ICs 25-1 to 25-2 are regularly performed regardless of the change in the data output from the device.
The load on the CPU 21 can be reduced as compared with the case of reading data from 5-n.

FIG. 8 is a block diagram showing the configuration of the data transmission system according to the third aspect of the present invention. According to the third aspect of the invention, the data transmission from the CPU to each device and the data transmission from each device to the CPU are basically performed by three control lines.

As shown in FIG. 8, a parallel interface IC 62 provided in the substrate of the CPU 61 is connected to a plurality of serial / parallel conversion ICs 63-1 to 63-n, and these serial / parallel conversion ICs are connected to the respective devices 6.
4-1 to 64-n and a parallel interface IC is connected to a plurality of parallel / serial conversion ICs 65.
1 to 65-n, and these parallel-serial conversion ICs are connected to the respective devices 66-2 to 66-n. One data line 67, one clock line 68, and one write line 69 connected to the parallel interface IC 62 are serial-parallel conversion ICs.
63-1 to 63-n and parallel-serial conversion IC
65-1 to 65-n are connected in parallel.

FIG. 9 is a signal waveform diagram showing the operation of the data transmission system of this example, and FIG. 10 shows the configuration of the serial-parallel conversion ICs 63-1 to 63-n of this example.
The serial / parallel conversion IC is the first shift register 7
1, a second shift register 72, a comparator 73, an identification data setting unit 74 and a latch 75. The data line 67 is connected to the input terminals of the first and second shift registers 71 and 72, and the write line 69. Is connected to the control terminal of the comparator 73.

First, when data is transmitted from the CPU 61 to a specific device, the CPU transmits data obtained by adding the identification data ID to the transmission data DT as shown in FIG. 9A. In the previous example, the identification data ID was added after the transmission data DT, but in this example, it is added before the transmission data. As described above, in the present invention, any positional relationship may be used as long as the identification data and the transmission data can be separated.

Identification data ID transmitted from the CPU 61
Is a second shift register 72 of all the serial-parallel conversion ICs 63-1 to 63-n under the control of the clock transmitted via the clock line 68 as shown in FIG. 9B.
Accumulate in. The timing of reading the identification data ID is the same as that described with reference to FIGS. Figure 9C
As shown in FIG. 3, all the serial-parallel conversion ICs 63-1 respond in response to the write signal transmitted via the write line 69 rising from the L level to the H level when the transmission of the k-bit identification data ID is completed. ~ 63
The comparator 73 of −n is operated to compare the identification data ID stored in the second shift register 72 with the identification data supplied from the identification data setting unit 74.

As a result of this comparison, the comparator 73 of any one of the serial / parallel conversion ICs, for example, the serial / parallel conversion IC 63-2 outputs a coincidence signal. When this coincidence signal is supplied to the first shift register 71, the first shift register temporarily stores the m-bit transmission data DT supplied subsequently from the CPU 61 under the control of the clock. That is, at the rising edge of the write signal shown in FIG. 9C, the first shift register 71 of the selected serial-parallel conversion IC is activated and receives the transmission data DT (D1 to Dm).

As shown in FIG. 9C, the write signal falls to the L level at the end of transmission of the transmission data DT, but in response to this fall, the first shift register 71 becomes inactive and is stored therein. The transmission data DT is taken in the latch 75 as parallel data, and is further transmitted as parallel data to the device 64-2 connected to the serial / parallel conversion IC 63.2. In this way, the serial transmission data DT output from the CPU 61 and designated to be received by a predetermined device is transferred to the predetermined device 64-
2 can be transmitted as parallel data.

Since the operation of transmitting the parallel data from the devices 66-1 to 66-n to the CPU 61 as serial data is the same as that of the above-mentioned embodiment, its explanation is omitted. Also in this example, the parallel interface I
One busy line 70 connected to C62 is connected in parallel to all the parallel-serial conversion ICs 65-1 to 65-n, and the CPU 61 operates only when the data changes in any of the devices 66-1 to 66-n. Although the data is read, the description of the operation is the same as in the previous example, and therefore the description thereof is omitted.

As described above, according to the third invention of the present application, the parallel interface IC 62 provided in the substrate of the CPU 61 and the plurality of serial / parallel conversion I are provided.
Since only one data line 67, one clock line 68 and one write line 69 are provided between each of the C63-1 to 63-n and the plurality of parallel-serial conversion ICs 65-1 to 65-n, a parallel interface IC The number of pins can be further reduced as compared with the previous example.

FIG. 11 shows the comparator 73 shown in FIG.
FIG. 3 is a circuit diagram showing a detailed configuration of an example of the identification data setting unit 74, and in this example, the identification data ID is composed of 4 bits. Identification data setting unit 74
Is provided with four switches 74-1 to 74-4, and one input terminal of each of these switches is connected to a resistor 74-5.
It is connected to a power supply via 74-8, the other input terminal is commonly grounded, and each bit of the identification data can be set to H level or L level.

The comparator 73 is provided with four exclusive NOR gates 73-1 to 73-4, one input terminal of which is connected to the output terminals of the switches 74-1 to 74-4, respectively, and the other input. The terminals are connected to the output terminals of the second shift register 72, respectively. The output terminals of the four exclusive NOR gates 73-1 to 73-4 are connected to the AND gate 73-5.

Switch 7 of the identification data setting unit 74
If the four bits of the identification data set in 4-1 to 74-4 and the four bits of the identification data stored in the second shift register 72 match, four exclusive.
The outputs of the NOR gates 73-1 to 73-4 are all at the H level, and therefore the output of the AND gate 73-5 is at the H level. On the other hand, if even one bit of the identification data is different, the output of the AND gate 73-5 becomes L level. In this way, it is possible to determine whether the identification data transmitted from the CPU matches the previously assigned identification data. It goes without saying that the circuit shown in FIG. 11 can be applied to the first comparator 54 and the identification data setting unit 55 shown in FIG.

The present invention is not limited to the above-mentioned embodiments, but various modifications and variations are possible. For example, in the above-described embodiment, when the data is transmitted from the device to the CPU, the CPU is configured to read the data only when the data output from any of the devices changes. Can also be configured to sequentially read the data of all devices, in which case the busy line connected between the parallel / serial conversion IC and the parallel / serial conversion IC becomes unnecessary,
The number of control lines can be further reduced.

When data is transmitted from the CPU to the devices, if the same data may be transmitted to all devices, one bit is added to the identification data, and if this bit is set, The serial / parallel conversion ICs connected to all the devices may be activated at the same time to transmit the transmission data to all the devices at the same time.

[0047]

According to the first aspect of the present invention described above, the parallel data output from the CPU is converted into serial data by the parallel interface IC and transmitted to the serial / parallel conversion IC. When converting to parallel data by the IC and transmitting to parallel to a predetermined device, one data line is provided between the parallel interface IC provided in the CPU board and the serial-parallel conversion IC connected to each device.
The clock line and the write line are simply connected, and in the second invention, the parallel data output from many devices is converted into a parallel-serial conversion IC.
Between the parallel / serial conversion IC and the parallel interface IC connected to each device, the serial data is converted into serial data and transmitted to the parallel interface IC, and the parallel interface IC is converted into parallel data and transmitted to the CPU. Respectively connect only one data line, one clock line and one write line. Further, in the third invention of the present application, the parallel data from the CPU is converted into serial data by the parallel interface IC, and a plurality of serial data are converted. -Transmit to a parallel conversion IC, convert to parallel data by these serial / parallel conversion ICs and transmit as parallel data to a plurality of devices, and convert parallel data from each device to serial data by a parallel / serial conversion IC. hand When transmitting to the parallel interface IC, converting into parallel data by the parallel interface IC and transmitting to the CPU, one data is provided between the parallel interface IC and the serial / parallel conversion IC and the parallel / serial conversion IC. Since only the lines, clock lines and write lines are connected, the number of pins of the parallel interface IC can be significantly reduced as compared with the conventional one, and the size can be reduced accordingly. Further, it is possible to easily deal with a change in specifications or a version upgrade without increasing the number of pins. Further, when transmitting data output from a large number of devices to the CPU, one busy line is added between the parallel / serial conversion IC and the parallel interface IC connected to each device so that the data of any device is In an embodiment in which the CPU reads data only when there is a change,
The load on the CPU can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional data transmission system for transmitting data from a CPU to a device.

FIG. 2 is a block diagram showing a configuration of a conventional data transmission system in which data is transmitted from a device to a CPU.

FIG. 3 is a block diagram showing a configuration of an embodiment of a data transmission system according to the present invention.

FIG. 4 is a signal waveform diagram for explaining an operation of transmitting data from a CPU to a device.

FIG. 5 is a block diagram showing a detailed configuration of an example of a serial-parallel conversion IC.

FIG. 6 is a signal waveform diagram for explaining an operation of transmitting data from a device to a CPU.

FIG. 7 is a block diagram showing a detailed configuration of an example of a parallel-serial conversion IC.

FIG. 8 is a block diagram showing the configuration of another embodiment of the data transmission system according to the present invention.

FIG. 9 is a signal waveform diagram for similarly explaining the operation.

FIG. 10 is a block diagram showing a detailed configuration of the serial-parallel conversion IC, similarly.

FIG. 11 is a circuit diagram showing a detailed configuration of the comparator and the identification data setting unit similarly.

[Explanation of symbols]

21 CPU 22 Parallel interface IC 23-1 to 23-n Serial-parallel conversion IC 24-1 to 24-n equipment 25-1 to 25-n parallel-serial conversion IC 26-1 to 26-n equipment 27,30 data lines 28,31 clock lines 29.32 Write line 33 Busy Line DT transmission data ID identification data 41 shift register 42 Comparator 43 Latch 44 Identification data setting unit 51 Input / output control circuit 52 First Shift Register 53 Second shift register 54 First Comparator 55 Identification data setting unit 56 latch 57 Second comparator 61 CPU 62 Parallel interface IC 63-1 to 63-n serial-parallel conversion IC 64-1 to 64-n equipment 65-1 to 65-n parallel-serial conversion IC 66-1 to 66-n equipment 67 data lines 68 clock lines 69 writing line 70 busy lines 71 First Shift Register 72 Second shift register 73 Comparator 73-1 to 73-4 Exclusive NOR Gate 73-5 AND GATE 74 Identification data setting unit 74-1 to 74-4 switches 74-5 to 74-8 Resistance 75 Latch

Claims (4)

[Claims] 1. A parallel interface IC for a CPU
Is connected to the plurality of serial / parallel conversion ICs connected to each of a plurality of devices, and the parallel data output from the CPU is converted into serial data by the parallel interface IC. When transmitting to a serial / parallel conversion IC of, and further converting to parallel data by these serial / parallel conversion ICs and transmitting to a plurality of devices,
A data line, a clock line, and a write line connected to the parallel interface IC are connected in parallel to the plurality of serial-parallel conversion ICs, and the data output from the CPU via the parallel interface IC receives the data. Transmission including identification data that specifies the destination, all serial / parallel conversion I
In C, this data is received and stored under the control of the clock supplied via the clock line, and at the end of the data transmission, all the serial / parallel conversion ICs respond to the write signal transmitted via the write line. In the step S1, the identification data for designation of the recipient, which is transmitted from the CPU, is compared with the identification data previously assigned to the respective serial / parallel conversion ICs, and only the serial / parallel conversion ICs in which they match are activated. A data transmission system characterized by converting serial data transmitted from a CPU into parallel data and transmitting the parallel data to a device connected to the serial-parallel conversion IC. 2. Parallel data output from a plurality of devices is converted into serial data by a plurality of parallel-serial conversion ICs connected to each device and transmitted to a parallel interface IC, and the parallel interface ICs perform parallel processing. When converting to data and transmitting to the CPU, the data line, clock line, and write line connected to the parallel interface IC are connected in parallel to the plurality of parallel-serial conversion ICs and output from the plurality of devices. Parallel data is stored in each parallel-serial conversion IC, and C
Identification data designating a parallel / serial conversion IC to which data should be sent from the PU to the CPU via the parallel interface IC and the data line is transmitted to all the parallel / serial conversion ICs, and this identification is performed in each parallel / serial conversion IC. Data is received and stored under the control of the clock supplied through the clock line, and at the end of the identification data transmission, all parallel signals are received in response to the write signal supplied through the parallel interface IC and the write line from the CPU. Serial conversion IC
In the above, the identification data transmitted from the CPU is compared with the identification data previously assigned to the respective parallel-serial conversion ICs, and the parallel
Only the serial conversion IC is activated, the parallel data output from the device connected to the parallel / serial conversion IC and accumulated therein is converted into serial data, and the data line and parallel interface I
A data transmission method characterized in that data is transmitted to the CPU via C. 3. A parallel interface IC for the CPU
Is connected to the plurality of serial / parallel conversion ICs connected to each of a plurality of devices, and the parallel data output from the CPU is converted into serial data by the parallel interface IC. To the serial / parallel conversion ICs, and the serial / parallel conversion ICs further convert the parallel data to multiple devices for transmission, or the parallel data output from the multiple devices is connected to each device. In parallel / serial conversion IC, the data is converted into serial data and transmitted to the parallel interface IC. When converted into parallel data by the parallel interface IC and transmitted to the CPU, the data line and clock connected to the parallel interface IC. Line and The writing line multiple serial
The data connected to the parallel conversion IC in parallel and connected to the plurality of parallel / serial conversion ICs in parallel, and the data output from the CPU via the parallel interface IC includes identification data designating a recipient of the data. All the serial-to-parallel conversion ICs receive this data under the control of the clock supplied via the clock line, store it, and store it at the end of the data transmission into the write signal transmitted via the write line. In response, C in all serial-parallel conversion ICs
Identification data for designation of the recipient transmitted from the PU,
The serial data to parallel conversion ICs are compared with the identification data assigned in advance, only the serial data to parallel data conversion ICs that match each other are activated, and the serial data transmitted from the CPU is converted into parallel data. The data is transmitted to a device connected to the serial / parallel conversion IC, the parallel data output from the plurality of devices is accumulated in each parallel / serial conversion IC, and C
Identification data designating a parallel / serial conversion IC to which data is to be sent from the PU via the parallel interface IC and the data line is transmitted to all parallel / serial conversion ICs, and this identification data is clocked in each parallel / serial conversion IC. Received and stored under the control of the clock supplied via the line, and the parallel interface IC from the CPU at the end of transmission of the identification data.
And C in all parallel-to-serial conversion ICs in response to the write signal supplied via the write line.
The identification data transmitted from the PU is compared with the identification data previously assigned to the respective parallel / serial conversion ICs, and only the parallel / serial conversion ICs that match the two are activated, and the parallel / serial conversion I
A data transmission method characterized in that parallel data supplied from a device connected to C is converted into serial data and transmitted to a CPU via a data line and a parallel interface IC. 4. A busy line connected to the parallel interface IC is connected in parallel to the plurality of parallel-serial conversion ICs, and when data supplied from a device changes in any of the parallel-serial conversion ICs. Then, the busy signal is transmitted to the CPU through the busy line and the parallel interface IC, and C
4. The data transmission method according to claim 2, wherein the PU is configured to transmit the identification signal to all parallel-serial conversion ICs only when receiving the busy signal.