JP2008103620A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2008103620A JP2008103620A JP2006286395A JP2006286395A JP2008103620A JP 2008103620 A JP2008103620 A JP 2008103620A JP 2006286395 A JP2006286395 A JP 2006286395A JP 2006286395 A JP2006286395 A JP 2006286395A JP 2008103620 A JP2008103620 A JP 2008103620A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
【解決手段】本発明では、半導体ウエハW上に電気接続用の第1バンプ21に隣接して基板接合用の第2バンプ22を形成し、この第2バンプ22を支持基板上の支持バンプ(バンプ受け部)32に圧着接合することによって、半導体ウエハWと支持基板30との間の仮固定性を得るようにしている。そして、半導体ウエハWをチップ領域単位で切り出して半導体チップC1に個片化した後、この半導体チップC1を吸着保持して第2バンプ22を支持バンプ32から引き剥がす。これにより、第1バンプ22にダメージを与えることなく支持基板30からの分離を図ることが可能となり、これにより、半導体装置の電気接続構造の信頼性低下を防止することができる。
【選択図】図5
Description
特に、図1は半導体ウエハWおよび支持基板30の準備と貼り合せ工程を示し、図2は半導体ウエハWの一チップ領域の概略平面図である。また、図3及び図4はバンプ形成工程、図5は裏面バンプの形成工程とダイシング工程、図6はチップ分離工程、図7はチップマウント工程、図8は支持基板30の再生工程を、それぞれ示している。
Claims (9)
- チップオンチップ構造の半導体装置の製造方法であって、
一方の面に、電気接続用の第1バンプ及び基板接合用の第2バンプがチップ領域毎にそれぞれ形成された半導体ウエハを準備する工程と、
一方の面に前記第2バンプの形成位置に対応してバンプ受け部を形成した支持基板を準備する工程と、
前記半導体ウエハと前記支持基板とを重ね合わせて前記第2バンプと前記バンプ受け部とを互いに圧着接合する工程と、
前記半導体ウエハの他方の面にビアを介して前記第1バンプと連絡する第3バンプを形成する工程と、
前記支持基板上で前記半導体ウエハを上記チップ領域単位で切り出して個々の半導体チップに個片化する工程と、
前記半導体チップを吸着保持して前記第2バンプを前記バンプ受け部から引き剥がし、前記第1バンプを介して他の半導体チップに実装する工程とを有する
ことを特徴とする半導体装置の製造方法。 - 前記半導体ウエハの一方の面からの前記第2バンプの突出長と、前記支持基板の一方の面からの前記バンプ受け部の突出長との和は、前記半導体ウエハの一方の面からの前記第1バンプの突出長よりも大きい
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第2バンプは、前記第1バンプと同一プロセスで作製される
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第2バンプは、前記第1バンプの周囲を囲む枠状に連続形成される
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記バンプ受け部は、前記支持基板の一方の面に突出形成されたはんだ層からなる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記支持基板の周縁部に接着層を形成し、前記接着層の接着力で前記半導体ウエハと前記支持基板とを一体接合する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第3バンプのバンプピッチは、前記第1バンプのバンプピッチよりも広く形成される
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記半導体チップを他の半導体チップに実装した後、前記第2バンプをダムとしてチップ間にアンダーフィル材を充填する工程を有する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記半導体ウエハの内部に、前記第1バンプと電気的に接続された埋込導体層を形成しておき、前記半導体ウエハの他方の面の研削処理によって前記ビアを形成する
ことを特徴とする請求項1に記載の半導体装置の製造方法。
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JP2006286395A JP4779924B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置の製造方法 |
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JP2006286395A JP4779924B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置の製造方法 |
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JP2008103620A true JP2008103620A (ja) | 2008-05-01 |
JP4779924B2 JP4779924B2 (ja) | 2011-09-28 |
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JP2006286395A Expired - Fee Related JP4779924B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置の製造方法 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012054353A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置 |
KR20150131964A (ko) * | 2014-05-16 | 2015-11-25 | 가부시기가이샤 디스코 | 웨이퍼 가공 방법 및 중간 부재 |
WO2021117585A1 (ja) * | 2019-12-09 | 2021-06-17 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子パッケージおよび撮像素子パッケージの製造方法 |
-
2006
- 2006-10-20 JP JP2006286395A patent/JP4779924B2/ja not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012054353A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 半導体装置 |
KR20150131964A (ko) * | 2014-05-16 | 2015-11-25 | 가부시기가이샤 디스코 | 웨이퍼 가공 방법 및 중간 부재 |
KR102455708B1 (ko) | 2014-05-16 | 2022-10-17 | 가부시기가이샤 디스코 | 웨이퍼 가공 방법 및 중간 부재 |
WO2021117585A1 (ja) * | 2019-12-09 | 2021-06-17 | ソニーセミコンダクタソリューションズ株式会社 | 撮像素子パッケージおよび撮像素子パッケージの製造方法 |
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