JP2008067088A - Phase adjustment circuit and phase-locked loop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase adjustment circuit which is obtained with a small circuit scale without using a high frequency clock and performs phase adjustment with finer resolution, and to provide a phase-locked loop circuit. <P>SOLUTION: A horizontal synchronizing signal SYNC_IN to be inputted is shifted by a phase shift circuit 21 in response to the value of the high-order 2 bits of a phase adjustment data CKPHASE. An up/down counter 22 up/down-counts the clock NCKP, based on the shift output. The count result is outputted to a latch circuit 23 by way of a multiplying circuit 32, etc. The latch circuit 23 performs latching by a pulse ENCKP for data enabling, so as to output a phase adjustment output HD_SIG. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase adjustment circuit and a phase-locked loop circuit that perform clock phase adjustment in synchronization with a synchronization signal of an input video signal.

In a television receiver or the like, a phase-locked loop circuit (abbreviated as a PLL circuit) is widely used to generate a clock such as a system clock synchronized with a horizontal synchronizing signal that is a synchronizing signal of an input video signal.
In addition, when a PLL circuit is used, when a system clock synchronized with the horizontal sync signal is generated, a phase adjustment circuit that finely adjusts the phase of the system clock is necessary to improve resolution such as contrast in video processing. It may become.
For example, Patent Document 1 discloses a first PLL circuit that generates a multiplied clock obtained by multiplying a horizontal synchronization signal, and a first pulse generation that generates a pulse that can control the phase of the horizontal synchronization signal in units of the frequency of the multiplied clock. A phase shift control device including a circuit and a second PLL circuit for keeping the horizontal screen position constant is disclosed.

In this conventional example, in order to adjust the horizontal screen position with finer resolution, in addition to the first PLL circuit that generates the multiplied clock, a plurality of different phases can be obtained without increasing the frequency of the multiplied clock. A multi-phase clock generating means for generating a shift clock is formed using a second PLL circuit.
In this way, when a plurality of PLL circuits are configured using different voltage controlled oscillators (abbreviated as VCO), the circuit scale becomes larger than that formed by a single VCO. For this reason, when it is going to implement | achieve a phase adjustment circuit and a PLL circuit with a large scale integrated circuit (LSI) etc., the cost will increase.

Accordingly, there is a demand for a phase adjustment circuit that can be realized with a small circuit scale without using a clock having a high frequency and can perform phase adjustment with finer resolution.
JP 2001-157081 A

  The present invention has been made in view of the above points, and provides a phase adjustment circuit and a phase-locked loop circuit that can be realized with a small circuit scale without using a high-frequency clock and can perform phase adjustment with finer resolution. The purpose is to do.

  The phase adjustment circuit according to an embodiment of the present invention uses the second clock set to N (N is an integer equal to or greater than 2) times the first clock synchronized with the synchronization signal of the video signal. Input to generate the first clock that is phase-shifted with respect to the phase of the synchronization signal by the number of steps of M exceeding N (M is an integer exceeding N) with the period of 2 clocks as a unit. A phase shift circuit that generates a phase-shifted signal according to a phase adjustment instruction value up to the number of M steps using the second clock with respect to the synchronization signal, and the phase-shifted signal according to the phase-shifted signal A time resolution in units of a period of the first clock from the latch circuit, the counter circuit counting a second clock; and a latch circuit latching a signal based on the output of the counter circuit. , And generates a phase shift adjustment output signals having M different signal waveform in response to said phase adjustment value.

  A phase-locked loop circuit according to an embodiment of the present invention generates a system clock by dividing a clock output from a voltage controlled oscillator by N (N is an integer of 2 or more) by a frequency divider, and generates the clock. A first phase-locked loop unit that controls the oscillation frequency of the voltage controlled oscillator with a signal that is directly or divided and phase-compared by a first phase comparator, and phase adjustment with respect to a synchronizing signal of an input video signal A phase adjustment output signal generated by phase-shifting by the number of steps of M exceeding N (M is an integer exceeding N) in units of the clock period from the system clock to the period of the synchronization signal. The comparison signal generated for synchronization is phase-compared with the second phase comparator, and the analog waveform signal generated based on the result of the phase comparison is compared with the first signal. And a second phase-locked loop unit that controls the oscillation frequency of the voltage-controlled oscillator in common with the case of the first phase-locked loop unit, and the phase adjustment circuit includes: The phase shift adjustment output signal having the M different signal waveforms can be output with a time resolution in units of the period of the first clock.

  According to the present invention, it can be realized with a small circuit scale without using a high-frequency clock, and the phase can be adjusted with finer resolution.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration of a phase-locked loop circuit (abbreviated as PLL circuit) 1 according to an embodiment of the present invention.
The PLL circuit 1 includes a phase adjustment circuit 3 to which a horizontal synchronization signal is input via a synchronization separation circuit 2 and a horizontal PLL circuit 4 to which an output signal of the phase adjustment circuit 3 is input.
The synchronization separation circuit 2 separates the horizontal synchronization signal from the input video signal and outputs the horizontal synchronization signal to the phase adjustment circuit 3.
The phase adjustment circuit 3 outputs a phase adjustment output HD_SIG that is phase-adjusted with respect to an input horizontal synchronization signal in accordance with phase adjustment data CKPHASE input from the phase adjustment data signal input terminal. The horizontal synchronization signal input to the phase adjustment circuit 3 is indicated by SYNC_IN as shown in FIG.

The phase adjustment data CKPHASE is data that can be arbitrarily selected and set within a predetermined range corresponding to the phase adjustment instruction value to be phase adjusted by the user or the like, and the phase adjustment circuit 3 has a phase corresponding to the value of this data. The adjustment output HD_SIG is output as an output signal.
This phase adjustment output HD_SIG is a first phase comparator (abbreviated as first PD in FIG. 1) that constitutes a horizontal PLL circuit 4 that performs phase correction so as to generate a system clock CKP synchronized with a horizontal synchronization signal. 5 is input to the first input terminal.
The horizontal PLL circuit 4 includes a first PLL circuit unit 14 a and a second PLL circuit unit 14 b configured using a common voltage controlled oscillator (abbreviated as VCO) 11.
The output signal of the horizontal counter 6 that counts the system clock CKP is input as a ramp signal to the second input terminal of the first phase comparator 5 constituting the first PLL circuit section 14a.
Then, the first phase comparator 5 compares the phase of the output signal of the horizontal counter 6 and the center period of the phase adjustment output HD_SIG with respect to the phase adjustment output HD_SIG phase-adjusted by the phase adjustment circuit 3. The phase error obtained by the comparison is output to a low-pass filter (abbreviated as LPF) 7.

The horizontal counter 6 counts the number of system clocks CKP from 0, and when it reaches a predetermined count number that is about the number of horizontal pixels of the video signal, it resets itself and then repeats counting from 0 again. Accordingly, the output waveform of the horizontal counter 6 has a sawtooth shape.
FIG. 2 is a diagram for explaining the operation of phase adjustment by the first phase comparator 5. 2A is input to the first input terminal of the first phase comparator 5, and the output signal of the horizontal counter 6 shown in FIG. 2B is input to the second input terminal. Is entered.
The first phase comparator 5 outputs the phase adjustment output at the timing of the falling edge of the output signal of the horizontal counter 6 in the gate signal period shown in FIG. 2C set slightly wider than the pulse width of the phase adjustment output HD_SIG. Divide HD_SIG into two pulse waveforms (around and behind in time). The first phase comparator 5 compares the areas of the two divided pulse waveforms, and outputs a signal corresponding to the difference to the LPF 7 as a phase error.

Then, by the horizontal PLL correction operation by the horizontal PLL circuit 4, the phase of the output signal of the horizontal counter and the phase of the phase adjustment output HD_SIG are corrected so as to reduce this phase error.
Since the output signal of the horizontal counter 6 is generated by counting the system clock CKP, detection of the phase error by the first phase comparator 5 is performed with a time resolution in units of the clock period of the system clock CKP. Is called.
Note that the phase adjustment output HD_SIG in FIG. 2A has a signal waveform in which phase information corresponding to the phase adjustment data CKPHASE is added to the rising edge portion and the falling edge portion of the horizontal synchronization signal.
As described above, the detection of the phase error by the first phase comparator 5 is performed with the time resolution in units of the clock cycle of the system clock CKP. Therefore, if the signal waveform of the phase adjustment output HD_SIG remains 1 bit, It is difficult to detect a phase shift finer than the clock period of the system clock CKP.

Therefore, in the present embodiment, the phase adjustment output HD_SIG is set to a signal waveform to which phase information is added, that is, a signal waveform having multiple bits information.
The phase information is set so as to differ depending on the value of the phase adjustment data CKPHASE.
Further, this phase information is a voltage controlled oscillator (N is an integer of 2 or more, and N = 4 in a specific example described later), which is higher than the clock cycle of the system clock CKP, as will be described later. It is generated using the clock NCKP of 11). Then, different signal waveforms of the phase adjustment output HD_SIG are generated according to the value of the phase adjustment data CKPHASE in units of one clock cycle of the system clock CKP (FIGS. 9 to 12 described later). . Further, by causing the horizontal PLL circuit 4 to perform the horizontal PLL correction operation, the phase adjustment output HD_SIG is phase-shifted from the horizontal synchronization signal in units of time smaller than the cycle of the clock NCKP of the VCO 11 as shown in FIG. It will be a thing.

  The LPF 7 extracts the low frequency component of the phase error and outputs it to the analog waveform sine wave generator 8 at the next stage. The sine wave generator 8 generates, for example, a sine wave of an analog waveform and outputs it to a first input terminal of a second phase comparator (abbreviated as second PD in FIG. 1) 9.

The second phase comparator 9 receives the output signal of the second frequency divider 10 at its second input end, and compares the phase of the signals input to both input ends. The second phase comparator 9 applies the phase error output signal obtained by the comparison to the oscillation control input terminal of the VCO 11.

The VCO 11 oscillates at an oscillation frequency in such a direction that the phase error of the output signal of the second phase comparator 9 becomes zero. The clock NCKP as the oscillation output signal of the VCO 11 is output to the first frequency divider 12 and the second frequency divider 10 together with the phase adjustment circuit 3.
In this case, the VCO 11, the second frequency divider 10, and the second phase comparator 9 constitute a second PLL circuit unit 14b. The first and second PLL circuit portions 14 a and 14 b are formed using a common VCO 11.
The first frequency divider 12 divides the clock NCCK output from the VCO 11 to generate a system clock CKP, and the system clock CKP (including the PLL circuit 1) is output from the output terminal of the PLL circuit 1 as a video signal. Output to processing LSI. The system clock CKP is a system clock (or main clock) used in the video signal processing LSI.

The system clock CKP is output to the horizontal counter 6 and to the data enable pulse generator 13. The data enable pulse generator 13 changes only the duty of the system clock CKP to generate a data enable pulse ENCKP and outputs it to the phase adjustment circuit 3. Specifically, the data enable pulse ENCKP is obtained by converting a 50% duty system clock CKP to a 25% duty, and becomes High with a pulse width synchronized with the clock NCKP. In this embodiment, the first phase comparator 5 → LPF 7 → sine wave generator 8 → second phase comparator 9 → VCO 11 → first frequency divider 12 → horizontal counter 6 → first phase comparator. The first PLL circuit portion 14a is formed by five loops.
The first PLL circuit unit 14 a is a PLL circuit configured to perform phase comparison with respect to the output signal of the phase adjustment circuit 3.

In the present embodiment, the VCO 11 is used in common for the first PLL circuit unit 14a and the second PLL circuit unit 14b, and can be realized with a smaller circuit scale than in the case of separate configuration.
Then, the horizontal PLL circuit 4 generates an analog waveform sine wave signal using the above-described phase information, and the second phase comparator 9 divides the sine wave signal by a signal obtained by dividing the clock NCKP of the VCO 11. By controlling the oscillation frequency of the clock NCKP of the VCO 11 based on the output signal thus compared, the system clock CKP phase-shifted from the phase of the horizontal synchronization signal can be generated according to the value of the phase adjustment data CKPHASE.
The PLL circuit 1 shown in FIG. 1 has a system clock so that the falling period of the output signal of the horizontal counter 6 compared by the first phase comparator 5 and the center period of the phase-adjusted synchronization signal substantially coincide. Control is performed so that the frequency and phase of CKP are always corrected.

Further, as described above, since the first phase comparator 5 performs phase correction in one clock cycle of the system clock CKP, the phase adjustment that requires correction accuracy within the one clock cycle is used as the second phase comparator 9. This is performed on the side, and the clock phase of the VCO 11 is corrected by the output of the second phase comparator 9, thereby enabling more detailed phase correction.
The phase adjustment circuit 3 adds phase information in units of the clock NCKP of the VCO 11 to the input horizontal synchronization signal SYNC_IN according to the value of the phase adjustment data CKPHASE instructed by the user or the like. . The phase adjustment circuit 3 outputs an output signal that is phase-shifted from the input horizontal synchronization signal SYNC_IN in accordance with the value of the phase adjustment data CKPHASE by the horizontal PLL correction operation of the horizontal PLL circuit 4.

As described above, the phase adjustment circuit 3 adds phase information to both ends of the signal waveform according to the value of the phase adjustment data CKPHASE with respect to the input 1-bit horizontal synchronization signal SYNC_IN, and performs phase adjustment of a plurality of bits. Output HD_SIG is generated. In other words, the phase adjustment circuit 3 adds offset information corresponding to the value of the phase adjustment data CKPHASE to the input horizontal synchronization signal SYNC_IN.
Further, in the PLL circuit 1 shown in FIG. 1, the horizontal PLL correction operation is performed, that is, by setting the closed-loop operation state as shown in FIG. 1, the first PLL circuit unit for the phase adjustment output HD_SIG. By operating 14a and further operating the second PLL circuit unit 14b, it becomes possible to generate the system clock CKP whose phase has been adjusted according to the value of the phase adjustment data CKPHASE.
Next, before describing the configuration of the phase adjustment circuit 3 according to the present embodiment, the configuration of a reference phase adjustment circuit 3 ′ as a prototype for configuring the phase adjustment circuit 3 will be described. FIG. 3 shows the configuration of the phase adjustment circuit 3 'of this reference example.

The PLL circuit of the reference example using the phase adjustment circuit 3 'has the same configuration as that of the PLL circuit 1 of FIG. 1 in which only the phase adjustment circuit 3 portion is replaced with the phase adjustment circuit 3'. The phase adjustment circuit 3 'is a phase adjustment circuit that can perform the phase adjustment step for, for example, four steps with respect to one clock of the system clock CKP.
Corresponding to these four steps, the clock NCKP of the VCO 11 in the PLL circuit used in the phase adjustment circuit 3 'has a frequency four times (the number of steps times) the system clock CKP, and the data enable pulse ECKP has the same frequency as the system clock CKP.
On the other hand, the phase adjustment circuit 3 having the configuration described later uses the clock NCKP of the VCO 11 used in the phase adjustment circuit 3 ′ of FIG. That is, the phase adjustment of 8) is enabled. That is, the phase adjustment circuit 3 described later adds an addition / subtraction circuit or the like to the phase adjustment circuit 3 'of this reference example, and enables the phase adjustment in more detail while keeping the same clock NCKP of the VCO 11.

As shown in FIG. 3, the phase adjustment circuit 3 ′ includes a phase shift circuit 21 that shifts the phase of the input horizontal synchronization signal SYNC_IN in accordance with the phase adjustment data CKPHASE.
The phase shift circuit 21 receives the phase adjustment data CKPHASE as described above and the clock NCKP of the VCO 11 as described above.
The phase shift circuit 21 shifts the input horizontal synchronization signal (here positive polarity) SYNC_IN by four steps for each rising phase of the clock NCKP according to the value of the phase adjustment data signal (CKPHASE). The phase-shifted 1-bit shift output DLSYNC is input to the up / down counter 22.
The phase adjustment data CKPHASE is 2 bits, and when the user changes the data value of the phase adjustment data CKPHASE to 00, 01, 10 and 11, the phase of the shift output DLSYNC becomes the phase of the input horizontal synchronization signal SYNC_IN. On the other hand, the rising phase of the clock NCKP changes in a direction that is delayed by one clock (see FIGS. 4 and 5).

The up / down counter (abbreviated as U / D counter in FIG. 3 and the like) 22 sets the clock NCKP to 0 at the start phase of the phase-shifted shift output DLSYNC (when the shift output DLSYNC changes from Low to High). Is counted up to 4, and the value of 4 is held until the end phase. In FIG. 3, the function of holding 4 is indicated by a limiter that limits 4. The up / down counter 22 counts down from 4 to 0 at the end phase (when the shift output DLSYNC changes from High to Low), and holds the value of 0 until the next start phase. The up / down counter 22 outputs the output CTR counted by 3 bits to the latch circuit 23.
The latch circuit 23 latches the value of the output CTR of the up / down counter 22 during a period when the data enable pulse ENCKP, in which only the duty is changed from the system clock CKP, is High, so that the 3-bit phase adjustment output HD_SIG to which the phase information is added. Is generated.

Then, as will be described later (see FIG. 6), the phase adjustment of the signal waveforms different from each other according to the data value of the phase adjustment data CKPHASE using the clock period of the data enable pulse ENCKP, that is, the clock period of the system clock CKP as a time unit Output HD_SIG is generated. Note that the clock NCKP of the VCO 11 is also applied to the latch circuit 23.
In order to easily understand the operation of the phase adjustment circuit 3 'shown in FIG. 3 in an easy-to-understand manner, FIGS. 4 and 5 show operation waveform diagrams of the respective parts when the phase correction in the horizontal PLL circuit 4 is ignored. More specifically, FIG. 4 shows an operation waveform diagram when the phase adjustment data CKPHASE data is 00 and 01, and FIG. 5 shows an operation waveform diagram when the phase adjustment data CKPHASE data is 10 and 11, respectively.

In FIG. 4 and the like, the period during which the data enable pulse ENCKP is High is indicated by hatching. Then, the relationship between the data fetching by the latch circuit 23 with respect to the output CTR (of the up / down counter 22) and the latch circuit output, that is, the phase adjustment output HD_SIG is shown to make it easier to understand.
As shown in FIGS. 4 and 5, in accordance with the value of the phase adjustment data CKPHASE, the phase shift circuit 21 shifts the input horizontal synchronization signal SYNC_IN by a ¼ period of the system clock CKP. Is output to the up / down counter 22.
Then, at the start phase of the signal when the shift output DLSYNC becomes High, the up / down counter 22 counts up the clock NCKP. Further, at the end phase of the signal when the shift output DLSYNC becomes Low, the up / down counter 22 counts down the clock NCKP. The output CTR of the up / down counter 22 is input to the latch circuit 23.

The latch circuit 23 latches the output CTR with the data enable pulse ENCKP. The latch circuit 23 outputs a phase adjustment output HD_SIG in which the phase information of the four steps has changed from the output terminal.
In FIG. 4, the state where the phase adjustment output HD_SIG is generated from the output CTR by the latch circuit 23 when the data of the phase adjustment data CKPHASE is 01 is indicated by a circle and an arrow.
In the start phase, the values 0, 1, and 4 indicated by the circles in the output CTR are the next falling at the falling edge as indicated by the arrows during the period of High indicated by the diagonal lines in the data enable pulse ENCKP. During the period until the edge is reached, it is taken into the latch circuit 23 and held in a state of outputting the value.

Also, at the end phase, the values of 4, 3, and 0 indicated by ◯ in the output CTR are the following at the falling edge as indicated by the arrows in the period of High indicated by the diagonal lines in the data enable pulse ENCKP. During the period until the falling edge is reached, it is taken into the latch circuit 23 and the value is held in the output state.
FIG. 6 shows the phase adjustment output HD_SIG finally generated in the timing charts of FIGS. 4 and 5.
As shown in FIG. 6, the phase adjustment output HD_SIG has a signal waveform of four steps (system clock CKP) with the clock period of the system clock CKP as a unit according to 00, 01, 10, and 11 of the phase adjustment data CKPHASE. For a value four times the clock NCKP of the VCO 11).

4 and 5 (and FIG. 6) are cases in which the operation of the horizontal PLL correction in the PLL circuit 1 of FIG. 1 is ignored. By performing the horizontal PLL correction operation, the phase information change in the four steps is performed by correcting the clock phase of the VCO 11 by the closed loops of the first and second PLL circuit units 14a and 14b. Is adjusted in 1/4 cycle steps.
Further, when the phase correction of the horizontal PLL circuit 4 is applied, as shown in FIG. 7, due to the effect of phase correction by phase error detection by phase comparison of the first phase comparator 5 and the second phase comparator 9. The waveform of the phase adjustment output HD_SIG is equivalent to the waveform when the phase adjustment data CKPHASE in FIG. 4 is 00 regardless of the phase adjustment data CKPHASE data.
Note that the signal waveform of the phase adjustment output HD_SIG when the data of the phase adjustment data CKPHASE is 00 is symmetrical with respect to the center of the signal waveform. Even when the phase of the horizontal PLL circuit 4 is corrected, the phase state is maintained. On the other hand, the other phase adjustment output HD_SIG is not symmetrical with respect to its signal waveform with respect to its median value (or its area) and is phase-corrected by phase correction of the horizontal PLL circuit 4.

FIG. 6 also shows how the horizontal PLL is corrected. The waveform of the phase adjustment output HD_SIG when the phase adjustment data CKPHASE data is 01 in FIG. 6 is different from the case where the phase adjustment data CKPHASE data is 00 in the portion indicated by a two-dot chain line.
That is, when the phase adjustment data CKPHASE data is 01, the waveform of the phase adjustment output HD_SIG is lower by one level corresponding to the one step width in the number of four steps on the left end side than on the right end side. Then it is larger by one level.
This shift causes the horizontal PLL circuit 4 to shift the waveform of the phase adjustment output HD_SIG to the left side (the phase advance side) by the clock NCKP of the VCO 11. After the effect of this phase shift, the waveform of the phase adjustment output HD_SIG is the same as when the phase adjustment data CKPHASE is 00 except for the phase shift.

Further, as shown by the two-dot chain line in FIG. 6, when the phase adjustment data CKPHASE data is 10, the waveform of the phase adjustment output HD_SIG is lower by 2 levels on the left end side than on the left side, and the right end side Then it has increased by 2 levels.
Therefore, in this case, the phase shift data CKPHASE has the effect of shifting the phase to the left by the clock NCKP of the VCO 11 from the case where the data is 01.
Further, when the phase adjustment data CKPHASE data is 11, the waveform of the phase adjustment output HD_SIG is lower by 3 levels on the left end side and larger by 3 levels on the right end side than in the case of 00 (2 (Not shown in dotted line).
In this case, the phase shift operation to the left by the clock NCKP of the VCO 11 from the case where the data of the phase adjustment data CKPHASE is 10 works. When the phase adjustment circuit 3 'of the reference example shown in FIG. 3 is used to increase the number of phase adjustment steps by an integral multiple, the ratio of the frequency of the clock NCKP of the VCO 11 to the frequency of the system clock CKP is an integral multiple. Needs to be increased.
For example, in order to change the 4-step phase adjustment in the reference example to the 8-step phase adjustment, the frequency of the clock NCKP must be eight times the frequency of the system clock CKP.
In the current video signal processing LSI, the oscillation frequency of the VCO 11 is about 400 MHz. However, when the number of steps is doubled from four steps as described above, the oscillation frequency of the VCO 11 requires 800 MHz. This leads to a decrease in accuracy and disturbance resistance performance.
For this reason, if the number of phase adjustment steps can be doubled while maintaining the same oscillation frequency of the VCO 11 as in the reference example, it is possible to prevent the performance of the VCO 11 and the disturbance resistance performance from being lowered. In addition, a video signal processing LSI can be manufactured with a small circuit scale, and the cost can be reduced.

Hereinafter, the configuration and the like of the phase adjustment circuit 3 according to this embodiment in which the phase adjustment circuit 3 ′ of the reference example of FIG. FIG. 8 shows the phase adjustment circuit 3 according to this embodiment.
The phase adjustment circuit 3 in FIG. 8 has the same components as the phase shift circuit 21, the up / down counter 22, and the latch circuit 23 in the reference example of FIG. 3.
Here, the phase adjustment step is described as a phase adjustment circuit having eight steps as described above. Then, as shown in FIG. 14, a phase adjustment output HD_SIG having a phase shift smaller than (in this case, half of) the clock cycle of the clock NCKP of the VCO 11 can be generated.
In the configuration of FIG. 8, the clock NCKP of the VCO 11 input to the phase shift circuit 21 and the up / down counter 22 has a frequency that is four times the system clock CKP (times the number of steps) and is applied to the latch circuit 23. The data enable pulse ECKP has the same frequency as the system clock CKP.
The phase shift circuit 21 shifts the input horizontal synchronization signal (here positive polarity) SYNC_IN by 4 steps (here, not 8 steps) for each rising phase of the clock NCKP according to the value of the phase adjustment data CKPHASE. Do.

As shown in FIG. 8, in this embodiment, the phase adjustment data CKPHASE is data of 3 bits in order to perform phase adjustment for 8 steps, and the upper 2 bits thereof are applied to the phase shift circuit 21.
The phase shift circuit 21 converts the phase-shifted 1-bit shift output DLSYNC to the up / down counter 22 in the same manner as in the reference example of FIG. 3 (in this case, the phase adjustment data CKPHASE is 2-bit data). Output to.
That is, when the upper 2 bits of the 3-bit phase adjustment data CKPHASE are input to the phase shift circuit 21 and the data changes to 00, 01, 10, and 11, the phase of the shift output DLSYNC is input to the horizontal synchronization signal. With respect to the phase of SYNC_IN, the rising phase of the clock NCKP changes in a direction of being delayed by one clock.

The up / down counter 22 counts up from 0 to 5 at the start phase of the phase-shifted shift output DLSYNC, and holds 5 until the end phase. In FIG. 7, the function of holding 5 is indicated by a limiter that limits 5.
The up / down counter 22 counts down from 5 to 0 in the end phase and holds 0 until the start phase.
The lower 1-bit data of the phase adjustment data CKPHASE and the shift output DLSYNC of the phase shift circuit 21 are input to an exclusive OR circuit (abbreviated as EX-OR) 31.
In the phase adjustment circuit 3 'of FIG. 3, the output CTR of the up / down counter 22 is input to the latch circuit 23. However, in the case of the phase adjustment circuit 3 of FIG. The subtracting circuit 33, the first limiter circuit 34, the switching circuit (abbreviated as SW in FIG. 8) 35, and the second limiter circuit 36 are added.

The phase adjustment circuit 3 shown in FIG. 8 can be realized by changing the phase adjustment circuit 3 ′ of FIG. 3 by adding simple circuit elements such as an addition / subtraction circuit, and manufactured with a simple circuit configuration by a small design change. To be able to. Therefore, this phase adjustment circuit 3 can be realized at low cost. As in the case of the phase adjustment circuit 3, the PLL circuit 1 shown in FIG. 1 can be manufactured on a small scale and at low cost.
As shown in FIG. 8, the output CTR of the up / down counter 22 is input to the multiplier circuit 32. The multiplication circuit 32 outputs an output CTR2 obtained by doubling the value of the output CTR to one input terminal of the switching circuit 35.
Instead of the multiplier circuit 32, an adder circuit that adds and outputs the output CTR of the up / down counter 22 may be used. In this example, the number is doubled. However, in the case of P times, a P-input adder circuit may be employed.

The output CTR2 of the multiplication circuit 32 is input to the subtraction circuit 33. The subtraction circuit 33 subtracts 1 from the output CTR2 and outputs the result to the first limiter circuit 34. The first limiter circuit 34 limits the value to 0 when the value is 0 or less by the subtraction processing of the subtraction circuit 33. The output signal CTR2_LIM of the first limiter circuit 34 is input to the other input terminal of the switching circuit 35.
The switching of the switching circuit 35 is controlled by the output of the EX-OR 31.
The EX-OR 31 generates an EX-OR (exclusive OR) of the signal obtained by extracting the lower 1 bit of the phase adjustment data CKPHASE and the shift output DLSYNC of the phase shift circuit 21. This output selects one of the two inputs of the switching circuit 35 as a selection signal.

Specifically, when the shift output DLSYNC of the phase shift circuit 21 is 1 (High) (that is, when the up / down counter 22 counts up), if the phase adjustment data CKPHASE is 0 (Low), one input The output CTR2 of the multiplier circuit 32 input to the terminal is selected. If it is 1, the output CTR2_LIM of the first limiter circuit 34 input to the other input is selected.
On the contrary, when the shift output DLSYNC of the phase shift circuit 21 is 0 (that is, when the up / down counter 22 counts down), if the phase adjustment data CKPHASE is 0, the first input to the other input terminal is performed. The output CTR2_LIM of the limiter circuit 34 is selected. If it is 1, the output CTR2 of the multiplier circuit 32 input to one input terminal is selected. Note that a 1-bit addition circuit may be used instead of the EX-OR 31.

The output selected by the switching circuit 35 is input to the second limiter circuit 36, and the second limiter circuit 36 outputs an output CTR 2 _LIM 2 in which the value of 8 or more is limited to 8 to the latch circuit 23.
The latch circuit 23 latches the value of the output CTR2_LIM2 of the second limiter circuit 36 during the High period of the data enable pulse ENCKP in which only the duty is changed from the system clock CKP, thereby adjusting the phase of 3 bits to which the phase information is added. Output HD_SIG is generated.
Next, the operation of the phase adjustment circuit 3 according to this embodiment will be described. Similarly to the operation description of the reference example, in order to make the operation of the phase adjustment circuit 3 alone in FIG. 8 easy to understand, the operation when the horizontal PLL correction operation is ignored will be described first.

9 to 12 show operation waveform diagrams when the phase adjustment data CKPHASE data is 000 to 111 when the phase correction operation of the horizontal PLL is ignored in this way. The phase shift circuit 21 shifts the horizontal synchronization signal SYNC_IN inputted in the same manner as in the reference example in a quarter cycle of the system clock CKP according to the value of the phase adjustment data CKPHASE (however, the upper 2 bits in 3 bits). The shifted output DLSYNC is output.
As described above, this shift output DLSYNC is the same output signal as in the reference example. The shift output DLSYNC can be selected by selecting a plurality of outputs by the lower 1 bit of the phase adjustment data CKPHASE as well as the count process by the up / down counter 22 and the multiplication process by the multiplication circuit 32 as described below. The phase adjustment output HD_SIG having the number of 8 steps which is twice that of the phase adjustment output HD_SIG having the number of 4 steps in the reference example can be generated.

In this case, as in the case of the reference example, the shift output DLSYNC is generated by the phase shift circuit 21 using the value of the upper 2 bits in the phase adjustment data CKPHASE, and the clock NCKP is generated by the up / down counter 22 with respect to this shift output DLSYNC. By counting, the phase adjustment output HD_SIG is generated as shown in FIGS.
More specifically, the up / down counter 22 to which the shift output DLSYNC of the phase shift circuit 21 is input counts up from 0 to 5 at the start phase, and counts down from 5 to 0 at the end phase.
The output CTR of the up / down counter 22 is doubled by a multiplier circuit (more specifically, a double circuit) 32. This double processing is performed to generate a signal waveform having twice the number of steps as in the reference example.
Further, in order to generate the signal waveform of the odd number of steps in addition to the even number of steps when the number is doubled, processing by the subtracting circuit 33 or the like is performed.

Further, the output CTR2 of the multiplier circuit 32 and the output CTR1_LIM of the first limiter circuit 34 are switched using the lower 1 bit value in the phase adjustment data CKPHASE and output to the output side of the switching circuit 35.
In this case, in order to switch between when the shift output DLSYNC of the phase shift circuit is High and when it is Low, the value of the lower 1 bit in the phase adjustment data CKPHASE and the shift output DLSYNC of the phase shift circuit are output through the EX-OR 31. Switch with. For example, as shown in the vicinity of the center of FIG. 9, when the phase adjustment data CKPHASE is 000, the EX-OR output becomes High (1) during the period when the shift output DLSYNC of the phase shift circuit is High. Then, the switching circuit 35 selects and outputs the output CTR2 of the multiplying circuit 32. Conversely, when it becomes Low (0), the output CTR1_LIM of the first limiter circuit 34 is selected and output.

The output of the switching circuit 35 is output to the latch circuit 23 after the value of 8 or more is limited to 8 in the second limiter circuit 36. The latch circuit 23 is latched by the data enable pulse ENCKP, and a phase adjustment output HD_SIG whose phase information changes in 8 steps is output from the latch circuit 23.
Therefore, the change in the phase information in the 8 steps adjusts the phase of the system clock CKP in 1/8 cycle steps by correcting the clock phase of the VCO in the second phase comparator 9 loop of FIG. Become.
FIG. 13 shows four phase adjustment outputs HD_SIG with phase adjustment data CKPHASE data of 000, 010, 100, and 110 when the horizontal PLL correction operation is ignored.

Next, when the horizontal PLL is corrected, the phase adjustment output HD_SIG is output from the phase adjustment data CKPHASE by the action of the loop of the first phase comparator 5 and the second phase comparator 9 as shown in FIG. Depending on the value of data (000 to 111), the clock NCKP is halved, that is, 1/8 of the clock period of the system clock CKP. The signal waveform is equivalent to the signal waveform when the phase adjustment data CKPHASE is 000 or 001. In FIG. 14, the phase adjustment data CKPHASE data changes from 000 to 111 in a concise manner, so that the phase on the horizontal synchronization signal SYNC_IN side input to the phase adjustment circuit 3 according to the value of the phase adjustment data CKPHASE is shown. Is shown in a shifted display form.
When the horizontal PLL correction is applied and the phase adjustment data CKPHASE is 000, the phase adjustment output HD_SIG is not a symmetrical signal waveform, but a signal waveform that is not phase shifted from the case where the horizontal PLL correction is not performed. Become.

The operation when the horizontal PLL is not corrected will be described with reference to FIG. As shown in FIG. 13, the signal waveform of the phase adjustment output HD_SIG when the data of the phase adjustment data CKPHASE is 010 is compared with the waveform of the phase adjustment output HD_SIG when the data of the phase adjustment data CKPHASE shown above is 000. The portion indicated by the two-dot chain line is different.
That is, when the data of the phase adjustment data CKPHASE is 010, the signal waveform of the phase adjustment output HD_SIG is lower by 2 levels corresponding to the 2-step width in the number of 8 steps on the left end side than the case of 000. On the side, it is larger by 2 levels. This shift causes the horizontal PLL circuit 4 to shift the phase of the phase adjustment output HD_SIG to the left side (the phase advance side) by one clock NCKP of the VCO 11. After the effect of this phase shift, the signal waveform of the phase adjustment output HD_SIG is the same as when the phase adjustment data CKPHASE data is 000 except for the phase shift.
In the case of FIG. 6, since the maximum level of the signal waveform is 4, a phase shift of one clock NCKP has occurred with respect to the difference of one level at both ends, but in the case of FIG. Since the level is 8, a phase shift of one clock NCKP occurs with a level difference twice that of FIG.

When the data of the phase adjustment data CKPHASE is 100 or 110, the horizontal PLL operation of the horizontal PLL circuit 4 causes a phase shift of 2 and 3 clocks NCKP.
Note that the phase adjustment output HD_SIG when the data of the phase adjustment data CKPHASE is 001 causes a phase shift of 1/2 clock NCKP from the case where the data of the phase adjustment data CKPHASE is 000, as shown in FIG. The signal waveform of the phase adjustment output HD_SIG in this case is different from the case where the phase adjustment data CKPHASE data is 000 by one level at both ends.
When the phase adjustment data CKPHASE data is 011, 101, 111, the horizontal PLL operation of the horizontal PLL circuit 4 causes a phase shift of 1, 2, 3 clocks NCKP, and the phase adjustment data CKPHASE data becomes The signal waveform of the phase adjustment output HD_SIG in the case of 001 is obtained.

As described above, according to the phase adjustment circuit 3 according to the present embodiment, the ratio of the frequency of the clock NCCK that is the oscillation output signal of the VCO 11 with respect to the frequency of the system clock CKP can be increased with a small and simple circuit configuration. The number of phase adjustment steps can be increased. Therefore, the phase adjustment circuit 3 and the PLL circuit 1 can be manufactured at low cost by LSI.
When the number of phase adjustment steps is increased by P times from the phase adjustment circuit 3 ′ of the reference example, it can be realized by setting the multiplication number of the multiplication circuit 32 to P.
By doing so, the number of phase adjustment steps of the reference example can be increased by P times by the multiplication circuit 32, and the desired phase adjustment step accuracy can be ensured without changing the duty of the system clock.

  Note that two normal (up) counters may be used instead of the above-described up / down counter 22. In this case, one of the first counters is counted on the start phase side, the other second counter is counted on the end phase side, and the output value of the second counter is subtracted from the output value of the first counter by the subtraction circuit. What is necessary is just to make it the structure which subtracts.

1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention. Explanatory drawing of the operation | movement of the phase comparison by a 1st phase comparator. The block diagram which shows the structure of the phase adjustment circuit of a reference example. 6 is a timing chart showing the operation of each unit when the phase adjustment data is 00 and 01 in a state where the horizontal PLL is not corrected in the phase adjustment circuit of the reference example. 9 is a timing chart showing the operation of each unit when the phase adjustment data is 10 and 11 in a state where the horizontal PLL is not corrected in the phase adjustment circuit of the reference example. The figure which shows the signal waveform of a phase adjustment output in case the phase adjustment data is 00 to 11 in the state which does not correct | amend horizontal PLL in the phase adjustment circuit of a reference example. 9 is a timing chart showing the operation of each unit when phase adjustment data is 00 to 11 in a state where the horizontal PLL is corrected in the phase adjustment circuit of the reference example. The block diagram which shows the structure of the phase adjustment circuit which concerns on one Embodiment. 6 is a timing chart showing the operation of each unit when the phase adjustment data is 000 and 001 in a state where the horizontal PLL is not corrected in the phase adjustment circuit according to the embodiment. 9 is a timing chart showing the operation of each unit when the phase adjustment data is 010 and 011 in a state where the horizontal PLL is not corrected in the phase adjustment circuit according to the embodiment. The timing chart which shows the operation | movement of each part in case the phase adjustment data is 100 and 101 in the state which does not correct | amend horizontal PLL in the phase adjustment circuit which concerns on one Embodiment. 12 is a timing chart illustrating the operation of each unit when the phase adjustment data is 110 and 111 in a state where the horizontal PLL is not corrected in the phase adjustment circuit according to the embodiment. The figure which shows the signal waveform of a phase adjustment output in case the phase adjustment data is 000, 010,100,110 in the state which does not correct | amend horizontal PLL in the phase adjustment circuit which concerns on one Embodiment. 12 is a timing chart showing the operation of each unit when the phase adjustment data is from 000 to 111 in a state where the horizontal PLL is corrected in the phase adjustment circuit according to the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... PLL circuit 3 ... Phase adjustment circuit 4 ... Horizontal PLL circuit 14a ... 1st PLL circuit part 14b ... 2nd PLL circuit part 21 ... Phase shift circuit 22 ... Up / down counter 23 ... Latch circuit

Claims (5)

The second clock set to N (N is an integer equal to or greater than 2) times the first clock synchronized with the synchronization signal of the video signal, and exceeds the N in units of the period of the second clock. In order to generate the first clock phase-shifted with respect to the phase of the synchronization signal by the number of steps of M (M is an integer exceeding N),
A phase shift circuit that generates a phase-shifted signal corresponding to a phase adjustment instruction value up to the number of M steps using the second clock with respect to the input synchronization signal, and the phase-shifted signal In response, the counter circuit counts the second clock, and a latch circuit that latches a signal based on the output of the counter circuit.
A phase shift adjustment output signal having M different signal waveforms according to the phase adjustment instruction value is generated from the latch circuit with a time resolution in units of the period of the first clock. Phase adjustment circuit.   The phase shift adjustment output signal is input to a phase comparator that performs phase comparison constituting a phase-locked loop circuit, and an oscillation output signal of a voltage controlled oscillator whose oscillation frequency is controlled based on the output signal of the phase comparator is When input to the phase shift circuit as the second clock and the phase-locked loop circuit is set to an operating state, the phase adjustment circuit determines whether the phase adjustment instruction value is greater than the period of the second clock. 2. The phase adjustment circuit according to claim 1, wherein phase adjustment output signals having different phase shift amounts are output in units of a small time.   The counter circuit includes an up / down counter that counts up the second clock on a start phase side of the phase shift signal and down-counts the second clock on an end phase side. The phase adjustment circuit according to claim 1 or 2.   4. The circuit according to claim 1, further comprising: a P multiplier circuit that multiplies the value of the output signal of the counter circuit when the M is P times the N (P is an integer of 2 or more). 5. The phase adjustment circuit according to any one of claims. A clock output from the voltage controlled oscillator is divided by N (N is an integer of 2 or more) by a frequency divider to generate a system clock, and the clock is directly or divided to be phase-shifted by a first phase comparator. A first phase-locked loop unit that controls the oscillation frequency of the voltage-controlled oscillator with a compared signal;
A phase adjustment output generated by shifting the phase of the input video signal synchronization signal by the number of steps of M exceeding N (M is an integer exceeding N) in units of the clock cycle by a phase adjustment circuit. A comparison signal generated to synchronize the signal from the system clock with the period of the synchronization signal is phase-compared by a second phase comparator, and an analog waveform generated based on the result of the phase comparison A second phase-locked loop unit that inputs a signal to the first phase comparator and controls the oscillation frequency of the voltage-controlled oscillator in common with the case of the first phase-locked loop unit;
The phase adjustment circuit is capable of outputting the phase shift adjustment output signals having the M different signal waveforms with a time resolution in units of the period of the first clock. Locked loop circuit.

Images