JP2008054352A - Signal transmission circuit, cmos device and circuit substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a transmission characteristic of a transmission line having a large electrostatic capacitance formed by a long signal line formed in a large-scale integrated circuit, a large number of connected driven circuits or the like. <P>SOLUTION: A middle-point voltage in electric source voltages of driving and driven circuits is output. Then, an additional circuit with low output impedance is connected to the signal line to keep a potential of the drive circuit at the middle-point voltage of the electric source voltage. Besides, a drive signal output from the drive circuit is excited at small amplitude with the middle-point voltage (a threshold voltage of the driven circuit) defined as a center of the amplitude, so that the driven circuit is driven by the drive signal whose amplitude is limited to the small amplitude. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal transmission circuit, a CMOS semiconductor device, and a circuit board, and more particularly to a signal transmission circuit, a CMOS semiconductor device, and a circuit board having an additional circuit.

  As the scale of the semiconductor integrated circuit element increases, the shape of the semiconductor chip that forms the semiconductor integrated circuit element also increases in size, and the signal lines formed therein (for example, signal lines that distribute clocks, signal lines that constitute bus lines, etc.) The wiring length tends to be long.

  FIG. 1 shows various forms of signal lines formed in an integrated circuit element. The large-scale integrated circuit element is formed on a regular square semiconductor chip CP having a side of about 15 to 20 mm. Therefore, the signal line LIN formed inside has a long line length, and in many cases reaches 20 mm or more.

  A shown in FIG. 1 indicates a wiring configuration in which the line length of the signal line LIN between the drive circuit DR and the driven circuit RC is 100 μm or less. B shows the wiring configuration when the line length is 20 mm or more. C indicates a wiring configuration in the case where a number of driven circuits RC are connected to the signal line LIN, such as a bus line or a clock distribution line.

  FIG. 2 shows an electrical equivalent circuit of each of these wiring forms A, B, and C.

  A wiring capacitance CL is generated in the signal line LIN connecting the drive circuit DR and the driven circuit RC, and an input capacitance CG is formed at the input end of the driven circuit RC. These wiring capacitance CL and input capacitance CG have different values depending on the wiring configurations A, B, and C, respectively. The input capacitance CG has a value proportional to the number of driven circuits RC to be connected, and the wiring capacitance CL has a value proportional to the length of the signal line LIN.

  When the wiring forms A, B, and C are viewed from this viewpoint, the capacitance value of the wiring form A connected to the signal line LIN is the smallest, and the capacitance value increases in the order of the wiring form B and the wiring form C next. Thus, a large difference occurs in the signal transmission characteristics depending on the capacitance value.

  FIG. 3 shows step response waveforms when step pulses are applied to the signal lines of these various wiring forms A, B, and C. 3A shows a step response waveform of the wiring configuration A shown in FIG. 1, FIG. 3B shows a step response waveform of the wiring configuration B shown in FIG. 1, and FIG. 3C shows a step response waveform of the wiring configuration C shown in FIG. As is clear from FIG. 3, the delay of the rise of the step waveform is hardly observed in the line length of the wiring form A shown in FIG. 1, but the step waveform becomes large in the wiring forms B and C, and a large response delay is generated. To do. In particular, the tendency appears remarkably in the wiring form C in which the signal line LIN is long and many driven circuits RC are connected.

  FIG. 4 shows a pulse response waveform. In the wiring form A, the input pulse is transmitted to the driven circuit RC almost normally, but in the wiring forms B and C, the pulse is hardly transmitted to the driven circuit RC. That is, it can be understood that a pulse having a narrow pulse width cannot be transmitted through a signal line having a large capacitance. This is a factor that hinders the increase in size of semiconductor chips.

  Further, as a similar phenomenon, the same applies to signal lines that connect integrated circuit elements mounted on a circuit board (printed wiring board).

  In order to increase the degree of integration of semiconductor integrated circuit elements, the processing dimensions of elements such as transistors must be miniaturized and the line width of wiring must be narrowed. In this respect, the capacitance value generated in the signal line is considered to be small. However, since the insulating layer is formed thin at the same time as the line width is narrowed, the wiring capacity CL of the signal line and The input capacitance CG of the driven circuit RC is not greatly reduced even if the formation area is reduced to improve the degree of integration.

On the other hand, in order to solve this inconvenience, for example, in a circuit that distributes clock pulses to a large number of circuit areas MAP as shown in FIG. 5, a large-capacity driving circuit DR ₁ , a medium-capacity driving circuit DR ₂ , Although a method of connecting DR ₃ is also conceivable, connecting the drive circuits DR ₁ , DR ₂ , DR ₃ to each signal line LIN in this way increases the number of circuits in the integrated circuit and increases power consumption. In addition, since more circuits pass through, the timing accuracy also deteriorates.

  An object of the present invention is to propose a signal transmission circuit capable of reliably transmitting a signal even with a long signal line without increasing the degree of integration in the integrated circuit.

  Accordingly, an object of the present invention is to provide a signal transmission circuit, a CMOS semiconductor device, and a circuit board that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  The present invention proposes a signal transmission circuit having a configuration in which an additional circuit having a low output impedance and outputting a midpoint voltage of a power supply voltage is connected to one of signal lines.

  According to the signal transmission circuit of the present invention, by connecting an additional circuit that outputs a potential at the midpoint of the power supply voltage to a signal line having a large wiring capacitance or input capacitance, the output impedance is low. The potential is driven around the midpoint potential of the power supply voltage. That is, the driven circuit is driven around its own threshold voltage.

  Since the output impedance of the additional circuit is low, the amplitude of the signal is suppressed to a small amplitude. However, since the driven circuit is driven around its own threshold, even if the amplitude of the applied signal is small, it can be reliably turned on and off to receive the signal. In addition, since the output impedance of the additional circuit is low, the time constant for determining the transition time of the transmission signal (in this case, the product of the resistance and the capacitance) is small, so that a high-speed signal can be passed.

  Therefore, even a signal line having a large sum of wiring capacitance and input capacitance can be transmitted without giving waveform distortion to the input pulse.

  In addition, since the amplitude of the transmission signal is reduced, the transient charge / discharge current to the wiring capacitance and the input capacitance is reduced, and the power consumption during operation can be reduced.

In order to solve the above-described problem, one form of the present invention is a drive circuit for sending a transmission signal, a signal line for propagating the transmission signal, and two power supply voltages V _SS and V _DD (V _DD > V _SS ). driven by the signal transmission circuit comprising a driven circuit incorporating the transmission signal propagated in the signal line, to said signal line, greater than said power supply voltage V _SS, the power supply voltage V _DD is less than a predetermined voltage A signal transmission circuit including an additional circuit that outputs the signal is provided.

  In one aspect of the present embodiment, in the signal transmission circuit, the driven circuit includes a digital circuit that outputs one of binary output voltages according to the input voltage, and the additional circuit includes: The digital circuit outputs a voltage that substantially matches the threshold voltage at which one of the binary output voltages is inverted from one to the other.

In another aspect of the present embodiment, in the signal transmission circuit, the additional circuit outputs a voltage approximately at the midpoint between the power supply voltages V _SS and V _DD .

  In still another aspect of the embodiment, in the signal transmission circuit, the additional circuit has an output impedance lower than the output impedance of the drive circuit.

  In still another aspect of this embodiment, in the signal transmission circuit, the output impedance of the additional circuit is 1/2 to 1/4 of the output impedance of the drive circuit.

  In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit includes a first inverter and a feedback circuit in which an input terminal and an output terminal of the first inverter are connected.

  In still another aspect of the embodiment, in the signal transmission circuit, the driven circuit includes a second inverter, and the first inverter has a beta ratio substantially equal to that of the second inverter.

  In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit includes a P-type FET and an N-type FET, and a forward bias is applied to each of the gates of the P-type FET and the N-type FET. A voltage is applied.

In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit includes a voltage source that outputs a predetermined voltage that is higher than the power supply voltage V _{SS and} lower than the power supply voltage V _DD .

  In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit further includes a low impedance buffer circuit that lowers an output impedance of the voltage output from the voltage source.

  In still another aspect of the present embodiment, the signal transmission circuit includes a blocking unit that blocks a current flowing between the signal line and the additional circuit.

  In still another aspect of the embodiment, in the signal transmission circuit, the additional circuit includes a NAND gate and a feedback circuit in which one input terminal and an output terminal of the NAND gate are connected.

  In still another aspect of the present embodiment, in the signal transmission circuit, the NAND gate has a control terminal to which a control signal for cutting off a current flowing between the signal line and the additional circuit is input.

  In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit includes a NOR gate and a feedback circuit in which one input terminal and an output terminal of the NOR gate are connected.

  In still another aspect of the present embodiment, in the signal transmission circuit, the NOR gate has a control terminal to which a control signal for cutting off a current flowing between the signal line and the additional circuit is input.

  In still another aspect of the present embodiment, in the signal transmission circuit, the additional circuit is connected to a terminal end of the signal line.

In order to solve the above problem, another embodiment of the present invention provides a drive circuit for sending a transmission signal, a signal line for propagating the transmission signal, and two power supply voltages V _SS and V _DD (V _DD > V _In the CMOS semiconductor device formed with a signal transmission circuit having a driven circuit that takes in the transmission signal that is driven by _SS ) and propagated through the signal line, the signal transmission circuit has the power supply voltage with respect to the signal line. There is provided a CMOS semiconductor device having an additional circuit for outputting a predetermined voltage larger than V _{SS and} smaller than the power supply voltage V _DD .

  In one aspect of the present embodiment, in the CMOS semiconductor device, the additional circuit has an output impedance lower than the output impedance of the drive circuit.

  In another aspect of the present embodiment, in the CMOS semiconductor device, a beta ratio of the additional circuit is substantially equal to a beta ratio of the driven circuit.

In order to solve the above-described problem, still another embodiment of the present invention provides a first semiconductor device having a drive circuit for sending a transmission signal, and two power supply voltages V _SS and V _DD (V _DD > V _SS ). A circuit board comprising: a second semiconductor device that is driven and has a driven circuit that captures the transmission signal; and a signal line pattern that propagates the transmission signal from the driving circuit to the driven circuit. A circuit board comprising an additional circuit that outputs a predetermined voltage that is larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _DD is provided.

  In one aspect of the present invention, the additional circuit has an output impedance lower than the output impedance of the drive circuit.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

According to the present invention, by connecting the additional circuit to the signal line LIN, the signal line LIN is excited with a slight amplitude around the midpoint voltage of the power supply voltage. Moreover, the transition time is shortened by inserting a low resistance in parallel with the capacitor that degrades the response speed. As a result, the driven circuit RC inverts at a timing when the voltage slightly changes from the timing of inversion of the signal of the driving circuit DR, and detects the inversion timing of the signal sent from the driving circuit DR with a slight time delay. be able to. That is, the response speed of the driven circuit RC can be increased. As a result, even if a pulse with a narrow pulse width is output from the drive circuit DR, this pulse can be reliably detected and reproduced on the output side of the driven circuit RC. Further, in the present invention, even if the power supply voltage fluctuates, the midpoint voltage V _C output from the additional circuit changes following the fluctuation. Therefore, even if the power supply voltage fluctuates at this point, the threshold value of the driven circuit RC. Can always be operated normally.

  Therefore, in a large-scale semiconductor integrated circuit having a large shape of the semiconductor chip CP, for example, even if the total length of the signal line for clock distribution becomes long, the clock can be reliably sent to the terminal side of the signal line for clock distribution. it can.

  In addition, not only clock distribution lines but also bus lines such as bus lines, data is sent to all data reception circuits even if the signal line is connected to a large number of input capacitors. Can do. Therefore, a large-scale integrated circuit can be realized by applying the present invention.

  An additional circuit having a beta ratio equal to the beta ratio of the driven circuit and comprising a full feedback circuit can automatically generate a voltage that matches the logical threshold voltage of the driven circuit. In particular, when both the driven circuit RC and the additional circuit are formed on the same device (semiconductor chip), even if the logical threshold voltage of the driven circuit RC varies due to temperature variation, for example, Since the output voltage also fluctuates following the logical threshold voltage, highly accurate transmission is possible. Further, when the driven circuit RC and the additional circuit are formed on the same device, signal transmission in the device is not affected by the manufacturing deviation.

  Further, the present invention proposes a configuration in which a cutoff terminal CUT is attached to a circuit such as an additional circuit and a midpoint voltage source, and the current flowing through the circuit such as the additional circuit and the midpoint voltage source can be controlled to a cutoff state by this cutoff means. Therefore, even if the additional circuit and the midpoint voltage source are in a stationary state and a circuit that consumes an idling current, the idling current can be removed by controlling the circuit to the cut-off state.

  As a result, when an integrated circuit element incorporating an additional circuit or a midpoint voltage source is manufactured, when testing the semiconductor integrated circuit element, there is also an advantage that a quiescent current measurement can be easily performed.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are the solution of the invention. It is not always essential to the means.

  FIG. 6 shows an embodiment of a signal transmission circuit according to the present invention. DR, RC, LIN, CL, and CG shown in FIG. 6 indicate a drive circuit, a driven circuit, a signal line, a wiring capacitance, and an input capacitance, respectively, as described in the figure.

  In the present invention, an additional circuit is connected to one of the signal lines LIN. The additional circuit can be configured by connecting the entire feedback circuit NF to an inverter IV (polarity inverting circuit) configured by a CMOS circuit, for example.

  When high-speed signal transmission is performed, the signal propagated through the signal line is reflected by the driven circuit, and an overshoot and undershoot may occur in the signal waveform captured by the driven circuit. In order to reduce such overshoot and undershoot, an additional circuit may be connected to the end of the signal line LIN.

FIG. 7 shows an example of a specific circuit structure. In this example, an example is shown in which the drive circuit DR and the driven circuit RC also use inverters configured by CMOS circuits. The additional circuit can also be configured by connecting the full feedback circuit NF to an inverter having a CMOS circuit structure. According to the circuit structure of the additional circuit, the potential at the common connection point J of the input terminal and the output terminal of the inverter can be stabilized at substantially the midpoint potential of the power supply voltage V _DD -V _SS . The reason will be described with reference to FIG.

  In FIG. 8, a curve Y indicates the DC transfer characteristic (relationship of the output voltage with respect to the input voltage) of the inverter IV.

  Since the inverter has a logic inversion (negation) function, it exhibits a downward-sloping characteristic in the vicinity of the logical threshold.

  Here, in order to construct the additional circuit according to the present invention, if the input and output terminals are short-circuited (or connected by an element such as a resistor) and the total feedback is applied, the input and output voltages are equal. When a straight line X of Vin = Vout is drawn on the curve Y, it can be seen that the output voltage of this circuit is equal to the intersection of the straight line X and the curve Y.

  This intersection is just the point at which the output voltage inverts in the DC transfer characteristic, i.e., equal to the logical threshold of the inverter.

  If the on-resistances of the P-type FET and N-type FET constituting the inverter are equal, this intersection is the exact midpoint of the power supply voltage.

  Here, for simplicity, the term on-resistance is used, but it actually has non-linearity. In order to express a bit more accurately, a number called a drain coefficient β is used as an index representing the ease of flow of the drain current of the FET.

  Drain current coefficient β: a proportionality constant determined by the size, aspect ratio, etc. of the MOSFET.

  When β of N-type FET and P-type FET are βn and βp, respectively,

  βn = (W / Leff) · (εox / Tox) · μn, eff

  βp = (W / Leff) · (εox / Tox) · μp, eff

  W: gate width, Leff: effective gate length, Tox: gate oxide film thickness, εox: gate oxide film dielectric constant, μn, eff: effective electron mobility, μp, eff: effective hole mobility

If this β is used, the drain current of the MOSFET can be simply expressed as follows.
Id = β {(Vgs−Vt) Vds− (1/2) (Vds ² )}

(Vds ≦ Vgs−Vt)
Id = (1/2) β (Vgs−Vt) ² (Vds> Vgs−Vt)

In the case of silicon, the mobility of holes is about half of the mobility of electrons, so if N-type FET and P-type FET are made in the same shape (assuming that the threshold voltages are equal)
(1) N-type FETs have twice as much current as P-type FETs.
(2) The on-resistance of the N-type FET is half that of the P-type FET.
It can be said.

  In a normal element, it is usual to make β of N-type FET and P-type FET equal or make the shapes (W, H) equal.

  When the ratio of βp of the P-type FET to βn of the N-type FET (βR = βn / βp, beta ratio) is changed by about 10 times, the change is about the curves Y1 and Y2 shown in FIG. However, Y1 can be, for example, βn> βp, (βR = 10), and Y2 can be βn <βp, (βR = 0.1) (βn, βp are the drain currents of the N-type FET and P-type FET, respectively. coefficient).

In this case, by setting as with additional circuit beta ratio of the inverter IV is also N-type FETs Q _N and P-type FETs Q _P which constitutes the driven circuit RC, the power supply voltage V threshold voltage driven circuit RC is inverted operation it can be matched to the midpoint voltage of _DD -V _SS. Accordingly, by setting the relationship between the inverter IV constituting the additional circuit and the inverter constituting the driven circuit RC to the above-described relationship (generally said to have the same beta ratio), the driven circuit RC is self- The signal sent from the drive circuit DR is received centering on the threshold voltage.

FIG. 9 shows an equivalent circuit of this signal transmission circuit. The drive circuit DR can be equivalently represented by a switch SW. R _OUT represents the output impedance of the drive circuit DR. In FIG. 9, the DC resistance of the signal line LIN is omitted. RM represents an equivalent resistor equal to the output impedance of the additional circuit. That is, the additional circuit can be represented as a circuit connected to the midpoint voltage V _C through the equivalent resistor RM having a resistance value R _T.

When the switch SW is switched to the contact A side in the drive circuit DR, the positive voltage V _DD is applied to the signal line LIN through the output impedance R _OUT . At this time, a current I ₁ flows through the impedance R _T of the equivalent resistor RM, and a voltage E ₁ (FIGS. 10A and 10B) that deviates to the positive side from the midpoint voltage V _C is generated at the connection point J. This voltage _{E 1} is

E ₁ = (V _DD −V _C ) R _T / (R _T + R _OUT )
It is represented by

On the other hand, when the switch SW is switched to the contact B side in the drive circuit DR, the power supply voltage V _SS is applied to the signal line LIN. Therefore, at this time, the current I ₂ flows through the impedance _{RT of the} additional circuit, and the voltage at the contact J swings to the negative side by E ₂ from the midpoint potential V _C. This voltage _{E 2} is

E ₂ = (V _SS −V _C ) R _T / (R _T + R _OUT )
It is represented by

The resistance value R _T of the equivalent resistor RM of the additional circuit is a small value as described above, and has a relationship of R _T << R _OUT . Therefore, the amplitudes E ₁ and E ₂ of the signal generated at the connection point J are very small values. However, since the driven circuit RC operates using the midpoint potential V _C as the threshold value for the inversion operation, the voltages E _A and E _B (within the amplitude range of the voltages E ₁ and E ₂ generated at the connection point J) The inversion operation is reliably performed in FIG. 10B). Accordingly, the driven circuit RC inverts immediately when the potential at the connection point J slightly crosses the midpoint voltage V _C , the sum of the wiring capacitance CL and the input capacitance CG is large, and the potential change in the signal line LIN is delayed. Even if it exists, the output of the driven circuit RC can be transmitted in a waveform with almost no waveform distortion, as shown in FIG. 10C.

The relationship between the output impedance _RT and the output impedance _ROUT will be described.
The voltages E ₁ and E ₂ are a function of R _T and R _OUT as shown in the above equation. The smaller the value of R _T, the voltage _{E 1} and _{E 2} is a very small value. However, the driven circuit RC has a threshold voltage, and the value of _RT must be determined within the sensitivity range of the signal of the driven circuit RC. The maximum input voltage at which the driven circuit RC can output a stable L or H value when the input is L is V _thL, and when the input is H, the driven circuit RC is stable H or Let V _thH be the minimum input voltage that can output the value of L. When the input is gradually increased from L, the input voltage when the output of the driven circuit RC starts to change substantially is V _thL, and when the input is gradually decreased from H, the output of the driven circuit RC is The input voltage when V substantially starts to change may be V _thH . For example, the input voltage V _thH of the driven circuit RC is about V _C + (V _DD −V _C ) × 0.2, and similarly the input voltage V _thL is about V _C + (V _SS −V _C ) × 0.2. , The ratio of R _T and R _OUT is preferably (1) :( 4 or less) from the equations of voltages E ₁ and E ₂ . The value obtained by dividing _RT by _ROUT is more preferably between 1/2 and 1/4.

In this specification, the term “midpoint voltage” does not necessarily mean only the central voltage between the power supply voltages V _DD and V _SS . As described with reference to FIG. 8, the midpoint voltage means any voltage between the power supply voltages V _DD and V _SS depending on the value of the beta ratio, and may vary from the center voltage.

  Therefore, even if the signal line LIN has a large number of driven circuits RC connected to the signal line LIN as shown in FIG. 11, each of the driven circuits RC is connected by connecting an additional circuit to the signal line LIN. It operates following the change of the output voltage of the drive circuit DR, and for example, clock pulses having the same timing (no time lag) can be given to each driven circuit RC.

  FIG. 12 shows a modified embodiment of FIG. In this embodiment, it indicates that the circuit operates normally regardless of the position of the signal line LIN connected to the additional circuit.

In the above description, the signal lines LIN formed in the same semiconductor chip are all described. When the present invention is applied to the signal line LIN formed outside the integrated circuit, as shown in FIG. 13, for example, in the case of the signal line LIN connected between the integrated circuit elements LSI ₁ and LSI ₂ , the signal line LIN An additional circuit must be connected to the terminal side of LIN. That is, the signal line LIN formed outside the integrated circuit element generally uses a distributed constant circuit such as a microstrip line in order to match the characteristic impedance to a predetermined impedance. Since the distributed constant circuit is partially inductive and capacitive, as a result, it is desirable to connect an additional circuit to the end of the signal line LIN as shown in FIG.

FIG. 13 shows a circuit board which is an embodiment of the present invention. This circuit board has a pattern of LSI ₁ and LSI ₂ and a signal line LIN. An additional circuit is connected to the signal line LIN. The LSI ₁ has a drive circuit that sends out a transmission signal, and the LSI ₂ has a driven circuit that takes in the transmission signal. As described above, the additional circuit is connected to the end of the signal line LIN. This additional circuit outputs a predetermined voltage that is higher than the power supply voltage V _{SS and} lower than the power supply voltage V _DD as in the previous embodiments. The additional circuit has an output impedance lower than the output impedance of the driving circuit of the LSI ₁ .

14 and 15 show a modified embodiment of the additional circuit. The additional circuit shown in FIG. 14 shows a case where a forward bias voltage is directly applied to the gates of the P-type FET Q _P and the N-type FET Q _N , respectively. With this configuration, the P-type FET Q _P and the N-type FET Q _N are always kept on, the potential at the connection point J is maintained at the midpoint voltage of the voltages V _DD and V _SS , and low impedance Operates as a midpoint voltage source.

FIG. 15 shows a case where the additional circuit is configured by combining the low impedance buffer circuit LOW and the midpoint voltage source EJV. The configuration of the low impedance buffer circuit LOW is exactly the same as that of the inverter. The drain of the N-type FET Q _N is connected to the positive voltage V _DD side, the drain of the P-type FET Q _P is connected to the negative voltage V _SS side, and the gate and source are respectively connected. The common point is connected, and the midpoint voltage V _C is applied from the midpoint voltage source EJV to the common connection point of the gates.

FIG. 16 shows an equivalent circuit of the low impedance buffer circuit LOW shown in FIG. N-type FETs Q _N and P-type FETs Q _P which constitutes the impedance buffer circuit LOW shown in FIG. 15 can be viewed as a voltage buffer with a gain 1, having the same resistance value R _U to the output impedance in the same manner as shown in FIG. 10 It can be expressed by an equivalent resistor RM and a midpoint voltage source EJV.

Therefore, in a state where the drive circuit DR outputs L logic, the current I ₁ flows from the equivalent resistor RM toward the signal line LIN, and the potential at the connection point J is slightly decreased from the midpoint potential to the negative potential V _SS. It is biased in the (L logic) direction. Therefore, at this time, the driven circuit RC is in a state of outputting H logic.

On the other hand, when the drive circuit DR is inverted to the state of outputting H logic, the current I ₂ flows from the signal line LIN to the midpoint voltage source EJV through the equivalent resistor RM. The potential at the connection point J by the current I ₂ flows is biased proximally Nuisance direction slightly positive voltage V _DD from the middle point potential V _C. Therefore, in this state, the driven circuit RC is inverted to a state of outputting L logic.

The resistance value R _U of the equivalent resistor RM shown in FIG. 16 is larger than the resistance value R _T of the equivalent resistor shown in FIG. 9, the potential of R _OUT >> R relationship _U is maintained connection point J The change can be suppressed to a slight amplitude fluctuation. Accordingly, as described with reference to FIGS. 9 and 10, the time (because the voltage change is small) from the timing when the output state of the drive circuit DR is inverted to the threshold value of the driven circuit RC can be shortened. The response speed of the driven circuit RC can also be increased by the embodiment shown in FIG.

In the embodiment shown in FIG. 15, the case where the midpoint voltage source EJV is constituted by a resistance dividing circuit is shown. However, the midpoint voltage source EJV has an additional circuit shown in FIG. 7 or an additional circuit shown in FIG. Can also be used. When the additional circuit is configured by the midpoint voltage source EJV and the low impedance buffer circuit LOW, the midpoint voltage V _C is applied to a plurality of low impedance buffer circuits LOW by one midpoint voltage source EJV as shown in FIG. The additional circuit may be connected to a plurality of signal lines.

  By the way, in the semiconductor integrated circuit having the CMOS structure, the current consumption almost converges to a value close to 0 when the active element is maintained in a stationary state. Therefore, when testing a semiconductor integrated circuit device, there is usually an item for measuring the current at rest and testing whether the current value is equal to or less than a specified value. On the other hand, if the additional circuit described above is incorporated in a semiconductor integrated circuit element, the additional circuit consumes current even in a stationary state. As a result, the integrated circuit element incorporating the additional circuit becomes an element incapable of measuring the quiescent current.

  In the embodiment shown in FIG. 18 to FIG. 21, in order to eliminate this inconvenience, a blocking means CUT is added to the additional circuit, a control signal is given to this blocking means CUT, and the current flowing through the additional circuit is cut off as necessary. It is configured to allow current measurement.

  The example shown in FIG. 18 shows an example in which a blocking means CUT is added to the additional circuit shown in FIG. The shut-off means CUT has a control terminal CT, and in this example, the additional circuit is maintained in the operating state by applying H logic to this control terminal CT, and is switched to the non-operating state when L logic is applied. The case where it is configured to be controlled so as not to consume at all will be shown.

That is, when H logic is applied to the control terminal CT, the FETs Q ₁ and Q ₃ are controlled to be off and Q ₂ and Q ₄ are controlled to be on. FETs Q ₂ is turned on, _{since Q 1} is controlled to the OFF state, FETs Q ₅ is turned on, _{Q 6} is controlled to the OFF state. As a result, the FETs Q ₄ and Q ₅ are controlled to be in an ON state, and the gates of the FETs Q _P and Q _N are connected to each other through the FETs Q ₄ and Q _{5 to} operate as an additional circuit.

When L logic is applied to the control electron CT, the FETs Q ₁ and Q ₃ are controlled to be on and the FETs Q ₂ and Q ₄ are controlled to be off. FETs Q ₁ is turned on, since the FETs Q ₂ is controlled to the OFF state, FETs Q ₅ is turned off, _{Q 6} is controlled to the ON state. That, FETs Q ₄ and _{Q 5} are controlled to the OFF state, since FETs Q ₃ and _{Q 6} are controlled to ON-state, FETs Q _P and Q _N are controlled in the OFF state. Here, FETs Q ₁ , Q ₃ , and Q ₆ are controlled to be in an on state, but FETs Q ₂ , Q ₄ , and Q ₅ connected in series to these are controlled to be in an off state. Current will not flow. Therefore, the quiescent current measurement can be performed if the control terminal CT is in a state where L logic is applied.

In the embodiment shown in FIG. 19, the blocking means CUT is constituted by a switch element ANS generally called an analog switch or the like. By controlling the switch terminal ANS in the off state, the FETs Q _P and Q _N constituting the additional circuit are controlled in the off state.

FIG. 20 shows a case where a blocking means CUT is added to the additional circuit shown in FIG. The difference between Figure 18 and that the source electrode of the FETs Q ₄ is connected to the negative electrode power supply V _SS, is that the source electrode of the FETs Q ₅ is connected to a positive source V _DD. When these FETs Q ₄ and Q ₅ are controlled to be in an ON state by applying H logic to the control terminal CT, forward bias voltages V _SS and V _DD are applied to the gates of the P-type FET Q _P and the N-type FET Q _N , respectively. Given, the P-type FET Q _P and the N-type FET Q _N are controlled to be in an ON state and operate as an additional circuit.

When the control terminal CT give L logic, FETs Q ₄ and _{Q 5} are turned off, _{Q 3} and _{Q 6} are controlled to ON-state, P-type FETs Q _P and N-type FETs Q _N in this state is controlled to the OFF state The current consumption is controlled to be almost zero.

FIG. 21 shows a configuration in which a blocking means is added when the additional circuit is configured by combining the low impedance buffer circuit LOW and the midpoint voltage source EJV shown in FIG. In this embodiment, the additional circuit shown in FIG. 7 is used as the midpoint voltage source EJV. CUT1 is a cutoff means for controlling the P-type FET Q _P1 and N-type FET Q _N1 constituting the midpoint voltage source EJV to be in a cutoff state, and CUT ₂ is an N-type FET Q _N2 and P-type FET Q _P2 constituting the low impedance buffer circuit LOW. The shut-off means for controlling to a shut-off state is shown.

When logic H is applied to the control terminal CT, the FET Q _4-1 and Q _5-1 are controlled to be turned on in the cutoff means CUT ₁ , and each of the P-type FET Q _P1 and N-type FET Q _N1 constituting the midpoint voltage source EJV is controlled. The gate is connected through these FETs Q _4-1 and Q _5-1 . As a result, the same circuit as that shown in FIG. 7 is formed, and a midpoint voltage is output to the connection point J1.

On the other hand, by the H logic is supplied to the blocking means CUT2 the input terminal CT, _{FETs Q 4-2} and _{FETs Q 5-2} are controlled to ON-state. Midpoint result, N-type FETs Q _N2 and P-type FETs Q _P2 constituting the low-impedance buffer circuit LOW has a gate commonly connected through _{FETs Q 4-2} and _{FETs Q 5-2,} from the midpoint voltage source EJV to the common connection point A voltage is given. Therefore, in this state, the N-type FET Q _N2 and the P-type FET Q _P2 have the same circuit structure as the low-impedance buffer circuit LOW shown in FIG. 15, and a signal potential is applied to the connection point J2 from the drive circuit DR. It operates in the same way as described in.

When L logic is applied to the input terminal CT, _{FETs Q 3-1} and _{Q 6-1} in blocking means CUT1 is _{on, Q 4-1} and _{Q 5-1} constitute an intermediate voltage source EJV from being controlled to be off The P-type FET Q _P1 and the N-type FET Q _N1 are controlled to be off.

Since _{FETs Q 4-2} and _{FETs Q 5-2} in blocking means CUT2 _{off, Q 3-2} and _{Q 6-2} are controlled to ON-state, N-type FETs Q _N2 and the P-type constituting the low-impedance buffer circuit LOW The FET Q _P2 is controlled to be in an off state.

  Therefore, even in the additional circuit shown in FIG. 21, when the logic L is applied to the control terminal CT, all currents are cut off, and the quiescent current can be measured.

  In the embodiments so far, the configuration in which the full feedback circuit NF is connected to the inverter IV has been described as the additional circuit. Hereinafter, an embodiment in which an additional circuit is formed using a circuit other than the inverter IV, for example, a NAND gate and a NOR gate will be described.

  FIG. 22 shows another embodiment of the signal transmission circuit according to the present invention. Compared with the embodiment shown in FIG. 6, the additional circuit shown in FIG. 6 has an inverter IV, whereas the additional circuit according to this embodiment has a NAND gate. The additional circuit shown in FIG. 22 is configured by connecting a total feedback circuit NF to a NAND gate. Since the NAND gate has a plurality of input terminals, one terminal can be used as the control terminal CT as shown in the figure.

  FIG. 23 shows an example of a specific configuration of an additional circuit using NAND gates. In this circuit configuration, the operation of the additional circuit can be turned on / off by switching the input signal of the control terminal CT between H logic and L logic. In this embodiment, when an H logic is applied to the control terminal CT, the additional circuit is maintained in an operating state, and a midpoint potential can be output. When an L logic is applied to the control terminal CT, the additional circuit is not operated. The state is switched and the output is set to H.

Referring to the circuit diagram of FIG. 23, given a logical H to the control terminal CT, FETs Q ₁ is turned on, FETs Q ₄ is controlled to the OFF state. Therefore, it is maintained in the drain mutual FETs Q ₂ and FETs Q ₃ is connected, the additional circuitry is maintained in the operating state, and outputs a midpoint potential. As described above, by setting as with additional circuit beta ratio of N-type FETs Q _N and P-type FETs Q _P which constitutes the driven circuit, a power supply voltage threshold voltage driven circuit RC is reversed operation V _DD - can be matched to the midpoint voltage of V _SS, the driven circuit RC becomes possible to receive a signal sent from the driving circuit DR mainly its own threshold voltage.

On the other hand, given a logic L to the control terminal CT, FETs Q ₁ is off, FETs Q ₄ is controlled to ON-state. Therefore, the potential of the common connection point J is always H. At the time of a leakage current test (static current test) of a semiconductor integrated circuit element, it is necessary to set the output of the transmission side (drive circuit DR) equal to the potential at the common connection point J.

  In this manner, by controlling the input of the control terminal CT, the operation of the additional circuit configured using the NAND gate can be turned on / off.

  FIG. 24 shows still another embodiment of the signal transmission circuit according to the present invention. Compared to the embodiment shown in FIG. 6, the additional circuit shown in FIG. 6 has an inverter IV, whereas the additional circuit according to this embodiment has a NOR gate. The additional circuit shown in FIG. 24 is configured by connecting a total feedback circuit NF to a NOR gate. Further, since the NOR gate has a plurality of input terminals, one terminal can be used as the control terminal CT as shown in the figure.

  FIG. 25 shows an example of a specific configuration of an additional circuit using a NOR gate. In this circuit configuration, the operation of the additional circuit can be turned on / off by switching the input signal of the control terminal CT between H logic and L logic. In this embodiment, when an L logic is applied to the control terminal CT, the additional circuit is maintained in an operating state, and a midpoint potential can be output. When an H logic is applied to the control terminal CT, the additional circuit is not operated. The state is switched and the output is set to L.

Referring to the circuit diagram of FIG. 25, given a logic L to the control terminal CT, FETs Q ₁ is off, FETs Q ₂ is controlled to the ON state. The drain of the FETs Q ₃ are connected to the source of the FETs Q _2, since the FETs Q ₂ is turned on, is maintained in the drain mutual FETs Q ₃ and FETs Q ₄ are connected, the operating state as an additional circuit Is maintained and the midpoint potential is output. As described above, by setting as with additional circuit beta ratio of N-type FETs Q _N and P-type FETs Q _P which constitutes the driven circuit, a power supply voltage threshold voltage driven circuit RC is reversed operation V _DD - can be matched to the midpoint voltage of V _SS, the driven circuit RC becomes possible to receive a signal sent from the driving circuit DR mainly its own threshold voltage.

On the other hand, given a logical H to the control terminal CT, FETs Q ₁ is turned on, FETs Q ₂ is controlled to the OFF state. Since FETs Q ₁ is turned on, the potential of the common connection point J becomes always L. At the time of a leakage current test (static current test) of a semiconductor integrated circuit element, it is necessary to set the output of the transmission side (drive circuit DR) equal to the potential at the common connection point J.

  As described above, by controlling the input of the control terminal CT, the operation of the additional circuit configured using the NOR gate can be turned on / off.

Although the term “midpoint voltage” has been used to describe embodiments of the present invention, the “midpoint voltage” does not necessarily mean only the central voltage between the power supply voltages V _DD and V _SS. is not. As described with reference to FIG. 8, the midpoint voltage means any voltage between the power supply voltages V _DD and V _SS depending on the value of the beta ratio, and may vary from the center voltage. For example, the “midpoint voltage source” shown in FIG. 15 does not necessarily output only the central voltage between the power supply voltage V _DD and V _SS , but outputs a voltage corresponding to the threshold voltage of the driven circuit RC. Can be output.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

It is an enlarged plan view of a semiconductor chip for explaining the disadvantages of the prior art. It is a connection diagram for demonstrating the prior art. It is a wave form diagram for demonstrating the operation state of FIG. It is a wave form diagram for demonstrating the other state of the operation | movement of FIG. It is an enlarged plan view of a semiconductor chip for explaining one method for solving the problem that occurs in the prior art. It is a block diagram for demonstrating the outline | summary of this invention. FIG. 7 is a connection diagram specifically showing each part of the block diagram shown in FIG. 6. It is a graph for demonstrating operation | movement of the Example shown in FIG. It is an equivalent circuit diagram for demonstrating operation | movement of the Example shown in FIG. FIG. 10 is a waveform diagram showing waveforms at various parts of the equivalent circuit shown in FIG. 9. It is a block diagram for demonstrating the practical example of this invention. It is a block diagram for demonstrating the other example of the practical example of this invention. It is a block diagram which shows the further another example of the practical example of this invention. It is a connection diagram for demonstrating the modification of the additional circuit used for this invention. It is a connection diagram for demonstrating the further another modification of the additional circuit used for this invention. FIG. 16 is an equivalent circuit diagram of FIG. 15. It is a block diagram for demonstrating the practical example of the Example shown in FIG. It is a connection diagram for demonstrating the example which added the interruption | blocking means to the additional circuit used for this invention. It is a connection diagram for demonstrating the other example of the interruption | blocking means shown in FIG. It is a connection diagram for demonstrating the structure which added the interruption | blocking means to the additional circuit shown in FIG. 15 is a connection diagram for explaining a configuration in which a blocking means is added to the additional circuit and the midpoint voltage source when the additional circuit illustrated in FIG. 15 and the additional circuit illustrated in FIG. is there. It is a block diagram which shows another Example of the signal transmission circuit by this invention. An example of a specific configuration of an additional circuit using a NAND gate is shown. It is a block diagram which shows another Example of the signal transmission circuit by this invention. An example of a specific configuration of an additional circuit using a NOR gate is shown.

Explanation of symbols

DR drive circuit RC driven circuit LIN signal line CL line capacity CG input capacity EJV midpoint voltage source CUT cutoff means

Claims (21)

A drive circuit for sending a transmission signal, a signal line for propagating the transmission signal, and two power supply voltages V _SS and V _DD (V _DD > V _SS ) are driven to capture the transmission signal propagated through the signal line In a signal transmission circuit comprising a driven circuit,
A signal transmission circuit comprising: an additional circuit that outputs a predetermined voltage that is greater than the power supply voltage V _{SS and} smaller than the power supply voltage V _DD to the signal line. The driven circuit includes a digital circuit that outputs one of binary output voltages according to the input voltage;
2. The signal transmission circuit according to claim 1, wherein the additional circuit outputs a voltage that substantially matches a threshold voltage at which an output of the digital circuit is inverted from one of the binary output voltages to the other. The signal transmission circuit according to claim 2, wherein the additional circuit outputs a voltage at a substantially middle point between the power supply voltages V _SS and V _DD .   The signal transmission circuit according to claim 1, wherein the additional circuit has an output impedance lower than an output impedance of the drive circuit.   5. The signal transmission circuit according to claim 4, wherein the output impedance of the additional circuit is 1/2 to 1/4 of the output impedance of the drive circuit.   The signal transmission circuit according to claim 1, wherein the additional circuit includes a first inverter and a feedback circuit in which an input terminal and an output terminal of the first inverter are connected.   The signal transmission circuit according to claim 6, wherein the driven circuit includes a second inverter, and the first inverter has a beta ratio substantially equal to that of the second inverter.   The said additional circuit has P-type FET and N-type FET, and a forward bias voltage is applied to each of the gate of said P-type FET and said N-type FET. Signal transmission circuit. The additional circuit is greater than the power supply voltage V _SS, the signal transmission circuit according to claim 1, characterized in that it comprises a voltage source for outputting the power supply voltage V _DD is less than a predetermined voltage.   The signal transmission circuit according to claim 9, wherein the additional circuit further includes a low impedance buffer circuit that lowers an output impedance of the voltage output from the voltage source.   11. The signal transmission circuit according to claim 1, further comprising a blocking unit configured to block a current flowing between the signal line and the additional circuit.   The signal transmission circuit according to claim 1, wherein the additional circuit includes a NAND gate and a feedback circuit in which one input terminal and an output terminal of the NAND gate are connected.   The signal transmission circuit according to claim 12, wherein the NAND gate has a control terminal to which a control signal for cutting off a current flowing between the signal line and the additional circuit is input.   The signal transmission circuit according to claim 1, wherein the additional circuit includes a NOR gate and a feedback circuit in which one input terminal and an output terminal of the NOR gate are connected.   The signal transmission circuit according to claim 14, wherein the NOR gate has a control terminal to which a control signal for cutting off a current flowing between the signal line and the additional circuit is input.   The signal transmission circuit according to claim 1, wherein the additional circuit is connected to a terminal end of the signal line. A drive circuit for sending a transmission signal, a signal line for propagating the transmission signal, and two power supply voltages V _SS and V _DD (V _DD > V _SS ) are driven to capture the transmission signal propagated through the signal line In a CMOS semiconductor device formed with a signal transmission circuit having a driven circuit,
The signal transmission circuit, to the signal line, greater than said power supply voltage V _SS, CMOS semiconductor device characterized by having an additional circuit for outputting the power supply voltage V _DD is less than a predetermined voltage.   The CMOS semiconductor device according to claim 17, wherein the additional circuit has an output impedance lower than an output impedance of the driving circuit.   18. The CMOS semiconductor device according to claim 17, wherein a beta ratio of the additional circuit is substantially equal to a beta ratio of the driven circuit. A first semiconductor device having a drive circuit for sending out a transmission signal; a second semiconductor device having a driven circuit driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ) and taking in the transmission signal; In a circuit board comprising a signal line pattern for propagating the transmission signal from the driving circuit to the driven circuit,
With respect to the signal line, the greater than the power supply voltage V _SS, the circuit board characterized in that it comprises an additional circuit for outputting the power supply voltage V _DD is less than a predetermined voltage.   The circuit board according to claim 20, wherein the additional circuit has an output impedance lower than an output impedance of the drive circuit.

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