WO2019082245A1 - Signal transmission circuit and chip module - Google Patents

Signal transmission circuit and chip module

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Publication number
WO2019082245A1
WO2019082245A1 PCT/JP2017/038211 JP2017038211W WO2019082245A1 WO 2019082245 A1 WO2019082245 A1 WO 2019082245A1 JP 2017038211 W JP2017038211 W JP 2017038211W WO 2019082245 A1 WO2019082245 A1 WO 2019082245A1
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WO
WIPO (PCT)
Prior art keywords
signal transmission
negative feedback
transmission circuit
inverter amplifier
feedback inverter
Prior art date
Application number
PCT/JP2017/038211
Other languages
French (fr)
Japanese (ja)
Inventor
長谷川　雅俊
安藤　学
Original Assignee
ウルトラメモリ株式会社
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Publication date
Application filed by ウルトラメモリ株式会社 filed Critical ウルトラメモリ株式会社
Priority to PCT/JP2017/038211 priority Critical patent/WO2019082245A1/en
Priority to JP2019549693A priority patent/JP7002146B2/en
Publication of WO2019082245A1 publication Critical patent/WO2019082245A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines

Definitions

  • the present invention relates to a signal transmission circuit and a chip module.
  • bus lines for example, bus lines for distributing a clock, bus lines for forming a bus line, etc.
  • the bus lines formed inside the semiconductor chip tend to be thin and narrow, and the line length also becomes long.
  • the circuit drives the bus line by capacitive coupling and receives this by the negative feedback inverter amplifier.
  • the operating point of the negative feedback inverter amplifier can be optimized. Further, the reduction of the signal amplitude of the bus wiring and the setting of the potential can be optimized.
  • the input and output of the negative feedback inverter amplifier are DC balanced, the output data is lost.
  • the signal amplitude can be made small without using capacitive coupling, and the signal level can be set in the vicinity of the operating point of the inverter amplifier.
  • the bus line amplitude is determined by the drive side and the MOS size ratio of the input / output inverter giving a bias, there is a problem that the bus line has a large through current between the drive circuit and the input / output shorting inverter. I understand. It is preferable if a signal transmission circuit that can solve these problems can be provided.
  • An object of the present invention is to provide a signal transmission circuit and a chip module that improve the signal transmission characteristics of bus wiring and reduce the power required for transmission.
  • the present invention is a signal transmission circuit including a bus line, a drive circuit connected to one end of the bus line, and a negative feedback inverter amplifier connected to the other end of the bus line,
  • a signal transmission comprising: a coupling portion connecting an output end of a drive circuit to the bus wiring, the coupling portion including a capacitor disposed in series with the bus wiring and a resistor disposed in parallel with the capacitor It relates to a circuit.
  • the capacitance of the capacitor of the coupling portion is C1
  • the capacitance of the bus wiring is C2
  • the resistance value of the resistance of the coupling portion is R1
  • the resistance value of the negative feedback resistor of the negative feedback inverter amplifier is R2.
  • the present invention relates to a chip module including a plurality of the signal transmission circuits.
  • the present invention is the method of designing a signal transmission circuit according to the above (i), wherein the electrostatic capacitance of the capacitor and the resistance value of the resistor are used as the H / L of the input voltage to the negative feedback inverter amplifier. It is preferable to determine based on the level.
  • the present invention it is possible to provide a signal transmission circuit and a chip module that improve the signal transmission characteristics of bus wiring and reduce the power required for transmission.
  • FIG. 5 is a waveform diagram showing the relationship between an input, a reception first stage input, and an output of the circuit of FIG. 4;
  • FIG. 5 is another waveform diagram showing the relationship between the input of the circuit of FIG. 4, the reception first stage input, and the output.
  • 5 is a graph showing an example of current-frequency characteristics of the circuit of FIG. 4;
  • 5 is a graph showing another example of the current-frequency characteristic of the circuit of FIG. 4;
  • the signal transmission circuit 1 is disposed, for example, inside a chip module (not shown).
  • the signal transmission circuit 1 is used for signal transmission between semiconductor integrated circuit elements (not shown) inside a chip module.
  • the signal transmission circuit 1 includes a bus line 10, a drive circuit 20, and a negative feedback inverter amplifier 30.
  • the bus wiring 10 is a so-called metal wiring and has a resistance component.
  • an electrostatic capacitance is formed on the bus wiring 10 by a material (substrate, insulating film, etc.) that functions as a dielectric.
  • the bus lines 10 are arranged to connect the semiconductor integrated circuit elements.
  • the drive circuit 20 is connected to one end of the bus line 10.
  • the drive circuit 20 is a so-called inverting amplifier, and is disposed at a signal transmission source.
  • the drive circuit 20 amplifies the signal and outputs it to the bus wiring 10.
  • the negative feedback inverter amplifier 30 is connected to the other end of the bus line 10.
  • the negative feedback inverter amplifier 30 is composed of an inverting amplifier 32 for inverting and amplifying a signal input from the bus wiring 10, and a negative feedback resistor 31 for returning the inverted and amplified signal from the output side to the input side.
  • the signal transmission circuit 1 according to an embodiment includes a coupling unit 40, as shown in FIG.
  • Coupling portion 40 is disposed on bus line 10. Specifically, the coupling unit 40 connects the output end of the drive circuit 20 and the bus wiring 10.
  • the coupling unit 40 includes a capacitor 41 and a resistor 42.
  • the capacitor 41 is connected to the drive circuit 20 by capacitive coupling.
  • the resistor 42 is disposed in parallel to the capacitor 41.
  • the resistor 42 of the coupling unit 40 holds the output voltage of the negative feedback inverter amplifier 30 by connecting the drive circuit 20 and the negative feedback inverter amplifier 30 in a DC manner.
  • the signal transmission circuit 1 it is preferable that the H / L level of the input voltage of the negative feedback inverter amplifier 30 be constant even if the cycle time or the duty ratio of the input waveform changes. That is, it is preferable that the signal transmission circuit 1 be constant when the values of V1L and V1H in FIG. 3 are either when the cycle time is short or long, and when the duty ratio is high or low.
  • the signal transmission circuit 1 can be configured without changing the delay time of the negative feedback inverter amplifier 30 and reducing the signal timing design margin of the circuit.
  • the coupling capacitance of the capacitor 41 and the coupling resistance of the resistor 42 be determined so as to satisfy equation 8 described later. That is, the coupling capacitance (electrostatic capacitance) of the capacitor 41 and the coupling resistance (resistance value) of the resistor 42 are preferably determined based on the H / L level of the input voltage to the negative feedback inverter amplifier 30.
  • the value may be deviated from the value obtained from the equation 8 described later.
  • the resistance value and the capacitance value do not strictly satisfy the equation (8), and may deviate by about 20%. Although this deviation causes fluctuation of the input amplitude of the negative feedback inverter amplifier 30 due to the operation cycle time and consequently results in fluctuation of the delay time of the negative feedback inverter amplifier 30, this fluctuation amount is required from the design of the entire chip It is acceptable to deviate from the value determined by Equation 8 as long as the operating margin is satisfied.
  • the capacitance of the capacitor 41 of the coupling unit 40 is indicated as C1.
  • the resistance value of the resistor 42 of the coupling portion 40 is shown as R1.
  • the capacitance of the bus line 10 is shown as C2.
  • the resistance value of the negative feedback resistor 31 connected between the input and output of the inverting amplifier 32 is shown as R2.
  • the input capacitance of the negative feedback inverter amplifier 30 is shown as C3.
  • the node between the coupling portion 40 and the negative feedback inverter amplifier input is shown as N1.
  • the nodes on the input side are shown as IN.
  • the output of the negative feedback inverter amplifier 30 is shown as OUT.
  • the DC level (hereinafter simply referred to as L) level of the node N1 is indicated as V1L.
  • the DC high (hereinafter simply referred to as H) level of the node N1 is shown as V1H.
  • the DC level L of the node OUT is indicated as VOL.
  • the DC level H of the node OUT is indicated as VOH.
  • the voltage at any time of the node N1 is shown as VN1.
  • the voltage amplitude of the node N1 that changes due to capacitive coupling is indicated as ⁇ V1ac.
  • the power supply voltage is also shown as VDD.
  • the voltage of the node N1 gradually rises or falls from V1L + ⁇ V1ac to V1H.
  • the voltage at the node N1 can be prevented from changing from the value of V1L + ⁇ V1ac.
  • the input changes from VDD to 0 V, and the operation reverse to that at time 0 is performed. Also in this case, the voltage of the node N1 is maintained at the level after decreasing to V1L at time t2.
  • the voltage at the node N1 is determined by the resistance division of the voltages of IN and OUT. That is, the voltage of the node N1 is determined by the following equation 3.
  • the signal amplitude ⁇ V1dc at a very long cycle time of the node N1 is determined by the following equation 4.
  • the amplitude of the node N1 is determined only by the capacitances C1 to C3.
  • the resistors R1 to R2 are set to resistance values sufficiently larger than the impedance values of C1 to C2 in a very short cycle time).
  • the signal amplitude ⁇ V1ac of the node N1 at this time is determined by the following equation 5.
  • the coupling capacitance value C1 is obtained from Expression 6, and the ratio of the coupling resistance R1 to the negative feedback resistance R2 is determined from Expression 4. Therefore, if the value of R2 is determined, the value of R1 is determined. If the value of R2 is too small, the consumption current increases due to an increase in through current flowing through the resistor, so it is desirable that the value of R2 be somewhat large. Practically, the value of R2 is determined in consideration of the characteristics of the usable element, the dispersion, the exclusive area, etc. in addition to the through current.
  • the negative feedback inverter amplifier input node N1 is obtained after the voltage is determined by capacitive coupling at the time of signal change. Voltage can be kept constant.
  • the signal transmission circuit 1 satisfy the equation (8).
  • the signal transmission circuit 1 satisfies the equation 8 it means that the manufacturing variations of C1, R1 and R2 are satisfied to an extent that is acceptable. As long as the variation of the delay time of the negative feedback inverter amplifier 30 satisfies the operation margin required from the design of the entire chip, it can be said that the equation 8 is satisfied.
  • the charge / discharge current of the bus line 10 is proportional to the bus line capacitance and the amplitude ⁇ V1ac of the bus signal, and inversely proportional to the cycle time. Since the bus wiring capacitance and the minimum cycle time are fixed, the maximum allowable bus signal amplitude can be determined from the power consumption target value. From the viewpoint of the charge and discharge current of the bus interconnection 10, the smaller the ⁇ V1ac, the smaller the charge and discharge current can be. On the other hand, if .DELTA.V1ac becomes smaller than the minimum value of DC bus signal amplitude .DELTA.V1dc described below, the through current in the negative feedback inverter amplifier and the CMOS circuit in the next stage increases.
  • the minimum value of ⁇ V1ac be approximately the same as the minimum value of ⁇ V1dc.
  • the value to be taken of the DC-like bus signal amplitude ⁇ V1dc is determined.
  • the DC input / output characteristics of the negative feedback inverter amplifier 30, that is, the relationship between the DC input voltage and the output voltage and the through current are examined. Generally, it is necessary to prevent the through current from flowing (or to a value sufficiently smaller than the allowable current value) in the next stage to which the negative feedback inverter output is connected.
  • the purpose of the signal transmission circuit 1 is to reduce the current consumption due to the charge and discharge of the bus line capacitance by reducing the bus signal amplitude.
  • the H level of the output of the negative feedback inverter amplifier 30 is made to be equal to or higher than (or near) a voltage lower than the power supply voltage by the absolute value of the PMOS threshold voltage of the next stage.
  • the L level of the output of the negative feedback inverter amplifier 30 is made to be equal to or lower than (or near) a voltage higher than the ground level by the NMOS threshold voltage of the next stage.
  • the H level of the output of the negative feedback inverter amplifier 30 is 0.8V or more
  • the L level is 0.25V.
  • the input voltage of the negative feedback inverter amplifier 30 is set to be as follows. From the relationship between the input voltage and the output voltage, the range between the H level and the L level of the input of the negative feedback inverter amplifier 30 which satisfies the above can be obtained. From this, the minimum value of ⁇ V1dc is determined. On the other hand, the maximum value of ⁇ V1dc is determined by the charge / discharge current target value of bus interconnection 10 at the maximum cycle time.
  • the delay characteristics of the negative feedback inverter amplifier 30 are examined. That is, the MOSFET size dependency and input amplitude dependency of the delay time are examined. Within the range of the minimum value and the maximum value of the AC and DC bus signal amplitudes ( ⁇ V1ac, ⁇ V1dc) already obtained above, the delay time target value of the signal transmission circuit 1 given in the entire chip design is realized.
  • the MOSFET size and input amplitude (.DELTA.V1ac, .DELTA.V1dc) are determined. If ⁇ V1ac is determined, the coupling capacitance C1 is determined from Equation 6. On the other hand, when ⁇ V1dc is determined, the relationship between R1 and R2 is determined from Equation 4.
  • the values of R1 and R2 are preferably as large as possible in terms of current consumption, but in practice they are determined in consideration of the variation in resistance value, the area on the chip occupied by the resistance element, and the like. In many cases, the values of R1 and R2 are suitably selected in the range of 10 K ⁇ to several hundred kilo ohms. Further, it is desirable that the above ⁇ V1ac and ⁇ V1dc be the same value in many cases. This is because the delay time of the negative feedback inverter amplifier 30 does not change with respect to the fluctuation of the operation cycle time and becomes a constant value, so that the operation timing margin in the entire chip can be increased.
  • ⁇ V1ac and ⁇ V1dc may be set to different values as long as the design target is satisfied. This is because in an actual design, it is necessary to consider many factors such as the area occupied by a circuit, how to select a wiring layer, and the arrangement of wiring of other circuits.
  • Equation 11 is obtained.
  • the internal resistance of the drive element of the drive circuit 20 for driving the bus wiring 10 is sufficiently lower than the resistance value used here.
  • the rise / fall time of the output signal of the drive circuit 20 is sufficiently shorter than the time when the bus line 10 is charged and discharged by the resistor 42 and the negative feedback resistor 31.
  • the rise / fall time of the output of the negative feedback inverter amplifier 30 is also sufficiently shorter than the time when the bus line 10 is charged / discharged by the negative feedback resistor 31.
  • the input capacitance of the negative feedback inverter amplifier 30 is sufficiently smaller than the sum of the coupling capacitance connecting the drive circuit 20 and the bus wiring 10 and the bus capacitance.
  • the time constant of charging / discharging of the bus wiring 10 is about 30 ns.
  • the rise / fall time of the internal signal is several tens picoseconds or less depending on the technology, so the charge / discharge time constant of the bus wiring 10 is larger by two digits or more. Therefore, the above assumptions (2) and (3) are satisfied.
  • the low amplitude bus wiring 10 of the circuit constant mentioned as an example looks at a load capacitance of 83 fF when viewed from the drive circuit 20, in order to drive this at a rise / fall of 50 ps, for example,
  • the internal resistance should be 600 ohms, about two orders of magnitude less than the coupling resistance. Therefore, assumption (1) is also satisfied.
  • the values of R1 to R2 can have a width that is within the range in which the desired effect can be obtained.
  • Example 1 Example 1 of the signal transmission circuit 1 according to the present embodiment will be described.
  • R1 83 K.OMEGA.
  • R2 100 K.OMEGA.
  • And 400 .OMEGA. was inserted in the bus as the wiring resistance R4.
  • a signal is applied to the input terminal INPUT ("input" in FIG. 4), amplified by two stages of inverters to drive the signal transmission circuit.
  • the signal from the bus wiring is amplified by the negative feedback inverter amplifier 30, and then amplified by the inverter and output from the output terminal OUTPUT ("output" and "inverted output” in FIG. 4).
  • Figure 7 measured under conditions of supply voltage 1.3 V, chip temperature (junction temperature) 105 ° C (permissible maximum temperature), and MOSFET performance: Fast (highest performance of MOSFET) It is a current-frequency specific graph.
  • Figure 8 is a graph of current-frequency specification measured under the conditions of power supply voltage 1.2 V, chip temperature (junction temperature) 55 ° C (standard operating temperature), and MOSFET performance: Typ (center condition of manufacturing range) is there. That is, FIG. 7 shows the current-frequency characteristics when the operating current is the largest, and FIG. 8 shows the current-frequency specification when operating at standard power supply voltage and temperature. As shown in FIG. 7 and FIG.
  • the signal transmission circuit 1 As described above, the signal transmission circuit 1 according to the present embodiment has the following effects.
  • the signal transmission circuit 1 includes the coupling portion 40 disposed on the bus wiring 10 in the vicinity of the drive circuit 20.
  • the coupling portion 40 is parallel to the capacitor 41 and the capacitor 41 disposed in series on the bus wiring 10 And a resistor 42 disposed on the
  • the coupling section 40 makes it possible to reduce the element size of the circuit to be driven because the load capacity looks small.
  • the area of the module in which the signal transmission circuit 1 is disposed can be reduced, and the power consumption of the signal transmission circuit 1 can be reduced.
  • the output data of the negative feedback inverter amplifier 30 does not disappear, there is no need to use a latch circuit, and the signal transmission circuit 1 can be configured inexpensively.
  • the capacitance of the capacitor 41 and the resistance value of the resistor 42 are determined based on the H / L level of the input voltage to the negative feedback inverter amplifier 30. As a result, it is possible to obtain the stable signal transmission circuit 1 of the operation without significantly changing the delay time of the negative feedback inverter amplifier 30.

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Abstract

Provided are: a signal transmission circuit and a chip module that improve signal transmission characteristics of bus wiring and reduce the power required for transmission. A signal transmission circuit 1 comprises a bus line 10, a drive circuit 20 connected to one end of the bus line 10, and a negative feedback inverter amplifier 30 connected to the other end of the bus line 10. The signal transmission circuit 1 further comprises a coupling unit 40 for connecting an output terminal of the drive circuit 20 and the bus line 10. The coupling unit 40 comprises a capacitor 41 disposed in series with the bus line 10, and a resistor 42 disposed in parallel with the capacitor 41.

Description

信号伝送回路及びチップモジュールSignal transmission circuit and chip module
　本発明は、信号伝送回路及びチップモジュールに関する。 The present invention relates to a signal transmission circuit and a chip module.
　従来より、半導体集積回路素子を内包する半導体チップが知られている。近年では、半導体チップにおいて、半導体集積回路素子の集積化が進んでいる。半導体集積回路素子が集積化されることによって、半導体チップ内部に形成されるバス配線（例えば、クロックを分配するバス配線や、バスラインを構成するバス配線等）の本数が多くなる。そのため、半導体チップ内部に形成されるバス配線は、細くかつ間隔が狭くなり、また、配線長も長くなる傾向にある。 Conventionally, semiconductor chips containing semiconductor integrated circuit elements are known. In recent years, in semiconductor chips, integration of semiconductor integrated circuit elements has progressed. As semiconductor integrated circuit elements are integrated, the number of bus lines (for example, bus lines for distributing a clock, bus lines for forming a bus line, etc.) formed inside a semiconductor chip increases. Therefore, the bus lines formed inside the semiconductor chip tend to be thin and narrow, and the line length also becomes long.
　バス配線には静電容量（配線容量）が存在することが知られており、この静電容量は、配線の間隔が狭くなるほど大きくなり、また、配線長が長くなるほど大きくなる。配線容量が大きくなると、立ち上がり応答の遅れが顕著になる。この遅れは、信号伝送を阻害する大きな要因となる。 It is known that a capacitance (wiring capacitance) is present in the bus wiring, and the capacitance becomes larger as the wiring interval becomes narrower, and becomes larger as the wiring length becomes longer. As the wiring capacitance increases, the delay in the rise response becomes noticeable. This delay is a major factor that impedes signal transmission.
　そこで、静電容量の容量値が大きいバス配線の信号伝送特性を改善し、伝送に要する電力を削減するために、容量結合でバス配線を駆動し、これを負帰還インバータアンプで受ける回路が考えられる。 Therefore, in order to improve the signal transmission characteristics of the bus line having a large capacitance value and reduce the power required for transmission, it is considered that the circuit drives the bus line by capacitive coupling and receives this by the negative feedback inverter amplifier. Be
　これに関連する回路として、出力信号の動作点を負荷に合せて設定し、信号振幅を減少させる容量結合を用いた回路が提案されている（例えば、特許文献１参照）。また、動作時と待機時のそれぞれの状態に合わせて、入力増幅回路に最適な電圧を与える回路が提案されている（例えば、特許文献２参照）。また、駆動回路から出力される駆動信号を被駆動回路の電源電圧のしきい値電圧を中心に小振幅で励振させる回路が提案されている（例えば、特許文献３参照）。 As a circuit relating to this, there has been proposed a circuit using capacitive coupling in which the operating point of the output signal is set according to the load and the signal amplitude is reduced (see, for example, Patent Document 1). Further, there has been proposed a circuit which provides an input amplifier circuit with an optimum voltage in accordance with each of operating and standby states (see, for example, Patent Document 2). Further, there has been proposed a circuit which excites the drive signal output from the drive circuit with a small amplitude around the threshold voltage of the power supply voltage of the driven circuit (see, for example, Patent Document 3).
特開２００６－２４３１７６号公報JP, 2006-243176, A 特開２００７－３６４８６号公報JP 2007-36486 A 特開２００８－５４３５２号公報JP 2008-54352 A
　特許文献１及び２に開示された回路を組み合わせた回路では、負帰還インバータアンプの動作点を最適化することができる。また、バス配線の信号振幅の小振幅化と電位の設定とを最適化することができる。一方で、負帰還インバータアンプの入出力がＤＣ的には均衡してしまうので、出力データが消失してしまう。出力データの消失を防止するために、負帰還インバータアンプの後段に同期又は非同期のラッチ回路を設けなければならない。同期型のラッチ回路を用いる場合、クロック制御が必要になり、非同期型のラッチ回路では、設計が難しいという問題があることが判った。 In the circuit combining the circuits disclosed in Patent Documents 1 and 2, the operating point of the negative feedback inverter amplifier can be optimized. Further, the reduction of the signal amplitude of the bus wiring and the setting of the potential can be optimized. On the other hand, since the input and output of the negative feedback inverter amplifier are DC balanced, the output data is lost. In order to prevent the loss of output data, it is necessary to provide a synchronous or asynchronous latch circuit after the negative feedback inverter amplifier. It has been found that, in the case of using a synchronous latch circuit, clock control is required, and in the case of an asynchronous latch circuit, there is a problem that design is difficult.
　特許文献３に開示された回路では、容量結合を用いずに信号振幅を小振幅にすることができるとともに、インバータアンプの動作点付近に信号レベルを設定することができる。しかしながら、バス配線振幅は、駆動側とバイアスを与える入出力インバータのＭＯＳサイズ比とで決まるので、バス配線には駆動回路と入出力短絡インバータとの間で大きな貫通電流を生じるという問題があることが判った。これらの問題を解決できる信号伝送回路を提供することができれば好ましい。 In the circuit disclosed in Patent Document 3, the signal amplitude can be made small without using capacitive coupling, and the signal level can be set in the vicinity of the operating point of the inverter amplifier. However, since the bus line amplitude is determined by the drive side and the MOS size ratio of the input / output inverter giving a bias, there is a problem that the bus line has a large through current between the drive circuit and the input / output shorting inverter. I understand. It is preferable if a signal transmission circuit that can solve these problems can be provided.
　本発明は、バス配線の信号伝送特性を改善し、伝送に要する電力を削減する信号伝送回路及びチップモジュールを提供することを目的とする。 An object of the present invention is to provide a signal transmission circuit and a chip module that improve the signal transmission characteristics of bus wiring and reduce the power required for transmission.
　（ｉ）本発明は、バス配線と、前記バス配線の一端に接続される駆動回路と、前記バス配線の他端に接続される負帰還インバータアンプと、を備える信号伝送回路であって、前記駆動回路の出力端と前記バス配線とを接続する結合部を備え、前記結合部は、前記バス配線に直列に配置されるコンデンサと、前記コンデンサに並列に配置される抵抗と、を備える信号伝送回路に関する。 (I) The present invention is a signal transmission circuit including a bus line, a drive circuit connected to one end of the bus line, and a negative feedback inverter amplifier connected to the other end of the bus line, A signal transmission comprising: a coupling portion connecting an output end of a drive circuit to the bus wiring, the coupling portion including a capacitor disposed in series with the bus wiring and a resistor disposed in parallel with the capacitor It relates to a circuit.
　（ｉｉ）また、前記結合部のコンデンサの容量をＣ１、前記バス配線の静電容量をＣ２、前記結合部の抵抗の抵抗値をＲ１、負帰還インバータアンプの負帰還抵抗の抵抗値をＲ２、前記負帰還インバータアンプの出力のＤＣ的ローレベルをＶＯＬ、前記負帰還インバータアンプの出力のＤＣ的ハイレベルをＶＯＨ、電源電圧をＶＤＤとして、以下の数１
Figure JPOXMLDOC01-appb-M000002
 を満たすことが好ましい。 (Ii) Further, the capacitance of the capacitor of the coupling portion is C1, the capacitance of the bus wiring is C2, the resistance value of the resistance of the coupling portion is R1, and the resistance value of the negative feedback resistor of the negative feedback inverter amplifier is R2. Assuming that the DC low level of the output of the negative feedback inverter amplifier is VOL, the DC high level of the output of the negative feedback inverter amplifier is VOH, and the power supply voltage is VDD,
Figure JPOXMLDOC01-appb-M000002
 It is preferable to satisfy
　（ｉｉｉ）また、本発明は、上記信号伝送回路を複数備えるチップモジュールに関する。 (Iii) Further, the present invention relates to a chip module including a plurality of the signal transmission circuits.
　（ｉｖ）また、本発明は、上記（ｉ）の信号伝送回路の設計方法であって、前記コンデンサの静電容量及び前記抵抗の抵抗値を前記負帰還インバータアンプへの入力電圧のＨ／Ｌレベルに基づいて決定することが好ましい。 (Iv) Further, the present invention is the method of designing a signal transmission circuit according to the above (i), wherein the electrostatic capacitance of the capacitor and the resistance value of the resistor are used as the H / L of the input voltage to the negative feedback inverter amplifier. It is preferable to determine based on the level.
　本発明によれば、バス配線の信号伝送特性を改善し、伝送に要する電力を削減する信号伝送回路及びチップモジュールを提供することができる。 According to the present invention, it is possible to provide a signal transmission circuit and a chip module that improve the signal transmission characteristics of bus wiring and reduce the power required for transmission.
本発明の一実施形態に係る信号伝送回路を示す概略構成図である。It is a schematic block diagram which shows the signal-transmission circuit based on one Embodiment of this invention. 一実施形態の信号伝送回路の回路図である。It is a circuit diagram of a signal transmission circuit of one embodiment. 一実施形態の信号伝送回路の波形特性を示す模式図である。It is a schematic diagram which shows the waveform characteristic of the signal-transmission circuit of one Embodiment. 一実施形態の信号伝送回路の実施例１の回路図である。It is a circuit diagram of Example 1 of a signal transmission circuit of one embodiment. 図４の回路の入力、受信初段入力、及び出力の関係を示す一波形図である。FIG. 5 is a waveform diagram showing the relationship between an input, a reception first stage input, and an output of the circuit of FIG. 4; 図４の回路の入力、受信初段入力、及び出力の関係を示す他の波形図である。FIG. 5 is another waveform diagram showing the relationship between the input of the circuit of FIG. 4, the reception first stage input, and the output. 図４の回路の電流－周波数特性の一例を示すグラフである。5 is a graph showing an example of current-frequency characteristics of the circuit of FIG. 4; 図４の回路の電流－周波数特性の他の例を示すグラフである。5 is a graph showing another example of the current-frequency characteristic of the circuit of FIG. 4;
　以下、本発明の一実施形態に係る信号伝送回路１及びチップモジュールの各実施形態について、図面を参照して説明する。
　まず、一実施形態に係る信号伝送回路１及びチップモジュールの概要について、図１を用いて説明する。 Hereinafter, embodiments of a signal transmission circuit 1 and a chip module according to an embodiment of the present invention will be described with reference to the drawings.
First, an overview of a signal transmission circuit 1 and a chip module according to an embodiment will be described with reference to FIG.
　信号伝送回路１は、例えば、チップモジュール（図示せず）の内部に配置される。信号伝送回路１は、チップモジュールの内部において、半導体集積回路素子（図示せず）の間の信号伝送に用いられる。この信号伝送回路１は、図１に示すように、バス配線１０と、駆動回路２０と、負帰還インバータアンプ３０と、を備える。 The signal transmission circuit 1 is disposed, for example, inside a chip module (not shown). The signal transmission circuit 1 is used for signal transmission between semiconductor integrated circuit elements (not shown) inside a chip module. As shown in FIG. 1, the signal transmission circuit 1 includes a bus line 10, a drive circuit 20, and a negative feedback inverter amplifier 30.
　バス配線１０は、いわゆる金属配線であり、抵抗成分を有する。また、誘電体として機能する素材（基板や絶縁膜等）によって、バス配線１０には、静電容量が形成される。バス配線１０は、半導体集積回路素子の間を接続するために配置される。 The bus wiring 10 is a so-called metal wiring and has a resistance component. In addition, an electrostatic capacitance is formed on the bus wiring 10 by a material (substrate, insulating film, etc.) that functions as a dielectric. The bus lines 10 are arranged to connect the semiconductor integrated circuit elements.
　駆動回路２０は、バス配線１０の一端に接続される。駆動回路２０は、いわゆる反転増幅器であり、信号の送出元に配置される。駆動回路２０は、信号を増幅してバス配線１０に出力する。 The drive circuit 20 is connected to one end of the bus line 10. The drive circuit 20 is a so-called inverting amplifier, and is disposed at a signal transmission source. The drive circuit 20 amplifies the signal and outputs it to the bus wiring 10.
　負帰還インバータアンプ３０は、バス配線１０の他端に接続される。負帰還インバータアンプ３０は、バス配線１０から入力された信号を反転増幅する反転増幅器３２と、反転増幅された信号を、出力側から入力側に戻す負帰還抵抗３１とで構成される。 The negative feedback inverter amplifier 30 is connected to the other end of the bus line 10. The negative feedback inverter amplifier 30 is composed of an inverting amplifier 32 for inverting and amplifying a signal input from the bus wiring 10, and a negative feedback resistor 31 for returning the inverted and amplified signal from the output side to the input side.
　次に、一実施形態に係る信号伝送回路１について、図１～図７を参照して説明する。
　本実施形態に係る信号伝送回路１は、図１に示すように、結合部４０を備える。 Next, a signal transmission circuit 1 according to an embodiment will be described with reference to FIGS. 1 to 7.
The signal transmission circuit 1 according to the present embodiment includes a coupling unit 40, as shown in FIG.
　結合部４０は、バス配線１０に配置される。具体的には、結合部４０は、駆動回路２０の出力端とバス配線１０とを接続する。結合部４０は、コンデンサ４１と、抵抗４２と、を備える。 Coupling portion 40 is disposed on bus line 10. Specifically, the coupling unit 40 connects the output end of the drive circuit 20 and the bus wiring 10. The coupling unit 40 includes a capacitor 41 and a resistor 42.
　コンデンサ４１は、容量結合により駆動回路２０に接続される。 The capacitor 41 is connected to the drive circuit 20 by capacitive coupling.
　抵抗４２は、コンデンサ４１に並列に配置される。結合部４０の抵抗４２は、駆動回路２０及び負帰還インバータアンプ３０をＤＣ的に接続することで、負帰還インバータアンプ３０の出力電圧を保持する。 The resistor 42 is disposed in parallel to the capacitor 41. The resistor 42 of the coupling unit 40 holds the output voltage of the negative feedback inverter amplifier 30 by connecting the drive circuit 20 and the negative feedback inverter amplifier 30 in a DC manner.
　次に、結合部４０におけるコンデンサ４１の結合容量と、抵抗４２の結合抵抗との決定方法について図２及び図３を用いて説明する。
　まず、信号伝送回路１が満たさなければならない条件を説明する。
　多くの場合、信号伝送回路１は、入力波形のサイクル時間やデューティ比が変わっても、負帰還インバータアンプ３０の入力電圧のＨ／Ｌレベルが一定であることが好ましい。即ち、信号伝送回路１は、図３のＶ１Ｌ，Ｖ１Ｈの値が、サイクル時間が短いときも長いときも、デューティ比が大きいときも小さいときも一定であることが好ましい。これにより、負帰還インバータアンプ３０の遅延時間を変動させず、回路の信号タイミング設計余裕を減少させないで信号伝送回路１を構成することができる。
　これを実現するためには、後述する数８を満足するようにコンデンサ４１の結合容量と、抵抗４２の結合抵抗とが決定されるのが好ましい。即ち、コンデンサ４１の結合容量（静電容量）及び抵抗４２の結合抵抗（抵抗値）は、負帰還インバータアンプ３０への入力電圧のＨ／Ｌレベルに基づいて決定されるのが好ましい。ただし、信号伝送回路１を含む回路システム（チップモジュール）としての動作タイミングに余裕があれば、後述する数８から求められる値から外れてもよい。現実的には、製造上のばらつきがあるため、抵抗値、容量値は数８を厳密に満たす値にはならず、２０％程度外れることがあり得る。このずれは、負帰還インバータアンプ３０の入力振幅の動作サイクル時間による変動を生じ、結果的に負帰還インバータアンプ３０の遅延時間の変動を生じるが、この変動量がチップ全体の設計から要求される動作余裕を満たしている限り、数８で決まる値からずれることは許容される。 Next, a method of determining the coupling capacitance of the capacitor 41 and the coupling resistance of the resistor 42 in the coupling portion 40 will be described with reference to FIGS. 2 and 3.
First, conditions that the signal transmission circuit 1 must satisfy will be described.
In many cases, in the signal transmission circuit 1, it is preferable that the H / L level of the input voltage of the negative feedback inverter amplifier 30 be constant even if the cycle time or the duty ratio of the input waveform changes. That is, it is preferable that the signal transmission circuit 1 be constant when the values of V1L and V1H in FIG. 3 are either when the cycle time is short or long, and when the duty ratio is high or low. Thus, the signal transmission circuit 1 can be configured without changing the delay time of the negative feedback inverter amplifier 30 and reducing the signal timing design margin of the circuit.
In order to realize this, it is preferable that the coupling capacitance of the capacitor 41 and the coupling resistance of the resistor 42 be determined so as to satisfy equation 8 described later. That is, the coupling capacitance (electrostatic capacitance) of the capacitor 41 and the coupling resistance (resistance value) of the resistor 42 are preferably determined based on the H / L level of the input voltage to the negative feedback inverter amplifier 30. However, if there is a margin in the operation timing as a circuit system (chip module) including the signal transmission circuit 1, the value may be deviated from the value obtained from the equation 8 described later. In practice, due to manufacturing variations, the resistance value and the capacitance value do not strictly satisfy the equation (8), and may deviate by about 20%. Although this deviation causes fluctuation of the input amplitude of the negative feedback inverter amplifier 30 due to the operation cycle time and consequently results in fluctuation of the delay time of the negative feedback inverter amplifier 30, this fluctuation amount is required from the design of the entire chip It is acceptable to deviate from the value determined by Equation 8 as long as the operating margin is satisfied.
　なお、以下の説明では、図２に示すように、結合部４０のコンデンサ４１の静電容量は、Ｃ１として示される。結合部４０の抵抗４２の抵抗値は、Ｒ１として示される。バス配線１０の静電容量は、Ｃ２として示される。反転増幅器３２の入出力間に接続される負帰還抵抗３１の抵抗値は、Ｒ２として示される。負帰還インバータアンプ３０の入力容量は、Ｃ３として示される。また、結合部４０と負帰還インバータアンプ入力との間の節点はＮ１として示される。入力側の節点はＩＮとして示される。負帰還インバータアンプ３０の出力はＯＵＴとして示される。 In the following description, as shown in FIG. 2, the capacitance of the capacitor 41 of the coupling unit 40 is indicated as C1. The resistance value of the resistor 42 of the coupling portion 40 is shown as R1. The capacitance of the bus line 10 is shown as C2. The resistance value of the negative feedback resistor 31 connected between the input and output of the inverting amplifier 32 is shown as R2. The input capacitance of the negative feedback inverter amplifier 30 is shown as C3. Also, the node between the coupling portion 40 and the negative feedback inverter amplifier input is shown as N1. The nodes on the input side are shown as IN. The output of the negative feedback inverter amplifier 30 is shown as OUT.
　また、図３において、節点Ｎ１のＤＣ的ロー（以下、単にＬとする）レベルは、Ｖ１Ｌとして示される。節点Ｎ１のＤＣ的ハイ（以下、単にＨとする）レベルは、Ｖ１Ｈとして示される。また、節点ＯＵＴのＤＣ的Ｌレベルは、ＶＯＬとして示される。節点ＯＵＴのＤＣ的Ｈレベルは、ＶＯＨとして示される。また、節点Ｎ１の任意の時刻での電圧は、ＶＮ１として示される。容量結合で変化する節点Ｎ１の電圧振幅は、ΔＶ１ａｃとして示される。また電源電圧は、ＶＤＤとして示される。 Further, in FIG. 3, the DC level (hereinafter simply referred to as L) level of the node N1 is indicated as V1L. The DC high (hereinafter simply referred to as H) level of the node N1 is shown as V1H. Also, the DC level L of the node OUT is indicated as VOL. The DC level H of the node OUT is indicated as VOH. Also, the voltage at any time of the node N1 is shown as VN1. The voltage amplitude of the node N1 that changes due to capacitive coupling is indicated as ΔV1ac. The power supply voltage is also shown as VDD.
　入力（節点ＩＮ）に矩形波の入力信号が加えられる時刻０以前は入力が接地電圧０Ｖで、出力がＨ（ＶＯＨ）の定常状態になっているとする。このとき、節点Ｎ１の電圧がＶ１Ｌとなっている。時刻０で入力が０ＶからＶＤＤに上昇すると、節点Ｎ１の電圧は、容量分割比で決まる電圧ΔＶ１ａｃだけ瞬時に上昇する。これにより、節点ＯＵＴの電圧は、ＶＯＬに落ちる。節点Ｎ１には、抵抗Ｒ１を介して電荷が節点ＩＮから供給される一方、抵抗Ｒ２を介して出力ＯＵＴに電荷が抜けていく。これにより、節点Ｎ１の電圧は、Ｖ１Ｌ＋ΔＶ１ａｃからＶ１Ｈまで徐々に上昇又は下降する。各抵抗、容量、及び電圧値を適切に設定することで、節点Ｎ１の電圧はＶ１Ｌ＋ΔＶ１ａｃの値から変化しないようにすることができる。 Before time 0 when the input signal of the rectangular wave is applied to the input (node IN), it is assumed that the input is at the ground voltage 0 V and the output is in the steady state of H (VOH). At this time, the voltage of the node N1 is V1L. When the input rises from 0 V to VDD at time 0, the voltage at the node N1 instantaneously rises by a voltage ΔV1ac determined by the capacitance division ratio. As a result, the voltage at the node OUT falls to VOL. The charge is supplied to the node N1 from the node IN via the resistor R1, while the charge is discharged to the output OUT via the resistor R2. As a result, the voltage of the node N1 gradually rises or falls from V1L + ΔV1ac to V1H. By appropriately setting each resistance, capacitance, and voltage value, the voltage at the node N1 can be prevented from changing from the value of V1L + ΔV1ac.
　時刻ｔ２では、入力がＶＤＤから０Ｖに変化し、時刻０における場合と逆の動作をする。この場合も、節点Ｎ１の電圧は、時刻ｔ２でＶ１Ｌに低下した後、そのレベルが維持される。 At time t2, the input changes from VDD to 0 V, and the operation reverse to that at time 0 is performed. Also in this case, the voltage of the node N1 is maintained at the level after decreasing to V1L at time t2.
　次に、このような波形を実現するための各抵抗、容量、電圧値の関係を説明する。
　負帰還インバータアンプ３０の入力波形がサイクルタイムによらず一定となるようにするための条件として、まず、長いサイクルでの動作について考える。長いサイクルでは、抵抗だけで、各節点の電圧が決まり、静電容量は無関係となる。
　入力ＩＮがＶＤＤの場合、ＯＵＴはＶＯＬであり、節点Ｎ１の電圧は、ＩＮとＯＵＴの電圧の抵抗分割で決まる。即ち、節点Ｎ１の電圧は、以下の数２で決まる。
Figure JPOXMLDOC01-appb-M000003
 Next, the relationship between resistances, capacitances and voltage values for realizing such a waveform will be described.
As a condition for making the input waveform of the negative feedback inverter amplifier 30 constant regardless of the cycle time, first, an operation in a long cycle will be considered. In a long cycle, the resistance alone determines the voltage at each node and the capacitance is irrelevant.
When the input IN is VDD, OUT is VOL, and the voltage at the node N1 is determined by the resistance division of the voltages of IN and OUT. That is, the voltage of the node N1 is determined by the following equation 2.
Figure JPOXMLDOC01-appb-M000003
　同様に、入力ＩＮが０Ｖの場合、ＯＵＴはＶＯＨであり、節点Ｎ１の電圧は、ＩＮとＯＵＴの電圧の抵抗分割で決まる。即ち、節点Ｎ１の電圧は、以下の数３で決まる。
Figure JPOXMLDOC01-appb-M000004
 Similarly, when the input IN is 0 V, OUT is VOH, and the voltage at the node N1 is determined by the resistance division of the voltages of IN and OUT. That is, the voltage of the node N1 is determined by the following equation 3.
Figure JPOXMLDOC01-appb-M000004
　従って、節点Ｎ１の非常に長いサイクル時間での信号振幅ΔＶ１ｄｃは、以下の数４で決まる。
Figure JPOXMLDOC01-appb-M000005
 Therefore, the signal amplitude ΔV1dc at a very long cycle time of the node N1 is determined by the following equation 4.
Figure JPOXMLDOC01-appb-M000005
　一方、サイクル時間が非常に短いときには、節点Ｎ１の振幅は容量Ｃ１～Ｃ３だけで決まる。（抵抗Ｒ１～Ｒ２は非常に短いサイクル時間におけるＣ１～Ｃ２のインピーダンス値より十分に大きい抵抗値に設定される）。この時の節点Ｎ１の信号振幅ΔＶ１ａｃは、以下の数５で決まる。
Figure JPOXMLDOC01-appb-M000006
 On the other hand, when the cycle time is very short, the amplitude of the node N1 is determined only by the capacitances C1 to C3. (The resistors R1 to R2 are set to resistance values sufficiently larger than the impedance values of C1 to C2 in a very short cycle time). The signal amplitude ΔV1ac of the node N1 at this time is determined by the following equation 5.
Figure JPOXMLDOC01-appb-M000006
　ここで、Ｃ３の容量は通常、Ｃ１＋Ｃ２より二桁程度以上小さいので省略して、以下の数６が得られる。
Figure JPOXMLDOC01-appb-M000007
 Here, since the capacity of C3 is usually smaller by about two digits or more than C1 + C2, the following formula 6 can be obtained.
Figure JPOXMLDOC01-appb-M000007
　サイクル時間によらずＮ１の振幅が一定になるようにするためには、上記のΔＶ１ｄｃがΔＶ１ａｃと等しくなければならないので、以下の数７のようになる。
Figure JPOXMLDOC01-appb-M000008
 In order to make the amplitude of N1 constant regardless of the cycle time, the above ΔV1dc must be equal to ΔV1ac, and the following equation 7 is obtained.
Figure JPOXMLDOC01-appb-M000008
　変形すると、以下の数８が得られる。
Figure JPOXMLDOC01-appb-M000009
 When deformed, the following equation 8 is obtained.
Figure JPOXMLDOC01-appb-M000009
　即ち、入出力振幅が決まると、数６から結合容量値Ｃ１が求められ、また数４から、結合抵抗Ｒ１と負帰還抵抗Ｒ２の比が決まる。ゆえに、Ｒ２の値を決めれば、Ｒ１の値が決まる。Ｒ２の値が小さすぎると抵抗を通して流れる貫通電流増加によって消費電流が増加するので、Ｒ２の値は、ある程度大きいことが望ましい。現実的には、Ｒ２の値は、貫通電流のほか、使える素子の特性、ばらつき、専有面積等を考慮して決められる。 That is, when the input / output amplitude is determined, the coupling capacitance value C1 is obtained from Expression 6, and the ratio of the coupling resistance R1 to the negative feedback resistance R2 is determined from Expression 4. Therefore, if the value of R2 is determined, the value of R1 is determined. If the value of R2 is too small, the consumption current increases due to an increase in through current flowing through the resistor, so it is desirable that the value of R2 be somewhat large. Practically, the value of R2 is determined in consideration of the characteristics of the usable element, the dispersion, the exclusive area, etc. in addition to the through current.
　以上示したように、ΔＶ１ａｃとΔＶ１ｄｃとが同じ値になるようにＣ１、Ｒ１、Ｒ２の値を決めれば、信号変化時に容量結合によって決まった電圧になった後は、負帰還インバータアンプ入力節点Ｎ１の電圧を一定に保つことができる。なお、上記では、入力がＬからＨに変化する場合について説明したが、ＨからＬに変化する場合も同様である。信号伝送回路１は数８を満たすのが好適である。なお、信号伝送回路１が数８を満たすとは、Ｃ１、Ｒ１，Ｒ２の製造上のばらつきを許容する程度に満たすことを意味する。負帰還インバータアンプ３０の遅延時間の変動がチップ全体の設計から要求される動作余裕を満たしている限り、数８を満たしているといえる。 As described above, if the values of C1, R1 and R2 are determined so that ΔV1ac and ΔV1dc have the same value, the negative feedback inverter amplifier input node N1 is obtained after the voltage is determined by capacitive coupling at the time of signal change. Voltage can be kept constant. Although the case where the input changes from L to H has been described above, the same applies to the case where the input changes from H to L. It is preferable that the signal transmission circuit 1 satisfy the equation (8). When the signal transmission circuit 1 satisfies the equation 8, it means that the manufacturing variations of C1, R1 and R2 are satisfied to an extent that is acceptable. As long as the variation of the delay time of the negative feedback inverter amplifier 30 satisfies the operation margin required from the design of the entire chip, it can be said that the equation 8 is satisfied.
　具体的な設計手法を以下に示す。
　実際の設計では、チップ全体の設計から、電源電圧ＶＤＤ、バス配線容量Ｃ２、及び、信号伝送回路１が満たすべき遅延時間の最小値、最大値、サイクル時間の最大値、最小値、消費電力の目標値が与えられ、それらを満たすようにＣ１、Ｒ１、Ｒ２が決められる。
　まず、バス配線１０の振幅（ΔＶ１ａｃ及びΔＶ１ｄｃ）の許容値（最小値、最大値）が調べられる。
　ΔＶ１ａｃは、容量成分、Ｃ１，Ｃ２で決まる信号振幅であり、この値が大きいほどバス配線１０の充放電電流は大きくなる。具体的には、バス配線１０の充放電電流は、バス配線容量と、バス信号の振幅ΔＶ１ａｃに比例し、サイクル時間に逆比例する。バス配線容量と最小サイクル時間は決まっているので、消費電力の目標値から、許容される最大のバス信号振幅を求めることができる。バス配線１０の充放電電流の観点では、ΔＶ１ａｃは小さいほど充放電電流を小さくできる。一方で、ΔＶ１ａｃは、以下に述べるＤＣ的なバス信号振幅ΔＶ１ｄｃの最小値より小さくなると負帰還インバータアンプ及び、その次段のＣＭＯＳ回路での貫通電流が増加する。このため、ΔＶ１ａｃの最小値は、ΔＶ１ｄｃの最小値とほぼ同じ値であることが望ましい。
　次に、ＤＣ的バス信号振幅ΔＶ１ｄｃのとるべき値が求められる。まず、負帰還インバータアンプ３０のＤＣ入出力特性、つまり、直流的な入力電圧と出力電圧及び貫通電流との関係が調べられる。通常、負帰還インバータ出力が接続される次段で貫通電流が流れない（又は許容電流値より十分に小さい値になる）ようにする必要がある。信号伝送回路１では、バス信号振幅を小さくして、バス配線容量の充放電による消費電流を低減することが目的である。バス配線容量の充放電電流に対して、上記貫通電流を十分に小さい値にすることで、信号振幅を小さくする効果を得ることができる。従って、負帰還インバータアンプ３０の出力のＨレベルは、電源電圧から次段のＰＭＯＳスレッショルド電圧の絶対値だけ低い電圧以上（又はその近傍）になるようにされる。また、負帰還インバータアンプ３０の出力のＬレベルは、接地レベルから次段のＮＭＯＳスレッショルド電圧だけ高い電圧以下（又はその近傍）になるようにされる。例えば、電源電圧が１Ｖ、ＰＭＯＳスレッショルド電圧が－０．２Ｖ、ＮＭＯＳスレッショルド電圧が０．２５Ｖであれば、負帰還インバータアンプ３０の出力のＨレベルは０．８Ｖ以上に、Ｌベルは０．２５Ｖ以下になるように負帰還インバータアンプ３０の入力電圧が設定される。入力電圧と出力電圧との関係から、これを満たす負帰還インバータアンプ３０の入力のＨレベルとＬレベルの範囲が求められる。これからΔＶ１ｄｃの最小値が決まる。一方、ΔＶ１ｄｃの最大値は、サイクル時間最大値でのバス配線１０の充放電電流目標値により決まる。
　次に、負帰還インバータアンプ３０の遅延特性が調べられる。即ち、遅延時間のＭＯＳＦＥＴサイズ依存性、入力振幅依存性が調べられる。
　すでに上で求めたＡＣ的、及びＤＣ的バス信号振幅（ΔＶ１ａｃ、ΔＶ１ｄｃ）の最小値、最大値の範囲の中で、チップ全体設計で与えられた信号伝送回路１の遅延時間目標値を実現するための、ＭＯＳＦＥＴサイズと入力振幅（ΔＶ１ａｃ、ΔＶ１ｄｃ）が決められる。
　ΔＶ１ａｃが決まると、数６から結合容量Ｃ１が決まる。
　一方、ΔＶ１ｄｃが決まると数４からＲ１とＲ２の関係が決まる。Ｒ１、Ｒ２の値は、高いほど抵抗を通して流れる電流が減少する。したがって、Ｒ１、Ｒ２の値は、消費電流の観点では大きいほど良いが、実際は、抵抗値ばらつきや抵抗素子が占めるチップ上の面積等を考慮して決められる。多くの場合、Ｒ１、Ｒ２の値は、１０ＫΩ～数百キロオームの範囲で選択されるのが適切である。
　また、上記のΔＶ１ａｃとΔＶ１ｄｃとは、多くの場合、同じ値とされるのが望ましい。これは動作サイクル時間の変動に対して負帰還インバータアンプ３０の遅延時間が変化せず一定値となるので、チップ全体での動作タイミング余裕が大きくできる場合からである。ただし、ΔＶ１ａｃとΔＶ１ｄｃとの値を同一にするようにＣ１，Ｃ２，Ｒ１，Ｒ２が設定されたとしても、現実的には、素子ばらつき等により厳密に同一にはならず、２０％程度の差が生じることがある。
　また、チップ全体の設計から決まる、サイクル時間、遅延時間、消費電流値等によっては、設計目標を満たす範囲内であれば、ΔＶ１ａｃとΔＶ１ｄｃとが異なる値に設定されても良い。これは、実際の設計では回路の占める面積や、配線層の選び方、他の回路の配線の配置等多くの要素を考慮する必要があるためである。例えば、結合容量をΔＶ１ａｃ＝ΔＶ１ｄｃとするために必要な値より３０％小さくして、回路が占める面積を削減することも、それによってチップ全体の設計から決まってくる設計目標を満足する限り、許容される。抵抗Ｒ１、Ｒ２に関しても同様である。 The specific design method is shown below.
In the actual design, from the design of the entire chip, the minimum value, maximum value, maximum value of cycle time, minimum value, and power consumption of the power supply voltage VDD, the bus line capacitance C2, and the delay time that the signal transmission circuit 1 should satisfy Target values are given, and C1, R1 and R2 are determined to satisfy them.
First, allowable values (minimum value, maximum value) of the amplitude (ΔV1ac and ΔV1dc) of the bus wiring 10 are examined.
ΔV 1 ac is a signal amplitude determined by the capacitance component C 1 and C 2, and the larger the value, the larger the charge / discharge current of the bus line 10. Specifically, the charge / discharge current of the bus line 10 is proportional to the bus line capacitance and the amplitude ΔV1ac of the bus signal, and inversely proportional to the cycle time. Since the bus wiring capacitance and the minimum cycle time are fixed, the maximum allowable bus signal amplitude can be determined from the power consumption target value. From the viewpoint of the charge and discharge current of the bus interconnection 10, the smaller the ΔV1ac, the smaller the charge and discharge current can be. On the other hand, if .DELTA.V1ac becomes smaller than the minimum value of DC bus signal amplitude .DELTA.V1dc described below, the through current in the negative feedback inverter amplifier and the CMOS circuit in the next stage increases. Therefore, it is desirable that the minimum value of ΔV1ac be approximately the same as the minimum value of ΔV1dc.
Next, the value to be taken of the DC-like bus signal amplitude ΔV1dc is determined. First, the DC input / output characteristics of the negative feedback inverter amplifier 30, that is, the relationship between the DC input voltage and the output voltage and the through current are examined. Generally, it is necessary to prevent the through current from flowing (or to a value sufficiently smaller than the allowable current value) in the next stage to which the negative feedback inverter output is connected. The purpose of the signal transmission circuit 1 is to reduce the current consumption due to the charge and discharge of the bus line capacitance by reducing the bus signal amplitude. The effect of reducing the signal amplitude can be obtained by setting the through current to a sufficiently small value with respect to the charge and discharge current of the bus wiring capacitance. Therefore, the H level of the output of the negative feedback inverter amplifier 30 is made to be equal to or higher than (or near) a voltage lower than the power supply voltage by the absolute value of the PMOS threshold voltage of the next stage. Further, the L level of the output of the negative feedback inverter amplifier 30 is made to be equal to or lower than (or near) a voltage higher than the ground level by the NMOS threshold voltage of the next stage. For example, if the power supply voltage is 1V, the PMOS threshold voltage is -0.2V, and the NMOS threshold voltage is 0.25V, the H level of the output of the negative feedback inverter amplifier 30 is 0.8V or more, and the L level is 0.25V. The input voltage of the negative feedback inverter amplifier 30 is set to be as follows. From the relationship between the input voltage and the output voltage, the range between the H level and the L level of the input of the negative feedback inverter amplifier 30 which satisfies the above can be obtained. From this, the minimum value of ΔV1dc is determined. On the other hand, the maximum value of ΔV1dc is determined by the charge / discharge current target value of bus interconnection 10 at the maximum cycle time.
Next, the delay characteristics of the negative feedback inverter amplifier 30 are examined. That is, the MOSFET size dependency and input amplitude dependency of the delay time are examined.
Within the range of the minimum value and the maximum value of the AC and DC bus signal amplitudes (ΔV1ac, ΔV1dc) already obtained above, the delay time target value of the signal transmission circuit 1 given in the entire chip design is realized The MOSFET size and input amplitude (.DELTA.V1ac, .DELTA.V1dc) are determined.
If ΔV1ac is determined, the coupling capacitance C1 is determined from Equation 6.
On the other hand, when ΔV1dc is determined, the relationship between R1 and R2 is determined from Equation 4. As the values of R1 and R2 are higher, the current flowing through the resistor decreases. Therefore, the values of R1 and R2 are preferably as large as possible in terms of current consumption, but in practice they are determined in consideration of the variation in resistance value, the area on the chip occupied by the resistance element, and the like. In many cases, the values of R1 and R2 are suitably selected in the range of 10 KΩ to several hundred kilo ohms.
Further, it is desirable that the above ΔV1ac and ΔV1dc be the same value in many cases. This is because the delay time of the negative feedback inverter amplifier 30 does not change with respect to the fluctuation of the operation cycle time and becomes a constant value, so that the operation timing margin in the entire chip can be increased. However, even if C1, C2, R1, and R2 are set to equalize the values of ΔV1ac and ΔV1dc, in reality, they do not become exactly the same due to element variations, and the difference of about 20% May occur.
Also, depending on the cycle time, delay time, current consumption value, etc., which are determined from the design of the entire chip, ΔV1ac and ΔV1dc may be set to different values as long as the design target is satisfied. This is because in an actual design, it is necessary to consider many factors such as the area occupied by a circuit, how to select a wiring layer, and the arrangement of wiring of other circuits. For example, reducing the area occupied by the circuit by making the coupling capacitance 30% smaller than the value required to set ΔV1ac = ΔV1dc is acceptable, as long as it satisfies the design goal determined from the design of the entire chip. Be done. The same applies to the resistors R1 and R2.
　具体的な数値例として、例えばΔＶ１ａｃ＝ΔＶ１ｄｃ＝０．２Ｖ、Ｃ２＝５００ｆＦ, Ｃ３＝５ｆＦ,ＶＤＤ＝１．２Ｖ,ＶＯＨ＝１．１０７Ｖ，ＶＯＬ＝０．１０４Ｖ,とすると、数６を変形して以下の数９が得られる。
Figure JPOXMLDOC01-appb-M000010
 これを解くと、Ｃ１＝１００ｆＦとなる。（Ｃ３はＣ２の５００ｆＦより十分小さいので無視した）
また、
VOH-VOL =1.107-0.104=1.003
よって、数４を変形して以下の数１０が得られる。
Figure JPOXMLDOC01-appb-M000011
 ここで負帰還抵抗Ｒ２を１００ｋΩとすれば、数１１が得られる。
Figure JPOXMLDOC01-appb-M000012
 For example, assuming that ΔV1ac = ΔV1dc = 0.2 V, C2 = 500 fF, C3 = 5 fF, VDD = 1.2 V, VOH = 1.107 V, VOL = 0.104 V, the equation 6 is modified. The following equation 9 is obtained.
Figure JPOXMLDOC01-appb-M000010
 When this is solved, C1 = 100 fF. (Since C3 is sufficiently smaller than 500 fF of C2, we ignored it)
Also,
VOH-VOL = 1.107-0.104 = 1.003
Therefore, the following equation 10 is obtained by modifying the equation 4.
Figure JPOXMLDOC01-appb-M000011
 Assuming that the negative feedback resistor R2 is 100 kΩ, Equation 11 is obtained.
Figure JPOXMLDOC01-appb-M000012
　以上では、いくつかの仮定を置いている。それらは、以下の通りである。
（１）バス配線１０を駆動する駆動回路２０の駆動素子の内部抵抗は、ここで用いる抵抗値に比べて十分に低い。
（２）駆動回路２０の出力信号の立上り／立下り時間はバス配線１０が抵抗４２、及び負帰還抵抗３１で充放電される時間に比べて十分に短い。
（３）負帰還インバータアンプ３０出力の立上り／立下り時間もバス配線１０が抵抗４２負帰還抵抗３１で充放電される時間に比べて十分に短い。
（４）負帰還インバータアンプ３０の入力容量は、駆動回路２０とバス配線１０を接続する結合容量とバス容量の和に比べて十分に小さい。 Above, we have made some assumptions. They are as follows.
(1) The internal resistance of the drive element of the drive circuit 20 for driving the bus wiring 10 is sufficiently lower than the resistance value used here.
(2) The rise / fall time of the output signal of the drive circuit 20 is sufficiently shorter than the time when the bus line 10 is charged and discharged by the resistor 42 and the negative feedback resistor 31.
(3) The rise / fall time of the output of the negative feedback inverter amplifier 30 is also sufficiently shorter than the time when the bus line 10 is charged / discharged by the negative feedback resistor 31.
(4) The input capacitance of the negative feedback inverter amplifier 30 is sufficiently smaller than the sum of the coupling capacitance connecting the drive circuit 20 and the bus wiring 10 and the bus capacitance.
　なお、例として挙げた容量、抵抗値では、バス配線１０の充放電の時定数は、約３０ｎｓである。高速ＬＳＩでは内部信号の立上り／立下り時間は、テクノロジによるが数十ピコ秒以下であるから、このバス配線１０の充放電時定数は二桁以上大きい。よって上記（２）（３）の仮定は満たされる。 In addition, in the capacity | capacitance and resistance value mentioned as an example, the time constant of charging / discharging of the bus wiring 10 is about 30 ns. In the high-speed LSI, the rise / fall time of the internal signal is several tens picoseconds or less depending on the technology, so the charge / discharge time constant of the bus wiring 10 is larger by two digits or more. Therefore, the above assumptions (2) and (3) are satisfied.
　また、例として挙げた回路定数の低振幅のバス配線１０は駆動回路２０から見ると負荷容量が８３ｆＦに見えるが、これを例えば５０ｐｓの立上り／立下りで駆動するためには、駆動回路２０の内部抵抗は６００Ωでなければならず、結合抵抗よりも二桁ほど小さい。よって仮定（１）も満たされる。 Also, although the low amplitude bus wiring 10 of the circuit constant mentioned as an example looks at a load capacitance of 83 fF when viewed from the drive circuit 20, in order to drive this at a rise / fall of 50 ps, for example, The internal resistance should be 600 ohms, about two orders of magnitude less than the coupling resistance. Therefore, assumption (1) is also satisfied.
　仮定（４）も、負帰還インバータアンプ３０の入力容量が５ｆＦで、バス配線１０と結合容量１００ｆFの合計容量６００ｆＦに比べてはるかに小さいので満たされている。 Assumption (4) is also satisfied because the input capacitance of the negative feedback inverter amplifier 30 is 5 fF, which is much smaller than the total capacitance 600 fF of the bus wiring 10 and the coupling capacitance 100 fF.
　なお、実際の設計では、ＰＭＯＳとＮＭＯＳのＭＯＳＦＥＴ特性の違い等があるので、上記の計算で求めた抵抗値には微調整が必要である。またＲ１～Ｒ２の値は所望の効果が得られる範囲である程度の幅を許容することができる。 In the actual design, since there are differences between the PMOS and NMOS MOSFET characteristics, etc., it is necessary to finely adjust the resistance value obtained by the above calculation. Also, the values of R1 to R2 can have a width that is within the range in which the desired effect can be obtained.
［実施例１］
　次に、本実施形態に係る信号伝送回路１の実施例１を説明する。
　図４に示す回路において、Ｒ１＝８３ＫΩ、Ｒ２＝１００ＫΩとし、バスには配線抵抗Ｒ４として、４００Ωを挿入した。信号は入力端子ＩＮＰＵＴに与えられ（図４の「入力」）、インバータ２段により増幅されて信号伝送回路が駆動される。バス配線からの信号は負帰還インバータアンプ３０により増幅されたのち、更にインバータによって増幅されて出力端子ＯＵＴＰＵＴから出力される（図４の「出力」及び「反転出力」）。 Example 1
Next, Example 1 of the signal transmission circuit 1 according to the present embodiment will be described.
In the circuit shown in FIG. 4, R1 = 83 K.OMEGA., R2 = 100 K.OMEGA., And 400 .OMEGA. Was inserted in the bus as the wiring resistance R4. A signal is applied to the input terminal INPUT ("input" in FIG. 4), amplified by two stages of inverters to drive the signal transmission circuit. The signal from the bus wiring is amplified by the negative feedback inverter amplifier 30, and then amplified by the inverter and output from the output terminal OUTPUT ("output" and "inverted output" in FIG. 4).
　入力電圧を１．２Ｖで１ＧＨｚの矩形信号を入力した場合、図５に示すように、入力波形に対して、小振幅の負帰還インバータアンプ３０の受信初段入力波形が得られた。また、負帰還インバータアンプ３０の次段のインバータからの出力波形が得られた。また、入力電圧を１．２Ｖで１０ＭＨｚの矩形信号を入力した場合、図６に示すように、入力波形に対して、小振幅の負帰還インバータアンプ３０の受信初段入力波形と、負帰還インバータアンプ３０の次段のインバータからの出力波形が得られた。 When a 1 GHz rectangular signal is input at an input voltage of 1.2 V, as shown in FIG. 5, a reception first stage input waveform of the negative feedback inverter amplifier 30 with a small amplitude is obtained with respect to the input waveform. Also, an output waveform from the inverter at the next stage of the negative feedback inverter amplifier 30 was obtained. When a 10 MHz rectangular signal is input at an input voltage of 1.2 V, as shown in FIG. 6, the input first stage input waveform of the negative feedback inverter amplifier 30 with a small amplitude and the negative feedback inverter amplifier An output waveform from the inverter at the next stage of 30 was obtained.
　電流－周波数特性については、図７は、電源電圧１．３Ｖ、チップ温度（ジャンクション温度）１０５℃（動作許容最高温度）、ＭＯＳＦＥＴの性能：Ｆａｓｔ（最もＭＯＳＦＥＴの性能が高い）の条件で計測した電流－周波数特定のグラフである。図８は、電源電圧１．２Ｖ、チップ温度（ジャンクション温度）５５℃（標準的な動作温度）、ＭＯＳＦＥＴの性能：Ｔｙｐ（製造範囲のセンター条件）の条件で計測した電流－周波数特定のグラフである。即ち、図７は、動作電流が最も大きくなる場合の電流―周波数特性を示し、図８は、標準的な電源電圧及び温度で動作している場合の電流―周波数特定を示す。
　図７及び図８のように、３００ＭＨｚ以上の高い周波数になると、低振幅によるバス配線１０の充放電電流低減効果が顕著に現れ、ＣＭＯＳによるインバータのみで構成される信号伝送回路の１／３程度に低減できることがわかった。 For current-frequency characteristics, Figure 7 measured under conditions of supply voltage 1.3 V, chip temperature (junction temperature) 105 ° C (permissible maximum temperature), and MOSFET performance: Fast (highest performance of MOSFET) It is a current-frequency specific graph. Figure 8 is a graph of current-frequency specification measured under the conditions of power supply voltage 1.2 V, chip temperature (junction temperature) 55 ° C (standard operating temperature), and MOSFET performance: Typ (center condition of manufacturing range) is there. That is, FIG. 7 shows the current-frequency characteristics when the operating current is the largest, and FIG. 8 shows the current-frequency specification when operating at standard power supply voltage and temperature.
As shown in FIG. 7 and FIG. 8, when the frequency is 300 MHz or higher, the reduction effect of the charge / discharge current of the bus line 10 due to the low amplitude appears remarkably, and it is about 1/3 of the signal transmission circuit composed only of the inverter by CMOS. It can be reduced to
　以上、本実施形態に係る信号伝送回路１では、以下の効果を奏する。 As described above, the signal transmission circuit 1 according to the present embodiment has the following effects.
（１）信号伝送回路１は、駆動回路２０の近傍のバス配線１０に配置される結合部４０を備え、結合部４０は、バス配線１０に直列に配置されるコンデンサ４１と、コンデンサ４１に並列に配置される抵抗４２と、を備える。結合部４０により、負荷容量が小さく見えるので、駆動する回路の素子サイズを小さくすることができる。これにより、信号伝送回路１が配置されるモジュールの面積の縮小と、信号伝送回路１の消費電力の低減とをすることができる。また、負帰還インバータアンプ３０の出力データが消失しないので、ラッチ回路を用いる必要がなく、信号伝送回路１を安価に構成することができる。 (1) The signal transmission circuit 1 includes the coupling portion 40 disposed on the bus wiring 10 in the vicinity of the drive circuit 20. The coupling portion 40 is parallel to the capacitor 41 and the capacitor 41 disposed in series on the bus wiring 10 And a resistor 42 disposed on the The coupling section 40 makes it possible to reduce the element size of the circuit to be driven because the load capacity looks small. Thus, the area of the module in which the signal transmission circuit 1 is disposed can be reduced, and the power consumption of the signal transmission circuit 1 can be reduced. Further, since the output data of the negative feedback inverter amplifier 30 does not disappear, there is no need to use a latch circuit, and the signal transmission circuit 1 can be configured inexpensively.
（２）また、結合部４０のコンデンサ４１の容量をＣ１、バス配線１０の静電容量をＣ２、結合部４０の抵抗４２の抵抗値をＲ１、負帰還インバータアンプの負帰還抵抗値をＲ２、前記負帰還インバータアンプの出力のＤＣ的ローレベルをＶＯＬ、前記負帰還インバータアンプの出力のＤＣ的ハイレベルをＶＯＨ、電源電圧をＶＤＤとして、以下の数１２
Figure JPOXMLDOC01-appb-M000013
 を満たすようにした。これにより、負帰還インバータアンプ３０の遅延時間が動作サイクル時間によらず一定に近付けられるので、チップのタイミング設計の余裕度を大きくすることができる。 (2) The capacitance of the capacitor 41 of the coupling unit 40 is C1, the capacitance of the bus wiring 10 is C2, the resistance value of the resistor 42 of the coupling unit 40 is R1, and the negative feedback resistance of the negative feedback inverter amplifier is R2. Assuming that the DC low level of the output of the negative feedback inverter amplifier is VOL, the DC high level of the output of the negative feedback inverter amplifier is VOH, and the power supply voltage is VDD:
Figure JPOXMLDOC01-appb-M000013
 To meet As a result, the delay time of the negative feedback inverter amplifier 30 can be made nearly constant regardless of the operation cycle time, so that the margin of the timing design of the chip can be increased.
（３）また、信号伝送回路１の設計方法において、コンデンサ４１の静電容量及び抵抗４２の抵抗値は、負帰還インバータアンプ３０への入力電圧のＨ／Ｌレベルに基づいて決定される。これにより、負帰還インバータアンプ３０の遅延時間を大きく変動させずに動作の安定した信号伝送回路１を得ることができる。 (3) Further, in the method of designing the signal transmission circuit 1, the capacitance of the capacitor 41 and the resistance value of the resistor 42 are determined based on the H / L level of the input voltage to the negative feedback inverter amplifier 30. As a result, it is possible to obtain the stable signal transmission circuit 1 of the operation without significantly changing the delay time of the negative feedback inverter amplifier 30.
　１　信号伝送回路
　１０　バス配線
　２０　駆動回路
　３０　負帰還インバータアンプ
　３１　負帰還抵抗
　３２　反転増幅器
　４０　結合部
　４１　コンデンサ
　４２　抵抗 DESCRIPTION OF SYMBOLS 1 signal transmission circuit 10 bus wiring 20 drive circuit 30 negative feedback inverter amplifier 31 negative feedback resistance 32 inverting amplifier 40 coupling part 41 capacitor 42 resistance

Claims (4)

  1. 　バス配線と、前記バス配線の一端に接続される駆動回路と、前記バス配線の他端に接続される負帰還インバータアンプと、を備える信号伝送回路であって、
    　前記駆動回路の出力端と前記バス配線とを接続する結合部を備え、
    　前記結合部は、
    　前記バス配線に直列に配置されるコンデンサと、
    　前記コンデンサに並列に配置される抵抗と、
    を備える信号伝送回路。     A signal transmission circuit comprising: a bus line; a drive circuit connected to one end of the bus line; and a negative feedback inverter amplifier connected to the other end of the bus line,
    And a connecting portion connecting the output terminal of the drive circuit and the bus line,
    The connecting portion is
    A capacitor disposed in series with the bus line;
    A resistor placed in parallel with the capacitor;
    A signal transmission circuit comprising:
  2. 　前記結合部のコンデンサの容量をＣ１、前記バス配線の静電容量をＣ２、前記結合部の抵抗の抵抗値をＲ１、負帰還インバータアンプの負帰還抵抗値をＲ２、前記負帰還インバータアンプの出力のＤＣ的ローレベルをＶＯＬ、前記負帰還インバータアンプの出力のＤＣ的ハイレベルをＶＯＨ、電源電圧をＶＤＤとして、以下の数１
    Figure JPOXMLDOC01-appb-M000001
     を満たす請求項１に記載の信号伝送回路。     The capacitance of the capacitor of the coupling portion is C1, the capacitance of the bus wiring is C2, the resistance value of the resistor of the coupling portion is R1, the negative feedback resistance value of the negative feedback inverter amplifier is R2, the output of the negative feedback inverter amplifier Where the DC low level of the negative feedback inverter amplifier is VOL, the DC high level of the output of the negative feedback inverter amplifier is VOH, and the power supply voltage is VDD.
    Figure JPOXMLDOC01-appb-M000001
     The signal transmission circuit according to claim 1, wherein
  3. 　請求項１又は２に記載の信号伝送回路を複数備えるチップモジュール。 A chip module comprising a plurality of the signal transmission circuits according to claim 1 or 2.
  4. 　請求項１に記載の信号伝送回路の設計方法であって、
    　前記コンデンサの静電容量及び前記抵抗の抵抗値を前記負帰還インバータアンプへの入力電圧のＨ／Ｌレベルに基づいて決定する信号伝送回路の設計方法。     A method of designing a signal transmission circuit according to claim 1, wherein
    A design method of a signal transmission circuit, wherein the capacitance of the capacitor and the resistance value of the resistor are determined based on the H / L level of the input voltage to the negative feedback inverter amplifier.
PCT/JP2017/038211 2017-10-23 2017-10-23 Signal transmission circuit and chip module WO2019082245A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008054352A (en) * 1997-08-20 2008-03-06 Advantest Corp Signal transmission circuit, cmos device and circuit substrate
JP2008227635A (en) * 2007-03-09 2008-09-25 Nec Corp Differential transmission circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025608A (en) * 1988-06-23 1990-01-10 Nec Ic Microcomput Syst Ltd Amplifier circuit formed into semiconductor integrated circuit
JP2690212B2 (en) * 1991-04-30 1997-12-10 日本電気アイシーマイコンシステム株式会社 Current detection type data bus amplifier for semiconductor memory device
US5717715A (en) * 1995-06-07 1998-02-10 Discovision Associates Signal processing apparatus and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008054352A (en) * 1997-08-20 2008-03-06 Advantest Corp Signal transmission circuit, cmos device and circuit substrate
JP2008227635A (en) * 2007-03-09 2008-09-25 Nec Corp Differential transmission circuit

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