JP2008227635A - Differential transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential transmission circuit which can be prevented from malfunctioning when instable signals occurs when a signal line is not connected. <P>SOLUTION: When the signal line is not connected in the differential reception circuit 14 of the differential transmission circuit 10, the true signal input of the differential reception circuit is pulled up to the voltage Vcc of a power source 20 and the output voltage of the differential reception circuit 14 is fixed at a high level HI. During the normal operation of the differential transmission circuit 10, when the terminating voltage VT of the differential transmission circuit 10 is set to 1/2Vcc, resistance values R1, R2 and R3 of resistors 22, 24 and 26 are set to R1+R2=R3, and the voltage of the true signal input in+ is made equal to the voltage of complementary signal input in-. Encoded data signals are made to pass through capacitors 28 and 30 as they are. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a differential transmission circuit, and more particularly to a differential transmission circuit effective in preventing malfunction of a differential reception circuit due to an indefinite signal when a signal line is not connected.

  In a differential transmission circuit generally used in a high-speed interface connecting one transmission device and one reception device, if the signal of the receiver circuit is not input due to the power supply Off of the transmission device, the cable not being connected, etc. The potential difference between the differential signals (true signal / complement signal) disappears, and the receiver output becomes indefinite. As a result, the indefinite signal may turn into a valid signal and cause the device to malfunction.

  Means for avoiding such inconvenience have also been adopted in the past. For example, a circuit that adds a pull-up / pull-down resistor to the input of the receiver circuit to provide a potential difference in advance, an effective signal inspection circuit is provided in the internal logic, and the pull-up / pull-down resistor is separated, or an effective signal inspection in the internal logic A system in which a circuit is provided and an invalid signal is ignored has been used.

However, when a circuit such as a switch is added to the receiver input circuit in the above-described conventional means, the waveform affects the distortion signal quality. Further, if a potential difference is given to the input of the receiver circuit in advance, there is a problem that the amplitude becomes small during normal signal transmission and transmission over a long distance becomes impossible.
In addition, in order to provide an effective signal inspection circuit in the internal logic, a click signal is required and the amount of hardware increases. Therefore, it is difficult to provide an effective signal inspection circuit in a relay circuit such as a simple buffer or repeater. It was.
Also, in a high-speed interface that employs an encoding method typified by 8B10B, AC coupling is performed by a capacitor. However, even in this high-speed interface, if a signal is not input in the receiving circuit and the signal becomes indefinite, A malfunction occurs in the circuit, and there is a similar technical problem.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a differential transmission circuit capable of preventing malfunction when an indefinite signal is generated when a signal line is not connected.

  In order to solve the above problem, the invention according to claim 1 is characterized in that a true signal output of a differential transmission circuit is connected to a true signal input of a differential reception circuit via a first signal line, and the differential signal is transmitted. The present invention relates to a differential transmission circuit for connecting a complement signal output of a transmission circuit to a complement signal input of a differential reception circuit via a second signal line, and a DC voltage of the true signal input when the signal line is not connected. Voltage application means for making the DC voltage of the complement signal input higher than the DC voltage of the complement signal input or lowering the DC voltage of the complement signal input than the DC voltage of the true signal input is provided as an output of the differential transmission circuit and an input of the differential reception circuit And a first capacitive element is connected between the signal output and the signal input opposite to the signal output and the signal input. When To have.

  A second aspect of the present invention relates to the differential transmission circuit according to the first aspect, wherein the voltage applying means includes the true signal output and a first voltage source having a voltage lower than a termination voltage of the differential receiving circuit. A first resistive element to be connected; a second resistive element and a second capacitive element connected in parallel between the first signal line and the true signal input; and the true signal input; A third resistive element connected between a second voltage source having a voltage higher than the termination voltage, and a voltage at a connection point between the second resistive element and the third resistive element The resistance values of the first resistive element, the second resistive element, and the third resistive element are set so that becomes the termination voltage, and the first capacitive element It is characterized by being connected between a signal line and the complement signal input.

  A third aspect of the present invention relates to the differential transmission circuit according to the second aspect, wherein the first voltage source is a ground potential, and the second voltage source is a driving voltage source of the differential receiving circuit. It is characterized by being.

  A fourth aspect of the present invention relates to the differential transmission circuit according to the second or third aspect, wherein the true signal input to which the third resistive element is connected is lower than the termination voltage of the differential reception circuit. A fourth resistive element is connected between the first voltage source and the third voltage source, and the voltage at the connection point of the second, third and fourth resistors is the terminal voltage. It is characterized in that the resistance values of the third and fourth resistive elements are set.

  A fifth aspect of the invention relates to the differential transmission circuit according to the fourth aspect of the invention, wherein the third voltage source is a ground potential.

  A sixth aspect of the present invention relates to the differential transmission circuit according to the first aspect, wherein the voltage applying means includes the true signal output and a fourth voltage source having a voltage lower than a termination voltage of the differential receiving circuit. A fourth resistive element to be connected; a fifth resistive element and a third capacitive element connected in parallel between the true signal output and the first signal line; and the true signal input; A sixth resistive element connected between a fifth voltage source having a voltage higher than the termination voltage, and a voltage at a connection point between the fifth resistive element and the sixth resistive element The resistance values of the fourth resistive element, the fifth resistive element, and the sixth resistive element are set so that the terminal voltage becomes the termination voltage, and the first capacitive element It is characterized by being connected between an output and the second signal line.

  A seventh aspect of the present invention relates to the differential transmission circuit according to the second aspect, wherein the fourth voltage source is a ground potential, and the fifth voltage source is a driving voltage source of the differential receiving circuit. It is characterized by being.

  The invention according to claim 8 relates to the differential transmission circuit according to claim 6 or 7, wherein the true signal input to which the sixth resistive element is connected is lower than the termination voltage of the differential reception circuit. A seventh resistive element is connected between the voltage source and the fourth, fifth, and sixth voltage sources so that the voltage at the connection point of the fifth, sixth and seventh resistors becomes the termination voltage. A feature is that the resistance values of the sixth and seventh resistive elements are set.

  A ninth aspect of the invention relates to the differential transmission circuit according to the eighth aspect of the invention, wherein the sixth voltage source is a ground potential.

  A tenth aspect of the present invention relates to the differential transmission circuit according to the first aspect, wherein the voltage applying means is a seventh voltage source having a voltage higher than the complementary signal output and the termination voltage of the differential receiving circuit. An eighth resistive element, a ninth resistive element and a fourth capacitive element connected in parallel between the second signal line and the complement signal input, and the complementary A tenth resistive element connected between an input signal and an eighth voltage source having a voltage lower than the termination voltage, and the ninth resistive element and the tenth resistive element The resistance values of the eighth resistive element, the ninth resistive element, and the tenth resistive element are set so that the voltage at the connection point becomes the termination voltage, and the first capacitive element is Connected between the first signal line and the true signal input It is characterized.

  An eleventh aspect of the present invention relates to the differential transmission circuit according to the tenth aspect, wherein the seventh voltage source is a driving voltage source of the differential transmission circuit, and the eighth voltage source is a ground potential. It is characterized by being.

  A twelfth aspect of the present invention relates to the differential transmission circuit according to the tenth or eleventh aspect, wherein the complementary signal input to which the ninth resistive element is connected and a termination voltage of the differential reception circuit are higher. An eleventh resistive element is connected between the ninth voltage source and the eighth, ninth, and ninth voltages so that the voltage at the connection point of the ninth, tenth and eleventh resistors becomes the termination voltage. The resistance values of the tenth and eleventh resistive elements are set.

  A thirteenth aspect of the invention relates to the differential transmission circuit according to the twelfth aspect of the invention, wherein the ninth voltage source is a driving power source for the differential receiving circuit.

  A fourteenth aspect of the present invention relates to the differential transmission circuit according to the first aspect, wherein the voltage applying means is a tenth voltage source having a voltage higher than the complementary signal output and the termination voltage of the differential receiving circuit. , A thirteenth resistive element and a fifth capacitive element connected in parallel between the complement signal output and the second signal line, and the complement A fourteenth resistive element connected between an input signal and an eleventh voltage source having a voltage lower than the termination voltage, and the thirteenth resistive element and the fourteenth resistive element The resistance values of the twelfth resistive element, the thirteenth resistive element, and the fourteenth resistive element are set so that the voltage at the connection point becomes the termination voltage, and the first capacitive element is Between the true signal output and the first signal line It is characterized by being continued.

  A fifteenth aspect of the present invention relates to the differential transmission circuit according to the fourteenth aspect, wherein the tenth voltage source is a driving voltage source of the differential transmission circuit, and the eleventh voltage source is a ground potential. It is characterized by being.

  A sixteenth aspect of the present invention relates to the differential transmission circuit according to the fourteenth or fifteenth aspect, wherein the complementary signal input to which the fourteenth resistive element is connected and a twelfth voltage higher than the termination voltage are connected. A fifteenth resistive element is connected to a voltage source, and the twelfth, thirteenth, fourteenth, and fourteenth voltages are set so that the voltage at the connection point of the thirteenth, fourteenth and fifteenth resistors becomes the termination voltage. And the resistance value of the fifteenth resistive element is set.

  A seventeenth aspect of the present invention relates to the differential transmission circuit according to the sixteenth aspect, wherein the twelfth voltage source is a driving power source of the differential receiving circuit.

  According to the present invention, the DC voltage of the true signal input of the differential receiving circuit when the signal line is not connected is made higher than the DC voltage of the complement signal input, or the DC voltage of the complement signal input is increased to the DC voltage of the true signal input. Therefore, malfunction of the differential receiving circuit can be prevented. Further, during normal operation, the DC voltage of the true signal input and the DC voltage of the complement signal input of the differential receiving circuit can be set as termination voltages, so that signal transmission can also be performed normally.

  In the present invention, when the signal line is not connected to the differential receiving circuit, the DC voltage of the true signal input is made higher than the DC voltage of the complement signal input, or the DC voltage of the complement signal input is made higher than the DC voltage of the true signal input. Along with any of the means for lowering, and means for setting the DC voltage of the true signal input and the DC voltage of the complement signal input of the differential receiving circuit to the termination voltage during normal operation.

1 is a diagram illustrating an electrical configuration of a differential transmission circuit according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an operation of the differential transmission circuit when a signal line is not connected. FIG. 3 is a diagram for explaining an operation during a normal operation in the differential transmission circuit.
The differential transmission circuit 10 of this embodiment relates to a circuit that prevents malfunction of the differential reception circuit even if the differential signal becomes indefinite when the signal line is not connected. The differential transmission circuit (differential driver) 12 A differential receiver circuit (differential receiver) 14, a true signal transmission line 16, a complement signal transmission line 18, a power supply (Vcc) 20, a resistor 22, a resistor 24, a resistor 26, and an AC coupling. Capacitor 28 and AC coupling capacitor 30.

The differential transmission circuit 12 converts binary information 1 and 0 to be transmitted to the differential reception circuit 14 into a differential signal composed of a true signal and a complement signal, and the differential signal is used as a true signal output 12T and a complement. This is a circuit for transmitting the signal output 12C to the true signal transmission line 16 and the complement signal transmission line 18. The true signal output of the differential transmission circuit 12 is grounded via a resistor 24 having a resistance value R1.
The true signal transmission line 16 is a line for transmitting the true signal output from the true signal output 12 </ b> T of the differential transmission circuit 12 to the differential reception circuit 14. The true signal transmission line 16 is connected to the true signal input of the differential receiving circuit 14 through a parallel circuit of a resistor 26 having a resistance value R 2 and an AC coupling capacitor 28. In addition, the output of the power source (Vcc) 20 that outputs the voltage Vcc is connected to the true signal input of the differential receiving circuit 14 via the resistor 22 having a resistance value R3.
The resistance values of the resistors 24, 26, and 22 are set so that the relationship R1 + R2 = R3 is established between the resistance values R1, R2 of the resistors 24 and 26 and the resistance value R3 of the resistor 22. The

In addition, the complement signal transmission line 18 is a line for transmitting the complement signal output from the complement signal output 12 </ b> C of the differential transmission circuit 12 to the differential reception circuit 14. The complement signal transmission line 18 is connected to the complement signal input of the differential receiving circuit 14 via the AC coupling capacitor 30 to constitute the entire embodiment of the present invention.
The differential receiving circuit 14 is a circuit that receives a differential signal transmitted through the true signal transmission line 16 and the complement signal transmission line 18 and outputs a binary signal.
The differential receiving circuit 14 includes termination resistors 32 and 34 having a termination voltage VT equal to the impedance (generally 50Ω) of the true signal transmission line 16 and the complement signal transmission line 18 to the termination voltage VT. Terminated.

Next, the operation of this embodiment will be described with reference to FIGS.
In the differential transmission circuit 10 of this embodiment, the operation state of the differential reception circuit 14 when the differential signal of the differential reception circuit 14 is not input without signal line connection is equivalent to that in FIG. Thus, since the true signal input is pulled up to the voltage Vcc of the power supply 20, the voltage of the true signal input in + of the differential receiving circuit 14 becomes higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

In normal operation of the differential transmission circuit 10 (FIG. 3), when the termination voltage VT of the differential transmission circuit 10 is set to 1/2 Vcc, the resistors 22 and 24 are set so that the relationship of R1 + R2 = R3 is established. 26, the voltage of the true signal input in + of the differential receiving circuit 14 is equal to the voltage of the complement signal input in-, and the voltage of the true signal input in + of the differential receiving circuit 14 is complementary. The potential difference is no longer between the input signal and the input signal.
Therefore, the encoded data signal passes through the capacitors 28 and 30 as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Thus, according to the configuration of this embodiment, one resistor is provided between the true signal output of the differential transmission circuit and the ground potential, and between the true signal line and the true signal input of the differential reception circuit. One resistor and one capacitor connected in parallel add one resistor between the true signal input of the differential receiver circuit and the power supply, while the complement signal line and the complement signal of the differential receiver circuit By adding one capacitor between the input and the input, the differential receiver circuit's input signal becomes indefinite when the signal line is not connected, without affecting the normal operation signal transmission. Can be prevented from malfunctioning.

4 is a diagram showing an electrical configuration of a differential transmission circuit according to a second embodiment of the present invention.
The configuration of this embodiment differs greatly from that of the first embodiment in that the inventive concept shown in the first embodiment is changed so that it can be applied to a complement signal line.
That is, in the differential transmission circuit 10A of this embodiment, as shown in FIG. 4, the complement signal output of the differential signal transmission circuit 12 is connected to the power source (Vcc) 50 through the resistor 44 having the resistance value R4. On the other hand, the complement signal transmission line 16 is connected to the complement signal input of the differential receiver circuit 14 through a parallel circuit of the resistor 46 having the resistance value R5 and the AC coupling capacitor 30, and the complement is connected. The main part of this embodiment is configured by connecting the signal input to the ground potential via a resistor 42 having a resistance value R6.
The resistance values of the resistors 44, 46 and 42 are set so that the relationship R4 + R5 = R6 is established between the resistance values R4 and R5 of the resistors 44 and 46 and the resistance value R6 of the resistor 42. The
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
In the differential transmission circuit 10A of this embodiment, when the differential signal of the differential receiving circuit 14 is not input without being connected to the signal line, the complement signal input of the differential receiving circuit 14 is pulled down to the ground potential. The voltage of the true signal input in + of the differential receiving circuit 14 becomes higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

In normal operation of the differential transmission circuit 10A, when the termination voltage VT of the differential transmission circuit 10A is set to 1/2 Vcc, the resistances of the resistors 44, 46, and 42 are established so that the relationship of R4 + R5 = R6 is established. Since the value is set, the voltage of the complement signal input in− of the differential reception circuit 14 is equal to the voltage of the true signal input in +, and the true signal input in + of the differential reception circuit 14 and the complement signal input in + The potential difference disappears from-.
Therefore, the encoded data signal passes through the capacitors 28 and 30 as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

FIG. 5 is a diagram showing an electrical configuration of the differential transmission circuit according to the third embodiment of the present invention.
The configuration of this embodiment is greatly different from that of the first embodiment in that a resistor is connected to both the power supply and the GND by a Thevenin connection for the true signal line on the differential receiver circuit (differential receiver) side. is there.
That is, in the differential transmission circuit 10B of this embodiment, as shown in FIG. 5, in the configuration of the first embodiment, the true signal input of the differential reception circuit 14 is grounded via the resistor 36 having the resistance value R7. Configured.
When the signal line is not connected, the resistance value of the resistor 22 is such that the voltage at the connection point between the resistor 22 and the resistor 36 is higher than the voltage (termination voltage) of the complement signal input of the differential receiver circuit 14. And the resistance value of the resistor 36 is set.
In addition, between the parallel combined resistance value of the resistor 24, the resistor 26, and the resistor 36 and the resistance value R3 of the resistor 22, the resistor 24, the resistor 26, and the resistor so that the relationship of (R1 + R2) R7 / R1 + R2 + R7 = R3 is established. The resistance values of 36 and the resistor 22 are set.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
In the differential transmission circuit 10B of this embodiment, when the differential signal of the differential reception circuit 14 is not input without signal line connection, the true signal input of the differential reception circuit 14 is powered by the resistor 22 and the resistor 36. Since the voltage Vcc is pulled up to a voltage higher than the termination voltage VT, the voltage of the true signal input in + of the differential reception circuit 14 becomes higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

In the normal operation of the differential transmission circuit 10B, when the termination voltage VT of the differential reception circuit 14 is set to 1/2 Vcc, each resistor 24, so that the relationship of (R1 + R2) R7 / R1 + R2 + R7 = R3 is established. Since the resistance values 26, 36, and 22 are set, the voltage of the complement signal input in− of the differential reception circuit 14 becomes equal to the voltage of the true signal input in +, and the true signal input of the differential reception circuit 14 is set. There is no potential difference between in + and complement signal input in−.
Therefore, the encoded data signal passes through the capacitors 28 and 30 as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

6 is a diagram showing an electrical configuration of a differential transmission circuit according to a fourth embodiment of the present invention.
The configuration of this embodiment is significantly different from that of the second embodiment in that, in the differential receiver circuit (differential receiver), a resistor is connected to both the power supply and the GND by a Thevenin connection for the complement signal line. is there.
That is, in the differential transmission circuit 10C of this embodiment, as shown in FIG. 6, in the configuration of the second embodiment, the complementary signal input of the differential reception circuit 14 is supplied to the power supply Vcc via the resistor 48 having the resistance value R8. Configured to connect to.
When the signal line is not connected, the resistance value of the resistor 42 and the voltage at the connection point between the resistor 42 and the resistor 48 are lower than the voltage (termination voltage) of the true signal input of the differential receiving circuit 14. The resistance value of the resistor 48 is set.
Further, the resistance 44, the resistance 46, and the resistance 46 are set so that the relationship (R4 + R5) R8 / R4 + R5 + R8 = R6 is established between the parallel combined resistance value of the resistance 44, the resistance 46, and the resistance 48 and the resistance value R6 of the resistance 42. The resistance values of 48 and the resistor 42 are set.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
In the differential transmission circuit 10C of this embodiment, when the differential signal of the differential reception circuit 14 is not input without signal line connection, the complementary signal input of the differential reception circuit 14 is caused by the resistor 48 and the resistor 42. Since it is pulled down to a voltage lower than the termination voltage VT obtained by dividing the power supply voltage Vcc, the voltage of the true signal input in + of the differential receiving circuit 14 becomes higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

In the normal operation of the differential transmission circuit 10C, when the termination voltage VT of the differential reception circuit 14 is set to 1/2 Vcc, each resistor 44, so that the relationship of (R4 + R5) R8 / R4 + R5 + R8 = R6 is established. Since the resistance values of 46, 48 and 42 are set, the voltage of the complement signal input in− of the differential reception circuit 14 becomes equal to the voltage of the true signal input in +, and the loop signal input of the differential reception circuit 14 There is no potential difference between in + and complement signal input in−.
Therefore, the encoded data signal passes through the capacitors 28 and 30 as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

FIG. 7 is a diagram showing an electrical configuration of a differential transmission circuit according to the fifth embodiment of the present invention.
The configuration of this embodiment is greatly different from that of the first embodiment in that a parallel circuit of a resistor and a capacitor connected between a true signal line and a true signal input of a differential receiver circuit (differential receiver). The capacitor connected between the complement signal line and the complement signal input is moved to the differential transmission circuit side.
That is, as shown in FIG. 7, the differential transmission circuit 10D according to this embodiment includes a resistor 26S corresponding to the resistor 26 and the capacitor 28S according to the first embodiment, and a true signal output and a true value of the differential transmission circuit 12. The capacitor 30S provided between the signal transmission line 16 and the capacitor 30S corresponding to the capacitor 30 of the first embodiment is provided between the complement signal output of the differential transmission circuit 12 and the complement signal transmission line 18. .
The sum of the resistance value of the resistor 26 </ b> S and the resistance value of the resistor 24 is set to be equal to the resistance value of the resistor 22.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
Also in this embodiment, the operation state of the differential receiving circuit 14 when the differential signal of the differential receiving circuit 14 is not input is equivalent to that in FIG. Since it is pulled up to the voltage Vcc, the voltage of the true signal input in + of the differential receiving circuit 14 becomes higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

Even in the normal operation of the differential transmission circuit 10D, when the termination voltage VT of the differential transmission circuit 10 is set to 1/2 Vcc, the sum of the resistance value of the resistor 26S and the resistance value of the resistor 24 is Since it is set to be equal to the resistance value, the voltage of the true signal input in + of the differential receiving circuit 14 becomes equal to the voltage of the complement signal input in−, and the true signal input in + of the differential receiving circuit 14 There is no potential difference with the complement signal input in−.
Therefore, the encoded data signal passes through the capacitors 28 and 30 as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

FIG. 8 is a diagram showing an electrical configuration of a differential transmission circuit according to the sixth embodiment of the present invention.
The configuration of this embodiment differs greatly from that of the second embodiment in that the capacitor connected between the true signal transmission line and the true signal input, the complement signal transmission line, and the complement signal input of the differential receiving circuit are different. The parallel circuit of the resistor and the capacitor connected to each other is moved to the differential transmission circuit side.
That is, as shown in FIG. 8, the differential transmission circuit 10E of this embodiment includes the resistor 46S of the second embodiment, the resistor 46S corresponding to the capacitor 30, and the capacitor 30S as the complement signal output of the differential transmission circuit 12. Provided between the complementary signal transmission line 18 and a capacitor 28S corresponding to the capacitor 28 of the second embodiment is provided between the true signal output of the differential transmission circuit 12 and the true signal transmission line 16. .
The sum of the resistance value R4 of the resistor 44 and the resistance value R5 of the resistor 46S is set to be equal to the resistance value R6 of the resistor 42.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
In this embodiment as well, the differential receiver circuit 14 operates when the differential signal of the differential receiver circuit 14 is no longer input because the complement signal input is pulled down to the ground potential. The voltage of the true signal input in + is higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

Even in the normal operation of the differential transmission circuit 10E, when the termination voltage VT of the differential reception circuit 14 is set to 1/2 Vcc, the sum of the resistance value of the resistor 46S and the resistance value of the resistor 44 is Since it is set to be equal to the resistance value, the voltage of the true signal input in + of the differential receiving circuit 14 becomes equal to the voltage of the complement signal input in−, and the true signal input in + of the differential receiving circuit 14 There is no potential difference with the complement signal input in−.
Therefore, the encoded data signal passes through the capacitors 28S and 30S as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

9 is a diagram showing an electrical configuration of a differential transmission circuit according to a seventh embodiment of the present invention.
The configuration of this embodiment differs greatly from that of the third embodiment in that a parallel circuit of a resistor and a capacitor connected between a true signal line and a true signal input of a differential receiver circuit (differential receiver) The capacitor connected between the complement signal line and the complement signal input is moved to the differential transmission circuit side.
That is, as shown in FIG. 9, the differential transmission circuit 10F according to this embodiment includes a resistor 26S and a capacitor 28S corresponding to the resistor 26 and the capacitor 28 according to the third embodiment. The capacitor 30S provided between the signal transmission line 16 and the capacitor 30S corresponding to the capacitor 30 of the third embodiment is provided between the complement signal output of the differential transmission circuit 12 and the complement signal transmission line 18. .
The method of setting the resistance value of the resistor 22 and the resistance value of the resistor 36 and the method of setting the resistance value of the resistor 24, the resistor 26S, the resistor 36, and the resistor 22 are the same as in the third embodiment.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
Also in this embodiment, the operation state of the differential receiver circuit 14 when the differential signal of the differential receiver circuit 14 is not input without the signal line being connected is the voltage divided by the resistor 22 and the resistor 36. Since the voltage is pulled up to a voltage higher than the voltage of the complement signal input in−, the voltage of the true signal input in + of the differential reception circuit 14 becomes higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

Even in the normal operation of the differential transmission circuit 10F, when the termination voltage VT of the differential transmission circuit 10 is set to 1/2 Vcc, the parallel combined resistance value of the resistor 24, the resistor 26S, and the resistor 36 is the resistance of the resistor 22. Therefore, the voltage of the true signal input in + of the differential receiving circuit 14 is equal to the voltage of the complement signal input in−, and is complementary to the true signal input in + of the differential receiving circuit 14. The potential difference is no longer between the input signal and the input signal.
Therefore, the encoded data signal passes through the capacitors 28S and 30S as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

10 is a diagram showing an electrical configuration of a differential transmission circuit according to an eighth embodiment of the present invention.
The configuration of this embodiment differs greatly from that of the fourth embodiment in that the capacitor connected between the true signal transmission line and the true signal input, the complement signal transmission line, and the complement signal input of the differential receiver circuit are different. The parallel circuit of the resistor and the capacitor connected to each other is moved to the differential transmission circuit side.
That is, as shown in FIG. 10, the differential transmission circuit 10G according to this embodiment includes a resistor 46S according to the fourth embodiment, a resistor 46S corresponding to the capacitor 30, and a capacitor 30S as a complement signal output of the differential transmission circuit 12. Provided between the complementary signal transmission line 18 and a capacitor 28S corresponding to the capacitor 28 of the fourth embodiment is provided between the true signal output of the differential transmission circuit 12 and the true signal transmission line 16. .
The method of setting the resistance value of the resistor 42 and the resistance value of the resistor 48 and the method of setting the resistance values of the resistor 44, the resistor 46S, the resistor 48, and the resistor 42 are the same as in the fourth embodiment.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIG.
Also in this embodiment, the operation state of the differential receiver circuit 14 when the differential signal of the differential receiver circuit 14 is not input without the signal line being connected is the voltage divided by the resistor 48 and the resistor 42. Since the voltage is lower than the voltage of the complement signal input in−, the voltage of the true signal input in + of the differential reception circuit 14 is higher than the voltage of the complement signal input in−.
Therefore, the output voltage of the differential receiving circuit 14 is fixed to the high level HI, and the output level is guaranteed.

Even in the normal operation of the differential transmission circuit 10G, when the termination voltage VT of the differential reception circuit 14 is set to 1/2 Vcc, the parallel combined resistance value of the resistor 44, the resistor 46S, and the resistor 48 is Since it is set to be equal to the resistance value, the voltage of the true signal input in + of the differential receiving circuit 14 becomes equal to the voltage of the complement signal input in−, and the true signal input in + of the differential receiving circuit 14 There is no potential difference with the complement signal input in−.
Therefore, the encoded data signal passes through the capacitors 28S and 30S as they are, that is, is input to the input of the differential receiving circuit 14 without being electrically influenced.

  Therefore, the same effect as that of the first embodiment can be obtained in the configuration of this embodiment.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration of the present invention is not limited to these embodiments, and the design does not depart from the gist of the present invention. These changes are included in the present invention.
For example, in any of the above-described embodiments, the example using the capacitor has been described. However, a differential transmission circuit that is replaced by another capacitive element may be configured.
Also, in any of the above-described embodiments, the example in which the termination voltage VT is set to 1/2 Vcc has been described. However, in any termination voltage other than this termination voltage, for example, in the configuration of the first embodiment, the resistor 22 The three resistors 22, 24, and 26 are divided by the three resistors 22, 24, and 26 so that the voltage appearing at the connection point between the resistors 26 and 22 is equal to the arbitrary termination voltage. If the resistance value is set, a differential transmission circuit corresponding to the arbitrary termination voltage can be configured.
Further, for example, a parallel circuit of a resistor 26 and a capacitor 28 may be provided on the true signal line 16 or the complement signal line 18.
Further, for example, in the first embodiment, when the true signal transmission signal 16 and the complement signal transmission line 18 are not connected, the line resistance 22 may be connected to the true signal input of the differential receiving circuit. . In other embodiments, an equivalent circuit configuration can be provided.

  The differential transmission circuit disclosed herein can be used for a transmission line that transmits signals at high speed between a computer and a peripheral device.

It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 1 of this invention. It is a figure explaining the operation | movement at the time of the signal line unconnected in the differential transmission circuit. It is a figure explaining the operation | movement at the time of normal operation | movement in the differential transmission circuit. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 2 of this invention. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 3 of this invention. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 4 of this invention. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 5 of this invention. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 6 of this invention. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 7 of this invention. It is a figure which shows the electrical constitution of the differential transmission circuit which is Example 8 of this invention.

Explanation of symbols

10, 10 A, etc. Differential transmission circuit 12 Differential transmission circuit 14 Differential reception circuit 16 Tru signal line 18 Complement signal line 22 Resistance (part of voltage application means)
24 Resistance (part of voltage application means)
26 Resistance (part of voltage application means)
28 capacitor (the remainder of the voltage applying means, the first capacitive element)
30 capacitor (remaining voltage applying means, first capacitive element)

Claims (17)

The true signal output of the differential transmitter circuit is connected to the true signal input of the differential receiver circuit via the first signal line, and the complement signal output of the differential transmitter circuit is connected via the second signal line. A differential transmission circuit connected to a complement signal input of a differential reception circuit,
Voltage applying means for making the DC voltage of the true signal input higher than the DC voltage of the complement signal input when the signal line is not connected or lowering the DC voltage of the complement signal input than the DC voltage of the true signal input. The signal output provided between the output of the differential transmission circuit and the input of the differential reception circuit, and provided with the voltage applying means, and the signal output and the signal input opposite to the signal input A differential transmission circuit, wherein a first capacitive element is connected between the two.   The voltage applying means includes a first resistive element that connects the true signal output and a first voltage source having a voltage lower than a termination voltage of the differential receiving circuit, the first signal line, and the true signal. A second resistive element and a second capacitive element connected in parallel with the input; and a second voltage element connected between the true signal input and a second voltage source having a voltage higher than the termination voltage. 3, and the first resistive element, the second resistive element, and the second resistive element so that a voltage at a connection point between the second resistive element and the third resistive element becomes the termination voltage. Resistance values of a resistive element and a third resistive element are set, and the first capacitive element is connected between the second signal line and the complement signal input. The differential transmission circuit according to claim 1.   The differential transmission circuit according to claim 2, wherein the first voltage source is a ground potential, and the second voltage source is a driving voltage source of the differential receiving circuit.   A fourth resistive element is connected between the true signal input to which the third resistive element is connected and a third voltage source lower than a termination voltage of the differential receiving circuit; and 3. The resistance values of the first, second, third and fourth resistive elements are set so that the voltage at the connection point of the third and fourth resistors becomes the termination voltage. Or the differential transmission circuit of 3.   The differential transmission circuit according to claim 4, wherein the third voltage source is a ground potential.   The voltage applying means includes a fourth resistive element that connects the true signal output and a fourth voltage source having a voltage lower than a termination voltage of the differential receiving circuit, the true signal output, and the first signal. A fifth resistive element and a third capacitive element connected in parallel with each other, and a fifth voltage source connected between the true signal input and a fifth voltage source having a voltage higher than the termination voltage. The fourth resistive element, the fifth resistive element, and the fifth resistive element so that the voltage at the connection point between the fifth resistive element and the sixth resistive element becomes the termination voltage. Resistance values of a resistive element and a sixth resistive element are set, and the first capacitive element is connected between the complement signal output and the second signal line. The differential transmission circuit according to claim 1.   The differential transmission circuit according to claim 2, wherein the fourth voltage source is a ground potential, and the fifth voltage source is a driving voltage source of the differential receiving circuit.   A seventh resistive element is connected between the true signal input to which the sixth resistive element is connected and a sixth voltage source lower than a termination voltage of the differential receiving circuit; and The resistance values of the fourth, fifth, sixth and seventh resistive elements are set so that the voltage at the connection point of the sixth and seventh resistors becomes the termination voltage. Or the differential transmission circuit according to 7;   The differential transmission circuit according to claim 8, wherein the sixth voltage source is a ground potential.   The voltage applying means includes an eighth resistive element that connects the complement signal output and a seventh voltage source having a voltage higher than a termination voltage of the differential receiving circuit, the second signal line, and the second signal line. Between the ninth resistive element and the fourth capacitive element connected in parallel between the complement signal input and the complement signal input and the eighth voltage source having a voltage lower than the termination voltage. The tenth resistive element connected, and the eighth resistive element so that the voltage at the connection point between the ninth resistive element and the tenth resistive element becomes the termination voltage, The resistance values of the ninth resistive element and the tenth resistive element are set, and the first capacitive element is connected between the first signal line and the true signal input. The differential transmission circuit according to claim 1, wherein:   The differential transmission circuit according to claim 10, wherein the seventh voltage source is a drive voltage source for the differential transmission circuit, and the eighth voltage source is a ground potential.   An eleventh resistive element is connected between the complement signal input to which the ninth resistive element is connected and a ninth voltage source that is higher than the termination voltage of the differential receiving circuit; and 9. The resistance values of the eighth, ninth, tenth and eleventh resistive elements are set so that the voltage at the connection point of the ninth, tenth and eleventh resistors becomes the termination voltage. The differential transmission circuit according to 10 or 11.   13. The differential transmission circuit according to claim 12, wherein the ninth voltage source is a driving power source for the differential receiving circuit.   The voltage applying means includes: a twelfth resistive element that connects the complement signal output and a tenth voltage source having a voltage higher than a termination voltage of the differential receiving circuit; the complement signal output; A thirteenth resistive element and a fifth capacitive element connected in parallel between the two signal lines, and the complement signal input and an eleventh voltage source having a voltage lower than the termination voltage. A twelfth resistive element connected to the thirteenth resistive element so that a voltage at a connection point between the thirteenth resistive element and the fourteenth resistive element becomes the terminal voltage; The resistance values of the thirteenth resistive element and the fourteenth resistive element are set, and the first capacitive element is connected between the true signal output and the first signal line. The differential transmission circuit according to claim 1, wherein:   15. The differential transmission circuit according to claim 14, wherein the tenth voltage source is a driving voltage source for the differential transmission circuit, and the eleventh voltage source is a ground potential.   A fifteenth resistive element is connected between the complement signal input to which the fourteenth resistive element is connected and a twelfth voltage source having a voltage higher than the termination voltage, and the thirteenth, 16. The resistance values of the twelfth, thirteenth, fourteenth and fifteenth resistive elements are set so that the voltage at the connection point of the fourteenth and fifteenth resistors becomes the termination voltage. The differential transmission circuit as described.   The differential transmission circuit according to claim 16, wherein the twelfth voltage source is a driving power source of the differential receiving circuit.

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