JP2008053752A - Power semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power loss of a power semiconductor device. <P>SOLUTION: An IGBT51 is provided with: a low-concentration N-type silicon substrate 1; an N-type silicon layer 2 with an impurity concentration of about 10<SP>18</SP>/cm<SP>3</SP>which is formed in a region with a predetermined depth from a first main surface 1S1 of the silicon substrate 1; a high concentration P-type collector region 20 which is formed on the first main surface 1S1 and is made of SiGe; a collector electrode 6C which is formed on a surface opposite to the N-type silicon layer 2 in the collector region 20; a low-concentration P-type base region 7, an emitter region 8, and a high-concentration P-type silicon region 9 which are formed in regions with predetermined depths from a second main surface 1S2, respectively; a trench 30 which extends to an interior of an N-base region 1A from the second main surface 1S2 over a P-type base region 7; a gate electrode 10 which is filled within the trench 30; and a metal electrode 6G which is connected to the gate electrode 10. The collector junction consists of hetero-junction (P<SP>+</SP>-SiGe/N<SP>-</SP>-Si). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power semiconductor device (power device), and more particularly to a technique for reducing power consumption of a power semiconductor device.

  In general, a power device handles a large power supply voltage and a rated current, and thus generates a large amount of heat during operation. When such heat generation is large, cracks may occur in the semiconductor element (hereinafter also simply referred to as “element”) or chip or its package. Therefore, by suppressing power loss in the power device, the heat generation amount itself can be reduced. The entire package or system (module) is provided with a cooling means capable of handling (or more) the amount of heat generated by the element.

  Here, first, the power loss in the power device or the semiconductor element will be described.

  The power loss is defined by (1) a loss defined by an element resistance when the element is in an on state and a current flowing in the element, a leakage current when the element is in an off state, and a voltage applied to the element And (2) a switching loss corresponding to the current / voltage product in the transition period when the element changes from the on-state to the off-state or from the off-state to the on-state. There is.

  In general, steady loss and switching loss are in a trade-off relationship. For example, when the carrier concentration in the device is increased, the on-resistance of the device can be reduced, so that steady loss can be suppressed. On the other hand, a large amount of carriers must be charged and discharged during switching, resulting in increased switching loss. .

For example, in the operation by the two-level inverter method, the heat generation amount P0 due to steady loss and the heat generation amount P1 due to switching loss are respectively
P0 = A01 / Ion / Von + A00 / Ioff / Vcc (Formula 1)
P1 = (A11 · Eon + A10 · Eoff) · f (Formula 2)
It is expressed. Here, Vcc is the power supply voltage, Von is a voltage generated in the element due to the element resistance when the element is in the on state, Ion is a current flowing in the element when the element is in the on state, and Ioff is in the off state. Leakage current. Eon is a switching loss corresponding to the turn-on loss in the transition period when the element changes from the off state to the on state, and Eoff is a switching loss corresponding to the turn-off loss in the transition period when the element changes from the on state to the off state. It is a loss. A01, A00, A11, and A10 are coefficients corresponding to the sharing ratio of one cycle determined by the output waveform, and f is a switching frequency.

In the above formulas 1 and 2, for example, if Vcc = 3 kV, Von = 3.2 V, Ion = 2 kA, Ioff = 0 A, Eon = Eoff = 1 J, A00 = A01 = Al0 = A11 = 0.25, total heat generation The quantity P (W) is
P = P1 + P2 = 1600 + 0.5 × f (Formula 3)
As required.

  In particular, since the noise generated by the inverter becomes harder to hear by human ears as the frequency becomes higher, it is desirable to use an element that can operate at a higher frequency. However, as can be seen from Equation 3, the higher the frequency f, the higher the element. There is a problem that the total calorific value generated by the is increased.

  In response to such an increase in the amount of heat generated, it is necessary to increase the cooling capacity of the device package or the entire system (module). However, these cooling capacities have limitations that depend on the thermal resistance of the package material, base substrate material, etc. interposed between the heat sink side and the element, and as a result, in terms of the steady loss and switching loss of the element. Therefore, the maximum frequency that can be used in the power device is limited.

  On the other hand, as a measure for reducing the noise generated by the inverter, there is a three-level inverter method as a method for suppressing the waveform distortion in addition to the method of increasing the frequency described above. However, this method is not worthy of adoption because it causes another problem such as high cost and large size of the device due to doubling the number of elements used. I must.

  As described above, power devices that can achieve low power consumption (energy saving) and low noise (that is, high-frequency driving) that are in a trade-off relationship with each other, that is, steady loss and a trade-off relationship with each other. Development of a power device in which both switching losses are reduced is desired.

  Hereinafter, power devices developed for the purpose of reducing steady loss or switching loss will be described as first to fourth conventional technologies.

  FIG. 9 is a longitudinal sectional view schematically showing a main part of a diode according to the first prior art, and such a structure is proposed in Japanese Patent Laid-Open No. 6-326317.

  In FIG. 9, 101 is a low-concentration N-type silicon substrate, 103 is an anode region composed of a low-concentration P-type silicon layer employing a transmission emitter, 104 is a high-concentration P-type anode region, and 105 is a high-concentration N-type silicon layer. A cathode region. Further, 106A and 106K are metal electrodes (also referred to as “anode electrode 106A” and “cathode electrode 106K”, respectively) provided in the anode regions 103 and 104 and the cathode region 105, respectively.

  Next, FIG. 10 is a vertical cross-sectional view schematically showing a main part of an insulated gate bipolar transistor (hereinafter referred to as “IGBT”) having a transmissive emitter structure on the collector region 203 side according to the second prior art. This structure is proposed in Japanese Patent Laid-Open No. 6-326317.

In FIG. 10, 201 is a low-concentration N-type silicon substrate, 202 is an N-type silicon layer having an impurity concentration of about 10 ¹⁸ / cm ³ formed by diffusion near the back surface of the silicon substrate 201, and 203 is a transmissive emitter. A collector region made of a low-concentration P-type silicon layer, 204 a high-concentration P-type collector region, 207 a P-base region made of a low-concentration P-type silicon layer, 208 an emitter region made of high-concentration N-type silicon, and 209 A high concentration P region for making contact with the P base region, 210 is usually a gate electrode made of a high concentration N-type polycrystalline silicon film, and 211 is a gate insulating film. 206E, 206G, and 206C are metal electrodes provided in the emitter region 208, the gate electrode 210, and the collector regions 203 and 204, respectively (the metal electrodes 206E and 206C are also referred to as “emitter electrode 206E” and “collector electrode 206C”, respectively). It is.

  Here, as shown in FIG. 11 which is an energy band diagram in the I1-I2 line portion in FIG. 10 and FIG. 10, in the transmission type collector structure, the neutral region in the substrate 201 including the N-type silicon layer 202 is used. Electrons existing in (a region extending from the collector region 203 side end of the depletion layer extending from the emitter region 208 side in the substrates 201 and 202) to the collector region 203 “transmit” through the collector region 203, and the metal electrode 206C To reach. In the diode of FIG. 9, the substrate 101 and the low-concentration P-type silicon layer 103 constitute a transmissive emitter structure, and the operation thereof is the same as that of the IGBT of FIGS.

  Thus, according to the transmission type emitter structure, electrons injected from the anode side or the collector side pass through the anode region 103 or the collector region 203 and reach the anode electrode 106A or the collector electrode 206C. Alternatively, no electrons accumulate near the interface (junction) between the collector region 203 and the neutral region in the substrates 101, 201, 202. For this reason, since injection of holes at the time of turn-off is suppressed by such electrons, the anode current or the collector current can be quickly cut off. That is, according to the transmission type emitter structure, there is an effect that a high-speed and low-loss switching operation can be realized.

  In particular, such an effect becomes more prominent in the transmissive emitter structure as the impurity concentration of the low-concentration anode region 103 or the low-concentration collector region 203 is lower or the thicknesses of the regions 103 and 203 are thinner.

  Next, FIG. 12 is a diagram schematically showing a longitudinal section of a main part of a diode having a heterojunction according to the third prior art. Such a structure is described in IEEE Electron Device Letters, vol. 17 (12), P589 (1996), F Chen, BA Orner, D. Guerin, A. Khan, PR Berger, S. Ismat Shah, and J. It is proposed in a paper entitled “Current Transport Characteristics of SiGeC / Si Heterojunction Diode” by Kolodzey.

  In FIG. 12, 301 is an N-type silicon substrate, 312 is a P-type SiGeC region formed on the surface of the silicon substrate 301, and 306A and 306K are provided on the same side surface of the silicon substrate 301, respectively. It is the metal electrode which comprises an electrode.

  According to the diode having such a structure, the forward voltage drop Vf of the diode can be reduced by using a heterojunction of Si and SiGeC (having a smaller band gap than Si). Here, the forward voltage drop Vf is a voltage generated in an on-state element (diode), and is a physical quantity corresponding to the on-voltage Von in Equation 1 described above. Therefore, according to such a diode, the steady loss in the on state can be reduced.

  FIG. 13 is a diagram schematically showing a longitudinal section of an essential part of an NPN type hetero bipolar transistor (HBT) using a heterojunction according to the fourth prior art. This structure is described in IEEE Transaction on Electron Devices, ED-37, P2331 (1990), "Si Hetero-Bipolar Transistor with a Fluorine-Doped SiC Emitter and Thin, Highly Doped Epitaxial Base" by T. Sugii et al. It is proposed in the title paper.

  In FIG. 13, 401 is a high-concentration N-type silicon substrate, 413 is a low-concentration N-type silicon layer formed by the epitaxial growth method on the surface of the silicon substrate 401, 417 is a first insulating film, and 418 is a refractory metal. Alternatively, the silicide film 414 is a base region (P base layer) made of a P-type silicon layer formed by an epitaxial growth method. The base region 414 has crystallinity close to a single crystal on and near the low-concentration N-type silicon layer 413, and has polycrystalline crystallinity in other portions.

  Further, in FIG. 13, reference numeral 415 denotes an emitter region made of N-type silicon carbide (SiC), and 416 denotes N-type polycrystalline silicon. Reference numeral 419 denotes a second insulating film made of, for example, a silicon oxide film. The second insulating layer 419 is provided for bonding only the above-described single crystal region in the emitter region 415 made of SiC and the base region 414 through the opening. 406E, 406B, and 406C are metal electrodes provided on the emitter region 415, the base region 414, and the collector region 401, respectively.

  In general, in a bipolar transistor, the operation speed can be increased by narrowing the base layer (corresponding to the P base layer 414 in FIG. 13). However, if the P base layer is narrowed, punch-through is likely to occur. Therefore, it is necessary to increase the concentration of the P base layer. However, when the concentration of the P base layer is increased, the efficiency of electron injection from the emitter region is lowered, and the grounded emitter current amplification factor hfe is lowered.

  On the other hand, in the HBT of FIG. 13, since the injection of minority carriers (holes) from the base region to the emitter region can be suppressed, the concentration of the base region is increased while keeping the injection efficiency of electrons into the emitter region high. There is an advantage that you can.

  As the structure of the HBT, in addition to the structure using a wide band gap material such as SiC as described above in the emitter region, GLPatton et al. Described in, for example, Technical Digest of 1990 Symposium on VLSI Technology, p49 (1990). Has a structure using a narrow bandgap material in the base region, which was announced as "63-75GHz fT SiGe-Base Heterojunction Bipolar Technology".

JP-A-7-193232 JP-A-8-37294 JP-A-6-326317

  As described above, the power device according to each of the first and second prior arts includes the transmissive emitter structure on the anode region 103 side and the cathode 203 side, and thereby, the power source from the anode region 103 or the collector region 203 is provided. It is intended to suppress the hole injection to increase the switching operation speed and reduce the loss at turn-off. However, the power devices according to the first and second prior arts have the following problems.

  First, in order to fully exhibit the above-described effects due to the transmission-type emitter structure in each power device of FIGS. 9 and 10, the impurity concentration of the low-concentration anode region 103 or the low-concentration collector region 203 is set as low as possible. Alternatively, it is necessary to form the regions 103 and 203 as thin as possible. However, in a device satisfying such manufacturing conditions, it is difficult to form a good ohmic contact between the metal forming the anode electrode 106A or the collector electrode 206C and the low concentration anode region 103 or the low concentration collector region 203. There is a problem that there is.

  Furthermore, due to the current manufacturing process in which a thick substrate wafer (for example, 500 μm to 600 μm) is used, there are the following problems.

  First, for example, in the case of an element (power device) with a breakdown voltage of 2000 V or less, a predetermined breakdown voltage level is defined by the thickness of the low-concentration N-type semiconductor layers 101, 201, and 202. In order to suppress power loss and reduce power loss (steady loss), it is necessary to reduce a voltage drop in portions other than the N-type semiconductor layers 101, 201, and 202. For this reason, it is necessary to set the impurity concentration of the anode region and the cathode region high.

  However, when an element is manufactured using a thick substrate wafer, the thickness of the anode region and the collector region corresponding to portions other than the low-concentration N-type semiconductor layers 101, 201, and 202 must be thick (deep). Therefore, the anode region 103 or the collector region 203 of the above-described transmission-type emitter structure, which is required to be as thin and thin as possible, cannot be applied to such a power device. That is, it is considered that a power device having such a withstand voltage level cannot realize a reduction in switching loss of the element by the transmission type emitter structure described above.

  If a very low concentration deep collector region (for example, a thickness exceeding 100 μm) is formed using a thick substrate wafer as a base material, a voltage drop due to resistance in the collector region is large. As a result, the power loss (steady loss) of the element increases.

  Further, when the above-described transmissive emitter structure having a low impurity concentration and a thin anode region or collector region is formed by using a thick substrate wafer as a non-punch through type element, a low concentration N-type semiconductor layer is formed. Will be thicker than necessary. For this reason, the performance (power loss, etc.) of the element is significantly reduced.

  To deal with these problems, for example, a countermeasure may be considered in which an element is manufactured using a thin substrate wafer having a thickness of 100 μm. However, in such a thin substrate wafer, the wafer is likely to be warped or cracked. There are problems. Furthermore, when the device is manufactured using the above thin substrate wafer with respect to the mass production apparatus of the current general specification, there arises a problem that a new investment is required.

  On the other hand, a manufacturing method in which an element is manufactured up to a predetermined manufacturing process using a thick substrate wafer, and then the substrate wafer is polished and thinned is also conceivable. However, this method fundamentally causes warpage and cracking of the substrate wafer. This is not a production method that can be suppressed, and causes another problem that the cost increases as the polishing process increases.

  Next, in the diode shown in FIG. 9, a forward current flows when the PN junction formed by the anode region 103 and the substrate 101 is forward-biased. At this time, a voltage drop of about 0.6 V occurs due to the difference in work function between the P-type Si forming the anode region 103 and the N-type Si forming the substrate 103. That is, since this voltage drop is a part of the voltage (ON voltage) generated in the entire diode in the ON state, there is a problem that steady loss occurs due to the voltage drop at the PN junction portion. is there. This also applies to the collector junction (P-type Si203 / N-type Si202) in the IGBT of FIG. 10 in the on state.

  Next, as a means for controlling (homogenizing) the carrier distribution in the vicinity of the PN junction in the ON state, there is a generally performed means for suppressing generation / injection of holes at the junction by lifetime control.

  However, since the hole density in the region near the PN junction is reduced by lifetime control, the voltage drop in such a region becomes larger than that in the case where lifetime control is not performed, and the steady loss increases. There is. (As described above, a loss corresponding to the voltage drop caused by the work function difference occurs in the PN junction portion).

  The present invention is intended to solve the above-described problems and further reduce the loss or total heat quantity of the power semiconductor device. To achieve this main purpose, the following more detailed sub-objects are provided. Have.

  First, a first object of the present invention is to provide a power semiconductor device having a transmissive emitter structure that can be formed by an existing manufacturing process, thereby reducing switching loss.

  It is a second object of the present invention to provide a power semiconductor device in which a voltage drop in an on-state element or a voltage required to turn on a PN junction is reduced, thereby reducing a steady loss. To do.

  A power semiconductor device according to the subject of the present invention includes a semiconductor, a first electrode provided on the first main surface side of the semiconductor, and a second main surface side opposite to the first main surface. A power semiconductor device having a main current path between the first electrode and the second electrode, the semiconductor being in contact with the first electrode and having a first current path A first semiconductor layer having a first conductivity type layer and at least a portion in contact with the first electrode, and a second portion of the main current path in contact with the first semiconductor layer. A second band-type second semiconductor layer; a third semiconductor layer sandwiched between the second semiconductor layer and the second electrode; and a first band gap of a semiconductor material forming the first semiconductor layer and the first semiconductor layer Different from the second band gap of the semiconductor material forming the two semiconductor layers, Gap is greater than said second band gap, wherein the first semiconductor layer is characterized by a semiconductor material effective density of states is larger than the second semiconductor layer.

  Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

  According to the subject of the present invention, the first band gap is larger than the second band gap, and the first semiconductor layer is made of a semiconductor material having a large effective state density, so that the first semiconductor layer and the second semiconductor layer In the formed junction, the height of the barrier against the second conductivity type is increased. For this reason, the second conductivity type carriers injected from the second semiconductor layer side are accumulated in the vicinity of the junction. As a result, since it becomes possible to inject carriers of the first conductivity type from the first semiconductor layer more efficiently, the voltage drop (on voltage) in the power semiconductor device in the on state can be reduced, Compared with an IGBT having the same amount of switching loss, the steady loss of the entire device can be reduced.

  In particular, since the first semiconductor layer is made of a semiconductor material having a large effective state density, it is possible to reduce the height of the barrier against the first conductivity type carrier at the junction. Therefore, since the applied voltage required to turn on the junction is reduced, the steady loss of the entire device can be reduced as compared with a conventional power semiconductor device having the same amount of switching loss.

  In the following description of the first to fourth embodiments, an IGBT (insulated gate bipolar transistor) having a trench gate structure will be described as an example of a power semiconductor device.

(Embodiment 1)
FIG. 1 is a longitudinal sectional view schematically showing a longitudinal section of a main part of the IGBT 51 according to the first embodiment. Below, the structure of this IGBT51 is demonstrated using FIG.

  The IGBT 51 is a low-concentration N-type silicon substrate 1 (hereinafter referred to as “(silicon) substrate”) containing an N-type (second conductivity type) impurity, for example, arsenic (As) or phosphorus (P), based on a silicon wafer. 1 ”).

An N-type silicon layer (second semiconductor) having an impurity concentration of about 10 ¹⁸ / cm ³ is formed in a region having a predetermined depth from the first main surface 1S1 over the entire first main surface 1S1 of the silicon substrate 1. Layer) 2 is formed by diffusion.

  Further, a semiconductor whose band gap E20 (see FIG. 2 to be described later) is smaller than the band gap E2 (see FIG. 2) of silicon (Si) forming the N-type silicon layer 2 over the first main surface 1S1. A high-concentration P-type collector region (first semiconductor layer) having a material (for example, SiGe, Ge, etc .; here, SiGe is used) as a base material and having a P-type (first conductivity type) impurity, for example, boron (B). 20 (hereinafter also simply referred to as “collector region 20”) is formed with a predetermined film thickness.

  In particular, in the relationship between the two semiconductor layers 2 and 20 that are bonded to each other to form a heterojunction, when a predetermined impurity concentration is set in both semiconductor layers, the work functions are comparable to each other. The work function of the semiconductor material forming the collector region 20 is selected or set. In other words, the semiconductor material constituting the collector region 20 is selected so that the change in the energy band at the heterojunction surface is moderated and a tunnel barrier peculiar to the heterojunction portion cannot be formed, and various conditions such as the impurity concentration are selected. Set. For this reason, the band offset is not shown in the energy band diagram shown in FIG. This also applies to IGBTs 52 to 54 according to Embodiments 2 to 4 described later.

  A metal electrode (first electrode) 6C (hereinafter also referred to as “collector electrode 6C”) is formed on the entire surface of the collector region 20 opposite to the N-type silicon layer 2.

  On the other hand, over the entire surface of the second main surface 1S2 opposite to the first main surface 1S1 of the silicon substrate 1, a relatively low concentration of P in the region having a predetermined depth from the second main surface 1S2. A silicon layer 7 having a type impurity (hereinafter also referred to as “P base region 7”) is formed. In the following description, the second main surface 1S2 is also expressed as “second main surface 1S2 of the P base region 7”, and the P base in the silicon substrate 1 corresponds to the P base region 7. A region sandwiched between the region 7 and the N-type silicon layer 2 is particularly referred to as “N base region 1A”.

Further, a plurality of portions of the substrate 1 are drilled from a predetermined position in the second main surface 1S2 toward the inside of the silicon substrate 1, whereby the silicon substrate 1 or N is formed beyond the P base region 7. A trench 30 reaching the inside of the base region 1A is formed. Then, on the bottom surface 30B of each trench 30 and the wall surface or side surface 30W of the trench 30 surrounding the bottom surface 30B, further on the second main surface 1S2 of the silicon substrate 1 or the second main surface 8S2 of the emitter region 8 described later. A gate oxide film (hereinafter also simply referred to as “oxide film”) 11 made of a silicon oxide film (SiO ₂ ) is formed on the entire surface in the vicinity of the opening corresponding to the entrance of the trench 30.

  Further, a part of the corner 30C of the P base region 7 near the entrance of each trench 30, that is, from the second main surface 1S2 of the P base region 7 to the inside thereof, and along the wall surface 30W of the trench 30, An emitter region 8 made of N-type silicon having a high concentration of N-type impurities is formed. In the following description, a portion of the second main surface 1S2 where the emitter region 8 is formed in the depth direction is referred to as “second main surface 8S2 of the emitter region”.

  The trench 30 is filled with, for example, high impurity concentration N-type polycrystalline silicon so as to be in contact with the wall surface 30W, and above the trench 30 and on the second main surface 8S2 of the emitter region 8. The N-type polycrystalline silicon is continuously formed on the surface of the silicon oxide film forming a part of the oxide film 11 formed in the above. The polycrystalline silicon forms the gate electrode 10 of the present IGBT. Furthermore, a metal electrode 6G is formed on the surface of the portion of the gate electrode 10 that protrudes outward from the second main surface 1S2.

  Further, the P base region 7 and an emitter electrode (second electrode described later) are disposed adjacent to the emitter region 8 within a predetermined depth from the second main surface 1S2 of the silicon substrate 1 or the P base region 7. ) A P-type silicon region 9 which is a high-concentration impurity region for making contact with 6E is formed. In the following description, the portion of the second main surface 1S2 of the silicon substrate 1 where the P-type silicon region 9 is formed in the depth direction is referred to as “the second main surface 9S2 of the P-type silicon region 9”. "

  The entire surface of the second main surface 9S2 of the P-type silicon region 9 and the vicinity of the portion of the second main surface 8S2 of the emitter region 8 adjacent to the second main surface 9S2 (however, the gate electrode A metal electrode (second electrode) 6E (hereinafter also referred to as “emitter electrode 6E”) is formed (so as not to contact 10). A portion from the surface of the N base layer 1A on the collector region 20 side to the second main surface 1S2 is referred to as a “third semiconductor layer”.

  The IGBT 51 having the above structure is a power semiconductor device having a main current path between the emitter electrode 6E and the collector electrode 6C.

  According to the present IGBT 51, the following effects can be obtained. 2 is an energy band diagram along the line A1-A2 in FIG. 1. In FIG. 2, “e” represents an electron and “h” represents a hole. This also applies to the energy band diagrams of FIGS. 4, 6, and 8, which will be described later.

First, as shown in FIG. 2, since high-concentration P-type SiGe is used as the material of the collector region 20, the height of the barrier against electrons at the collector junction (P ⁺ -SiGe / N ⁻ -Si junction) is increased. It can be made lower than before. Therefore, during the operation, a neutral region in the silicon substrate 1 (a region extending from the end of the depletion layer formed in the N base layer 1A and the N-type silicon layer 2 on the collector region 20 side to the collector region 20). ) Exist in the vicinity of the PN junction, pass through the collector region 20 and reach the collector electrode 6C. That is, according to the structure of the present IGBT 51, an IGBT having a transmissive emitter structure can be realized. For this reason, the effect (collector short-circuit effect) resulting from the transmissive emitter structure can be obtained.

  Therefore, according to the present IGBT 51, the driving speed of the element can be increased, so that the switching loss can be reduced as compared with the IGBT having the same steady loss amount. That is, the total power loss or total heat amount as the IGBT can be reduced.

  As described above, the steady loss and switching loss that give the total power loss of the IGBT are in a trade-off relationship. For example, the loss amount of both can be adjusted by controlling the impurity concentration of the N base layer 1A. Is possible. For this reason, by appropriately setting the impurity concentration and film thickness of each layer in the IGBT 51, the performance of the IGBT can be designed flexibly in accordance with the environment and purpose of use. For example, in an environment where high-speed operation is not required, the above-described switching loss reduced in the present IGBT 51 can be utilized for reducing steady loss. This also applies to IGBTs 52, 53, and 54 according to Embodiments 2 to 4 described later.

Further, since the concentration of the collector region 20 (P ⁺ -SiGe) is high, the collector electrode 6C and the collector region 20 are formed even when the thick (deep) collector region 20 having a depth exceeding 100 μm is formed. The ohmic contact between the two can be easily and reliably formed. For this reason, the voltage drop in the said junction part can be made small.

  On the other hand, even when the thick (deep) collector region 20 as described above is formed due to the high impurity concentration in the collector region 20, a voltage drop in the region 20 can be suppressed.

  Furthermore, according to the present IGBT 51, the performance (loss) generated when a device is manufactured using a thick substrate wafer like a conventional non-punch-through IGBT can be effectively avoided, so that a thick substrate wafer is used. In addition, there is an advantage that a high-performance IGBT that can exhibit the effect (collector short-circuit effect) of the transmissive emitter structure can be easily manufactured by using the conventional manufacturing apparatus and manufacturing method as they are.

  Further, according to the above-described paper relating to the third prior art (IEEE Electron Device Letters, vol. 17 (12), p589 (1996)), the IGBT 51 has a smaller band gap than N-type Si and Si. A heterojunction formed with a P-type semiconductor material (or a small work function difference) has an effect of reducing the applied bias necessary to turn on the collector-side PN junction (collector junction).

  Here, as a power semiconductor device having a heterojunction in the main current path, there is a structure proposed in JP-A-5-347406. Such a structure has a structure in which two P-type SiGe layers having different composition ratios are inserted into a PN junction formed of the same kind of semiconductor material (Si). The main current path has a laminated structure composed of type Si / P type Si / P type SiGe / P type Si / metal electrodes. On the other hand, in the present IGBT 51, the P-type SiGe forming the heterojunction of P-type SiGe / N-type Si constitutes the entire collector region 20, and the collector region 20 is directly connected to the collector electrode 6C. Is different from the structure disclosed in the above publication.

  In particular, in the present IGBT 51, electrons that have passed through the PN junction and reached the collector region 20 can reach the collector electrode 6 </ b> C without any barrier in the region 20. Compared to the power semiconductor device having the structure described above, it is considered that the electron transmittance is high, and thus the above-described effects can be obtained with certainty.

  In the above description, the silicon substrate (semiconductor substrate) 1 constituting a part of the IGBT 51 has the emitter electrode 6E from the surface (first main surface 1S1) on the collector region 20 side of the N-type silicon layer 2 in FIG. However, the shape of the silicon substrate is not limited to this. For example, from the surface of the N-type silicon layer 2 in FIG. 1 on the collector region 20 side (the first main surface 1S1) to the surface of the N base region 1A on the emitter electrode 6E side (corresponding to the second main surface 1S2). Alternatively, a silicon substrate on which an extended portion is formed may be prepared, and a layer forming the P base region 7 may be laminated on the surface of the N base region 1A on the emitter electrode 6E side. Alternatively, a P-type SiGe substrate forming the collector region 20 may be prepared, and a silicon film forming each layer 1, 2, 7, etc. may be laminated on one surface (corresponding to the second main surface).

(Embodiment 2)
Next, the structure of the IGBT 52 according to the second embodiment will be described using the longitudinal sectional view of FIG. In FIG. 3 and the following description, the same components as those of the IGBT 51 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. This also applies to Embodiments 3 and 4 described later.

  The IGBT 52 is a P-type semiconductor material (here, a band gap) having a larger band gap than the Si band gap E2 (see FIG. 4 to be described later) of the substrate 1 over the first main surface 1S1 of the silicon substrate 1. A collector region 21 (hereinafter also referred to as “SiC layer 21”) made of E21 (> E2 SiC) is formed. A metal electrode or a collector electrode 6C is formed on the entire surface of the SiC layer 21 opposite to the N-type silicon layer 2 over the entire surface.

  According to the IGBT 52 having such a structure, as shown in FIG. 4 which is an energy band diagram along the B1-B2 line in FIG. 3, the height of the barrier against electrons is high in the PN junction (P-type SiC / N-type Si junction). These electrons are accumulated in the vicinity of the PN junction. For this reason, holes can be more efficiently injected from the collector region 21 side, so that the voltage drop (on voltage) in the on-state element can be lowered, thereby reducing the steady loss. it can.

  In particular, when a semiconductor material having a larger band gap than Si and a larger effective state density is used for the collector region 21, as shown in FIG. 4, the height of the barrier against holes in the PN junction is also lowered. Can do. In such a case, the collector voltage required to turn on the collector region 21 of the PN junction can be reduced, so that power loss (steady loss) at the junction can be suppressed.

  Therefore, according to the present IGBT 52, it is possible to reduce the steady loss as the whole element as compared with the IGBT having the same switching loss amount. That is, the total power loss or total heat amount as the IGBT can be reduced.

  Here, as a semiconductor device having a heterojunction formed of Si and SiC in the main current path, there is a structure proposed in Japanese Unexamined Patent Publication No. 2-3393. Such a semiconductor device is a bipolar transistor comprising three layers of N-type β-SiC (collector) / P-type Si (base) / N-type Si (emitter), and the N-type β-SiC forming the collector is coupled to the collector electrode. ing.

  However, a collector electrode (first electrode) 6C is formed on the first main surface 1S1 side of the silicon substrate (semiconductor substrate), and an emitter electrode (second electrode) 6E (and gate electrode 6G) is formed on the second main surface 1S2 side. Compared to the present IGBT 52, the bipolar transistor described above is different in structure in that all of the collector electrode, the emitter electrode, and the base electrode are formed on one surface of the semiconductor substrate.

  Furthermore, in the present IGBT 52, the band gap is larger than that of Si. From the viewpoint of a semiconductor material that can increase the height of the barrier against electrons and reduce the height of the barrier against holes in a heterojunction with N-type Si. On the other hand, in the bipolar transistor proposed in the above publication, SiC is selected from the viewpoint of a semiconductor material having a saturation rate and a dielectric constant larger than that of Si. As described above, since the point of focus for selecting SiC is fundamentally different between the IGBT 52 and the bipolar transistor, it can be said that the structure according to the publication cannot be the beginning of the IGBT 52.

  In particular, due to the difference in structure, the IGBT 52 has an advantage that it can handle a higher voltage and a larger current than the bipolar transistor disclosed in the above publication.

(Embodiment 3)
Next, the structure of the IGBT 53 according to the third embodiment will be described using the longitudinal sectional view of FIG.

  This IGBT 53 has a bandgap smaller than the Si band gap E2 (see FIG. 6 described later) forming the substrate 1 over the first main surface 1S1 of the silicon substrate 1, and a low-concentration N-type semiconductor ( For example, a low-concentration N-type region 20N (hereinafter, also referred to as “N-type SiGe layer 20N”) formed of SiGe, Ge, etc., here using N-type SiGe having a band gap E20N (<E2) is formed. Further, on the entire surface of the N-type SiGe layer 20N opposite to the N-type silicon layer 2, the band gap is smaller than that of Si forming the substrate 1 and a high-concentration P-type semiconductor (for example, SiGe or Ge Here, a high-concentration P-type collector region 20P (hereinafter referred to as a “P-type SiGe layer 20P”) composed of a band gap E20P (= P20 type SiGe with E20N <E2) is used. Hereinafter) is formed. A metal electrode or a collector electrode 6C is formed on the entire surface of the P-type SiGe layer 20P opposite to the N-type SiGe layer 20N.

  According to the IGBT 53 having such a structure, a collector junction (PN junction) is formed by P-type SiGe and N-type SiGe, both of which have a smaller band gap than Si. Therefore, in the energy band diagram of the C1-C2 line in FIG. As shown in FIG. 6, the height of the barrier in the PN junction can be reduced with respect to both electrons and holes. Accordingly, the collector junction can be turned on (modulated) with a low bias, and as a result, the loss (steady loss) at the junction is suppressed more than the P-type Si / N-type Si junction. be able to. At this time, since there is a voltage drop at the hetero junction (N-type Si / N-type SiGe junction), the collector voltage itself required for forward biasing the entire collector region may not be so small.

  In particular, in the present IGBT 53, the height of the barrier against electrons in the collector junction (P-type SiGe / N-type SiGe) is low, and thus this portion constitutes the same transmissive emitter structure as that of the IGBT 51 described above. Therefore, according to the present IGBT 54, the switching loss can be reduced similarly to the IGBT 51.

  Further, a heterojunction (N-type Si / N-type SiGe) or N-type SiGe layer 20N in which holes are injected from the P-type SiGe layer 20P to increase the hole density can be formed at a position closer to the emitter side. Therefore, at the time of turn-off, holes accumulated in the heterojunction portion or the N-type SiGe layer 20N can be quickly moved to the emitter side. As a result, the IGBT can be driven at high speed, and the switching loss can be reduced as compared with the IGBT having the same steady loss amount. That is, the total power loss or total heat amount as the IGBT can be reduced.

(Embodiment 4)
Next, the structure of the IGBT 54 according to the fourth embodiment will be described using the longitudinal sectional view of FIG.

  The IGBT 54 is entirely formed on the first main surface 1S1 of the silicon substrate 1 with a low-concentration P-type collector region 22 (hereinafter referred to as “P-type Si”) made of a low-impurity concentration P-type semiconductor material (here, P-type Si is used). P-type silicon layer 22 ") is also formed. In particular, in the present IGBT 54, any bandgap E22 (see FIG. 8 described later) of a semiconductor material forming the low-concentration P-type collector region 22 may be arbitrary.

  Then, on the surface of the P-type silicon layer 22 opposite to the N-type silicon layer 2, a metal electrode or collector made of a metal whose work function is much higher (higher) than Si, such as platinum. An electrode 6Ch is formed.

  Since the work function of the metal forming the collector electrode 6Ch is large in the present IGBT 54, as shown in FIG. 8 which is an energy band diagram in the D1-D2 line in FIG. 7, the low concentration P-type collector region 22 and the N-type silicon layer 2 The energy band edge on the P-type collector region 22 side is bent at the collector junction and the junction (interface) between the P-type collector region 22 and the collector electrode 6Ch. In particular, in the present IGBT 54, the film thickness of the P-type collector region 22 is set to be thinner than that of the other embodiments in order to bend the energy band edge greatly. For this reason, since the height of the barrier with respect to the hole in this interface can be made small, the collector voltage required in order to make a collector junction into an ON state can be reduced. Therefore, loss (steady loss) at the collector junction can be suppressed. That is, the total power loss or total heat amount as the IGBT can be reduced.

  As described above, according to the IGBTs 51, 52, 53, and 54 according to the first to fourth embodiments, either the steady loss P0 or the switching loss P1 can be reliably reduced. Therefore, as compared with the power devices according to the first to fourth prior arts, the total amount of heat (= steady loss + switching loss) generated by each of the IGBTs 51 to 54 can be greatly reduced. Of course, the above-described effects can be obtained even in an element in which the conductivity types of the semiconductor materials in the respective IGBTs 51 to 54 are all opposite to each other.

  In particular, the structure from the first main surface 1S1 to the collector electrodes 6C and 6Ch proposed in the first to fourth embodiments can be applied to other power semiconductor devices such as diodes, thyristors, and bipolar elements, for example. In such a case, the same effect can be obtained.

(Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

1 is a longitudinal sectional view of a main part of a power semiconductor device according to a first embodiment. 3 is a schematic energy band diagram in the vicinity of a collector region of the power semiconductor device according to the first embodiment. FIG. FIG. 5 is a longitudinal sectional view of a main part of a power semiconductor device according to a second embodiment. FIG. 6 is a schematic energy band diagram in the vicinity of a collector region of a power semiconductor device according to a second embodiment. FIG. 6 is a longitudinal sectional view of a main part of a power semiconductor device according to a third embodiment. FIG. 10 is a schematic energy band diagram in the vicinity of a collector region of a power semiconductor device according to a third embodiment. FIG. 6 is a longitudinal sectional view of a main part of a power semiconductor device according to a fourth embodiment. FIG. 6 is a schematic energy band diagram in the vicinity of a collector region of a power semiconductor device according to a fourth embodiment. It is a longitudinal cross-sectional view of the principal part of the power semiconductor device which concerns on a 1st prior art. It is a longitudinal cross-sectional view of the principal part of the power semiconductor device which concerns on a 2nd prior art. It is a typical energy band figure of the collector region vicinity of the power semiconductor device which concerns on a 2nd prior art. It is a longitudinal cross-sectional view of the principal part of the power semiconductor device which concerns on a 3rd prior art. It is a longitudinal cross-sectional view of the principal part of the power semiconductor device which concerns on a 4th prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1, 1A, 2, 7, 8, 9, 20, 21, 20N, 20P, 22 Semiconductor, 1A N base area | region (3rd semiconductor layer), 1S1 1st main surface, 1S2 2nd main surface, 2 N-type silicon layer (second semiconductor layer), 6C, 6Ch collector electrode (first electrode), 6E emitter electrode (second electrode), 7P base region (third semiconductor layer), 8 emitter region (third semiconductor) Layer), 9 P-type silicon region (third semiconductor layer), 20, 21, 20P, 22 Collector region (first semiconductor layer), 20N N-type SiGe layer (fourth semiconductor layer), 51, 52, 53, 54 IGBT, E2 band gap (second band gap), E20, E20P, E20N, E21, E22 band gap (first band gap).

Claims (1)

Semiconductors,
A first electrode provided on the first main surface side of the semiconductor;
A second electrode provided on the second main surface side opposite to the first main surface,
A power semiconductor device having a main current path between the first electrode and the second electrode,
The semiconductor is
A first semiconductor layer that is in contact with the first electrode and forms a first portion of the main current path, and at least a portion in contact with the first electrode includes a first conductivity type layer;
A second semiconductor layer of a second conductivity type in contact with the first semiconductor layer and forming a second portion of the main current path;
A third semiconductor layer sandwiched between the second semiconductor layer and the second electrode;
A first band gap of the semiconductor material forming the first semiconductor layer is different from a second band gap of the semiconductor material forming the second semiconductor layer;
The first band gap is larger than the second band gap;
The first semiconductor layer is made of a semiconductor material having an effective density of states larger than that of the second semiconductor layer.
Power semiconductor device.

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