CN102544076A - Resistive random access memory gated by bipolar transistor, array and manufacturing method of array - Google Patents
Resistive random access memory gated by bipolar transistor, array and manufacturing method of array Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 52
- 230000015654 memory Effects 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 238000013459 approach Methods 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 7
- 239000002346 layers by function Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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Abstract
The invention discloses a bipolar transistor with multiple emitters, a resistance random access memory gated by the bipolar transistor and a manufacturing method of the resistance random access memory, wherein the transistor comprises: a collector electrode; a base formed on the collector; at least two emitters formed on the base electrode, wherein the emitters are arranged at intervals; wherein the base is common to all of the emitters and the collector is common to all of the emitters. The multiple emitters of the bipolar transistor share the base electrode and the collector electrode, so that the area of the bipolar transistor is reduced, and the resistive random access memory gated by the bipolar transistor with the multiple emitters reduces the area of the gated transistor, so that the storage density of the resistive random access memory is improved.
Description
Technical field
The present invention relates to the semiconductor memory technologies field, particularly a kind of resistance-variable storing device of bipolar transistor gating and manufacturing approach thereof.
Background technology
Resistance-variable storing device (RRAM) since have write operation voltage low, write short, advantage such as the retention time long, non-destructive reads, many-valued storage, simple in structure and required area are little of erasing time; Therefore become the research emphasis in the present novel non-volatility memorizer spare gradually, and the storage density that how to improve resistance-variable storing device important direction especially.
RRAM mainly comprises the resistance-variable storing device of MOS (metal oxide semiconductor) transistor selection and the resistance-variable storing device of bipolar transistor (BJT) gating; And the transistorized area of gating is an aspect of decision memory cell area; Because the area of bipolar transistor (BJT) is less than field-effect transistor (MOSFET); Therefore replacing MOSFET gating memory cell with bipolar transistor also is a kind of effective way of the RRAM of raising storage density; As shown in Figure 1; Be the resistance variation memory structure sketch map of positive-negative-positive bipolar transistor selection, base stage 102 is electrically connected the resistance-variable storing device 104 that comprises upper/lower electrode and change resistance layer on emitter 103 between collector electrode 101 and emitter 103.But, be necessary to propose to have the more resistance-variable storing device and the manufacturing approach thereof of the bipolar transistor gating of high storage density in order better to improve the RRAM storage density.
Summary of the invention
In order to address the above problem, the invention provides a kind of bipolar transistor of multi-emitter, said transistor comprises: collector electrode; Be formed at the base stage on the said collector electrode; Be formed at least two emitters on the said base stage, said emitter is spaced; Wherein, said base stage is the total base stage of all said emitters, and said collector electrode is the total collector electrode of all said emitters.
According to a further aspect in the invention, the invention allows for the resistance-variable storing device unit based on the bipolar transistor gating of above-mentioned multimitter pmultiple emitter transistor, said resistance-change memory unit comprises: collector electrode; Be formed at the base stage on the said collector electrode; Be formed at least two emitters on the said base stage, said emitter is separated by insulating barrier; Be formed at the resistance-variable storing device on each said emitter; Wherein, said base stage is the total base stage of all said emitters, and said collector electrode is the total collector electrode of all said emitters.
In addition; The present invention also provides the resistance-variable storing device array of the bipolar transistor gating that forms according to said memory cells; The resistance-variable storing device unit that comprises a plurality of above-mentioned bipolar transistor gatings; The resistance-variable storing device unit of wherein said bipolar transistor gating is arranged in parallel and has common collector electrode, and base stage and emitter between each said resistance-variable storing device unit are isolated by second insulating barrier.
In addition, the present invention also provides the manufacturing approach that forms above-mentioned resistance-variable storing device unit, and said method comprises: A, the Semiconductor substrate with first doping type is provided; B, on said Semiconductor substrate, form and have first heavily doped layer that second type is mixed; C, on said first heavily doped layer, form second heavily doped layer, and said second heavily doped layer is divided at least two emitters with insulating barrier, and on each said emitter, form resistance-variable storing device with first doping type; Wherein the Semiconductor substrate of first doping type is a collector electrode, and first heavily doped layer that second type is mixed is a base stage, and said base stage is the total base stage of all said emitters, and said collector electrode is the total collector electrode of all said emitters.
Bipolar transistor according to multi-emitter of the present invention; Because a plurality of emitter common bases and collector electrode; Thereby reduce the area of bipolar transistor; And adopt the resistance-variable storing device of the bipolar transistor gating of this multi-emitter, owing to reduced the area of gate transistor, and then improved the storage density of resistance-variable storing device.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 shows the structural representation of the resistance-variable storing device of bipolar transistor selection;
Fig. 2 shows the structural representation according to the bipolar transistor of the multi-emitter of the embodiment of the invention;
Fig. 3-Figure 15 shows the sketch map according to each fabrication stage of resistance-variable storing device of the bipolar transistor gating of the embodiment of the invention.
Embodiment
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
With reference to figure 2; Fig. 2 shows the structural representation according to the bipolar transistor of the multi-emitter of the embodiment of the invention; The bipolar transistor of said multi-emitter comprises: collector electrode 11, and said collector electrode comprises the doping of the first kind, the said first kind is doped to the N type or the P type mixes; Be formed at the base stage 12 on the said collector electrode 11, said base stage 12 has the doping of second type, opposite types doping each other that said second type is mixed and the first kind is mixed; Be formed at least two emitters 14 on the said base stage 12, said emitter 14 is spaced; Wherein, said base stage 12 is total base stages of all said emitters 14, and said collector electrode 11 is total collector electrodes of all said emitters 14, thereby has constituted the bipolar transistor structure that a plurality of emitters have a collector electrode and base stage.
Further, also comprise the base lead 18 that is formed on the said base stage 12, be formed at the emitter terminal 22 on the emitter 14, and be formed at the metal level 23 on said base lead 18 and the emitter terminal 22.
The bipolar transistor structure of said multi-emitter has higher integration, littler area, is applied in the resistance-variable storing device, can effectively reduce the area of gate transistor, thereby improves the storage density of resistance-variable storing device.With reference to Figure 13; Figure 13 shows the structural representation according to the resistance-variable storing device of the bipolar transistor gating of the embodiment of the invention; Said resistance-change memory unit comprises: collector electrode 11, and said collector electrode comprises the doping of the first kind, the said first kind is doped to the N type or the P type mixes; Be formed at the base stage 12 on the said collector electrode 11, said base stage 12 has the doping of second type, opposite types doping each other that said second type is mixed and the first kind is mixed; Be formed at least two emitters 14 on the said base stage 12, said emitter 14 is separated by insulating barrier 17; Be formed at the resistance-change memory unit 21 on each said emitter 14; Said resistance-change memory unit comprises that resistance becomes functional layer; Said resistance becomes functional layer and can be clipped between the top electrode and bottom electrode of resistance-change memory unit, also can be clipped between top electrode and the emitter, under the alive outside effect; But the inverse conversion between the high and low resistance state is realized in the resistance-change memory unit, can one or more resistance-change memories unit be set according to real needs on each said emitter; Wherein, said base stage 12 is total base stages of all said emitters 14, and said collector electrode 11 is total collector electrodes of all said emitters 14.
Alternatively; Comprise that also the base lead 18 that is formed on the said base stage 12, the repellel that is formed on the said resistance-change memory unit go between 22; And be formed at the metal level 23 on said base lead 18 and the emitter terminal 22; Metal level 23 on the said base lead 18 is the bit line of said memory cell, and the metal level 23 on the said emitter terminal 22 is the word line of said memory cell.
Alternatively, also comprise the lightly-doped layer 13 that is formed between base stage 12 and the emitter 14, said lightly-doped layer 14 has and base stage 12 identical doping types.
In addition; The invention allows for a kind of resistance-variable storing device array of bipolar transistor gating; The resistance-variable storing device unit that comprises many above-described bipolar transistor gatings; The resistance-variable storing device unit of wherein said bipolar transistor gating is arranged in parallel and has common collector electrode, and base stage and emitter between each said resistance-variable storing device unit are isolated by second insulating barrier.
Below introduced in detail multi-emitter bipolar transistor structure and by the structure of the resistance-variable storing device of this multi-emitter bipolar transistor gating; The bipolar transistor structure of said multi-emitter has higher integration, littler area; Be applied in the resistance-variable storing device, improve the storage density of resistance-variable storing device.Below will describe the manufacturing approach of the bipolar transistor and the resistance-variable storing device of multi-emitter in detail, the embodiment of this manufacturing approach is in order better to explain and to understand the present invention, rather than restriction the present invention.
At step S01, the Semiconductor substrate with first doping type is provided, with reference to figure 3.In the present embodiment, said substrate 11 is a silicon substrate, and in other embodiments, said substrate 11 can also comprise other compound semiconductors, like carborundum, GaAs, indium arsenide or indium phosphide etc.According to designing requirement (for example p type substrate or n type substrate), substrate 11 can comprise the doping configuration of first doping type, and in the present embodiment, it is the p type that said substrate has first doping type.
At step S02, on said Semiconductor substrate, form first heavily doped layer with the doping of second type.With reference to figure 3, can on the substrate 11 of first doping type, form first heavily doped layer 12 through ion implantation with the doping of second type, for example on p type substrate, form n
+First heavily doped layer 12.
At step S03, on said first heavily doped layer, form second heavily doped layer, and said second heavily doped layer is divided at least two emitters with insulating barrier, and on each said emitter, form resistance-variable storing device with first doping type.
In one embodiment; Specifically; At first can on first heavily doped layer 12, form second heavily doped layer 14 through ion implantation with first kind doping, as shown in Figure 4, and because the carrier moving between second heavily doped layer 14 (for example p type) and first heavily doped layer 12 (for example n type); Formed the shallow doped region 13 of n type, as shown in Figure 5.Then, deposition bottom electrode 15 on second heavily doped layer 14, and form mask layer 16, said mask layer 16 can be photoresist, and is as shown in Figure 6.Then, utilize the graphical said device of lithographic technique, and stop on the semiconductor layer 11 of first kind doping; Between piling up 25, form deep trench 26, shown in Fig. 7, Fig. 8 (AA of Fig. 7 is to view, BB to view still like Fig. 6); And utilize lithographic technique graphically to pile up 25 again, and stop on first heavily doped layer 12, second heavily doped layer 14 is separated into the part of a plurality of separations by shallow trench 17; Shown in Fig. 9, Figure 10 (BB of Fig. 9 is still as shown in Figure 8 to view to view, AA); Thereby formed the structure of the bipolar transistor of multi-emitter, the unit 30 of the bipolar transistor of each multi-emitter keeps apart through deep trench 26, forms a plurality of emitters by shallow trench 17 separated second heavily doped layers 14; Wherein the semiconductor layer 11 of first doping type is a collector electrode; First heavily doped layer 12 that second type is mixed is a base stage, and said base stage is the total base stage of all said emitters 14, and said collector electrode is the total collector electrode of all said emitters 14.Then fill the dielectric material and form isolation 17, and on the base stage of said first heavily doped layer 12, form base lead 18, shown in figure 11.Then, remove mask layer 16 and form opening 32, and utilize side wall technology in opening 32, to form medium side wall 19, shown in figure 12.Then; Form resistance change material layer 21 in the opening between side wall 19 inwalls, and on resistance change material layer 21, form top electrode 20, thereby formed the resistance variation memory structure that comprises bottom electrode 15, resistance change material layer 21, medium side wall 19, top electrode 20; Shown in Figure 13, Figure 14 (vertical view); Be merely example here, resistance-variable storing device can also be other structure, for example only comprises that resistance becomes the structure of material and top electrode.
Then, can further accomplish following process as required, for example, on said resistance-variable storing device, form emitter terminal 22, and on said base lead and emitter terminal, form metal level 23, shown in figure 15.
More than the bipolar transistor of multi-emitter of the present invention and the resistance-variable storing device and the manufacturing approach of gating thereof have been carried out detailed description; Because a plurality of emitter common bases and the collector electrode of bipolar transistor; Thereby reduce the area of bipolar transistor; And adopt the resistance-variable storing device of the bipolar transistor gating of this multi-emitter, owing to reduced the area of gate transistor, and then improved the storage density of resistance-variable storing device.
Though specify about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and accompanying claims, can carry out various variations, replacement and modification to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (12)
1. the bipolar transistor of a multi-emitter, said transistor comprises:
Collector electrode;
Be formed at the base stage on the said collector electrode;
Be formed at least two emitters on the said base stage, said emitter is spaced;
Wherein, said base stage is the total base stage of all said emitters, and said collector electrode is the total collector electrode of all said emitters.
2. transistor according to claim 1 also comprises the base lead that is formed on the said base stage, is formed at the emitter terminal on the emitter, and is formed at the metal level on said base lead and the emitter terminal.
3. the resistance-variable storing device unit of the bipolar transistor gating of a multi-emitter, said resistance-change memory unit comprises:
Collector electrode;
Be formed at the base stage on the said collector electrode;
Be formed at least two emitters on the said base stage, separate by insulating barrier between the said emitter;
Be formed at the resistance-variable storing device on each said emitter;
Wherein, said base stage is the total base stage of all said emitters, and said collector electrode is the total collector electrode of all said emitters.
4. resistance-variable storing device according to claim 3 unit; Also comprise the base lead that is formed on the said base stage, be formed at the emitter terminal on the said resistance-variable storing device; And be formed at the metal level on said base lead and the emitter terminal; Metal level on the said base lead is the bit line of said memory cell, and the metal level on the said emitter terminal is the word line of said memory cell.
5. resistance-variable storing device according to claim 3 unit also comprises the lightly-doped layer that is formed between base stage and the emitter, and said lightly-doped layer has identical doping type with base stage.
6. resistance-variable storing device according to claim 3 unit, wherein the resistance-change memory unit on each said emitter is at least one.
7. resistance-variable storing device according to claim 3 unit, wherein said resistance-variable storing device comprise that the resistance between top electrode, bottom electrode and the said upper and lower electrode becomes functional layer.
8. resistance-variable storing device according to claim 3 unit, wherein said resistance-variable storing device comprise that resistance becomes functional layer and said resistance becomes the electrode layer on the functional layer.
9. the resistance-variable storing device array of the bipolar transistor gating of a multi-emitter; Comprise a plurality of resistance-variable storing device unit like each described bipolar transistor gating among the claim 3-8; The resistance-variable storing device unit of wherein said bipolar transistor gating is arranged in parallel and has common collector electrode, and base stage between each said resistance-variable storing device unit and emitter are by deep trench isolation.
10. the manufacturing approach of the resistance-variable storing device unit of a bipolar transistor gating, said method comprises:
A, the Semiconductor substrate with first doping type is provided;
B, on said Semiconductor substrate, form and have first heavily doped layer that second type is mixed;
C, on said first heavily doped layer, form second heavily doped layer, and said second heavily doped layer is divided at least two emitters with insulating barrier, and on each said emitter, form resistance-variable storing device with first doping type;
Wherein the Semiconductor substrate of first doping type is a collector electrode, and first heavily doped layer that second type is mixed is a base stage, and said base stage is the total base stage of all said emitters, and said collector electrode is the total collector electrode of all said emitters.
11. according to 10 described methods, said step C comprises:
On said first heavily doped layer, form second heavily doped layer, bottom electrode and the mask layer with first doping type successively, graphical said second heavily doped layer, bottom electrode and mask layer are to expose first heavily doped layer, to form a plurality of emitters;
Fill insulant layer between second heavily doped layer, bottom electrode and mask layer;
Remove mask layer to form opening, in said opening, form side wall;
Form the resistance change material layer in the opening between said side wall inwall;
On said side wall and resistance change material layer, form top electrode, thereby form resistance-variable storing device.
12. according to the method for claim 10-12 described in each; Also comprising behind the said step C: on said base stage, form base lead; And on said resistance-variable storing device, form emitter terminal, and on said base lead and emitter terminal, form metal level.
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| CN103872246A (en) * | 2012-12-14 | 2014-06-18 | 马维尔国际贸易有限公司 | Resistive random acess memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements |
| CN108694983A (en) * | 2017-04-11 | 2018-10-23 | 财团法人交大思源基金会 | Non-volatility memory and its operating method |
| CN112652712A (en) * | 2020-12-09 | 2021-04-13 | 华中科技大学 | Phase change memory integrated unit of gate tube, preparation method of integrated unit and phase change memory device |
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Application publication date: 20120704 |