CN103872246B - Resistor-type random access memory with for controlling the method for manufacture conducting element and the corresponding Subresolution feature of resistance element - Google Patents

Abstract

The present invention be resistor-type random access memory with for controlling the method for manufacture conducting element and the corresponding Subresolution feature of resistance element, including：Form the stacking of resistive layer；Before or after forming the resistive layer and stacking, conductive layer is formed；Mask layer is applied in resistive layer stacking or conductive layer；The first spacer is formed on the mask layer；And the first part for etching away the mask layer using first spacer as the first mask, to provide remainder.This method further includes：The second spacer is formed in the stacking or conductive layer of the resistive layer and the remainder of the mask layer；The second part of the remainder of the mask layer is etched away, to form island body；And the stacking for etching the resistive layer using the island body as the second mask to form the resistance element of memory, and etches the conductive layer, to form the conducting element of the memory.

Description

Resistor-type random access memory and for controlling manufacture conducting element and resistance element The method of corresponding Subresolution feature

Cross reference to related applications

This application claims the priority of U.S. Provisional Patent Application 61/737512 submitted on December 14th, 2012.With The complete disclosure of the application of upper reference is merged into herein by reference.

Technical field

The present invention relates to resistor-type random access memory (RRAM) and the method for manufacturing RRAM.

Background technology

Provided herein is background technology description purpose be that general explanation is made to the background of the disclosure.Referred to The work of the inventor of name, that is, make the work of description in this background technology part and may not yet become the applying date The some aspects of the specification of the prior art before are not considered as relative to this public affairs either in a manner of explicitly or implicitly The prior art opened.

Random access memory (RAM) is a kind of form of computer data storage, wherein can be with any random sequence It is directly accessed the data stored in random access memory.There are various types of RAM, including resistor-type random access memory (RRAM).Fig. 1-2 shows resistor-type random access memory (RRAM) 10, including the memory provided by resistance element 14 Cellular array 12.Can resistance element 14 be accessed by access device 16.Access device 16 can include such as complementary metal Oxide semiconductor (CMOS) transistor, bipolar junction transistor (BJT), diode, etc..Each in resistance element 14 With corresponding conducting element 18 (such as through-hole or contact).Each resistance element 14 can be referred to as a stacking, and And including first (or bottom) electrode 20, variable resistive layer 22, collecting layer 24 and second (or top) electrode 26.It is variable resistive Layer 22 can include such as transition metal oxide.Collecting layer 22 can include such as active metal.Conducting element 18 is embodied as Stacking the conductive layer on 14.Can conducting element 18 be set between (i) access device 16 and (ii) stack 14.Alternatively, Access device 16 can be used as in the opposite side setting conducting element 18 for stacking 14.Two or more conducting elements 18 can lead to Upper level interconnection (showing single interconnection 30) is crossed to be connected with each other.

Traditionally, (such as electron beam lithography of photoresist or extreme ultraviolet (EUV) light are included the use of using miniaturization method Carve) come the graphical resistance element 14 and conducting element 18.These methods use low yield technology, and this method includes the use of phase The graphical resistance element 14 of mask and etch process difference and conducting element 18 answered.This method causes in resistance element 14 Element misalignment and component mismatch between conducting element 18.

Element misalignment refers to the lateral misalignment between conducting element and resistance element, as shown in misalignment difference X in Fig. 1.Member Part mismatch instructs the side of electric device and corresponding resistance element and the difference of shape.Due to the use of photoetching technique, cause resistive Element 14 and conducting element 18 have (i) coarse and/or jagged side and (ii) contact surface of different shapes.For example, The shape of first contact surface 32 of resistance element 14 is different from the shape of the second contact surface 34 of conducting element 18.Therefore it first connects Contacting surface 32 is mismatched with the second contact surface 34.The different shape of resistance element 14 and conducting element 18 is shown in FIG. 1, it is square Shape represents resistance element 14, and circle represents conducting element 18.The true form of resistance element 14 and conducting element 18 can not It is same and usually irregular.Element misalignment and component mismatch to increase with group shape element 14 and 18 relevant resistance of conducting element Add, and negatively influence the performance of RRAM10.

Invention content

It provides a method, including：Form the stacking of resistive layer；Before or after forming resistive layer and stacking, formed Conductive layer；Mask layer is applied in the stacking of (i) resistive layer or (ii) conductive layer；The first spacer is formed on mask layer；And And the first part of mask layer is etched away using the first spacer as the first mask, to provide remainder.This method is also Including：The second spacer is formed in the stacking or conductive layer of (i) resistive layer and the remainder of (ii) mask layer；It etches away The second part of the remainder of mask layer is to form island body；And using island body, (i) etches resistive as the second mask The stacking of layer, to form the resistance element of memory and (ii) etching conductive layer, to form the conducting element of memory.

It in other feature, provides a method, this method includes：Resistive layer is formed on access device to stack； Conductive layer is applied on resistive layer；Mask layer is applied on the electrically conductive；Spacer is formed on mask layer；Using spacer as One mask carrys out etch mask layer, to provide island body；And using island body, (i) etching resistive layer stacks as the second mask To form resistance element and (ii) etching conductive layer, to form conducting element, wherein resistance element provides memory cell.

In other feature, a kind of memory is provided, which includes resistance element and conducting element.Resistance element Memory cell array is provided, wherein resistance element includes the first contact surface.Conducting element includes through-hole or contact.It is conductive Element includes the second contact surface.Resistance element is contacted in corresponding conducting element, to provide element pair.For the element Each element of centering etches the element pair to using same period of single mask.Etched elements pair as a result, second Contact surface matches and is directed at corresponding first contact surface.

Other fields that the disclosure is applicable in will be become apparent by detailed description, claims and drawing.It retouches in detail It states and is only intended to illustrate with specific example, without being intended to limitation the scope of the present disclosure.

Description of the drawings

Fig. 1 is the top view of traditional RRAM.

Fig. 2 is the side cross-sectional view by the section line A-A of Fig. 1.

Fig. 3 illustrates the manufacturing method of the RRAM of multiple embodiments according to the present invention, which includes corresponding resistive Element and conducting element.

Fig. 4 is the top view of the part RRAM after resistive layer, conductive layer and hard mask layer is initially formed.

Fig. 5 is the side cross-sectional view by the section line B-B of Fig. 4.

Fig. 6 is the top view of the first mask and part RRAM after the first film layer is formed.

Fig. 7 is the side cross-sectional view by the section line C-C of Fig. 6.

Fig. 8 is the top view to form the part RRAM after the second film layer.

Fig. 9 is the side cross-sectional view by the section line D-D of Fig. 8.

Figure 10 be etch the second film layer after part RRAM top view.

Figure 11 is the side cross-sectional view by the section line E-E of Figure 10.

Figure 12 be etch hard mask layer after part RRAM top view.

Figure 13 is the side cross-sectional view by the section line F-F of Figure 12.

Figure 14 is the top view of part RRAM after removing the second film layer remainder to provide the first spacer.

Figure 15 is the side cross-sectional view by the section line G-G of Figure 14.

Figure 16 is the top view of the second mask and part RRAM after forming third film layer.

Figure 17 is the side cross-sectional view by the section line H-H of Figure 16.

Figure 18 is to form the 4th film layer to provide the top view of the part RRAM after the second spacer.

Figure 19 is the side cross-sectional view by the section line I-I of Figure 18.

Figure 20 is the top view for etching the 4th film layer and removing the part RRAM after third film layer.

Figure 21 is the side cross-sectional view by the section line J-J of Figure 20.

Figure 22 be etch hard mask layer remainder after part RRAM top view.

Figure 23 is the side cross-sectional view by the section line K-K of Figure 22.

Figure 24 is part after etching the 4th film layer to provide the remainder of hard mask layer in the form of the body of island The top view of RRAM.

Figure 25 is the side cross-sectional view by the section line L-L of Figure 24.

Figure 26 is the top view for etching the part RRAM after resistive layer and conductive layer.

Figure 27 is the side cross-sectional view by the section line M-M of Figure 26.

Figure 28 is the top view using the part RRAM after separation layer.

Figure 29 is the side cross-sectional view by the section line N-N of Figure 28.

Figure 30 is the thick view of part RRAM after removing part separation layer and removing mask layer island body.

Figure 31 is the side cross-sectional view by the section line O-O of Figure 30.

Figure 32 is the top view to form the part RRAM after interconnecting.

Figure 33 is the side cross-sectional view by the section line P-P of Figure 32.

In the accompanying drawings, reference numeral may be reused to refer to similar and/or identical element.

Specific embodiment

Disclosed herein is the formation of resistance element (or stacking) and conducting element (such as through-hole or contact) including RRAM Method.This method includes forming spacer and in a single step graphical (or etching) resistive layer and conductor layer.It uses The mask of single formation, resistive layer and conductive layer is graphical together.Formed spacer is used to provide mask.Then make With mask come graphical resistive layer and conductive layer.This graphically provides the Subresolution feature to resistance element and conducting element Control.Subresolution feature refers to the feature of the resolution ratio limitation less than feature patterning tool.Resistance element and conducting element Subresolution feature can include size, shape and the roughness on side of such as resistance element and conducting element.This method packet It includes etching and chemical vapor deposition (CVD) rather than uses conventional lithography and photolithographic techniques.This just minimizes and/or eliminates Element misalignment and component mismatch.As a result, resistance element and conducting element contraposition and contact surface matching.This is just minimum Change the resistance of corresponding RRAM, improve the reliability of RRAM and improve the performance of RRAM.

Fig. 3 illustrates the manufacturing method of the RRAM including corresponding resistance element and conducting element.Although to following task Description primarily with regard to Fig. 4-33 embodiment, thus it is possible to vary the task is to be applied to other embodiments of the present invention. This method is since 100.

According to fig. 3, Fig. 4-5 shows the top view and sectional view of the state of the part 90 of the RRAM after task 102. 102, in access device 112, (each box for being identified as 112 can include more in figs. 4-5 and in following chart A access device) array 110 on form resistive layer 104, conductive layer 106 and hard mask layer 108.Access device 112 can wrap Such as transistor (such as CMOS transistor and/or BJT transistors), diode, wordline, conducting element are included (for example, conducting wire, logical Hole, contact, etc.) or other electronic units.This is further described in Figure 32-33.

It can be set on access device and application resistive layer 104 is stacked with being formed.Resistive layer can include the first (or bottom Portion) electrode layer 114, variable resistive layer 116, collecting layer 118 and second (or top) electrode layer 120.Electrode layer 114,120 can be with It is formed by such as titanium nitride TiN and/or including such as titanium nitride TiN.In one embodiment, second is etched in subsequent task For electrode layer 120 to provide electrode, which may be coupled to bit line.Variable resistive layer 116 can be by such as transiting metal oxidation Object (such as hafnium oxide HfO₂) formed and/or including such as transition metal oxide (such as hafnium oxide HfO₂).Collecting layer 118 can be formed by such as active metal (such as Ti) and/or including such as active metal (such as Ti).Conductive layer 106 can be with The heap for being deposited on resistive layer 104 is stacked on, and can be W-shaped into and/or including such as Ti, aluminium by such as Ti, aluminium Al and/or tungsten Al and/or tungsten W.Hard mask layer 108 can be deposited on conductive layer 106, and can be by such as silicon nitride Si₃N₄And/or TiN It is formed and/or including such as silicon nitride Si₃N₄And/or TiN.Conductive layer 106 can mask harder than (i) resistive layer 104 and (ii) It is one or more thicker in layer 108.Hard mask layer 108 can be than one in (i) resistive layer 104 and (ii) conductive layer 106 It is a or more thinner.

Although conductive layer 106 is shown as being arranged between resistive layer 104 and hard mask layer 108, conductive layer 106 can be set It puts between access device 112 and resistive layer 104.When conductive layer 106 is arranged between resistive layer 104 and hard mask layer 108, In order to provide through-hole, conductive layer 106 can be etched in subsequent task.When conductive layer 106 is arranged on resistive layer 104 and covers firmly When between film layer 108, conductive layer 106 can be etched in subsequent task to provide contact.

According to fig. 3, Fig. 6-7 shows the top view and sectional view of the state of the part 90 of the RRAM after task 130.Figure 6-7 shows resistive layer 104, conductive layer 106, hard mask layer 108, access device 112,134 and first mask of the first film layer 134.130, the first film layer 132 is formed.First mask 134 has opening 136 and can be used to form and graphical described the One film layer 132.Can the memory cell layout based on scheduled RRAM and provide or formed the first mask 134.It can make The first film layer 132 is deposited on hard mask layer 108 with the first mask 134.CVD or other deposition techniques can be used (such as Physical vapour deposition (PVD) (PVD)) form the first film layer 132.The first film layer 132 can be by such as silica SiO₂And/or Silicon carbide SiC is formed and/or including such as silica SiO₂And/or silicon carbide SiC.

According to fig. 3, Fig. 8-9 shows the top view and sectional view of the state of the part 90 of the RRAM after task 140.Figure 8-9 shows resistive layer 104, conductive layer 106, hard mask layer 108, access device 112,132 and second film of the first film layer Layer 142.140, the second film layer 142 is applied in the top of the first film layer 132 and hard mask layer 108.Can use CVD, PVD or other suitable deposition techniques deposit the second film layer 142 on the first film layer 132 and hard mask layer 108.Second is thin Film layer 142 is formed by the material for being different from the first film layer 132.Second film layer 142 can be by such as carbon doped silicon nitride Si3N4 is formed and/or including such as carbon doped silicon nitride Si3N4.As what is carried out in following task 150, by by with The different material of the first film layer 132 forms the second film layer 142, can be in at least part for retaining the second film layer 142 While remove the first film layer 132.

According to fig. 3, Figure 10-11 shows the top view and sectional view of the state of the part 90 of the RRAM after task 150. Figure 10-11 show resistive layer 104, conductive layer 106, hard mask layer 108,112 and second film layer 142 of access device residue Part 152.150, the first film layer 132 and the second film layer 142 are etched to provide 152 (i.e. the second film of the first spacer The remainder of layer 142).First spacer 152 is the remainder of the second film layer 142 after the second film layer 142 is etched Point.The first film layer 132 is removed.As a result, the first spacer 152 is ring-shaped, and with central opening 154, previous the first film layer 132 is located at central opening 154.The first film layer can be removed using anisotropic etching 132 and the part of the second film layer 142 is etched away, to provide the first spacer 152.It can be wrapped in the etching that 150 perform Include wet etching or dry ecthing.

According to fig. 3, Figure 12-13 shows the top view and sectional view of the state of the part 90 of the RRAM after task 160. Figure 12-13 is shown between resistive layer 104, conductive layer 106, the remainder 162 of hard mask layer 108, access device 112 and first Spacing body 152. etches hard mask layer 108, to provide remainder 162 160 using the first spacer 152 as mask.It is surplus Remaining part point has central opening 164.Remainder 162 is ring-shaped and matches the circular pattern of the first spacer 152.It can A part for hard mask layer 108 is etched away to use anisotropic etching, to provide remainder 162.In the erosion that 162 perform Quarter can include dry ecthing.

According to fig. 3, Figure 14-15 shows the top view and sectional view of the state of the part 90 of the RRAM after task 160.Figure 14-15 shows resistive layer 104, conductive layer 106, the remainder 162 of hard mask layer 108 and access device 112.170, move In addition to the first spacer 152.The first spacer 152 can be etched away using anisotropic etching.It can in the etching that 170 perform To include wet etching or dry ecthing.

According to fig. 3, Figure 16-17 shows the top view or sectional view of the state of the part 90 of the RRAM after task 180.Figure 16-17 shows resistive layer 104, conductive layer 106, the remainder 162 of hard mask layer 108, access device 112, third film Layer 182,182 and second mask 184 of third film layer.180, third film layer 182 is formed.Can use has opening 186 The second mask 184 to be formed and graphical third film layer 182.It can be provided based on the layout of scheduled memory cell Or form the second mask 184.The second mask 184 can be used on conductive layer 106 and in the remainder of hard mask layer 108 Deposition third film layer 182 in 162 central opening 154.Third film layer 182 can be with the remainder of hard mask layer 108 162 are folded.Third film layer 182 can be formed using CVD or other deposition techniques (such as physical vapour deposition (PVD) (PVD)). Third film layer 182 can be by such as silica SiO₂And/or silicon carbide SiC is formed and/or comprising such as silica SiO₂And/or silicon carbide SiC.

According to fig. 3, Figure 18-19 shows the top view and sectional view of the state of the part 90 of the RRAM after task 190.Figure 18-19 shows that resistive layer 104, conductive layer 106, the remainder 162 of hard mask layer 108, third film layer 182 and the 4th are thin Film layer 192.190, the 4th film layer 192 is formed.CVD, PVD or other suitable deposition technique can be used in third film The 4th film layer 192 is deposited on layer 182 and conductive layer 106.4th film layer 192 is by the material different from third film layer 182 It is formed.4th film layer 192 can be by such as carbon doped silicon nitride Si₃N₄It is formed and/or including such as carbon doped silicon nitride Si₃N₄.As what is carried out in following task 200, by by forming the 4th film layer with 182 different materials of third film layer 192, third film layer 182 can be removed while at least part for retaining the 4th film layer 192.4th film layer 192 include raised profile region 194, raised profile region 194 be due to the 4th film layer be covered in third film layer 182 with Caused by the part that 108 remainder 162 of hard mask layer overlaps.

According to fig. 3, Figure 20-21 shows the top view and sectional view of the state of the part 90 of the RRAM after task 200.Figure 20-21 shows resistive layer 104, conductive layer 106, the remainder 162 of hard mask layer 108, access device 112, third film The remainder 202 of 201 and the 4th film layer 192 of remainder of layer 182.200, etching third film layer 182 and the 4th For film layer 192 to provide the second spacer 203, the second spacer 203 includes the remainder 201 and the of third film layer 182 The remainder 202 of four film layers 192.Second spacer 203 is ring-shaped.Each in spacer 162,203 is rectangle 's.The remainder 162 of hard mask layer 108 extends in a first direction.Second spacer 203 is perpendicular to the of first direction Two sides upwardly extend.182 and the 4th film layer 192 of third film layer can be etched to provide second using anisotropic etching Spacer 203.It can include dry ecthing in the etching that 200 perform.

According to fig. 3, Figure 22-23 shows the top view and sectional view of the state of the part 90 of the RRAM after task 210.Figure 22-23 shows resistive layer 104, conductive layer 106, access device 112, the second spacer 203 and hard mask layer island body 212. 210, the remainder of (as shown in Figure 20 and Figure 21) hard mask layer 108 is etched using the second spacer 203 as mask Divide 162, to provide hard mask layer island body 212.The one of remainder 162 can be etched away using anisotropic etching Point, to provide hard mask layer island body 212.It can include wet etching or dry ecthing in the etching that 210 perform.

According to fig. 3, Figure 24-25 shows the top view and sectional view of the state of the part 90 of the RRAM after task 220.Figure 24-25 shows resistive layer 104, conductive layer 106, access device 112 and hard mask layer island body 212.220, remove or (erosion Carve) the second spacer 203 is so that remaining element on conductive layer 106 is hard mask layer island body 212.Due to previous more The use of a etching step 160 and 210 and spacer 162,203, the side 222 of hard mask layer island body 212 is smooth.

According to fig. 3, Figure 26-27 shows the top view and sectional view of the state of the part 90 of the RRAM after task 230.Figure 26-27 shows the remainder 232 of resistive layer 104, the remainder 234 of conductive layer 106, access device 112 and hard mask Layer island body 212.230, resistive layer 104 and conductive layer 106 are etched using hard mask layer island body 212 as mask.It can The expose portion of resistive layer 104 is removed to use anisotropic etching, to provide remainder 232,234.It is performed 230 Etching can include wet etching or dry ecthing.Which provides resistance element 236 (the i.e. stacking of remainder 232, each stackings All be resistance element) and conducting element (i.e. remainder 234), cross section be mutually matched and with hard mask layer island body 237 cross section matching.Each in resistance element includes first electrode 235, variable resistance element 237, hardware 238 and second electrode 239.Second electrode 239 may be coupled to bit line.

Resistance element 236 and conducting element 234 are provided to the etching of resistive layer 104 and conductive layer 106 as described above, Resistance element 236 and conducting element 234 have the contact surface for being mutually matched and being mutually aligned accordingly.The one of resistance element A exemplary contact surface is defined as 241.One exemplary contact surface of conducting element is defined as 243.Due to the use of Identical correspondence mask, the patterns of the shape and size including each pair of contact surface (such as 241,243 pairs of contact surface), phase Mutually match and be aligned.Occurs the etching to resistive layer 104 and conductor layer 106 in single task role.Therefore, to resistive layer 101 etching and the etching of conductor layer 106 is appeared in same time period.Contact surface with corresponding contact surface region Size it is identical.

According to fig. 3, Figure 28-29 shows the top view and sectional view of the state of the part 90 of the RRAM after task 240.Figure 28-29 shows resistance element 236, conducting element 234, access device 112, hard mask layer island body 212 and dielectric isolation Film (or isolation) layer 242.240, in 234 disposed thereon dielectric isolation film of resistance element 236 and conducting element, to carry For separation layer 242.The part of resistance element 236 and the part of conducting element 234 are encapsulated in dielectric isolation film, will The conducting element and resistance element being connected with each stacking are kept apart from other conducting elements and resistance element of other stackings.

According to fig. 3, Figure 30-31 shows the top view and sectional view of the state of the part 90 of the RRAM after task 250.Figure 30-31 shows resistance element 236, conducting element 234, access device 112 and dielectric isolation layer (or isolation) layer 242. 250, remove hard mask layer island body 212.Hard mask island body 212 can be removed using anisotropic etching.The etching It can include wet etching or dry ecthing.The top surface of RRAM can be etched and/or polished using chemical-mechanical planarization, with sudden and violent Reveal conducting element 234.

According to fig. 3, Figure 32-33 shows the top view and sectional view of the state of the part 90 of the RRAM after task 260.Figure 32-33 shows resistance element 236, conductive layer 234, access device 112, separation layer 242 and interconnection 262.260, formed mutual Connect 262.Metallization can be performed to interconnect to be formed on the part of top surface.The interconnection by two in conducting element 234 or More conducting elements are connected with each other.The interconnection can include metal such as Ti, aluminium Al and/or tungsten W.This method can be 270 Terminate.

The electrode 235 of resistive layer 236 may be coupled to transistor.Only make example, single transistor 280 is shown with leakage Pole 282, source electrode 284 and grid 286.Drain electrode 282 is connected to one in electrode 235.Source electrode 284, which may be coupled to, to be for example grounded With reference to 288.Grid 286 may be coupled to wordline 290.

In above-mentioned task, the straight smooth side of the remainder 162 of hard mask layer 108 and the second spacer 203 Straight smooth side provide the mask used in etching task, to provide the straight smooth of resistance element and conducting element Side.Resistance element is aligned in corresponding with conducting element.

The other aspects of the present invention are related to one or more of following content content.

This document describes a kind of method, this method includes：Resistive layer is formed to stack；Formed resistive layer stack before or it Afterwards, conductive layer is formed；Mask layer is applied in (i) resistive layer stacking or (ii) conductive layer；The first interval is formed on mask layer Part；And the first part of mask layer is etched away using the first spacer as the first mask, remainder is configured.The party Method further includes：In (i) resistive layer stacking or the remainder of conductive layer and (ii) mask layer, the second spacer is formed；Erosion Carve the second part of the remainder of mask layer, to form island body；And island body is used as the second mask, (i) erosion It carves resistive layer stacking and forms the conducting element of memory to form the resistance element of memory and (ii) etching conductive layer.

The formation of first spacer can include：The first film layer is applied on mask layer；And etch the first film layer To provide the first spacer.The formation of second spacer can include：In (i) mask layer and (ii) resistive layer stacks or conductive layer The second film layer of upper application；And the second film layer is etched to provide the second spacer.In first spacer and the second spacer Each spacer can be ring-shaped.

The formation of second spacer can include：Using thin on (i) mask layer and (ii) resistive layer stacking or conductive layer Film layer；And etch thin film layer, to provide the second spacer.

This method can also include：The second part of the remainder of mask layer is etched away, to form island body；And make By the use of island body as mask, (i) etching resistive layer is stacked to form resistance element, and (ii) etches conductive layer to form conduction Element.

This method can also include：In resistance element and overlying conductive elements depositing isolation material, to encapsulate (i) resistive member The part and the part of (ii) conducting element that part stacks；By one that etches away (i) island body and (ii) isolated material Divide and expose conducting element；And metallization is performed, two or more conducting elements in conducting element are connected to be formed Interconnection.

This method can also include：In resistance element and overlying conductive elements depositing isolation material to encapsulate (i) resistive member A part for a part for part and (ii) conducting element；And by etching away the part of (i) isolated material and (ii) island Body and expose conducting element.

As an example, resistive layer stacking can be formed on access device.Access device can include transistor and Wordline.Resistance element includes first electrode and second electrode.First electrode is connected to the drain electrode of transistor.Second electrode is connected to Bit line.

As another example, conductive layer is formed before resistive layer is formed；And conductive unit is contact.

As an example, conductive layer is formed after resistive layer is stacked and to be formed；And conducting element is through-hole.

The invention discloses a kind of method, and this method includes：Resistive layer is formed on access device to stack；Resistive Heap is stacked on to apply conductive layer；Mask layer is applied on the electrically conductive；Spacer is formed on mask layer；Using spacer as first Mask carrys out etch mask layer to provide island body；And using island body, (i) etching resistive layer is stacked with shape as the second mask Into resistance element and (ii) etching conductive layer to form conducting element, wherein resistance element provides memory cell.

This method can also include：The first film layer is formed on mask layer；The first film layer is etched to be formed between first Spacing body；The first part of mask layer is etched away using the first spacer as mask, to provide remainder；It is thin to form second Film layer on the remainder of (i) conductive layer and (ii) mask layer to form the second spacer；And etch away the surplus of mask layer The second part of remaining part point, to form island body.

This method can also include：In resistance element stacking and overlying conductive elements depositing isolation material, hindered with encapsulating (i) Property element a part and (ii) conducting element a part；And by etching away (i) island body and (ii) isolated material A part and expose conducting element；And metallization is performed to form the mutual of two or more elements in connection conducting element Even.

The invention discloses a kind of memory, which includes resistance element and conducting element.Resistance element offer is deposited Memory cell array, wherein resistance element include the first contact surface.Conducting element includes through-hole or contact.Conducting element includes Second contact surface.Resistance element is in contact with corresponding electrically conductive element, to provide element pair.For each element to using The same period of single mask, etch the element pair.As it is etching the element pair as a result, the second contact surface with it is corresponding The first contact surface match and be aligned.

As an example, the contact surface region of the second contact surface can have and corresponding first contact surface The identical size in contact surface region.In addition, each during resistance element stacks can include：First electrode；With the first electricity The variable resistance of pole contact；The hardware contacted with variable resistance；And the second electrode contacted with hardware.

The memory can also include transistor, wherein：The drain electrode of transistor is connected to the first electrode of resistance element, and And the grid of transistor is connected to wordline.Second electrode may be coupled to bit line.

The memory can also include transistor, wherein each in transistor and corresponding (i) resistance element or (ii) contact in conducting element.Electrode in resistance element may be coupled to the grid of transistor.

The purpose of above-mentioned task is illustrated examples；According to application, which can be in the period be folded by sequentially, together Step ground simultaneously, continuously or is executed in different order.In addition, according to implement and/or event sequence, can not perform or Skip any task in the task.In addition, although Yi Shang task is described primarily with regard to RRAM, more than task can be applied To other memories.

Foregoing description is substantially exemplary only, and is not intended to the limitation disclosure, its application or uses.It can be with each Kind form realizes the extensive introduction of the disclosure.Therefore, although the present disclosure includes specific examples, the true model of the disclosure Enclosing so to be limited, this is because after research attached drawing, specification and appended, other modifications will be apparent. Phrase " at least one of A, B and C " used herein should be interpreted using non-exclusive logic or logic (A or B or C).It, can be in different order (or simultaneously) execution method it should be appreciated that under the premise of the principle of the present invention is not changed One or more steps).

Although herein phrase " first ", " second ", " third " etc. can be used for describing various layers, interconnection, element, Access device and/or component, these projects should not necessarily be limited by these phrases.These phrases may be only used for by a project with it is another One project difference.When phrase used herein such as " first ", " second " and other digital phrases, it is not intended to order Or sequence, unless explicitly pointing out in the text.Therefore, the first item being discussed below can mean second item without departing from The introduction that example is implemented.

In the following description, using various phrases to describe the physical relation between component.When first element is known as " above ", " being engaged in ... ", " being connected to ... ", " on being arranged on ... ", " in ... upper application " Or when " being coupled to ... ", first element can be directly in second element, be directly fixed in second element, directly Second element is connected to, is set up directly in second element, directly applies or be directly coupled to second yuan in second element Part or there may be intervenient elements.On the contrary, when element be known as " on directly existing ... ", " directly engagement In ... ", " on being set up directly on ... ", " in ... upper directly application ", " being directly connected to ... " or " straight Connect and be coupled to ... " another element when, there is no intervenient elements herein.It is other to be used to describe relationship between element Word should explain in this way (for example, " ... between " to " between directly existing ... ", " adjacent " is to " direct phase It is adjacent ", etc.).

Device and method described in this application can be one or more by being performed by one or more processors A computer program and partly or be completely carried out.The computer program includes processor-executable instruction, the instruction quilt It is stored at least one non-provisional, tangible computer readable medium.The computer program can also include and/or rely on Stored data.

Claims (11)

1. a kind of method for manufacturing memory, the method includes：

Form the stacking of resistive layer；

Before or after the stacking of the resistive layer is formed, conductive layer is formed；

Mask layer is applied in the stacking of (i) described resistive layer or (ii) described conductive layer；

The first spacer is formed on the mask layer, wherein first spacer is ring-shaped, and wherein described in formation First spacer includes：

The first cluster film layer is applied on the mask layer using chemistry or vapor deposition, wherein the first cluster film layer includes The first film layer and the second film layer, wherein the first film layer is made only in a part for the mask layer, wherein institute The second film layer is stated to be formed on the mask layer and the first film layer, and wherein described second film layer by with it is described The different material of the first film layer is formed；And

The first cluster film layer is etched, to provide first spacer；

The first part of the mask layer is etched away using first spacer as the first mask, to provide remainder Point, wherein the remainder is ring-shaped；

It is formed between second in the stacking of (i) described resistive layer or the conductive layer and on the remainder of (ii) described mask layer Spacing body, wherein second spacer is ring-shaped；

Fall the second part of the remainder of the mask layer using second spacer etch with first time from the mask Layer forms island body；And

Come (i) using the island body as the second mask and etch the stacking of the resistive layer to form the resistive member of memory Part and (ii) etch the conductive layer to form the conducting element of the memory.

2. according to the method described in claim 1, the formation of wherein described second spacer includes：

It should on (i) described mask layer and on the stacking of (ii) described resistive layer or the conductive layer using chemistry or vapor deposition With the second cluster film layer, wherein the second cluster film layer includes third film layer and the 4th film layer, wherein the third is thin Film layer is made only in a part for the conductive layer and a part for the mask layer, wherein the 4th film layer is formed in On the only second part of the third film layer and the conductive layer, and wherein described 4th film layer is by thin with the third The different material of film layer is formed；And

The second cluster film layer is etched, to provide second spacer.

3. according to the method described in claim 1, the formation of wherein described second spacer includes：

Multiple film layers are applied on (i) described mask layer and on the stacking of (ii) described resistive layer or the conductive layer；And

The multiple film layer is etched to provide second spacer.

4. it according to the method described in claim 1, further includes：

The second part of the remainder of the mask layer is etched away, to form multiple island bodies；And

Using the multiple island body as multiple masks, (i) etches the stacking of the resistive layer to form multiple resistance elements, And (ii) etches the conductive layer to form multiple conducting elements.

5. it according to the method described in claim 4, further includes：

In the multiple resistance element and the multiple overlying conductive elements depositing isolation material, to encapsulate (i) described resistive member A part for a part for the stacking of part and (ii) the multiple conducting element；

By etching away the part of (i) the multiple island body and (ii) described isolated material and the multiple conductive element of exposure Part；And

Metallization is performed, to form the interconnection for connecting two or more conducting elements in the multiple conducting element.

6. it according to the method described in claim 1, further includes：

In the resistance element and the overlying conductive elements depositing isolation material, to encapsulate one of (i) described resistance element Divide the part with (ii) described conducting element；And

By etching away a part and (ii) described island body of (i) described isolated material and the exposure conducting element.

7. according to the method described in claim 1, wherein：

The stacking of the resistive layer is formed on access device；

The access device includes transistor and wordline；

The resistance element includes first electrode and second electrode；

The first electrode is connected to the drain electrode of the transistor；And

The second electrode is connected to bit line.

8. according to the method described in claim 1, wherein：

The conductive layer is formed before the stacking for forming the resistive layer；And

The conducting element is contact.

9. according to the method described in claim 1, wherein：

The conductive layer is formed after the stacking for forming the resistive layer；And

The conducting element is through-hole.

10. a kind of method for manufacturing memory, the method includes：

The stacking of resistive layer is formed on multiple access devices, wherein the multiple access device includes multiple transistors；

It is stacked on using conductive layer in the heap of the resistive layer；

Mask layer is applied on the conductive layer；

Multiple spacers are formed on the mask layer；

The mask layer is etched using the multiple spacer as multiple first masks, to provide multiple island bodies, including：

The first cluster film layer is formed on the mask layer, wherein the first cluster film layer is thin including the first film layer and second Film layer, wherein the first film layer only covers a part for the mask layer, wherein second film layer be formed in it is described On mask layer and the first film layer, and wherein described second film layer is by the material shape different from the first film layer Into；

The first cluster film layer is etched, to form the first spacer, wherein first spacer is ring-shaped；

The first part of the mask layer is etched away using first spacer as mask, to provide remainder；

The second cluster film layer is formed, to be formed between second on the remainder of (i) described conductive layer and (ii) described mask layer Spacing body, wherein second spacer is ring-shaped, wherein the second cluster film layer includes third film layer and the 4th film Layer, wherein the third film layer is made only in a part for the conductive layer and a part for the mask layer, wherein institute It states the 4th film layer to be formed on the only second part of the third film layer and the conductive layer, and wherein described 4th thin Film layer is formed by the material different from the third film layer；And

Fall the second part of the remainder of the mask layer using second spacer etch, with respectively for the multiple Access device forms the multiple island body from the mask layer, wherein in the remainder for etching away the mask layer The second part does not form island body before the multiple island body to be formed from the mask layer；And

Using the multiple island body as multiple second masks, the stacking that (i) etches the resistive layer is multiple resistive to be formed Element and (ii) etch the conductive layer to form multiple conducting elements, wherein the multiple resistance element is the multiple Multiple memory cells are provided on access device.

11. it according to the method described in claim 10, further includes：

Stacking and the multiple overlying conductive elements depositing isolation material in the resistance element, it is the multiple to encapsulate (i) A part for a part for resistance element and (ii) the multiple conducting element；And

By etching away the part of (i) the multiple island body and (ii) described isolated material and the multiple conductive element of exposure Part；And

Metallization is performed, to form the interconnection for connecting two or more conducting elements in the multiple conducting element.