JP2008047274A - Nonvolatile semiconductor storage device, method for determining state of nonvolatile semiconductor storage device, and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rewritable nonvolatile memory cell which can increase a reading margin and control a word line and a bit line at a Vcc level. <P>SOLUTION: Inverters, in which storage transistors (nMOS transistors) are composed of transistors which can control threshold values by charging electric charges to a side spacer, are cross-connected to constitute flip-flops. When writing is made to one of the storage transistors, a high voltage is supplied to the source of the storage transistor via a source line, and a high voltage is also supplied to the gate of the storage transistor via the load transistor of the opposite-side inverter. When the writing is erased, a high voltage is supplied to the source of the storage transistor via the source line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electrically erasable and writable nonvolatile semiconductor memory device and a semiconductor integrated circuit device including the same.

  For example, the need for redundancy (redundancy) due to the increase in the capacity of the built-in SRAM, the need for individual tuning after board mounting such as an LCD driver, personal identification information (ID code, decryption key, IC card) The need for low-cost fuses is increasing along with the expansion of various applications.

  Conventionally, there are fuse elements that can be formed by a standard CMOS process, such as those in which a polysilicon or wiring metal layer is blown by a laser or current, and those in which an insulating gate film is destroyed by voltage. However, such a fusing or dielectric breakdown can be programmed only once and is not suitable for the above-mentioned use.

  On the other hand, if a floating gate type non-volatile element that can be formed by a CMOS process is used, a fuse that can be electrically erased and written can be realized. Introducing a special process like this is not worth the cost. Further, the floating gate type element in the standard CMOS process has a problem that the data retention characteristic is deteriorated when the insulating film is thinned with the high integration.

  Thus, for example, Patent Document 1, Patent Document 2, and Patent Document 3 show a nonvolatile memory device that can be manufactured by a standard CMOS process and a nonvolatile memory device that does not have a special floating gate.

US Pat. No. 6,518,614 JP 2004-56095 A JP-A-2005-353106

  FIG. 1 shows a memory cell configuration of a nonvolatile memory device manufactured by a standard CMOS process disclosed in Patent Document 3 as a conventional example. Basically, N-type MOS transistors MCN1 and MCN2 which are nonvolatile data storage units, and static latch type flip-flop units (MN3, MN4,...) Having differential inputs to the output nodes nodeT and nodeB of the nonvolatile data storage unit. MP1, MP2). The flip-flop unit can perform normal SRAM operation reading and writing operations, but can reload data in the nonvolatile data storage unit and store data in the flip-flop unit.

  FIG. 2 shows a data setting method in the conventional example. This data setting method is a method of determining data by the threshold voltage difference between MCN1 and MCN2. In the initial state before data writing, the N-type MOS transistors MCN1 and MCN2 are both at the threshold voltage Vth0, and in this state, the output data of the flip-flop is indefinite. Therefore, in order to determine the data, first, data “0” is written by raising the threshold voltage on the MCN1 side to Vth1 (Vth1> Vth0). In this configuration, since erasure (Vth cannot be reduced), subsequent writing of data “1” is performed by setting the threshold voltage on the MCN2 side to Vth2 (Vth2> Vth1) from the state of data “0”. Realized by raising

  FIG. 3 shows a method for changing the threshold voltage of the N-type MOS transistor in the nonvolatile data storage section in the above-described conventional example. As an example, data “0”, that is, a case where the threshold voltage on the MCN1 side is increased is shown. Basically, the characteristic degradation due to hot carriers of the N-type MOS transistor is actively utilized, and the source potential of MCN1, which is to increase the threshold voltage, is 0V, the gate potential (MLW) is 2.5V, the drain The potential (nodeT) is set to 5 V, and the threshold voltage is raised by hot carrier injection near the drain end. At this time, the drain potential of 5V is such that the bit line BLT potential is set to 5V, the word line WL of the flip-flop section is set to a sufficiently high voltage (7V), and the BLT potential of 5V is completely supplied to the nodeT. By supplying. The drain potential of MCN2, which does not want to increase the threshold voltage, is controlled so that hot carrier injection does not occur by setting the BLB potential to 0V. When data “1” is written, the threshold voltage on the MCN2 side is increased. Therefore, simply setting BLT = 0V and BLB = 5V, the other conditions are the same as when data “0” is written. .

FIG. 4 shows a data transfer method from the nonvolatile data storage unit to the flip-flop unit in the above-described conventional example. The operation in the drawing shows data “0”, that is, the threshold voltage Vth1 of MCN1 is higher than the threshold voltage Vth0 of MCN2. Under the condition that the word line WL = 0V and the restore control signal RESTORE = 0V in the flip-flop unit, the equalization control signal ZEQ is lowered from Vcc to 0V at time t0, so that nodeT and nodeB are equalized to the same potential. At time t1, the equalizing operation is terminated, and MLW, which is the gate potential of MCN1 and MCN2, is gradually increased from time t2, so that the MCN2 side having the lower threshold voltage is turned on first, and the potential of nodeB is lowered. Go. After a while, the MCN1 side also turns on, but finally the latch is determined when nodeB on the MCN2 side having a low threshold voltage is 0V and nodeT on the MCN1 side is Vcc. At time t3, MLW boosting is completed. At time t4, RESTORE is raised from 0V to Vcc to activate the latch of the flip-flop unit, to keep the data stable. Finally, at time t5, MLW is lowered to 0V. End.
Although the operation of the memory cell in the conventional example has been described above, the conventional configuration has the following problems.

  [1] The threshold voltage difference margin is small. The threshold voltage difference margin corresponds to Vth1−Vth0 for data “0” and Vth2−Vth1 for data “1”. The threshold voltage change amount in the hot carrier injection phenomenon has an upper limit value Vth_max. If the read margins of the data “0” and the data “1” are evenly distributed, each of the cases where one rewrite is assumed. The margin is (Vth_max−Vth0) / 2. When it is assumed that rewriting is performed N times, it is necessary to divide the Vth control into 2N with Vth_max as the maximum value, and the margin of each of the data “0” and data “1” is (Vth_max−Vth0) / 2N Thus, the margin is further reduced.

  [2] It is necessary to apply a high voltage (7 V and 5 V) to the word line WL and the bit lines BLT and BLB that need to be controlled for each memory cell as an operating voltage when writing data to the nonvolatile data storage unit There is. This means that it is necessary to use a high breakdown voltage transistor as a driver for driving the word line and the bit line and a column selection transistor for selecting the bit line. When operating at Vcc = 1.8 V as in the normal read operation, the high voltage transistor optimized for high voltage is not high speed, which causes an access delay. Increasing the transistor size in order to increase the current driving capability has the problem of increasing the chip area.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a rewritable nonvolatile memory device and a semiconductor integrated circuit device that can take a large read margin and can control a word line and a bit line at a Vcc level. To do.

[Nonvolatile semiconductor memory device]
The invention of claim 1 is a nonvolatile semiconductor memory device having a flip-flop configured by cross-connecting two inverters, and two gate transistors respectively connected to nodes on both sides of the flip-flop. ,
The inverter includes a load transistor and a storage transistor connected in series, and the storage transistor is configured by a storage transistor capable of controlling a threshold voltage by electron injection near the gate, and the two gate transistors include: Each bit line controlled between the operating power supply voltage and the ground voltage is connected, and the word line controlled between the operating power supply voltage and the ground voltage is common to the gate electrodes of the two gate transistors. Further, a high voltage supply line for supplying a high voltage at the time of writing or erasing is connected to the source of the storage transistor and the source of the load transistor.

  According to a second aspect of the invention, in the first aspect of the invention, the memory transistor has an insulating film side spacer formed on a side portion of the gate electrode and a low impurity concentration region formed on a peripheral portion of the drain. At the time of writing, a high voltage is applied to the source of the storage transistor, and a high voltage is applied to the gate of the storage transistor via the source of the load transistor, whereby channel hot electrons are applied to the insulating film side spacer. The information is written by injecting information, and at the time of erasing, a high voltage is applied to the source of the memory transistor to inject an avalanche hot hole into the insulating film side spacer to erase the information. .

  According to a third aspect of the invention, in the first and second aspects of the invention, the inverter has a precharge transistor in parallel with the load transistor, and the precharge transistor is separated from the load transistor by a precharge control voltage. It is characterized by being independently controlled on / off.

  According to a fourth aspect of the present invention, in the third aspect of the present invention, a high voltage supply line for supplying a high voltage to a source of the load transistor is provided separately for the two inverters.

  According to a fifth aspect of the present invention, in the third aspect of the present invention, a high voltage supply line for supplying a high voltage to the source of the storage transistor is provided separately for the two inverters.

  According to a sixth aspect of the present invention, in the fourth aspect of the present invention, the load transistor and the storage transistor connected in series are further connected between the load transistor and the storage transistor, and electrical connection between the load transistor and the storage transistor is turned on / off. The switch means is provided.

  According to a seventh aspect of the present invention, in the fifth aspect of the present invention, the load transistor and the storage transistor connected in series are further connected between the load transistor and the storage transistor, and electrical connection between the load transistor and the storage transistor is turned on / off. The switch means is provided.

  The invention of claim 8 is characterized in that, in the inventions of claims 1 to 7, the conduction resistances of the load transistors of the two inverters are unbalanced.

  According to a ninth aspect of the present invention, in the first to seventh aspects of the present invention, the capacitances of the two inverters with respect to the power supply voltage line or ground are unbalanced.

  According to a tenth aspect of the present invention, in the first to seventh aspects of the present invention, the conduction resistances of the memory transistors of the two inverters are unbalanced.

  In the embodiments to be described later, Embodiments 1 to 5 correspond to the inventions of claims 1 and 2. Embodiments 2 to 5 correspond to the invention of claim 3. Embodiments 2 and 4 correspond to the invention of claim 4. Embodiments 3 and 5 correspond to the invention of claim 5. Embodiment 4 corresponds to the invention of claim 6. Embodiment 5 corresponds to the invention of claim 7. The invention of claim 8 corresponds to the memorandums of FIGS. The invention of claim 9 corresponds to FIGS. 15, 32 and 50 of the first, second and third embodiments. The invention of claim 10 corresponds to FIGS. 14, 31, and 49 of the first, second, and third embodiments.

[State Determination Method for Nonvolatile Semiconductor Memory Device]
The invention of claim 11 uses the nonvolatile semiconductor memory device of claims 3 to 7 to increase the source voltage of the two memory transistors to turn off these memory transistors, via the precharge transistor, The method includes a step of applying a precharge voltage of the same voltage to the two storage transistors and a step of lowering the source voltages of the two storage transistors in synchronization.

  According to a twelfth aspect of the present invention, using the nonvolatile semiconductor memory device according to any one of the third to seventh aspects, the step of turning on the precharge transistor and applying the same precharge voltage to the two memory transistors, And a step of turning off the charging transistor to stop the application of the precharge voltage.

  According to a thirteenth aspect of the present invention, the non-volatile semiconductor memory device according to any one of the sixth and seventh aspects is used, the precharge transistor is turned on while the switch means is turned off, and the same voltage is applied to the two storage transistors. Applying the precharge voltage, turning on the switch means, and turning off the precharge transistor to stop the application of the precharge voltage.

  A fourteenth aspect of the present invention uses the nonvolatile semiconductor memory device according to any one of the first to seventh aspects, turns on the gate transistor while the source voltage of the two load transistors is low, and stores the two memories from the bit line. Applying a precharge voltage to the transistor; turning off the gate transistor to cut off the precharge voltage from the bit line; and raising the source voltage of the load transistor.

  According to a fifteenth aspect of the present invention, the state of the flip-flop is forced by turning on only one of the precharging transistors of the two inverters using the nonvolatile semiconductor memory device according to the third to seventh aspects. It is characterized by determining to.

  According to a sixteenth aspect of the present invention, using the nonvolatile semiconductor memory device according to the fourth or sixth aspect, the step of raising the source potential of the two storage transistors to turn off the two storage transistors, via the precharging transistor And a step of applying precharge voltages of different voltages to the two storage transistors, and a step of lowering the source potentials of the two storage transistors in synchronization.

  The invention of claim 17 uses the nonvolatile semiconductor memory device of claims 5 and 7 to raise the source potential of the two storage transistors to turn off the two storage transistors, via the precharging transistor. And a step of applying a precharge voltage of the same voltage to the two storage transistors, and a step of lowering the source potential of the two storage transistors with a potential difference.

  The invention according to claim 18 uses the nonvolatile semiconductor memory device according to any one of claims 3 to 7, and turns on one of the two precharge transistors and turns off the other, whereby a measurement voltage is applied to one of the memory transistors. It is characterized by supplying.

  A nineteenth aspect of the invention uses the nonvolatile semiconductor memory device according to the fifth and seventh aspects, and turns on one of the two precharging transistors and turns off the other, whereby a measurement voltage is applied to one of the storage transistors. And measuring voltage is supplied to the source of the other storage transistor.

  A twentieth aspect of the invention uses the nonvolatile semiconductor memory device according to the sixth and seventh aspects, and turns on one of the two precharge transistors and turns off the other, whereby a measurement voltage is applied to one of the storage transistors. And the switch means is turned off.

  In the embodiment described later, the invention of claim 11 corresponds to FIGS. 28, 46 and 65 of the second, third, and fourth embodiments. The invention of claim 12 corresponds to FIGS. 29, 47 and 66 of the second, third and fourth embodiments. The invention of claim 13 corresponds to FIG. 66 of the fourth embodiment. The invention of claim 14 corresponds to FIGS. 30, 48 and 67 of the second, third and fourth embodiments. The invention of claim 15 corresponds to FIGS. 25, 43 and 62 of the second, third and fourth embodiments. The invention of claim 16 corresponds to FIGS. 23 and 60 of the second and fourth embodiments. The invention of claim 17 corresponds to FIGS. 41 and 70 of the third and fifth embodiments. The invention of claim 18 corresponds to FIGS. 33, 51 and 68 of the second, third and fourth embodiments. The invention of claim 19 corresponds to FIG. 51 of the third embodiment. The invention of claim 20 corresponds to FIG. 68 of the fourth embodiment.

[Semiconductor integrated circuit memory device]
A twenty-first aspect of the invention includes the nonvolatile semiconductor memory device according to any one of the first to eighth aspects of the present invention, a repair target circuit, and a repair circuit that replaces the repair target circuit, and the nonvolatile memory device is replaced with the repair circuit. The present invention is characterized in that a storage circuit for repair information for specifying a circuit to be repaired is provided.

  A twenty-second aspect of the invention includes the nonvolatile semiconductor memory device according to any one of the first to eighth aspects, an analog circuit, and a constant trimming circuit that adjusts a circuit constant thereof, and the nonvolatile memory device is connected to the constant trimming circuit. An information storage circuit for specifying circuit constants is provided.

  A twenty-third aspect of the invention includes the nonvolatile semiconductor memory device according to any one of the first to eighth aspects, an oscillation circuit, and a frequency trimming circuit that adjusts an oscillation frequency thereof, and the nonvolatile memory device is included in the frequency trimming circuit. The information storage circuit is used to specify the oscillation frequency.

  A twenty-fourth aspect of the invention includes the nonvolatile semiconductor memory device according to any one of the first to eighth aspects, a reference voltage generation circuit, and a voltage trimming circuit that adjusts the generated reference voltage. An information storage circuit for specifying the reference voltage of the trimming circuit is provided.

  A twenty-fifth aspect of the invention includes the nonvolatile semiconductor memory device according to the first to eighth aspects and a security circuit for specifying a chip, and the non-volatile memory device is stored with information for specifying a chip of the security circuit. It is a memory circuit.

  In the embodiment described later, the seventh embodiment corresponds to the invention of claim 21. The sixth embodiment corresponds to the inventions of claims 22, 23, 24, and 25.

  In the present invention, the threshold voltage of the storage transistor is controlled, that is, a high voltage necessary for writing and erasing is supplied via a high voltage supply line connected to both ends of the inverter (the source of the load transistor and the source of the storage transistor). Do.

  As a result, according to the first aspect of the present invention, the word line can be used at the time of writing to increase the threshold voltage of the storage transistor of one inverter and at the time of erasing to decrease the threshold voltage of the written storage transistor. The bit lines need only be operated at the Vcc level, and the peripheral circuits can be downsized and read at high speed.

  In the present invention, a precharging transistor is provided in parallel with the load transistor. As a result, both nodes can be charged without changing the state of the flip-flop, and the state of the flip-flop can be determined by the unbalanced decrease in the charged voltage, so that the determination of the state is ensured. It becomes possible to do.

  In the present invention, a high voltage supply line for supplying a high voltage to the source of the load transistor or a high voltage supply line (source line) for supplying a high voltage to the source of the storage transistor is separately provided for the two inverters. As a result, a potential difference can be applied between the two inverters at the transition of the charging voltage of the two nodes constituting the flip-flop or the voltage after charging, and the state of the flip-flop in which both storage transistors are not written can be obtained. You can be sure of either.

  In the present invention, when writing is performed to any one of the storage transistors, the state is determined according to the writing to the storage transistor regardless of the potential difference between the charging voltage or the transition voltage. As a result, in a storage device in which a plurality of nonvolatile semiconductor storage devices (memory cells) are arranged in an array, writing can be performed even if memory cells where writing is performed and memory cells where writing is not performed are mixed. The state of the memory cell that is being performed is determined according to the writing, and the memory cell that is not being written is surely determined to be in one specific state according to the potential difference. Accordingly, even in a storage device in which a memory cell in which writing is performed and a memory cell in which writing is not performed are mixed, data does not become indefinite.

  In the present invention, the conduction resistances of the two load transistors are unbalanced. The conduction resistance of the transistor can be easily realized by changing the channel width or the channel length. In the present invention, the capacitances of the two inverters with respect to Vcc or ground are unbalanced. With the above unbalanced configuration, the rise in node potential when the power is supplied to the flip-flop becomes unbalanced, and the state branch point shifts to either one. Either one can be confirmed.

[First Embodiment]
A nonvolatile memory device according to a first embodiment and a semiconductor integrated circuit device including the nonvolatile memory device will be described with reference to FIGS.

  FIG. 5 is a circuit diagram of one nonvolatile memory cell of the nonvolatile memory device. This memory cell is composed of six MOS transistors. Static latch connection of an inverter (True side inverter) in which P-type MOS transistor MP1 and N-type MOS transistor MCN1 are connected in series and an inverter (Bar side inverter) in which P-type MOS transistor MP2 and N-type MOS transistor MCN2 are connected in series Flip-flops. Among these, the P-type MOS transistors MP1 and MP2 are called load transistors, and the N-type MOS transistors MCN1 and MCN2 are called storage transistors. The storage transistors MCN1 and MCN2 function as non-volatile elements that can change the threshold value in a non-volatile manner by accumulating and neutralizing charges in the sidewall portion, as will be described with reference to FIG.

  Among the flip-flops, an inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the True side, and an inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the Bar side. To do. A connection portion between the load transistor MP1 and the storage transistor MCN1 is nodeT, and a connection portion between the load transistor MP2 and the storage transistor MCN2 is nodeB. When nodeT is high potential and nodeB is low potential, the stored content is “0”, and when nodeT is low potential and nodeB is high potential, the stored content is “1”.

  The storage transistor side end of each inverter, that is, the source of the storage transistors MCN1 and MCN2, is connected to the source line SL. Load transistor side ends of the inverters, that is, the sources of the load transistors MP1 and MP2, are connected to the VPS line. The wells of the load transistors MP1 and MP2 are connected to the VPM line.

  The node T is connected to the bit line BLT (BitLine-True) via the transfer gate MN1, and the node B is connected to the bit line BLB (BitLine-Bar) via the transfer gate MN2. The transfer gates MN1 and MN2 are composed of N-type MOS transistors, and a common word line WL is connected to each gate.

  FIG. 6 is a diagram showing a configuration of a memory cell array in which the nonvolatile memory cells shown in FIG. 5 are arranged in an array. In this memory cell array, the nonvolatile memory cells of FIG. 5 are arranged in an X and Y matrix array. A word line WL is provided for each row (row), and one bit line BLT, BLB is provided for each column (column). These word lines WL and bit lines BLT and BLB are controlled independently. On the other hand, the other signal lines (VPS, VPM, SL) are provided in common to all the memory cells, and all the memory cells in the array are integrally controlled.

  7, 9 and 12 are diagrams showing a cross-sectional structure of the memory transistor MCN1 (MCN2). 7 shows the potential arrangement at the time of writing, FIG. 9 shows the potential arrangement at the time of erasing, and FIG. 12 shows the potential arrangement at the time of reading.

  8 is a diagram showing a voltage application procedure of the memory cell at the time of writing to the memory transistor MCN1, and FIG. 10 is a diagram showing a voltage application procedure at the time of erasing the nonvolatile memory cell including the memory transistors MCN1 and MC2. 13 is a diagram showing a voltage application procedure at the time of reading from a nonvolatile memory cell including the memory transistors MCN1 and MCN2. It is.

7, 9, and 12, a P-type well 104 having a depth of 0.8 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is formed in the surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm. . In this P-type well 104, two storage transistors MCN1 and MCN2 separated by a plurality of trenches (element isolation) 102 having a depth of 250 nm are formed. In this figure, only one storage transistor (MCN1) is shown.

The storage transistor is an N-channel transistor, and has a drain 109 and a source 115 formed adjacent to the trench 102 on both sides in the surface region of the P-type well 104 and a drain extension formed in the peripheral region of the drain 109. 107. The drain 109 and the source 115 are each formed with an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , and the drain extension 107 is formed with an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ .

On the substrate of the channel region, which is the region between the drain 109 and the source 115 on the surface of the P-type well 104, a gate oxide film 105 with a thickness of 5 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻ with a thickness of 200 nm. ^A gate electrode 106 made of ³ polysilicon film is formed. Further, side spacers 108 and 108S made of an insulating film having a thickness of 50 nm are formed on both sides of the gate oxide film 105 and the gate electrode 106. Since no extension region is formed around the source 115, the side spacer 108S on the source side is exposed to the channel region of the substrate.

In the region of the P-type well 104, the region separated from the memory transistor by the trench 102 has an average boron concentration of 1 × 10 ²⁰ cm ⁻³ that is an electrode for grounding the P-type well 104. A P-type diffusion layer 111 is formed.

  In this memory transistor, the threshold voltage can be increased by injecting carriers into the side spacer 108S on the source side. Further, as will be described with reference to FIG. 9, the threshold voltage can be returned to the initial state by extracting the carrier injected into the side spacer 108S. As a result, the storage transistor stores data in a nonvolatile manner.

  Note that the standard initial threshold voltage of the memory transistor is 1.2 V. However, since the transistor has a special structure, the variation is large, and it is difficult to use the memory transistor alone as a memory element from the viewpoint of reliability. It is. Therefore, in this embodiment, the memory cell is configured with the flip-flop configuration shown in FIG.

  As shown in FIG. 7, in the write operation to the storage transistor, 0V is applied to the drain line VD, a positive voltage (for example, 6V) below the junction breakdown voltage is applied to the source line VS, and channel hot electrons HE are changed to the side spacers 108S. It is the operation to inject. The threshold voltage rises due to the electrons trapped in the side spacer 108S due to the injection of channel hot electrons, and a write state is established.

  FIG. 8 is a diagram showing a voltage application procedure when data “0” is written by raising the threshold voltage of the memory transistor MCN1. In order to make the memory transistor MCN1 have the potential arrangement shown in FIG. 7, a voltage is applied to the memory cell by the procedure shown in FIG. Under the condition that VPS, VPM, and SL are set to 6V, the word line WL is set to Vcc (1.8V), the bit line BLT is set to 0V, and BLB is set to Vcc. When the transfer gate MN1 which is an N-type MOS transistor is turned on, the node T (the drain of the storage transistor MCN1) becomes substantially the same potential as the bit line BLT (0 V), and the load transistor MP2 is thereby turned on. The gate of the storage transistor MCN1 becomes substantially the same potential as VPS (6V). Thereby, the potential arrangement of the memory transistor MCN1 becomes the same as that in FIG. At this time, a current of about 300 μA flows through the transfer gate MN1 and the storage transistor MCN1, thereby raising the threshold voltage of the storage transistor MCN1 to Vth2.

  When data “1” is written, the threshold voltage on the memory transistor MCN2 side is increased. However, only the voltage setting is reversed to BLT = Vcc and BLB = 0V, and other conditions are set to data “0”. "Same as writing.

  In the above embodiment, 6V is applied to the gate (nodeB) of the transistor MCN1 and 6V is applied to the drain (source line SL) of the transistor MCN1, but these voltages may be different voltages. On the other hand, since VPM and VPS are the same voltage, these signals may be connected to form a common signal.

  9 and 10 are diagrams showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). As shown in FIG. 9, in the erasing operation, a positive voltage (for example, 9 V) lower than the junction breakdown voltage is applied to the source line VS, 0 V is applied to the gate line VG and the drain line VD, and the avalanche hot hole is applied from the source electrode 115. In this operation, HH is generated and injected into the side spacer 108S. As a result, the electrons trapped in the side spacer 108S in the write operation are neutralized, and the written data is erased by lowering the threshold voltage.

  FIG. 10 is a diagram showing a voltage application procedure when data is erased by lowering the threshold voltages of the memory transistors MCN1 and MCN2. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 9, a voltage is applied to the memory cell by the procedure shown in FIG. In general, the erase operation is performed collectively for all the memory cells of the memory array shown in FIG. Under the condition that VPM is set to Vcc, VPS is set to 0V, and SL is set to 9V, the word line WL is set to Vcc, and the bit lines BLT and BLB are set to 0V. When the transfer gates MN1 and MN2 which are N-type MOS transistors are turned on, nodeT and nodeB become 0V, and the voltages of the respective parts of the storage transistors MCN1 and MCN2 become the same as those shown in FIG. In FIG. 10, VPM is set to Vcc (1.8V), but the signal operates normally even at 0V. Therefore, the VPM may be connected to the VPS and used as a common signal.

  Thus, in the voltage application procedure at the time of writing shown in FIGS. 7 and 8 and the voltage application procedure at the time of erasing shown in FIGS. 9 and 10, word lines and bit lines that require independent control for each memory cell. In other words, a high voltage transistor is used for the word line and bit line control circuit because it is not necessary to apply a high voltage to the word line and bit line. There is no need, and high-speed transistors that operate at high speed can be used to speed up the read operation.

  FIG. 11 is a diagram for explaining threshold voltages set in the memory transistors MCN1 and MCN2 by the write operation, that is, a diagram for explaining a data setting method for a nonvolatile memory cell. Here, when the threshold voltage of the storage transistor MCN1 is low (on) and the threshold voltage of the storage transistor MCN2 is high (off), the data is “1” and the threshold of the storage transistor MCN1 When the voltage is high (off) and the threshold voltage of the storage transistor MCN2 is low (on), the data is “0”.

  FIG. 6A shows a case before data setting, that is, when the threshold voltages of the storage transistors MCN1 and MCN2 are both in the initial state Vth0. In this state, the state of the memory cell is indefinite.

  FIG. 5B shows the threshold voltage when data “0” is set in the nonvolatile memory cell. Writing of data “0” is realized by raising the threshold voltage of the storage transistor MCN1 from the initial state in FIG. 5A to Vth2 (Vth2> Vth0).

  FIG. 3C shows the threshold voltage when data “1” is set in the nonvolatile memory cell. Writing of data “1” is realized by raising the threshold voltage of the memory transistor MCN2 from the initial state of FIG. 5A to Vth2 (Vth2> Vth0).

  When the erase operation described with reference to FIGS. 9 and 10 is performed, the state shown in FIG. 9A is restored even if the threshold voltage is controlled as shown in FIGS.

  As described above, since the memory cell can be lowered to the initial state Vth0 again even if the threshold voltages of the storage transistors MCN1 and MCN2 are increased, the memory cell is used for an application that requires a plurality of data rewrites. However, a read margin that is the difference between the threshold voltages on the True side (storage transistor MCN1) and the Bar side (storage transistor MCN2) can be sufficiently large.

  12 and 13 are diagrams showing a voltage application procedure at the time of reading from the nonvolatile memory cell. As shown in FIG. 12, the storage contents of the memory cell according to the first embodiment are read by reading the voltage of the drain line VD when the source line VS is set to 0 V and Vcc is applied to the gate line VG. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 12, a voltage is applied to the memory cell in the procedure shown in FIG. The read operation uses a differential sense amplifier as in the SRAM read operation. Under the condition that VPS and VPM are set to Vcc, SL is set to 0 V, and the word line WL is set to Vcc, the change of the bit lines BLT and BLB corresponding to the data in the flip-flop is read by the differential sense amplifier. When the storage transistor MCN1 is on, BLT is at a low voltage (0V), and when the storage transistor MCN1 is off, BLT is at a high voltage (Vcc). When the storage transistor MCN2 is on, BLB is at a low voltage (0V), and when the storage transistor MCN2 is off, BLB is at a high voltage (Vcc). Data is "1" when BLT is low voltage (0V) and BLB is low voltage (Vcc), and data is "0" when BLT is high voltage (Vcc) and BLB is low voltage (0V).

[Modification of First Embodiment]
In the nonvolatile memory cell shown in FIG. 6, data is not determined in a state where writing is not performed, that is, in a state where the threshold voltages of the storage transistors MCN1 and MCN2 are both low. Therefore, as shown in FIGS. 14 and 15, the circuit configuration on the True side (storage transistor MCN1 side) and the Bar side (storage transistor MCN2 side) are unbalanced to start up even in a state where writing is not performed. Sometimes data can be fixed to either "0" or "1".

  In the nonvolatile memory cell shown in FIG. 14, the channel widths of the two load transistors MP1 and MP2 are unbalanced. In this example, the channel width of the load transistor MP1 (indicated by a thick line) is twice the channel width of the load transistor MP2, and the resistance value when the load transistor MP1 is on is compared with the resistance value when the load transistor MP2 is on. It is made to become 1/2.

  When the memory cell of this configuration is turned on when neither of the storage transistors MCN1 and MCN2 is written, the potential of nodeT rises faster than that of nodeB, and the load transistor MP1 and storage transistor MCN2 are turned on. The load transistor MP2 and the storage transistor MCN1 are in the off state, that is, the data becomes “0” and is stabilized.

  Note that the channel length may be unbalanced instead of making the channel width unbalanced. Further, the load transistor for changing the channel width or the channel length may be either MP1 or MP2. Further, the channel widths or channel lengths of the storage transistors MCN1 and MCN2 may be changed to be unbalanced.

  The nonvolatile memory cell shown in FIG. 15 is obtained by connecting capacitors to two nodeT and nodeB of a flip-flop. A capacitor C1 is connected between the node T and the power supply line Vcc, and a capacitor C2 is connected between the node B and the ground. The capacitance of these capacitors is about 50 fF, for example.

  As a result, when the power is turned on without writing / erasing to any of the two memory transistors MCN1 and MCN2, the potential rise of nodeT immediately after power-on is rapid and the potential rise of nodeB is slow. Therefore, the load transistor MP1 and the storage transistor MCN2 are in the on state, the load transistor MP2 and the storage transistor MCN1 are in the off state, that is, the data becomes “0” and is stabilized.

  In the example shown in FIG. 15, the capacitor is connected to both nodeT and nodeB, but the circuit configuration of the nonvolatile memory cell can be made asymmetric even if it is connected to only one of them.

[Second Embodiment]
A nonvolatile memory device according to a second embodiment and a semiconductor integrated circuit device including the nonvolatile memory device will be described with reference to FIGS.

  FIG. 16 is a circuit diagram of one nonvolatile memory cell of the nonvolatile memory device. This memory cell is a VPS-divided nonvolatile memory cell composed of 8 transistors. This memory cell includes an inverter (True side inverter) in which a P-type MOS transistor MP1 and an N-type MOS transistor MCN1 are connected in series, and an inverter (Bar-side inverter) in which a P-type MOS transistor MP2 and an N-type MOS transistor MCN2 are connected in series. ) In a static latch connection. Among these, the P-type MOS transistors MP1 and MP2 are called load transistors, and the N-type MOS transistors MCN1 and MCN2 are called storage transistors. The storage transistors MCN1 and MCN2 function as non-volatile elements that can change the threshold value in a non-volatile manner by accumulating and neutralizing charges in the sidewall portion, as will be described with reference to FIG.

  The storage transistor side end of each inverter, that is, the source of the storage transistors MCN1 and MCN2, is connected to the source line SL. The load transistor side end of the True side inverter, that is, the source of the load transistor MP1 is connected to the VPST line, and the load transistor side end of the Bar side inverter, that is, the source of the load transistor MP2 is connected to the VPSB line.

  Among the flip-flops, an inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the True side, and an inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the Bar side. To do. A connection portion between the load transistor MP1 and the storage transistor MCN1 is nodeT, and a connection portion between the load transistor MP2 and the storage transistor MCN2 is nodeB. When nodeT is high potential and nodeB is low potential, the stored content is “0”, and when nodeT is low potential and nodeB is high potential, the stored content is “1”.

  The node T is connected to the bit line BLT (BitLine-True) via the transfer gate MN1, and the node B is connected to the bit line BLB (BitLine-Bar) via the transfer gate MN2. The transfer gates MN1 and MN2 are composed of N-type MOS transistors, and a common word line WL is connected to each gate.

  Further, a P-type MOS transistor MP3, which is a precharging transistor, is connected in parallel to the load transistor MP1, that is, between nodeT and VPST. A P-type MOS transistor MP4, which is a precharging transistor, is connected in parallel with the load transistor MP2, that is, between nodeB and VPSB. A T-side precharge line PRET is connected to the gate of the P-type MOS transistor MP3, and a B-side precharge line PREB is connected to the gate of the P-type MOS transistor MP4. All the P-type MOS transistors MP1 to MP4 are formed in the same N well, and the N well potential is controlled by the VPM signal.

  FIG. 17 is a diagram showing a configuration of a memory cell array in which the nonvolatile memory cells shown in FIG. 16 are arranged in an array. In this memory cell array, the nonvolatile memory cells of FIG. 16 are arranged in an X and Y matrix array. A word line WL is provided for each row (row), and one bit line BLT, BLB is provided for each column (column). These word lines WL and bit lines BLT and BLB are controlled independently. On the other hand, the other signal lines (PREB, PRET, VPST, VPSB, VPM, SL) are provided in common to all the memory cells, and all the memory cells in the array are integrally controlled.

  18, FIG. 20, and FIG. 26 are diagrams showing the structure of the memory transistor MCN1 (MCN2) on the semiconductor substrate. 18 shows the potential arrangement at the time of writing, FIG. 20 shows the potential arrangement at the time of erasing, and FIG. 26 shows the potential arrangement at the time of reading.

  FIG. 19 is a diagram showing a voltage application procedure at the time of writing to the memory transistor MCN1. FIG. 21 is a diagram showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). FIG. 27 is a diagram showing a voltage application procedure at the time of reading from a nonvolatile memory cell.

In FIG. 18, a P-type well 104 having a depth of 0.8 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is formed in the surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm. In this P-type well 104, two storage transistors MCN1 and MCN2 separated by a plurality of trenches (element isolation) 102 having a depth of 250 nm are formed. In this figure, only one storage transistor (MCN1) is shown.

The storage transistor is an N-channel transistor, and has a drain 109 and a source 115 formed adjacent to the trench 102 on both sides in the surface region of the P-type well 104 and a drain extension formed in the peripheral region of the drain 109. 107. The drain 109 and the source 115 are each formed with an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , and the drain extension 107 is formed with an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ .

On the substrate of the channel region, which is the region between the drain 109 and the source 115 on the surface of the P-type well 104, a gate oxide film 105 with a thickness of 5 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻ with a thickness of 200 nm. ^A gate electrode 106 made of ³ polysilicon film is formed. Further, side spacers 108 and 108S made of an insulating film having a thickness of 50 nm are formed on both sides of the gate oxide film 105 and the gate electrode 106. Since no extension region is formed around the source 115, the side spacer 108S on the source side is exposed to the channel region of the substrate.

In the region of the P-type well 104, the region separated from the memory transistor by the trench 102 has an average boron concentration of 1 × 10 ²⁰ cm ⁻³ that is an electrode for grounding the P-type well 104. A P-type diffusion layer 111 is formed.

  In this memory transistor, the threshold voltage can be increased by injecting carriers into the side spacer 108S on the source side. Further, as will be described with reference to FIG. 20, the threshold voltage can be returned to the initial state by extracting the carrier injected into the side spacer 108S. As a result, the storage transistor stores data in a nonvolatile manner.

  Note that the standard initial threshold voltage of the memory transistor is 1.2 V. However, since the transistor has a special structure, the variation is large, and it is difficult to use the memory transistor alone as a memory element from the viewpoint of reliability. It is. Therefore, in this embodiment, the memory cell is configured with the flip-flop configuration shown in FIG.

  As shown in FIG. 18, in the write operation, 0 V is applied to the drain line VD, a positive voltage (for example, 6 V) lower than the junction breakdown voltage is applied to the source line VS, and channel hot electrons HE are injected into the side spacer 108S. Is the action. The threshold voltage rises due to electrons trapped in the side spacer 108S due to the injection of channel hot electrons, and the memory transistor enters a writing state.

  FIG. 19 is a diagram showing a voltage application procedure when data “0” is written by increasing the threshold voltage of the memory transistor MCN1. In order to make the memory transistor MCN1 have the potential arrangement shown in FIG. 18, a voltage is applied to the memory cell by the procedure shown in FIG. Under the condition that PREB, PRET, VPST, VPSB, VPM, SL are set to 6V, the word line WL is set to Vcc, the bit line BLT is set to 0V, and the BLB is set to Vcc. When the transfer gate MN1 which is an N-type MOS transistor is turned on, the node T (the drain of the storage transistor MCN1) becomes substantially the same potential as the bit line BLT (0 V), and the load transistor MP2 is thereby turned on. The gate of the storage transistor MCN1 becomes substantially the same potential as VPSB (6V). Thereby, the potential arrangement of the memory transistor MCN1 becomes the same as that in FIG. At this time, a current of about 300 μA flows through the transfer gate MN1 and the storage transistor MCN1, thereby raising the threshold voltage of the storage transistor MCN1 to Vth2.

  When data “1” is written, the threshold voltage on the memory transistor MCN2 side is increased. However, only the voltage setting is reversed to BLT = Vcc and BLB = 0V, and other conditions are set to data “0”. "Same as writing.

  In the above embodiment, 6V is applied to the gate (nodeB) of the transistor MCN1 and 6V is applied to the drain (source line SL) of the transistor MCN1, but these voltages may be different voltages. In FIG. 19, since PREB and PRET are the same voltage, they can be used as a common signal (for example, PRE signal). Furthermore, since VPSB and VPST have the same voltage, they can be a common signal (for example, a VPS signal). Furthermore, since VPM is the same voltage as VPS, a common signal including this may be used.

  20 and 21 are diagrams showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). As shown in FIG. 20, in the erasing operation, a positive voltage (for example, 9V) lower than the junction breakdown voltage is applied to the source line VS, 0V is applied to the gate line VG and the drain line VD, and the avalanche hot hole is applied from the source electrode 115. In this operation, HH is generated and injected into the side spacer 108S. As a result, the electrons trapped in the side spacer 108S in the write operation are neutralized, and the written data is erased by lowering the threshold voltage.

  FIG. 21 is a diagram showing a voltage application procedure when data is erased by lowering the threshold voltages of the memory transistors MCN1 and MCN2. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 20, a voltage is applied to the memory cell in the procedure shown in FIG. In general, the erase operation is performed on all the memory cells of the memory array shown in FIG. PREB, PRET, VPM are set to Vcc, VPST, VPSB are set to 0V, and SL is set to 9V, the word line WL is set to Vcc, and the bit lines BLT, BLB are set to 0V. When the transfer gates MN1 and MN2 which are N-type MOS transistors are turned on, nodeT and nodeB become 0V, and the potential arrangement of the storage transistors MCN1 and MCN2 is the same as that in FIG. In FIG. 21, since PREB and PRET are the same voltage, they can be used as a common signal (for example, PRE signal). Furthermore, since VPSB and VPST have the same voltage, they can be a common signal (for example, a VPS signal). Further, since the VPM operates normally even when the VPM is set to 0 V, the VPM may be connected to the VPS and used as a common signal.

  As described above, the voltage application procedure at the time of writing shown in FIGS. 18 and 19 and the voltage application procedure at the time of erasing shown in FIGS. 20 and 21 are the same as the word lines that require independent control for each memory cell. Because it is designed to apply 0V or Vcc to the bit line, that is, it is not necessary to apply a high voltage to the word line and bit line, high voltage transistors are used in the word line and bit line control circuits. Therefore, the reading operation can be speeded up using a high-performance transistor that operates at high speed.

  FIG. 22 is a diagram for explaining threshold voltages set in the memory transistors MCN1 and MCN2 by the write operation, that is, a diagram for explaining a data setting method for a nonvolatile memory cell. Here, when the threshold voltage of the storage transistor MCN1 is low (on) and the threshold voltage of the storage transistor MCN2 is high (off), the data is “1” and the threshold of the storage transistor MCN1 When the voltage is high (off) and the threshold voltage of the storage transistor MCN2 is low (on), the data is “0”.

  FIG. 6A shows a case before data setting, that is, when the threshold voltages of the storage transistors MCN1 and MCN2 are both in the initial state Vth0. Even in this state, the state of the nonvolatile memory cell is determined to be data “1” by the procedure shown in FIG.

  FIG. 5B shows the threshold voltage when data “0” is set in the nonvolatile memory cell. Writing of data “0” is realized by raising the threshold voltage of the storage transistor MCN1 from the initial state in FIG. 5A to Vth2 (Vth2> Vth0).

  FIG. 3C shows the threshold voltage when data “1” is set in the nonvolatile memory cell. Writing of data “1” is realized by raising the threshold voltage of the storage transistor MCN2 from the initial state of FIG.

  When the erase operation described with reference to FIGS. 20 and 21 is performed, the state shown in FIG. 20A is restored even if the threshold voltage is controlled as shown in FIGS.

  Thus, since this memory cell can be lowered again to the initial state Vth0 even if the threshold voltages of the storage transistors MCN1 and MCN2 are increased, both the storage transistors MCN1 and MCN2 are in the initial state Vth0. Even in this case, since the data can be forcibly determined to be “1”, the True side (the storage transistor MCN1) and the Bar side (the storage transistor MCN2) can be used for applications that require a plurality of data rewrites. The read margin, which is the difference between the threshold voltages, can be made sufficiently large.

  By the writing operation shown in FIGS. 18 and 19, writing can be performed to one of the storage transistors MCN1 and MCN2, and data “1” or “0” can be written to the memory cell. On the other hand, when no data is written in the memory cell in the initial state, that is, in the storage transistors MCN1 and MCN2, both of the threshold voltages of the storage transistors MCN1 and MCN2 are in the initial state Vth0. The memory content of the memory cell is indefinite. However, by applying a voltage to the memory cell in the initial state according to the following procedure, the memory content of this memory cell can be determined to be “1” or “0”.

  FIG. 23 is a diagram illustrating a voltage application procedure for determining data in the nonvolatile memory cell according to the second embodiment. In this procedure, when the stored content of the nonvolatile memory cell is “1” or “0”, the state of the memory cell (flip-flop) is set according to the stored content, and when the memory cell is in the initial state, This is an operation for forcibly fixing the data to “1”. In a memory array in which a plurality of memory cells are arranged, if the memory contents are "1" and "0" and the memory cells in the initial state coexist, this procedure is collectively applied to all the memory cells in the memory array. By doing so, the state of the flip-flop is set according to the stored content for the memory cell whose stored content is “1” or “0”, and the state of the flip-flop is set for the memory cell in the initial state. Forced to "1". This procedure is executed when the memory is activated.

  The procedure shown in FIG. 23 is as follows. This procedure is performed under the condition that the word line WL and the bit lines BLT and BLB are set to 0V. First, at time t0, the source potential SL is raised from 0 V to Vcc, and the storage transistors MCN1 and MCN2 are turned off. At time t1, the precharge transistors MP3 and MP4 are turned on by lowering the precharge control signals PRET and PREB from Vcc to 0V. At the same time, among the precharge voltages set to Vcc, the True-side precharge voltage VPST is lowered by ΔV (voltage sufficiently smaller than Vth2−Vth0, for example, 0.2V). As a result, the precharge voltages of nodeT and nodeB are also Vcc−ΔV and Vcc, respectively, and the source-drain voltage of the storage transistor MCN2 becomes higher by ΔV than the source-drain voltage of the storage transistor MCN1. Thereby, the apparent threshold voltage on the memory transistor MCN2 side can be increased by ΔV.

  At time t2, PRET and PREB are returned to Vcc, and from time t3, the source potential SL is gradually lowered toward 0V. At this time, when the memory content of the memory cell is “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so that nodeT is first lowered to 0V, and nodeB is Vcc−ΔV Thus, the data of the flip-flop is fixed to “1”. On the other hand, when the memory content of the memory cell is “0”, even if the threshold voltage increases by ΔV, the threshold voltage of the memory transistor MCN2 is still lower than the threshold voltage of the memory transistor MCN1. Since the memory transistor MCN2 is turned on first, nodeB is first pulled down to 0V, nodeT becomes Vcc, and the data of the flip-flop is determined to be "0".

Further, when the memory content of the memory cell is “undefined”, that is, when the threshold voltages of MCN1 and MCN2 are both Vth0, the apparent threshold voltage of the memory transistor MCN1 is the threshold voltage of the memory transistor MCN2. Since it is lower than the voltage by ΔV, MCN1 is turned on earlier than MCN2, nodeT is first pulled down to 0V, nodeB becomes Vcc−ΔV, and the flip-flop data is determined to be “1”.
VPST is returned to Vcc at time t4 after the state of the flip-flop is determined.

  A memory cell in which the threshold voltages of MCN1 and MCN2 are both Vth0 is often a cell that has not yet been written or rewritten. In such a memory cell, there is no deterioration of the transistor due to rewriting. For the setting of, only the initial threshold voltage variation of the transistor needs to be considered. Therefore, for example, about 0.2V is considered sufficient.

  The voltage application procedure shown in FIG. 23 is a procedure for determining the memory cell in the initial state as data “1”. However, in the source potential control of the P-type MOS transistor, the voltage of VPSB is reduced by ΔV instead of VPST. By doing so, it is possible to determine the memory cell in the initial state as data “0”. In FIG. 23, since PREB and PRET have the same voltage waveform, they can be a common signal (for example, a PRE signal).

  FIG. 24 is a diagram for explaining a data determination margin when the voltage application procedure shown in FIG. 23 is performed. In the initial state where both the threshold voltages of MCN1 and MCN2 are Vth0, as described above, the apparent threshold voltage on the MCN2 side can be obtained by making the precharge voltage of nodeT lower by ΔV than nodeB. Is increased by ΔV to forcibly recognize the data as “1”. In a memory cell in which data “0” has already been written, the margin decreases by ΔV. However, if Vth2−Vth0 = 1V and ΔV = 0.2V, the margin becomes 0.8V. . In the memory cell in which data “1” has already been written, the margin is increased by ΔV. If Vth2−Vth0 = 1V and ΔV = 0.2V, the margin is 1.2V. It becomes.

  FIG. 25 is a diagram for explaining a voltage application procedure for determining data for a memory cell in an initial state. That is, the procedure of FIG. 23 is a procedure for determining the data of each memory cell collectively in a memory array in which memory cells with stored contents “1” and “0” and an initial state memory cell coexist. The procedure shown in FIG. 25 forcibly fixes the data in the memory cell to “1” or “0” regardless of the stored contents of each memory cell.

  This procedure should be executed on the memory array in a batch in both cases where there are mixed data memory cells and memory cells in the initial state, or if all memory cells are in the initial state. Thus, the data of the memory cell can be determined to be “1” or “0”. The following description shows a procedure for forcibly determining the stored contents of the memory cell in the initial state to “1”.

  Under the condition that the word line WL and the bit lines BLT and BLB are set to 0V, first, the source potential SL is raised from 0V to Vcc at time t0 to turn off MCN1 and MCN2, and at time t1, the precharge control signal PREB, PRET and the source potential VPST of the precharge transistor MP3 are lowered from Vcc to 0V. Thereby, nodeB is charged to Vcc by the precharge transistor MP4, and nodeT is discharged through the precharge transistor MP3. At time t2, PREB and PRET are returned to Vcc, and at time t3, SL is changed from Vcc to 0V. At this time, MCN1 having a higher gate potential is turned on earlier than MCN2, so that nodeT is lowered to 0V while nodeB is held at Vcc, and the data in the flip-flop is determined to be "1". To do. At time t4, VPST is returned to Vcc.

  The procedure shown in FIG. 25 is a procedure for forcibly confirming the stored contents of the memory cell to “1”, but it can also be forcibly determined to “0”. That is, by dropping the source potential VPSB of the precharge transistor MP4 from Vcc to 0V instead of the source potential VPST of the precharge transistor MP3 at time t1, nodeB is discharged and the data is determined to be “0”. In FIG. 25, since PREB and PRET have the same voltage waveform, they can be a common signal (for example, a PRE signal).

  By executing the procedure of FIG. 23 or FIG. 25, even if there is an initial state memory cell in which both of the two storage transistors MCN1 and MCN2 are in the initial state Vth0, the stored content is uniquely “1” or It can be fixed to “0”.

  When this nonvolatile memory cell is used in place of a fuse, if the stored content is uniquely determined to be “1”, the state before the fuse is blown (data “1” is maintained in the initial state). Response).

  26 and 27 are diagrams showing a voltage application procedure at the time of reading from the nonvolatile memory cell. As shown in FIG. 26, the memory contents of the second embodiment are read by reading the voltage of the drain line VD when the source line VS is 0 V and Vcc is applied to the gate line VG. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 26, a voltage is applied to the memory cell in the procedure shown in FIG. The read operation uses a differential sense amplifier as in the SRAM read operation. Under the condition that PREB, PRET, VPST, VPSB, and VPM are set to Vcc, SL is set to 0 V, and the word line WL is set to Vcc, the change of the bit lines BLT and BLB according to the data in the flip-flop is differential type. Read with a sense amplifier. The data is "1" when BLT is low voltage (0V) and BLB is low voltage (Vcc), and the data is "0" when BLT is high voltage (Vcc) and BLB is low voltage (0V). In FIG. 27, since PREB and PRET are the same voltage, they can be a common signal (for example, a PRE signal). Furthermore, since VPSB and VPST have the same voltage, they can be a common signal (for example, a VPS signal). Furthermore, since VPM and VPS are the same voltage, they may be connected to form a common signal.

  The data determination procedure shown in FIG. 25 forces the initial state memory cells (memory transistors MCN1 and MCN2 both in the initial state (threshold voltage = Vth0)) to exist. This was a procedure that could be fixed to “1”. When there is no memory cell in the initial state, or when the data value of the memory cell in the initial state may be indefinite, the determination procedure shown in FIGS. 28 to 30 can be used. In this determination procedure, the decrease in the determination margin of ΔV (see FIG. 24) as in the procedure shown in FIG. 23 does not occur.

  The data confirmation procedure shown in FIG. 28 is as follows. This procedure is performed under the condition that the word line WL and the bit lines BLT and BLB are set to 0 V and VPST, VPSB and VPM are set to Vcc. First, at time t0, the source potential SL is raised from 0 V to Vcc, and the storage transistors MCN1 and MCN2 are turned off. At time t1, the precharge control signals PRET and PREB are lowered from Vcc to 0V, the precharge transistors MP3 and MP4 are turned on, and nodeT and nodeB are precharged to Vcc. At time t2, PRET and PREB are returned to Vcc to complete the precharge. From time t3, the source potential SL is slowly lowered toward 0V. At this time, in the case of data “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so nodeT is first pulled down to 0V, nodeB becomes Vcc, and the flip-flop data is “1” is confirmed. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage is turned on earlier than MCN1, so that nodeB is first pulled down to 0V, nodeT becomes Vcc, and the flip-flop data is “ Confirm 0 ". In FIG. 28, since PREB and PRET have the same voltage waveform, they can be used as a common signal (for example, PRE signal). Furthermore, since VPSB and VPST have the same voltage, they can be a common signal (for example, a VPS signal). Furthermore, since VPM is the same voltage as VPS, VPM and VPS may be connected to form a common signal.

  The data confirmation procedure shown in FIG. 29 is as follows. This procedure is performed under the condition that the word line WL and the bit lines BLT and BLB are set to 0V, VPST, VPSB and VPM are set to Vcc, and the source potential SL is fixed to 0V. First, at time t0, the precharge control signals PRET and PREB are lowered from Vcc to 0V to turn on the precharge transistors MP3 and MP4 and precharge the nodes T and nodeB. The precharge levels of nodeT and nodeB are stabilized when the amount of current flowing through each of the MP1, MP3, and MCN1, or the MP2, MP4, and MCN2 is constant. At this time, in the case of data “1”, MCN1 having a lower threshold voltage has a higher current driving capability than MCN2, and therefore, the potential of nodeT becomes lower than that of nodeB, and after completion of precharging at time t1, the flip-flop The data of the group is fixed to “1”. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage has a larger current drive amount than MCN1, so that the potential of nodeB becomes lower than that of nodeT, and after completion of precharge at time t1, the flip-flop Is determined to be “1”. In FIG. 29, since PREB and PRET have the same voltage waveform, they can be a common signal (for example, a PRE signal). Furthermore, since VPSB and VPST have the same voltage, they can be a common signal (for example, a VPS signal). Furthermore, since VPM is the same voltage as VPS, VPM and VPS may be connected to form a common signal.

  Compared with the data determination procedure shown in FIG. 28, this data determination procedure has a demerit in terms of current consumption because a DC through current flows in the flip-flop during precharging, but the source line potentials SLT, SLB Has a merit from the viewpoint of controllability that can be controlled at a fixed voltage of 0V. Further, since the source-drain voltages of MCN1 and MC2 can be set high, there is an advantage that the respective current drive amounts can be increased.

  The data confirmation procedure shown in FIG. 30 is as follows. This data determination procedure is characterized in that nodeT and nodeB precharge voltages are supplied from the bit line side. The bit line BLT charged to Vcc is set by fixing PRET and PREB to Vcc, setting the word line WL and bit lines BLT and BLB to Vcc, setting the VPST and VPSB potentials to 0 V, and cutting off MP1 to MP4. , And BLB are precharged to Vcc-Vthn via the transfer gates MN1 and MN2, respectively. Here, Vthn is a threshold voltage of MN1 and MN2. At time t0, the word line WL is lowered from Vcc to 0V, and the nodes T and nodeB are floated, so that the flip-flop data is determined by the difference in the amount of charge discharged from MCN1 and MCN2. In the case of data “1”, MCN1 having a lower threshold voltage has a larger current driving capability than MCN2, so that node T has a lower potential than node B, and the VPST and VPSB potentials are changed from 0 V to Vcc at time t1. After the start-up, the data of this nonvolatile memory cell is fixed to “1”. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage has a larger current drive amount than MCN1, so that nodeB has a lower potential than nodeT, and the VPST and VPSB potentials are changed from 0V at time t1. After rising to Vcc, the data of this nonvolatile memory cell is determined to be “0”. In FIG. 30, since PREB and PRET are the same voltage, they can be a common signal (for example, a PRE signal). Furthermore, since VPSB and VPST have the same voltage, they can be a common signal (for example, a VPS signal).

[Modification of Second Embodiment]
In the nonvolatile memory cell having the VPS division type 8-transistor configuration according to the second embodiment, when writing is not performed, that is, when the threshold voltages of the storage transistors MCN1 and MCN2 are both low, FIG. In the start-up process 30 (data confirmation process), data is not confirmed. Therefore, as shown in FIGS. 31 and 32, the circuit configuration on the True side (storage transistor MCN1 side) and the Bar side (storage transistor MCN2 side) are unbalanced to start up even in a state where writing is not performed. Sometimes data can be fixed to either "0" or "1".

  In the nonvolatile memory cell shown in FIG. 31, the channel widths of the two load transistors MP1 and MP2 are unbalanced. In this example, the channel width of the load transistor MP1 (indicated by a thick line) is twice the channel width of the load transistor MP2, and the resistance value when the load transistor MP1 is on is compared with the resistance value when the load transistor MP2 is on. It is made to become 1/2.

  When the memory cell of this configuration is turned on when neither of the storage transistors MCN1 and MCN2 is written, the potential of nodeT rises faster than that of nodeB, and the load transistor MP1 and storage transistor MCN2 are turned on. The load transistor MP2 and the storage transistor MCN1 are in the off state, that is, the data becomes “0” and is stabilized.

  Note that the channel length may be unbalanced instead of the above channel width unbalance. Further, the load transistor for changing the channel width or the channel length may be either MP1 or MP2. Further, the channel widths or channel lengths of the storage transistors MCN1 and MCN2 may be changed to be unbalanced.

  The nonvolatile memory cell shown in FIG. 32 is obtained by connecting capacitors to two nodes nodeT and nodeB of a flip-flop. A capacitor C1 is connected between the node T and the power supply line Vcc, and a capacitor C2 is connected between the node B and the ground. The capacitance of these capacitors is about 50 fF, for example.

  As a result, when the power is turned on in a state where neither of the two storage transistors MCN1 and MCN2 is written / erased, the potential rise of nodeT immediately after power-on is quick and the potential rise of nodeB is slow. MP1 and storage transistor MCN2 are on, load transistor MP2 and storage transistor MCN1 are off, that is, data “0” is stabilized.

  In the example shown in FIG. 32, the capacitor is connected to both nodeT and nodeB, but the circuit configuration of the nonvolatile memory cell can be made asymmetric even if only one is connected.

[Threshold voltage measurement method in the second embodiment]
Note that in this 8-transistor nonvolatile memory cell, the threshold voltage of the memory transistor can be measured by arranging the potential as shown in FIG. By measuring the threshold voltage using this method, evaluation of threshold voltage variations in the initial state, threshold voltage variation during write and erase operations, high-temperature retention characteristics of the threshold voltage after rewriting, etc. Can be performed.

  FIG. 33 shows a case where the threshold voltage of the memory transistor MCN1 is determined. With the source potential SL = 0V of the storage transistor MCN1, 0.5V is supplied from the bit line BLT to the drain (nodeT) of the storage transistor MCN1 via the transfer gate MN1. The gate potential (nodeB) of the storage transistor MCN1 is supplied with the VPSB potential (MAP voltage) from the load transistors MP2 and MP4.

  Since the load transistor MP2 has a gate potential (nodeT) set to 0.5V, the load transistor MP2 is turned on and supplied to nodeB when the VPSB potential is 0.5V + Vthp or more. On the other hand, since the gate potential PREB is set to 0V, the load transistor MP4 is turned on when the VPSB potential is equal to or higher than Vthp and can supply potential to the nodeB. Vthp is a threshold voltage of the P-type MOS transistor indicated by MP1 to MP4, and is about 0.7 V in the standard CMOS process. In a voltage range higher than this, it is possible to determine the threshold voltage of MCN1 (the gate voltage necessary to pass a certain current). When measuring the threshold voltage on the MCN1 side, the gate potential nodeT of MCN2 is set to 0.5 V and turned off so that the gate potential nodeB of MCN1 is not lowered due to the leakage current on the MCN2 side. .

  FIG. 33 shows a voltage application procedure when the threshold voltage of the storage transistor MCN1 is measured. The threshold voltage of the storage transistor MCN2 is measured by the bit line BLT, BLB control, precharge signal PRET, PREB control. It is possible only by reversing each.

  The precharge line is divided into PRET and PREB for the threshold measurement. However, if this measurement is not performed, the precharge line may be common to the True side and the Bar side.

[Third Embodiment]
A nonvolatile memory device according to a third embodiment and a semiconductor integrated circuit device including the nonvolatile memory device will be described with reference to FIGS.

  FIG. 34 is a circuit diagram of one nonvolatile memory cell of the nonvolatile memory device. This memory cell is an SL-divided nonvolatile memory cell composed of 8 transistors. This memory cell includes an inverter (True side inverter) in which a P-type MOS transistor MP1 and an N-type MOS transistor MCN1 are connected in series, and an inverter (Bar-side inverter) in which a P-type MOS transistor MP2 and an N-type MOS transistor MCN2 are connected in series. ) In a static latch connection. Among these, the P-type MOS transistors MP1 and MP2 are called load transistors, and the N-type MOS transistors MCN1 and MCN2 are called storage transistors. The storage transistors MCN1 and MCN2 function as non-volatile elements that can change the threshold value in a non-volatile manner by accumulating and neutralizing charges in the sidewall portion, as will be described with reference to FIG.

  The end of the True-side inverter on the storage transistor side, that is, the source of the storage transistor MCN1 is connected to the True-side source line SLT. Further, the end of the Bar-side inverter on the storage transistor side, that is, the source of the storage transistor MCN2 is connected to the Bar-side source line SLB. Also, the load transistor side ends of both inverters, that is, the sources of the load transistors MP1 and MP2, are connected to the VPS line.

  Among the flip-flops, an inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the True side, and an inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the Bar side. To do. A connection portion between the load transistor MP1 and the storage transistor MCN1 is nodeT, and a connection portion between the load transistor MP2 and the storage transistor MCN2 is nodeB. When nodeT is high potential and nodeB is low potential, the stored content is “0”, and when nodeT is low potential and nodeB is high potential, the stored content is “1”.

  The node T is connected to the bit line BLT (BitLine-True) via the transfer gate MN1, and the node B is connected to the bit line BLB (BitLine-Bar) via the transfer gate MN2. The transfer gates MN1 and MN2 are composed of N-type MOS transistors, and a common word line WL is connected to each gate.

  A P-type MOS transistor MP3, which is a precharging transistor, is connected in parallel with the load transistor MP1, that is, between nodeT and VPS. A P-type MOS transistor MP4, which is a precharging transistor, is connected in parallel to the load transistor MP2, that is, between nodeB and VPS. A T-side precharge line PRET is connected to the gate of the P-type MOS transistor MP3, and a B-side precharge line PREB is connected to the gate of the P-type MOS transistor MP4. All the P-type MOS transistors MP1 to MP4 are formed in the same N well, and the N well potential is controlled by the VPM signal.

  FIG. 35 is a diagram showing a configuration of a memory cell array in which the nonvolatile memory cells shown in FIG. 34 are arranged in an array. In this memory cell array, the nonvolatile memory cells shown in FIG. 34 are arranged in an X and Y matrix array. A word line WL is provided for each row (row), and one bit line BLT, BLB is provided for each column (column). These word lines WL and bit lines BLT and BLB are controlled independently. On the other hand, the other signal lines (PREB, PRET, VPS, VPM, SLT, SLB) are provided in common to all the memory cells, and all the memory cells in the memory cell array are integrally controlled.

  36, 38, and 44 are views showing the structure of the memory transistor MCN1 (MCN2) on the semiconductor substrate. 36 shows the potential arrangement at the time of writing, FIG. 38 shows the potential arrangement at the time of erasing, and FIG. 44 shows the potential arrangement at the time of reading.

  FIG. 37 is a diagram showing a voltage application procedure at the time of writing to the memory transistor MCN1. FIG. 39 is a diagram showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). FIG. 45 is a diagram showing a voltage application procedure at the time of reading from a nonvolatile memory cell.

36, a P-type well 104 having a depth of 0.8 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is formed in the surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm. In this P-type well 104, two storage transistors MCN1 and MCN2 separated by a plurality of trenches (element isolation) 102 having a depth of 250 nm are formed. In this figure, only one storage transistor (MCN1) is shown.

The storage transistor is an N-channel transistor, and has a drain 109 and a source 115 formed adjacent to the trench 102 on both sides in the surface region of the P-type well 104 and a drain extension formed in the peripheral region of the drain 109. 107. The drain 109 and the source 115 are each formed with an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , and the drain extension 107 is formed with an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ .

  On the substrate of the channel region, which is the region between the drain 109 and the source 115 on the surface of the P-type well 104, a gate oxide film 105 with a thickness of 5 nm and a phosphorus concentration of 2 × 10 20 cm −3 with a thickness of 200 nm. A gate electrode 106 made of a polysilicon film is formed. Further, side spacers 108 and 108S made of an insulating film having a thickness of 50 nm are formed on both sides of the gate oxide film 105 and the gate electrode 106. Since no extension region is formed around the source 115, the side spacer 108S on the source side is exposed to the channel region of the substrate.

In the region of the P-type well 104, the region separated from the memory transistor by the trench 102 has an average boron concentration of 1 × 10 ²⁰ cm ⁻³ that is an electrode for grounding the P-type well 104. A P-type diffusion layer 111 is formed.

  In this memory transistor, the threshold voltage can be increased by injecting carriers into the side spacer 108S on the source side. Further, as will be described with reference to FIG. 38, the carrier voltage injected into the side spacer 108S can be extracted to return the threshold voltage to the initial state. As a result, the storage transistor stores data in a nonvolatile manner.

  Note that the standard initial threshold voltage of the memory transistor is 1.2 V. However, since the transistor has a special structure, the variation is large, and it is difficult to use the memory transistor alone as a memory element from the viewpoint of reliability. It is. Therefore, in this embodiment, the memory cell is configured with the flip-flop configuration shown in FIG.

  As shown in FIG. 36, in the write operation, 0 V is applied to the drain line VD, a positive voltage (for example, 6 V) lower than the junction breakdown voltage is applied to the source line VS, and channel hot electrons HE are injected into the side spacer 108S. Is the action. The threshold voltage rises due to electrons trapped in the side spacer 108S due to the injection of channel hot electrons, and the memory transistor enters a writing state.

  FIG. 37 is a diagram showing a voltage application procedure when data “0” is written by increasing the threshold voltage of the memory transistor MCN1. In order to make the memory transistor MCN1 have the potential arrangement shown in FIG. 36, a voltage is applied to the memory cell by the voltage application procedure shown in FIG. Under the condition that PREB, PRET, VPS, VPM, SLT, and SLB are set to 6V, the word line WL is set to Vcc, the bit line BLT is set to 0V, and BLB is set to Vcc. When the transfer gate MN1 which is an N-type MOS transistor is turned on, the node T (the drain of the storage transistor MCN1) becomes substantially the same potential as the bit line BLT (0 V), and the load transistor MP2 is thereby turned on. The gate of the storage transistor MCN1 becomes substantially the same potential as VPSB (6V). Thereby, the potential arrangement of the memory transistor MCN1 becomes the same as that in FIG. At this time, a current of about 300 μA flows through the transfer gate MN1 and the storage transistor MCN1, thereby raising the threshold voltage of the storage transistor MCN1 to Vth2.

  When data “1” is written, the threshold voltage on the memory transistor MCN2 side is increased. However, only the voltage setting is reversed to BLT = Vcc and BLB = 0V, and other conditions are set to data “0”. "Same as writing.

  In the above embodiment, 6V is applied to the gate (nodeB) of the transistor MCN1 and 6V is applied to the drain (source line SL) of the transistor MCN1, but these voltages may be different voltages. In FIG. 37, since PREB and PRET are the same voltage, they can be a common signal (for example, a PRE signal). Furthermore, since SLB and SLT have the same voltage, they can be a common signal (for example, an SL signal). Furthermore, since the voltages of VPS and VPM are the same, these signals may be connected to form a common signal.

  38 and 39 are diagrams showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). As shown in FIG. 38, in the erasing operation, a positive voltage (for example, 9V) lower than the junction breakdown voltage is applied to the source line VS, 0V is applied to the gate line VG and the drain line VD, and the avalanche hot hole is applied from the source electrode 115. In this operation, HH is generated and injected into the side spacer 108S. As a result, the electrons trapped in the side spacer 108S in the write operation are neutralized, and the written data is erased by lowering the threshold voltage.

  FIG. 39 is a diagram showing a voltage application procedure when data is erased by lowering the threshold voltages of the memory transistors MCN1 and MCN2. In order to make the memory transistor have the potential arrangement shown in FIG. 38, a voltage is applied to the memory cell by the procedure shown in FIG. In general, the erase operation is performed collectively for all the memory cells of the memory array shown in FIG. PREB, PRET, and VPM are set to Vcc, VPS is set to 0V, and SLT and SLB are set to 9V. The word line WL is set to Vcc, and the bit lines BLT and BLB are set to 0V. When the transfer gates MN1 and MN2 which are N-type MOS transistors are turned on, nodeT and nodeB become 0V, and the potential arrangement of the storage transistors MCN1 and MCN2 is the same as that in FIG. In FIG. 39, since PREB and PRET are the same voltage, they can be a common signal (for example, a PRE signal). Furthermore, since SLB and SLT have the same voltage, they can be a common signal (for example, an SL signal). Furthermore, since VPM operates normally even at 0V, it is possible to connect VPS and VPM to make a common signal.

  Thus, the voltage application procedure at the time of writing shown in FIGS. 36 and 37 and the voltage application procedure at the time of erasing shown in FIGS. 38 and 39 are the word lines that require independent control for each memory cell, In addition, since it is designed to apply 0 V or Vcc to the bit line, that is, it is not necessary to apply a high voltage to the word line and the bit line, a high voltage transistor is provided in the word line and bit line control circuit. There is no need to use it, and high-speed transistors that operate at high speed can be used to speed up the read operation.

  FIG. 40 is a diagram for explaining threshold voltages set in the memory transistors MCN1 and MCN2 by the write operation, that is, a diagram for explaining a data setting method for the nonvolatile memory cells. Here, when the threshold voltage of the storage transistor MCN1 is low (on) and the threshold voltage of the storage transistor MCN2 is high (off), the data is “1” and the threshold of the storage transistor MCN1 When the voltage is high (off) and the threshold voltage of the storage transistor MCN2 is low (on), the data is “0”.

  FIG. 6A shows a case before data setting, that is, when the threshold voltages of the storage transistors MCN1 and MCN2 are both in the initial state Vth0. Even in this state, the state of the nonvolatile memory cell is determined to be data “1” by the procedure shown in FIG. 41 or 43.

  FIG. 5B shows the threshold voltage when data “0” is set in the nonvolatile memory cell. Writing of data “0” is realized by raising the threshold voltage of the storage transistor MCN1 from the initial state in FIG. 5A to Vth2 (Vth2> Vth0).

  FIG. 3C shows the threshold voltage when data “1” is set in the nonvolatile memory cell. Writing of data “1” is realized by raising the threshold voltage of the memory transistor MCN2 from the initial state of FIG. 5A to Vth2 (Vth2> Vth0).

  When the erase operation described with reference to FIGS. 38 and 39 is performed, even if the threshold voltage is controlled as shown in FIGS.

  Thus, since this memory cell can be lowered again to the initial state Vth0 even if the threshold voltages of the storage transistors MCN1 and MCN2 are increased, both the storage transistors MCN1 and MCN2 are in the initial state Vth0. Even in this case, since the data can be forcibly determined to be “1”, the True side (the storage transistor MCN1) and the Bar side (the storage transistor MCN2) can be used for applications that require a plurality of data rewrites. The read margin, which is the difference between the threshold voltages, can be made sufficiently large.

  36 and 37, data can be written to one of the memory transistors MCN1 and MCN2 and data “1” or “0” can be written to the memory cell. On the other hand, when no data is written in the memory cell in the initial state, that is, in the storage transistors MCN1 and MCN2, both of the threshold voltages of the storage transistors MCN1 and MCN2 are in the initial state Vth0. The memory content of the memory cell is indefinite. However, by applying a voltage to the memory cell in the initial state according to the following procedure, the memory content of this memory cell can be determined to be “1” or “0”.

  FIG. 41 is a diagram for explaining a voltage application procedure for determining data in the nonvolatile memory cell according to the third embodiment. In this procedure, when the stored content of the nonvolatile memory cell is “1” or “0”, the state of the memory cell (flip-flop) is set according to the stored content, and when the memory cell is in the initial state, This is an operation for forcibly fixing the data to “1”. In a memory array in which a plurality of memory cells are arranged, if the memory contents are "1" and "0" and the memory cells in the initial state coexist, this procedure is collectively applied to all the memory cells in the memory array. By doing so, the state of the flip-flop is set according to the stored content for the memory cell whose stored content is “1” or “0”, and the state of the flip-flop is set for the memory cell in the initial state. Forced to "1". This procedure is executed when the memory is activated.

  The procedure shown in FIG. 41 is as follows. Under the condition that the word line WL and the bit lines BLT and BLB are set to 0V and VPS and VPM are set to Vcc, the source potentials SLT and SLB are first raised from 0V to Vcc at time t0, and the storage transistors MCN1 and MCN2 Turn off. Then, at time t1, the precharge control signals PRET and PREB are lowered from Vcc to 0V to turn on the precharge transistors MP3 and MP4 and charge nodeT and nodeB to Vcc.

  At time t2, PRET and PREB are returned to Vcc, and from time t3, the True-side source potential SLT is slowly lowered toward 0V. Then, the Bar-side source potential SLB is gradually lowered to 0 V at time t4 which is later than time t3. At this time, control is performed so that SLB-SLT = ΔVs (for example, ΔVs = 0.2 V). As a result, the source-drain voltage of the storage transistor MCN2 is controlled to be higher by ΔVs than the source-drain voltage of the storage transistor MCN1, thereby reducing the apparent threshold voltage on the storage transistor MCN2 side. It can be increased by ΔVs.

  At this time, when the memory content of the memory cell is “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so that nodeT is first lowered to 0V, and nodeB becomes Vcc, The data of the flip-flop is fixed to “1”. On the other hand, when the memory content of the memory cell is “0”, even if the threshold voltage increases by ΔVs, the threshold voltage of the memory transistor MCN2 is still lower than the threshold voltage of the memory transistor MCN1. Since the memory transistor MCN2 is turned on first, nodeB is first pulled down to 0V, nodeT becomes Vcc, and the data of the flip-flop is determined to be "0".

  When the memory contents of the memory cell are indefinite, that is, when the threshold voltages of MCN1 and MCN2 are both Vth0, the apparent threshold voltage of the memory transistor MCN1 is higher than the threshold voltage of the memory transistor MCN2. Is also lower by ΔVs, MCN1 is turned on earlier than MCN2, nodeT is first pulled down to 0V, nodeB becomes Vcc, and the flip-flop data is fixed to "1".

  A memory cell in which the threshold voltages of MCN1 and MCN2 are both Vth0 is often a cell that has not yet been written or rewritten. In such a memory cell, there is no deterioration of the transistor due to rewriting. For the setting of, only the initial threshold voltage variation of the transistor needs to be considered. Therefore, for example, about 0.2V is considered sufficient.

  The voltage application procedure shown in FIG. 41 is a procedure for determining the memory cell in the initial state as data “1”. However, in the source potential control of the storage transistor, only the potential relationship between SLT and SLB is reversed. It is also possible to fix the memory cell in the state to data “0”. In FIG. 41, since PREB and PRET have the same voltage waveform, they can be a common signal (for example, a PRE signal). Furthermore, since VPS and VPM are the same voltage, they may be connected to form a common signal.

  FIG. 42 is a diagram for explaining a data determination margin when the voltage application procedure shown in FIG. 41 is performed. In the initial state in which the threshold voltages of MCN1 and MCN2 are both Vth0, as described above, the source potential SLB on the Bar side is made higher by ΔVs than the source potential SLT on the True side, so that the MCN2 side The apparent threshold voltage is increased by ΔVs to forcibly recognize data “1”. In a memory cell in which data “0” has already been written, the margin decreases by ΔVs. However, if Vth2−Vth0 = 1V and ΔVs = 0.2V, the margin is 0.8V. . In the memory cell in which data “1” has already been written, the margin is increased by ΔV. If Vth2−Vth0 = 1V and ΔVs = 0.2V, the margin is 1.2V. Become.

  FIG. 43 is a diagram illustrating a voltage application procedure for determining data for a memory cell in an initial state. That is, the procedure of FIG. 41 is a procedure for determining data of each memory cell collectively in a memory array in which memory cells with stored contents “1” and “0” and an initial state memory cell coexist. The procedure shown in FIG. 43 forcibly fixes the data in the memory cell to “1” or “0” regardless of the stored contents of each memory cell.

  If there is a mix of data-written memory cells and memory cells in the initial state, either execute this procedure individually for the memory cells in the initial state, or all the memory cells will be stored in the memory array in the initial state. On the other hand, by executing this procedure collectively, the data of the memory cell can be fixed to “1” or “0”. The following description shows a procedure for forcibly determining the stored contents of the memory cell in the initial state to “1”.

  Under the condition that the word line WL and the bit lines BLT and BLB are set to 0 V and VPS and VPM are set to Vcc, the Bar-side source potential SLB is first raised from 0 V to Vcc at time t0 to set the storage transistor MCN2 The precharge control signal PREB is lowered from Vcc to 0V at time t1. As a result, nodeB is charged to Vcc by the precharge transistor MP4. At time t2, PREB is returned to Vcc, and at time t3, SLB is returned from Vcc to 0V. As a result, MCN1 having a higher gate potential is turned on earlier than MCN2, so that nodeT is lowered to 0V while nodeB is held at Vcc, and the data in the flip-flop is determined to be "1". To do.

  The procedure shown in FIG. 43 is a procedure for forcibly confirming the stored contents of the memory cell to “1”, but it can also be forcibly determined to “0”. That is, the True side source potential SLT is raised from 0 V to Vcc instead of the Bar side source potential SLB at time t0, and the gate potential PRET of the precharge transistor MP3 is changed to the gate potential PREB of the precharge transistor MP4 at time t1. By dropping the voltage from Vcc to 0V, nodeB becomes 0V, and the data is fixed to "0". Since VPS and VPM are the same voltage, they may be connected in common.

  By executing the procedure of FIG. 41 or FIG. 43, even if there is an initial state memory cell in which both of the two storage transistors MCN1 and MCN2 are in the initial state Vth0, the stored content is uniquely “1” or It can be fixed to “0”.

  When this nonvolatile memory cell is used in place of a fuse, if the stored content is uniquely determined to be “1”, the state before the fuse is blown (data “1” is maintained in the initial state). Response).

  44 and 45 are diagrams showing a voltage application procedure at the time of reading from the nonvolatile memory cell. As shown in FIG. 44, the storage contents of the memory cell according to the third embodiment are read by reading the voltage of the drain line VD when the source line VS is set to 0 V and Vcc is applied to the gate line VG. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 44, a voltage is applied to the memory cell in the procedure shown in FIG. The read operation uses a differential sense amplifier as in the SRAM read operation. Under the condition that PREB, PRET, VPS, and VPM are set to Vcc, SLT, and SLB are set to 0 V and the word line WL is set to Vcc, the change of the bit lines BLT and BLB according to the data in the flip-flop is differential type. Read with a sense amplifier. The data is "1" when BLT is low voltage (0V) and BLB is low voltage (Vcc), and the data is "0" when BLT is high voltage (Vcc) and BLB is low voltage (0V). In FIG. 45, since PREB and PRET have the same voltage, they can be used as a common signal (for example, a PRE signal). Furthermore, since SLB and SLT have the same voltage, they can be a common signal (for example, an SL signal). Furthermore, since VPS and VPM are the same voltage, they may be used as a common signal.

  The data determination procedure shown in FIG. 43 forces the initial state memory cells (memory cells MCN1 and MCN2 both in the initial state (threshold voltage = Vth0)) to exist. This was a procedure that could be fixed to “1”. When there is no memory cell in the initial state, or when the data value of the memory cell in the initial state may be indefinite, the determination procedure shown in FIGS. 46 to 48 can be used. This determination procedure does not cause a decrease in the determination margin of ΔVs (see FIG. 42) unlike the procedure shown in FIG.

  The data confirmation procedure shown in FIG. 46 is as follows. This procedure is performed under the condition that the word line WL and the bit lines BLT and BLB are set to 0 V, and VPS and VPM are set to Vcc. First, at time t0, the source potentials SLT and SLB are raised from 0 V to Vcc, and the storage transistors MCN1 and MCN2 are turned off. At time t1, the precharge control signals PRET and PREB are lowered from Vcc to 0V, so that the precharge transistors MP3 and MP4 are turned on to precharge nodeT and nodeB to Vcc. At time t2, PRET and PREB are returned to Vcc to complete the precharge. From time t3, the source potential SL is slowly lowered toward 0V. At this time, in the case of data “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so nodeT is first pulled down to 0V, nodeB becomes Vcc, and the flip-flop data is “1” is confirmed. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage is turned on earlier than MCN1, so that nodeB is first pulled down to 0V, nodeT becomes Vcc, and the flip-flop data is “ Confirm 0 ". In FIG. 46, since PREB and PRET have the same voltage waveform, they can be a common signal (for example, a PRE signal). Furthermore, since SLB and SLT have the same voltage, they can be a common signal (for example, an SL signal). Furthermore, since VPS and VPM have the same voltage, they may be used as a common signal.

  The data confirmation procedure shown in FIG. 47 is as follows. This procedure is performed under the condition that the word line WL and the bit lines BLT and BLB are set to 0V, VPS and VPM are set to Vcc, and the source potentials SLT and SLB are fixed to 0V. First, at time t0, the precharge control signals PRET and PREB are lowered from Vcc to 0V to turn on the precharge transistors MP3 and MP4 and precharge the nodes T and nodeB. The precharge levels of nodeT and nodeB are stabilized when the amount of current flowing through each of the MP1, MP3, and MCN1, or the MP2, MP4, and MCN2 is constant. At this time, in the case of data “1”, MCN1 having a lower threshold voltage has a higher current driving capability than MCN2, and therefore, the potential of nodeT becomes lower than that of nodeB, and after completion of precharging at time t1, the flip-flop The data of the group is fixed to “1”. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage has a larger current drive amount than MCN1, so that the potential of nodeB becomes lower than that of nodeT, and after completion of precharge at time t1, the flip-flop Is determined to be “1”. In FIG. 47, since PREB and PRET have the same voltage waveform, they can be a common signal (for example, a PRE signal). Furthermore, since SLB and SLT have the same voltage, they can be a common signal (for example, an SL signal). Furthermore, since VPS and VPM have the same voltage, they may be used as a common signal.

  Compared with the data determination procedure shown in FIG. 46, this data determination procedure has a demerit in terms of current consumption because a DC through current flows in the flip-flop during precharge, but the source line potentials SLT, SLB Has a merit from the viewpoint of controllability that can be controlled at a fixed voltage of 0V. Further, since the source-drain voltages of MCN1 and MC2 can be set high, there is an advantage that the respective current drive amounts can be increased.

  The data confirmation procedure shown in FIG. 48 is as follows. This data determination procedure is that precharge voltages of nodeT and nodeB are supplied from the bit line side. While fixing PRET and PREB to Vcc, the word lines WL and bit lines BLT and BLB are set to Vcc, the VPS potential is set to 0 V, and MP1 to MP4 are cut off to thereby cut the bit lines BLT and BLB charged to Vcc. Then, nodeT and nodeB are precharged to Vcc-Vthn via transfer gates MN1 and MN2, respectively. Here, Vthn is a threshold voltage of MN1 and MN2. At time t0, the word line WL is lowered from Vcc to 0V, and the nodes T and nodeB are floated, so that the flip-flop data is determined by the difference in the amount of charge discharged from MCN1 and MCN2. In the case of data "1", MCN1 having a lower threshold voltage has a higher current driving capability than MCN2, so that node T has a lower potential than node B, and the VPS potential is raised from 0 V to Vcc at time 1. After that, the data of the nonvolatile memory cell is fixed to “1”. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage has a larger current drive amount than MCN1, so that the potential of nodeB becomes lower than that of nodeT, and the VPS potential is changed from 0V to Vcc at time 1. After the start-up, the data of this nonvolatile memory cell is fixed to “0”. In FIG. 48, since PREB and PRET are the same voltage, they can be used as a common signal (for example, PRE signal). Furthermore, since SLB and SLT have the same voltage, they can be a common signal (for example, an SL signal). Furthermore, since VPS and VPM have the same voltage, they may be used as a common signal.

[Modification of Third Embodiment]
In the nonvolatile memory cell having the SL divided type 8-transistor configuration according to the third embodiment, when writing is not performed, that is, when the threshold voltages of the memory transistors MCN1 and MCN2 are both low, FIG. In 48 start-up processing (data confirmation processing), data is not confirmed. Therefore, as shown in FIGS. 49 and 50, the circuit configuration on the True side (storage transistor MCN1 side) and the Bar side (storage transistor MCN2 side) are unbalanced, so that even when no write is performed, Data can be fixed to either “0” or “1”.

  The nonvolatile memory cell shown in FIG. 49 is one in which the channel widths of the two load transistors MP1 and MP2 are unbalanced. In this example, the channel width of the load transistor MP1 (indicated by a thick line) is twice the channel width of the load transistor MP2, and the resistance value when the load transistor MP1 is on is compared with the resistance value when the load transistor MP2 is on. It is made to become 1/2.

  When the memory cell of this configuration is turned on when neither of the storage transistors MCN1 and MCN2 is written, the potential of nodeT rises faster than that of nodeB, and the load transistor MP1 and storage transistor MCN2 are turned on. The load transistor MP2 and the storage transistor MCN1 are in the off state, that is, the data becomes “0” and is stabilized.

  Note that the channel length may be unbalanced instead of the above channel width unbalance. Further, the load transistor for changing the channel width or the channel length may be either MP1 or MP2. Further, the channel widths or channel lengths of the storage transistors MCN1 and MCN2 may be changed to be unbalanced.

  The nonvolatile memory cell shown in FIG. 50 is obtained by connecting capacitors to two nodes nodeT and nodeB of a flip-flop. A capacitor C1 is connected between the node T and the power supply line Vcc, and a capacitor C2 is connected between the node B and the ground. The capacitance of these capacitors is about 50 fF, for example.

  As a result, when the power is turned on in a state where neither of the two storage transistors MCN1 and MCN2 is written / erased, the potential rise of nodeT immediately after power-on is quick and the potential rise of nodeB is slow. MP1 and storage transistor MCN2 are on, load transistor MP2 and storage transistor MCN1 are off, that is, data “0” is stabilized.

  In the example shown in FIG. 50, the capacitor is connected to both nodeT and nodeB, but the circuit configuration of the nonvolatile memory cell can be made asymmetric even if only one is connected.

[Threshold Voltage Measuring Method in Third Embodiment]
Note that in this 8-transistor nonvolatile memory cell, the threshold voltage of the memory transistor can be measured by arranging the potential as shown in FIG. By measuring the threshold voltage using this method, evaluation of threshold voltage variation in the initial state, threshold voltage variation during write and erase operations, high-temperature retention characteristics of the threshold voltage after rewrite, etc. Can be performed.

  FIG. 51 shows a case where the threshold voltage of the memory transistor MCN1 is determined. With the source potential SLT of the storage transistor MCN1 to be inspected set to 0 V, 1 V is supplied from the bit line BLT to the drain (nodeT) of the storage transistor MCN1 via the transfer gate MN1. The gate potential (nodeB) of the storage transistor MCN1 is supplied with the VPS potential (MAP voltage) from the load transistors MP2 and MP4.

  Since the gate potential (nodeT) is set to 1V, the load transistor MP2 is turned on and supplied to nodeB when the VPSB potential is 1V + Vthp or higher. On the other hand, since the gate potential PREB is set to 0V, the load transistor MP4 is turned on when the VPS potential is equal to or higher than Vthp and can supply the potential to the nodeB. Vthp is a threshold voltage of the P-type MOS transistor indicated by MP1 to MP4, and is about 0.7 V in the standard CMOS process. Therefore, it is possible to determine the threshold voltage of MCN1 (the gate voltage necessary for flowing a certain constant current) in a voltage range higher than this. When measuring the threshold voltage on the MCN1 side, the source potential SLB of the MCN2 is set to the MAP voltage and the bit line is left floating in order to eliminate an unnecessary leak path on the MCN2 side.

  FIG. 51 shows a voltage application procedure when measuring the threshold voltage of the storage transistor MCN1, but the threshold voltage of the storage transistor MCN2 is measured by the bit lines BLT, BLB control, source potentials SLT, SLB. This is possible only by reversing the control and precharge signals PRET and PREB control.

  The precharge line is divided into PRET and PREB for the threshold measurement. However, if this measurement is not performed, the precharge line may be common to the True side and the Bar side.

[Layout on Semiconductor Substrate in Second and Third Embodiments]
FIG. 52 shows the layout on the semiconductor substrate of the memory cells of the second and third embodiments.
FIG. 2A shows the layout of the active region on the substrate surface and the gate electrode. FIG. 5B shows the first level metal wiring. FIG. 2C shows the second and third layer metal wiring. As shown in FIG. 6A, the True-side and Bar-side storage transistors are laid out in the same direction so that the mutual characteristics are the same even if an error occurs in the oblique implantation of impurities.

  Further, as shown in FIG. 6C, the VPS line and the source line (SL) are divided into the True side and the Bar side in this layout, respectively, and by short-circuiting (sharing) one of them, The VPS split type of the second embodiment or the SL split type of the third embodiment can be used. Thus, with the layout shown in the figure, the VPS split type of the second embodiment or the third embodiment can be changed by changing the third metal wiring while keeping the same process up to the second metal wiring. An SL-divided nonvolatile semiconductor memory cell can be manufactured.

[Fourth Embodiment]
A nonvolatile memory device according to a fourth embodiment and a semiconductor integrated circuit device (memory cell array) including the nonvolatile memory device will be described with reference to FIGS.

  FIG. 53 is a circuit diagram of one nonvolatile memory cell of the nonvolatile memory device. This memory cell is a 12-transistor nonvolatile memory cell in which an analog switch is added to the VPS division type memory cell described in the second embodiment.

  This memory cell includes an inverter (True side inverter) in which a P-type MOS transistor MP1 and an N-type MOS transistor MCN1 are connected in series, and an inverter (Bar-side inverter) in which a P-type MOS transistor MP2 and an N-type MOS transistor MCN2 are connected in series. ) In a static latch connection. Among these, the P-type MOS transistors MP1 and MP2 are called load transistors, and the N-type MOS transistors MCN1 and MCN2 are called storage transistors. The storage transistors MCN1 and MCN2 function as non-volatile elements that can change the threshold value in a non-volatile manner by accumulating and neutralizing electric charges in the side wall portions, as will be described with reference to FIG.

  The memory cell further includes an analog switch including a P-type MOS transistor MP5 and an N-type MOS transistor MN3 between the P-type MOS transistor MP1 and the N-type MOS transistor MCN1, and the P-type MOS transistor MP2 and the N-type MOS transistor. Between the MCN2, an analog switch including a P-type MOS transistor MP6 and an N-type MOS transistor MN4 is provided. The gates of the P-type MOS transistor MP5 and the P-type MOS transistor MP6 are connected to the RESN line, and the gates of the N-type MOS transistor MN3 and the N-type MOS transistor MN4 are connected to the RESP line.

  The storage transistor side end of each inverter, that is, the source of the storage transistors MCN1 and MCN2, is connected to the source line SL. The load transistor side end of the True side inverter, that is, the source of the load transistor MP1 is connected to the VPST line, and the load transistor side end of the Bar side inverter, that is, the source of the load transistor MP2 is connected to the VPSB line.

  Among the flip-flops, an inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the True side, and an inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the Bar side. To do. A connection portion between the load transistor MP1 and the storage transistor MCN1 is nodeT, and a connection portion between the load transistor MP2 and the storage transistor MCN2 is nodeB. When nodeT is high potential and nodeB is low potential, the stored content is “0”, and when nodeT is low potential and nodeB is high potential, the stored content is “1”.

  The node T is connected to the bit line BLT (BitLine-True) via the transfer gate MN1, and the node B is connected to the bit line BLB (BitLine-Bar) via the transfer gate MN2. The transfer gates MN1 and MN2 are composed of N-type MOS transistors, and a common word line WL is connected to each gate.

  Further, a P-type MOS transistor MP3, which is a precharging transistor, is connected in parallel to the load transistor MP1, that is, between nodeT and VPST. A P-type MOS transistor MP4, which is a precharging transistor, is connected in parallel with the load transistor MP2, that is, between nodeB and VPSB. A T-side precharge line PRET is connected to the gate of the P-type MOS transistor MP3, and a B-side precharge line PREB is connected to the gate of the P-type MOS transistor MP4. All the P-type MOS transistors MP1 to MP6 are formed in the same N well, and the N well potential is controlled by the VPM signal.

  FIG. 54 is a diagram showing a configuration of a memory cell array in which the nonvolatile memory cells shown in FIG. 53 are arranged in an array. In this memory cell array, the nonvolatile memory cells of FIG. 53 are arranged in an X, Y matrix array. A word line WL is provided for each row (row), and one bit line BLT, BLB is provided for each column (column). These word lines WL and bit lines BLT and BLB are controlled independently. On the other hand, other signal lines (PREB, PRET, VPST, VPSB, VPM, SL, RESN, and RESP) are provided in common to all the memory cells, and the entire memory cell array is integrally controlled.

  55, 57, and 63 are diagrams showing the structure of the memory transistor MCN1 (MCN2) on the semiconductor substrate. FIG. 55 shows the potential arrangement at the time of writing, FIG. 57 shows the potential arrangement at the time of erasing, and FIG. 63 shows the potential arrangement at the time of reading.

  FIG. 56 is a diagram showing a voltage application procedure at the time of writing to the memory transistor MCN1. FIG. 58 is a diagram showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). FIG. 64 is a diagram showing a voltage application procedure at the time of reading from a nonvolatile memory cell.

55, a P-type well 104 having a depth of 0.8 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is formed in the surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm. In this P-type well 104, two storage transistors MCN1 and MCN2 separated by a plurality of trenches (element isolation) 102 having a depth of 250 nm are formed. In this figure, only one storage transistor (MCN1) is shown.

The storage transistor is an N-channel transistor, and has a drain 109 and a source 115 formed adjacent to the trench 102 on both sides in the surface region of the P-type well 104 and a drain extension formed in the peripheral region of the drain 109. 107. The drain 109 and the source 115 are each formed with an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , and the drain extension 107 is formed with an average arsenic concentration of 5 × 10 ¹⁸ cm ⁻³ .

On the substrate of the channel region, which is the region between the drain 109 and the source 115 on the surface of the P-type well 104, a gate oxide film 105 with a thickness of 5 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻ with a thickness of 200 nm. ^A gate electrode 106 made of ³ polysilicon film is formed. Further, side spacers 108 and 108S made of an insulating film having a thickness of 50 nm are formed on both sides of the gate oxide film 105 and the gate electrode 106. Since no extension region is formed around the source 115, the side spacer 108S on the source side is exposed to the channel region of the substrate.

In the region of the P-type well 104, the region separated from the memory transistor by the trench 102 has an average boron concentration of 1 × 10 ²⁰ cm ⁻³ that is an electrode for grounding the P-type well 104. A P-type diffusion layer 111 is formed.

  In this memory transistor, the threshold voltage can be increased by injecting carriers into the side spacer 108S on the source side. Further, as will be described with reference to FIG. 57, the carrier voltage injected into the side spacer 108S can be pulled out to return the threshold voltage to the initial state. As a result, the storage transistor stores data in a nonvolatile manner.

  Note that the standard initial threshold voltage of the memory transistor is 1.2 V. However, since the transistor has a special structure, the variation is large, and it is difficult to use the memory transistor alone as a memory element from the viewpoint of reliability. It is. Therefore, in this embodiment, the memory cell is configured with the flip-flop configuration shown in FIG.

  As shown in FIG. 55, in the write operation, 0V is applied to the drain line VD, a positive voltage (for example, 6V) lower than the junction breakdown voltage is applied to the source line VS, and channel hot electrons HE are injected into the side spacer 108S. Is the action. The threshold voltage rises due to electrons trapped in the side spacer 108S due to the injection of channel hot electrons, and the memory transistor enters a writing state.

  FIG. 56 is a diagram showing a voltage application procedure when data “0” is written by increasing the threshold voltage of the memory transistor MCN1. In order to make the memory transistor MCN1 have the potential arrangement shown in FIG. 55, a voltage is applied to the memory cell by the procedure shown in FIG. After RESN is set to 0V and RESP is set to Vcc, the word line WL is set to Vcc, the bit line BLT is set to 0V, and the BLB is set to Vcc under the condition that PREB, PRET, VPST, VPSB, VPM, and SL are set to 6V. When the transfer gate MN1 which is an N-type MOS transistor is turned on, the node T (the drain of the storage transistor MCN1) becomes substantially the same potential as the bit line BLT (0 V), and the load transistor MP2 is thereby turned on. The gate of the storage transistor MCN1 becomes substantially the same potential as VPSB (6V). Thereby, the voltage application procedure of the memory transistor MCN1 is the same as that in FIG. At this time, a current of about 300 μA flows through the transfer gate MN1 and the storage transistor MCN1, thereby raising the threshold voltage of the storage transistor MCN1 to Vth2.

  When data “1” is written, the threshold voltage on the memory transistor MCN2 side is increased. However, only the voltage setting is reversed to BLT = Vcc and BLB = 0V, and other conditions are set to data “0”. "Same as writing.

  In the above embodiment, 6V is applied to the gate (nodeB) of the transistor MCN1 and 6V is applied to the drain (source line SL) of the transistor MCN1, but these voltages may be different voltages.

  57 and 58 are diagrams showing a procedure for applying an erase voltage to the memory transistor MCN1 (MCN2). As shown in FIG. 57, in the erasing operation, a positive voltage (for example, 9V) lower than the junction breakdown voltage is applied to the source line VS, 0V is applied to the gate line VG and the drain line VD, and the avalanche hot hole is applied from the source electrode 115. In this operation, HH is generated and injected into the side spacer 108S. As a result, the electrons trapped in the side spacer 108S in the write operation are neutralized, and the written data is erased by lowering the threshold voltage.

  FIG. 58 is a diagram showing a voltage application procedure when data is erased by lowering the threshold voltages of the memory transistors MCN1 and MCN2. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 57, a voltage is applied to the memory cell by the procedure shown in FIG. In general, the erase operation is performed collectively for all the memory cells of the memory array shown in FIG. Under the condition that RESN is set to 0V, RESP is set to Vcc, PREB, PRET, and VPM are set to Vcc, VPST and VPSB are set to 0V, and SL is set to 9V, word line WL is set to Vcc, bit line BLT, BLB is set to 0V. When the transfer gates MN1 and MN2 which are N-type MOS transistors are turned on, nodeT and nodeB become 0V, and the voltage application procedure of the storage transistors MCN1 and MCN2 is the same as that in FIG.

  As described above, the voltage application procedure at the time of writing shown in FIGS. 55 and 56 and the voltage application procedure at the time of erasing shown in FIGS. 57 and 58 are the same as the word line that requires independent control for each memory cell. Because it is designed to apply 0V or Vcc to the bit line, that is, it is not necessary to apply a high voltage to the word line and bit line, high voltage transistors are used in the word line and bit line control circuits. Therefore, the reading operation can be speeded up using a high-performance transistor that operates at high speed.

  FIG. 59 is a diagram for explaining threshold voltages set in the memory transistors MCN1 and MCN2 by the write operation, that is, a diagram for explaining a data setting method for a nonvolatile memory cell. Here, when the threshold voltage of the storage transistor MCN1 is low (on) and the threshold voltage of the storage transistor MCN2 is high (off), the data is “1” and the threshold of the storage transistor MCN1 When the voltage is high (off) and the threshold voltage of the storage transistor MCN2 is low (on), the data is “0”.

  FIG. 6A shows a case before data setting, that is, when the threshold voltages of the storage transistors MCN1 and MCN2 are both in the initial state Vth0. Even in this state, the state of the nonvolatile memory cell is determined to be data “1” by the procedure shown in FIG. 60 or 62.

  FIG. 5B shows the threshold voltage when data “0” is set in the nonvolatile memory cell. Writing of data “0” is realized by raising the threshold voltage of the storage transistor MCN1 from the initial state in FIG. 5A to Vth2 (Vth2> Vth0).

  FIG. 3C shows the threshold voltage when data “1” is set in the nonvolatile memory cell. Writing of data “1” is realized by raising the threshold voltage of the memory transistor MCN2 from the initial state of FIG. 5A to Vth2 (Vth2> Vth0).

  When the erase operation described with reference to FIGS. 57 and 58 is performed, the state shown in FIG. 5A is restored even if the threshold voltage is controlled as shown in FIGS.

  Thus, since this memory cell can be lowered again to the initial state Vth0 even if the threshold voltages of the storage transistors MCN1 and MCN2 are increased, both the storage transistors MCN1 and MCN2 are in the initial state Vth0. Even in this case, since the data can be forcibly determined to be “1”, the True side (the storage transistor MCN1) and the Bar side (the storage transistor MCN2) can be used for applications that require a plurality of data rewrites. The read margin, which is the difference between the threshold voltages, can be made sufficiently large.

  With the write operation shown in FIGS. 55 and 56, data can be written to one of the memory transistors MCN1 and MCN2, and data “1” or “0” can be written to the memory cell. On the other hand, when no data is written in the memory cell in the initial state, that is, in the storage transistors MCN1 and MCN2, both of the threshold voltages of the storage transistors MCN1 and MCN2 are in the initial state Vth0. The memory content of the memory cell is indefinite. However, by applying a voltage to the memory cell in the initial state according to the following procedure, the memory content of this memory cell can be determined to be “1” or “0”.

  FIG. 60 is a diagram for explaining a voltage application procedure for determining data in the nonvolatile memory cell according to the fourth embodiment. In this procedure, when the stored content of the nonvolatile memory cell is “1” or “0”, the state of the memory cell (flip-flop) is set according to the stored content, and when the memory cell is in the initial state, This is an operation for forcibly fixing the data to “1”. In a memory array in which a plurality of memory cells are arranged, if the memory contents are "1" and "0" and the memory cells in the initial state coexist, this procedure is collectively applied to all the memory cells in the memory array. By doing so, the state of the flip-flop is set according to the stored content for the memory cell whose stored content is “1” or “0”, and the state of the flip-flop is set for the memory cell in the initial state. Forced to "1". This procedure is executed when the memory is activated.

  The procedure shown in FIG. 60 is as follows. This procedure is executed under the condition that the word line WL and the bit lines BLT and BLB are set to 0V, RESN is set to 0V, and RESP is set to Vcc. First, at time t0, the source potential SL is raised from 0 V to Vcc, and the storage transistors MCN1 and MCN2 are turned off. At time t1, the precharge transistors MP3 and MP4 are turned on by lowering the precharge control signals PRET and PREB from Vcc to 0V. At the same time, among the precharge voltages set to Vcc, the True-side precharge voltage VPST is lowered by ΔV (voltage sufficiently smaller than Vth2−Vth0, for example, 0.2V). As a result, the precharge voltages of nodeT and nodeB are also Vcc−ΔV and Vcc, respectively, and the source-drain voltage of the storage transistor MCN2 becomes higher by ΔV than the source-drain voltage of the storage transistor MCN1. Thereby, the apparent threshold voltage on the memory transistor MCN2 side can be increased by ΔV.

  At time t2, PRET and PREB are returned to Vcc, and from time t3, the source potential SL is gradually lowered toward 0V. At this time, when the memory content of the memory cell is “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so that nodeT is first lowered to 0V, and nodeB is Vcc−ΔV Thus, the data of the flip-flop is fixed to “1”. On the other hand, when the stored content of the memory cell is “0”, the threshold voltage of the storage transistor MCN2 is still higher than the threshold voltage of the storage transistor MCN1 even if the threshold voltage increases by ΔV. Since the memory transistor MCN2 is turned on first, nodeB is first pulled down to 0V, nodeT becomes Vcc, and the data of the flip-flop is determined to be “0”.

  Further, when the memory content of the memory cell is “undefined”, that is, when the threshold voltages of MCN1 and MCN2 are both Vth0, the apparent threshold voltage of the memory transistor MCN1 is the threshold voltage of the memory transistor MCN2. Since it is lower than the voltage by ΔV, MCN1 is turned on earlier than MCN2, nodeT is first pulled down to 0V, nodeB becomes Vcc−ΔV, and the flip-flop data is determined to be “1”.

  VPST is returned to Vcc at time t4 after the state of the flip-flop is determined.

  A memory cell in which the threshold voltages of MCN1 and MCN2 are both Vth0 is often a cell that has not yet been written or rewritten. In such a memory cell, there is no deterioration of the transistor due to rewriting. For the setting of, only the initial threshold voltage variation of the transistor needs to be considered. Therefore, for example, about 0.2V is considered sufficient.

  The voltage application procedure shown in FIG. 60 is a procedure for determining the memory cell in the initial state as data “1”. In the source potential control of the P-type MOS transistor, the voltage of VPSB is reduced by ΔV instead of VPST. By doing so, it is possible to determine the memory cell in the initial state as data “0”.

  FIG. 61 is a diagram for explaining a data determination margin when the voltage application procedure shown in FIG. 60 is performed. In the initial state where both the threshold voltages of MCN1 and MCN2 are Vth0, as described above, the apparent threshold voltage on the MCN2 side can be obtained by making the precharge voltage of nodeT lower by ΔV than nodeB. Is increased by ΔV to forcibly recognize the data as “1”. In a memory cell in which data “0” has already been written, the margin decreases by ΔV. However, if Vth2−Vth0 = 1V and ΔV = 0.2V, the margin becomes 0.8V. . In the memory cell in which data “1” has already been written, the margin is increased by ΔV. If Vth2−Vth0 = 1V and ΔV = 0.2V, the margin is 1.2V. Become.

  FIG. 62 is a diagram for explaining a voltage application procedure for determining data for a memory cell in an initial state. That is, the procedure of FIG. 60 is a procedure for determining the data of each memory cell collectively in a memory array in which memory cells with stored contents “1” and “0” and an initial state memory cell coexist. The procedure shown in FIG. 62 ensures that the data in the memory cell is “1” or “0” regardless of the stored contents of each memory cell.

  This procedure should be executed on the memory array in a batch in both cases where there are mixed data memory cells and memory cells in the initial state, or if all memory cells are in the initial state. Thus, the data of the memory cell can be determined to be “1” or “0”. The following description shows a procedure for forcibly determining the stored contents of the memory cell in the initial state to “1”.

  Under the conditions that the word line WL and the bit lines BLT and BLB are set to 0V, RESN is set to 0V, and RESP is set to Vcc, the source potential SL is first raised from 0V to Vcc at time t0, and MCN1 and MCN2 are set. At time t1, the precharge control signals PREB and PRET and the source potential VPST of the precharge transistor MP3 are lowered from Vcc to 0V. Thereby, nodeB is charged to Vcc by the precharge transistor MP4, and nodeT is discharged through the precharge transistor MP3. At time t2, PREB and PRET are returned to Vcc, and at time t3, SL is changed from Vcc to 0V. At this time, MCN1 having a higher gate potential is turned on earlier than MCN2, so that nodeT is lowered to 0V while nodeB is held at Vcc, and the data in the flip-flop is determined to be "1". To do. At time t4, VPST is returned to Vcc.

  The procedure shown in FIG. 62 is a procedure for forcibly confirming the stored contents of the memory cell to “1”, but can be forcibly determined to “0”. That is, by dropping the source potential VPSB of the precharge transistor MP4 from Vcc to 0V instead of the source potential VPST of the precharge transistor MP3 at time t1, nodeB is discharged and the data is determined to be “0”.

  By executing the procedure of FIG. 60 or FIG. 62, even if there is an initial state memory cell in which both of the two storage transistors MCN1 and MCN2 are in the initial state Vth0, the stored content is uniquely “1” or It can be fixed to “0”.

  When this nonvolatile memory cell is used in place of a fuse, if the stored content is uniquely determined to be “1”, the state before the fuse is blown (data “1” is maintained in the initial state). Response).

  63 and 64 are diagrams showing a voltage application procedure at the time of reading from the nonvolatile memory cell. As shown in FIG. 63, reading is performed by reading the voltage of the drain line VD when the source line VS is set to 0 V and Vcc is applied to the gate line VG. In order to make the memory transistors MCN1 and MCN2 have the potential arrangement shown in FIG. 65, a voltage is applied to the memory cell under the conditions shown in FIG. The read operation uses a differential sense amplifier as in the SRAM read operation. Bit according to the data in the flip-flop under the condition that RESN is set to 0V, RESP is set to Vcc, PREB, PRET, VPST, VPSB, VPM are set to Vcc, SL is set to 0V, and word line WL is set to Vcc. Changes in the lines BLT and BLB are read out by a differential sense amplifier. Data is "1" when BLT is low voltage (0V) and BLB is low voltage (Vcc), and data is "0" when BLT is high voltage (Vcc) and BLB is low voltage (0V).

  The data determination procedure shown in FIG. 62 is performed even if there is an initial state memory cell (a memory cell in which both storage transistors MCN1 and MCN2 are in an initial state (threshold voltage = Vth0)). It was a procedure that could be forcibly confirmed. When there is no memory cell in the initial state, or when the data value of the memory cell in the initial state may be indefinite, the determination procedure shown in FIGS. 65 to 67 can be used. In this determination procedure, the decrease in the determination margin of ΔV (see FIG. 61) as in the procedure shown in FIG. 60 does not occur.

  The data confirmation procedure shown in FIG. 65 is as follows. This procedure is performed under the condition that the word line WL and the bit lines BLT and BLB are set to 0V, RESN is set to 0V, RESP is set to Vcc, and VPST, VPSB, and VPM are set to Vcc. First, at time t0, the source potential SL is raised from 0 V to Vcc, and the storage transistors MCN1 and MCN2 are turned off. At time t1, the precharge control signals PRET and PREB are lowered from Vcc to 0V, so that the precharge transistors MP3 and MP4 are turned on to precharge nodeT and nodeB to Vcc. At time t2, PRET and PREB are returned to Vcc, and after precharge is completed, the source potential SL is gradually lowered toward 0V from time t3. At this time, in the case of data “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so nodeT is first pulled down to 0V, nodeB becomes Vcc, and the flip-flop data is “1” is confirmed. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage is turned on earlier than MCN1, so that nodeB is first pulled down to 0V, nodeT becomes Vcc, and the flip-flop data is “ Confirm 0 ".

  The data confirmation procedure shown in FIG. 66 is as follows. In this procedure, word line WL and bit lines BLT and BLB are set to 0V, VPST, VPSB and VPM are set to Vcc, RESN is set to Vcc, RESP is set to 0V, and source potential SL is fixed to 0V. Performed under the above conditions. First, at time t0, the precharge control signals PRET and PREB are lowered from Vcc to 0V to turn on the precharge transistors MP3 and MP4 and precharge the nodes T and nodeB. At this time, since the transistors MN3, MN4, MP5, and MP6 are off, both nodeT and nodeB are precharged to Vcc. On the other hand, since the drain AtrT of MCN1 and the drain AtrB of MCN2 are each in a floating state, they are almost 0V. At time t1, RESN is set to 0V and RESP is set to Vcc. At this time, the transistors MN3, MN4, MP5, and MP6 are turned on, so that nodeT and AtrT and nodeB and AtrB are electrically conducted, and AtrT and AtrB are both charged to Vcc. At time t2, the precharge control signals PRET and PREB are raised from 0V to Vcc. In the case of data “1”, MCN1 having a lower threshold voltage has a higher current driving capability than MCN2, so that node T has a lower potential than node B, and the flip-flop data is determined to be “1”. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage has a larger current drive amount than MCN1, so that the potential of nodeB becomes lower than that of nodeT, and the data of the flip-flop is determined to be “1”. To do.

  Compared with the data determination procedure of the second embodiment shown in FIG. 29, this data determination procedure can limit the period during which a DC through current flows in the flip-flop during precharge between t1 and t2. , Current consumption can be reduced.

  The data confirmation procedure shown in FIG. 67 is as follows. This data determination procedure is characterized in that nodeT and nodeB precharge voltages are supplied from the bit line side. The bit line BLT charged to Vcc is set by fixing PRET and PREB to Vcc, setting the word line WL and bit lines BLT and BLB to Vcc, setting the VPST and VPSB potentials to 0 V, and cutting off MP1 to MP4. , And BLB are precharged to Vcc-Vthn via the transfer gates MN1 and MN2, respectively. Here, Vthn is a threshold voltage of MN1 and MN2. At time t0, the word line WL is lowered from Vcc to 0V, and the nodes T and nodeB are floated, so that the flip-flop data is determined by the difference in the amount of charge discharged from MCN1 and MCN2. In the case of data “1”, MCN1 having a lower threshold voltage has a larger current driving capability than MCN2, so that node T has a lower potential than node B, and the VPST and VPSB potentials are changed from 0 V to Vcc at time t1. After the start-up, the data of this nonvolatile memory cell is fixed to “1”. On the other hand, in the case of data “0”, MCN2 having a lower threshold voltage has a larger current drive amount than MCN1, so that nodeB has a lower potential than nodeT, and the VPST and VPSB potentials are changed from 0V at time t1. After rising to Vcc, the data of this nonvolatile memory cell is determined to be “0”. Thereafter, VPS is raised to Vcc at time t1.

  In the nonvolatile memory cell according to the fourth embodiment, as described with reference to FIGS. 31 and 32 in the second embodiment, the channel widths of the storage transistors MCN1 and MCN2 or the load transistors MP1 and MP2 are used. Further, the circuit length of the flip-flop may be made asymmetric by changing the channel length or connecting a capacitor to one inverter.

[Threshold voltage measurement method in the fourth embodiment]
In this 12-transistor nonvolatile memory cell, the threshold voltage of the memory transistor can be measured by arranging the potential as shown in FIG. By measuring the threshold voltage using this method, evaluation of threshold voltage variation in the initial state, threshold voltage variation during write and erase operations, high-temperature retention characteristics of the threshold voltage after rewrite, etc. Can be performed.

  FIG. 68 shows a case where the threshold voltage of the memory transistor MCN1 is determined. With the source potential SLT of the storage transistor MCN1 to be inspected set to 0 V, 1 V is supplied from the bit line BLT to the drain (nodeT) of the storage transistor MCN1 via the transfer gate MN1. The gate potential (nodeB) of the storage transistor MCN1 is supplied with the VPSB potential (MAP voltage) from the load transistor MP4.

  Since the gate potential PRET is set to 0V, the load transistor MP3 is turned on to supply the MAP potential to the node T when the VPST potential is equal to or higher than Vthp. Similarly, since the gate potential PREB is set to 0V, the load transistor MP4 is turned on when the VPSB potential is equal to or higher than Vthp and can supply the MAP potential to the nodeB. Vthp is a threshold voltage of the P-type MOS transistor indicated by MP1 to MP4, and is about 0.7 V in the standard CMOS process. Therefore, it is possible to determine the threshold voltage of MCN1 (the gate voltage necessary for flowing a certain constant current) in a voltage range higher than this. When measuring the threshold voltage on the MCN1 side, the transistors MN3, MP5, MN4 and MP6 are all non-conductive, and the leak path from nodeT to SL and the leak path from nodeB to SL are electrically cut off, respectively. Therefore, there is no problem if BL is set to 0V.

  FIG. 68 shows a voltage application procedure for measuring the threshold voltage of the memory transistor MCN1, but the threshold voltage of the memory transistor MCN2 is measured only by reversing the bit line BLT and BLB control. Is possible.

  It is not necessary to divide the precharge line into PRET and PREB for this threshold measurement, and they may be shared.

[Fifth Embodiment]
A nonvolatile memory device according to a fifth embodiment and a semiconductor integrated circuit device including the nonvolatile memory device will be described with reference to FIGS. 69 and 70. FIG.

  FIG. 69 is a circuit diagram of one nonvolatile memory cell of the nonvolatile memory device. This memory cell is a 12-transistor nonvolatile memory cell in which an analog switch is added to the SL-divided memory cell described in the third embodiment.

  This memory cell includes an inverter (True side inverter) in which a P-type MOS transistor MP1 and an N-type MOS transistor MCN1 are connected in series, and an inverter (Bar-side inverter) in which a P-type MOS transistor MP2 and an N-type MOS transistor MCN2 are connected in series. ) In a static latch connection. Among these, the P-type MOS transistors MP1 and MP2 are called load transistors, and the N-type MOS transistors MCN1 and MCN2 are called storage transistors. The memory transistors MCN1 and MCN2 function as nonvolatile elements that can change the threshold value in a nonvolatile manner by accumulating and neutralizing charges in the sidewall portions.

The memory cell further includes an analog switch including a P-type MOS transistor MP5 and an N-type MOS transistor MN3 between the P-type MOS transistor MP1 and the N-type MOS transistor MCN1, and the P-type MOS transistor MP2 and the N-type MOS transistor. Between the MCN2, an analog switch including a P-type MOS transistor MP6 and an N-type MOS transistor MN4 is provided.
The gates of the P-type MOS transistor MP5 and the P-type MOS transistor MP6 are connected to the RESN line, and the gates of the N-type MOS transistor MN3 and the N-type MOS transistor MN4 are connected to the RESP line.

  The end of the True-side inverter on the storage transistor side, that is, the source of the storage transistor MCN1 is connected to the True-side source line SLT. Further, the end of the Bar-side inverter on the storage transistor side, that is, the source of the storage transistor MCN2 is connected to the Bar-side source line SLB. Also, the load transistor side ends of both inverters, that is, the sources of the load transistors MP1 and MP2, are connected to the VPS line.

  Among the flip-flops, an inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the True side, and an inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the Bar side. To do. A connection portion between the load transistor MP1 and the storage transistor MCN1 is nodeT, and a connection portion between the load transistor MP2 and the storage transistor MCN2 is nodeB. When nodeT is high potential and nodeB is low potential, the stored content is “0”, and when nodeT is low potential and nodeB is high potential, the stored content is “1”.

  The node T is connected to the bit line BLT (BitLine-True) via the transfer gate MN1, and the node B is connected to the bit line BLB (BitLine-Bar) via the transfer gate MN2. The transfer gates MN1 and MN2 are composed of N-type MOS transistors, and a common word line WL is connected to each gate.

  Further, a P-type MOS transistor MP3, which is a precharging transistor, is connected in parallel to the load transistor MP1, that is, between nodeT and VPST. A P-type MOS transistor MP4, which is a precharging transistor, is connected in parallel with the load transistor MP2, that is, between nodeB and VPSB. A T-side precharge line PRET is connected to the gate of the P-type MOS transistor MP3, and a B-side precharge line PREB is connected to the gate of the P-type MOS transistor MP4. All the P-type MOS transistors MP1 to MP6 are formed in the same N well, and the N well potential is controlled by the VPM signal.

  The configuration and operation procedure of the storage transistors MCN1 and MCN2 of the nonvolatile memory cell of the fifth embodiment are the same as those of the nonvolatile memory cell of the fourth embodiment described with reference to FIGS. The operation procedure is the same. For this reason, the data determination procedure will be described below, and description of other operation procedures will be omitted.

  FIG. 70 is a diagram for explaining a voltage application procedure for determining data in the nonvolatile memory cell according to the fifth embodiment. In this procedure, when the stored content of the nonvolatile memory cell is “1” or “0”, the state of the memory cell (flip-flop) is set according to the stored content, and when the memory cell is in the initial state, This is an operation for forcibly fixing the data to “1”. In a memory array in which a plurality of memory cells are arranged, if the memory contents are "1" and "0" and the memory cells in the initial state coexist, this procedure is collectively applied to all the memory cells in the memory array. By doing so, the state of the flip-flop is set according to the stored content for the memory cell whose stored content is “1” or “0”, and the state of the flip-flop is set for the memory cell in the initial state. Forced to "1". This procedure is executed when the memory is activated.

  The procedure shown in FIG. 70 is as follows. This procedure is executed under the condition that the word line WL and the bit lines BLT and BLB are set to 0V, RESN is set to 0V, RESP is set to Vcc, and VPS and VPM are set to Vcc. First, at time t0, the source potentials SLT and SLB are raised from 0 V to Vcc, and the storage transistors MCN1 and MCN2 are turned off. At time t1, the precharge control signals PRET and PREB are lowered from Vcc to 0V to turn on the precharge transistors MP3 and MP4 and charge nodeT and nodeB to Vcc.

  At time t2, PRET and PREB are returned to Vcc, and from time t3, the True-side source potential SLT is slowly lowered toward 0V. Then, the Bar-side source potential SLB is gradually lowered to 0 V at time t4 which is later than time t3. At this time, control is performed so that SLB-SLT = ΔVs (for example, ΔVs = 0.2 V). As a result, the source-drain voltage of the storage transistor MCN2 is controlled to be higher by ΔVs than the source-drain voltage of the storage transistor MCN1, thereby reducing the apparent threshold voltage on the storage transistor MCN2 side. It can be increased by ΔVs.

  At this time, when the memory content of the memory cell is “1”, MCN1 having a lower threshold voltage is turned on earlier than MCN2, so that nodeT is first lowered to 0V, and nodeB becomes Vcc, The data of the flip-flop is fixed to “1”. On the other hand, when the memory content of the memory cell is “0”, even if the threshold voltage increases by ΔVs, the threshold voltage of the memory transistor MCN2 is still lower than the threshold voltage of the memory transistor MCN1. Since the memory transistor MCN2 is turned on first, nodeB is first pulled down to 0V, nodeT becomes Vcc, and the data of the flip-flop is determined to be "0".

  Further, when the memory content of the memory cell is “undefined”, that is, when the threshold voltages of MCN1 and MCN2 are both Vth0, the apparent threshold voltage of the memory transistor MCN1 is the threshold voltage of the memory transistor MCN2. Since it is lower than the voltage by ΔVs, MCN1 is turned on earlier than MCN2, nodeT is first pulled down to 0V, nodeB becomes Vcc, and the flip-flop data is determined to be “1”.

  A memory cell in which the threshold voltages of MCN1 and MCN2 are both Vth0 is often a cell that has not yet been written or rewritten. In such a memory cell, there is no deterioration of the transistor due to rewriting. For the setting of, only the initial threshold voltage variation of the transistor needs to be considered. Therefore, for example, about 0.2V is considered sufficient.

  The voltage application procedure shown in FIG. 70 is a procedure for determining the memory cell in the initial state as data “1”. However, in the source potential control of the storage transistor, only the potential relationship between SLT and SLB is reversed. It is also possible to determine the memory cell of “0” as data “0”. In FIG. 70, since PREB and PRET are the same voltage, they can be a common signal (for example, a PRE signal).

[Sixth and seventh embodiments]
FIG. 71 is a circuit block of an RFID chip on which the above-described nonvolatile memory cell is mounted. An antenna L disposed outside the chip is connected to the pads P1 and P2 in order to receive an RF signal transmitted from an external reader. A power supply capacitor CT having a capacitance of 120 pF, a voltage clamp circuit (Voltage Clamp), a power supply modulator (Modulator), and a bridge rectifier are connected between the pads P1 and P2. A power supply stabilization capacitor CF is connected to the output of the bridge rectifier, and a control signal of a voltage regulator (Regulator) for detecting the output voltage is fed back to the voltage clamp circuit to stabilize the power supply voltage. The output of the bridge rectifier is connected to a Vcc detection circuit (Vcc Detector) that generates an internal power supply voltage (Vcc) and a booster circuit (Vpp Generator) that generates various voltages other than Vcc. The output of the bridge rectifier includes a circuit (Mode) for detecting an operation mode included in the RF signal received by the bridge rectifier.
A selector, a clock detection circuit (Clock Extractor), and a circuit (Data Modulator) for extracting write data to the module (EEPROM) of the nonvolatile memory device are provided. The controller (C controller) receives operation mode data and controls the operation of the module (EEPROM) of the nonvolatile memory device.

  The module (EEPROM) of the non-volatile storage device mounted on the RFID chip has an ID number for chip authentication, an address for courier service, and product information (price, date of production, production location, production) that replaces the barcode. The required information (e.g. flight number, owner name, boarding place, destination).

  FIG. 72 is a schematic chip plan view of a system LSI which is an example of a semiconductor integrated circuit device on which the nonvolatile memory cell of the present invention is mounted. The system LSI shown in the figure is not particularly limited, but a large number of external connection electrodes 120 such as bonding pads are arranged on the periphery of the semiconductor substrate, and an external input / output circuit 121 and an analog input / output circuit 122 are provided inside thereof. Yes. The external input / output circuit 121 and the analog input / output circuit 122 use an external power supply having a relatively high level such as 3.3V as an operation power supply. The level shift circuit 123 steps down the external power supply to an internal power supply voltage such as 1.8V.

  Inside the level shift circuit 123 are a static random access memory (SRAM) 124, a central processing unit (SPU) 125, a cache memory (CACH) 126, a logic circuit (Logic) 127, a phase locked loop circuit ( PLL) 128, an analog / digital conversion circuit (ADC) 129, a digital / analog conversion circuit (DAC) 130, and a system controller (SYSC) 131. Reference numerals 132, 133, and 134 denote electrically erasable and writable nonvolatile memories (EEPROMs), respectively, each having a predetermined capacity of the nonvolatile memory device of the present invention.

  The nonvolatile memory 132 is used for storing relief information (control information for replacing defective memory cells with redundant memory cells) of the SRAM 124.

  The nonvolatile memory 133 is used for storing information for specifying the circuit constant of the constant trimming circuit for adjusting the circuit constant of the analog circuit, or for storing trimming data of the oscillation frequency of the analog circuit. Further, it is used for storing information for specifying the reference voltage of the voltage trimming circuit, and is mounted in place of the relief program circuit by the fuse.

  The nonvolatile memory 134 has a memory capacity of 256 bits and is used for storing chip ID information, chip operation mode information, and desired data.

A diagram showing a conventional memory cell configuration The figure explaining the data setting method and read margin in the conventional memory cell The figure which shows the write-voltage application procedure to the non-volatile data storage part in the conventional memory cell The figure explaining the data transfer method from the non-volatile data storage part to the flip-flop part in the said conventional memory cell The figure which shows the structure of the memory cell of 6 transistor structure which is 1st Embodiment of this invention. The figure which shows the structure of the memory | storage device which arranged the said memory cell in the array form The figure which shows the data write voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data write voltage application procedure to the memory transistor in the said memory cell. The figure which shows the data erasing voltage application procedure of the said memory transistor The figure which shows the data erase voltage application procedure to the memory transistor in the said memory cell The figure explaining the data setting method and read-out margin in the said memory cell The figure which shows the data read-out voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data read voltage application procedure to the memory transistor in the said memory cell. Configuration diagram of a memory cell in which the channel width of one load transistor is widened and the conduction resistances of both inverters are unbalanced Configuration diagram of a memory cell with an additional capacitor connected to unbalance the capacitance of both inverters The figure which shows the structure of the memory cell of the VPS division | segmentation type | mold 8 transistor structure which is 2nd Embodiment of this invention. The figure which shows the structure of the memory | storage device which arranged the said memory cell in the array form The figure which shows the data write voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data write voltage application procedure to the memory transistor in the said memory cell. The figure which shows the data erasing voltage application procedure of the said memory transistor The figure which shows the data erase voltage application procedure to the memory transistor in the said memory cell The figure explaining the data setting method and read-out margin in the said memory cell FIG. 6 is a diagram for explaining a data confirmation procedure for confirming to “1” even when the memory cell is not yet written. The figure explaining the read margin of each data of the above-mentioned data confirmation procedure The figure explaining the procedure which fixes the said memory cell of an initial state to "1" The figure which shows the data read-out voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data read voltage application procedure to the memory transistor in the said memory cell. The figure explaining the data confirmation procedure of the said memory cell The figure explaining the data confirmation procedure of the said memory cell The figure explaining the data confirmation procedure of the said memory cell Configuration diagram of a memory cell in which the channel width of one load transistor is widened and the conduction resistances of both inverters are unbalanced Configuration diagram of a memory cell with an additional capacitor connected to unbalance the capacitance of both inverters The figure explaining the method of measuring the threshold voltage of a memory transistor The figure which shows the structure of the memory cell of the source line division | segmentation type 8 transistor structure which is 3rd Embodiment of this invention. The figure which shows the structure of the memory | storage device which arranged the said memory cell in the array form The figure which shows the data write voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data write voltage application procedure to the memory transistor in the said memory cell. The figure which shows the data erasing voltage application procedure of the said memory transistor The figure which shows the data erase voltage application procedure to the memory transistor in the said memory cell The figure explaining the data setting method and read-out margin in the said memory cell FIG. 6 is a diagram for explaining a data confirmation procedure for confirming to “1” even when the memory cell is not yet written. The figure explaining the read margin of each data of the above-mentioned data confirmation procedure The figure explaining the procedure which fixes the said memory cell of an initial state to "1" The figure which shows the data read-out voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data read voltage application procedure to the memory transistor in the said memory cell. The figure explaining the data confirmation procedure of the said memory cell The figure explaining the data confirmation procedure of the said memory cell The figure explaining the data confirmation procedure of the said memory cell Configuration diagram of a memory cell in which the channel width of one load transistor is widened and the conduction resistances of both inverters are unbalanced Configuration diagram of a memory cell with an additional capacitor connected to unbalance the capacitance of both inverters The figure explaining the method of measuring the threshold voltage of a memory transistor The figure which shows the layout on the semiconductor substrate of the memory cell of 2nd, 3rd embodiment. The figure which shows the structure of the memory cell of the VPS division type 12 transistor structure which is 4th Embodiment of this invention. The figure which shows the structure of the memory | storage device which arranged the said memory cell in the array form The figure which shows the data write voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data write voltage application procedure to the memory transistor in the said memory cell. The figure which shows the data erasing voltage application procedure of the said memory transistor The figure which shows the data write voltage application procedure to the memory transistor in the said memory cell. The figure explaining the data setting method and read-out margin in the said memory cell FIG. 6 is a diagram for explaining a data confirmation procedure for confirming to “1” even when the memory cell is not yet written. The figure explaining the read margin of each data of the above-mentioned data confirmation procedure The figure explaining the procedure which fixes the said memory cell of an initial state to "1" The figure which shows the data read-out voltage application procedure of the memory transistor of the said memory cell. The figure which shows the data read voltage application procedure to the memory transistor in the said memory cell. The figure explaining the data confirmation procedure of the said memory cell The figure explaining the data confirmation procedure of the said memory cell The figure explaining the data confirmation procedure of the said memory cell The figure explaining the method of measuring the threshold voltage of a memory transistor The figure which shows the structure of the memory cell of the source line division | segmentation type 12 transistor structure which is 5th Embodiment of this invention. FIG. 6 is a diagram for explaining a data confirmation procedure for confirming to “1” even when the memory cell is not yet written. Configuration diagram of an RFID chip using the memory cell Schematic plan view of a system LSI chip using the memory cell

Explanation of symbols

MP1, MP2 Load transistor MP3, MP4 Precharging transistor MCN1, MCN2 Memory transistor MN1, MN2 Transfer gate (gate transistor)
108 Insulating film side spacer

Claims (25)

A nonvolatile semiconductor memory device having a flip-flop configured by cross-connecting two inverters and two gate transistors respectively connected to nodes on both sides of the flip-flop,
The inverter includes a load transistor and a storage transistor connected in series,
The storage transistor is configured by a storage transistor capable of controlling a threshold voltage by electron injection near the gate,
Each of the two gate transistors is connected to an individual bit line controlled between an operating power supply voltage and a ground voltage,
A word line controlled between an operating power supply voltage and a ground voltage is commonly connected to the gate electrodes of the two gate transistors,
Further, a high-voltage supply line for supplying a high voltage at the time of writing or erasing is connected to the source of the storage transistor and the source of the load transistor. The memory transistor includes an insulating film side spacer formed on a side portion of the gate electrode, and a low impurity concentration region formed on a peripheral portion of the drain,
At the time of writing, a high voltage is applied to the source of the storage transistor and a high voltage is applied to the gate of the storage transistor via the source of the load transistor, thereby injecting channel hot electrons into the insulating film side spacer. Write information,
2. The nonvolatile semiconductor memory device according to claim 1, wherein at the time of erasing, information is erased by applying an avalanche hot hole to the insulating film side spacer by applying a high voltage to the source of the memory transistor. The inverter has a precharging transistor in parallel with the load transistor,
3. The nonvolatile semiconductor memory device according to claim 1, wherein the precharge transistor is on / off controlled independently of the load transistor by a precharge control voltage. 4.   The nonvolatile semiconductor memory device according to claim 3, wherein a high voltage supply line for supplying a high voltage to a source of the load transistor is separately provided for the two inverters.   The nonvolatile semiconductor memory device according to claim 3, wherein a high voltage supply line for supplying a high voltage to a source of the storage transistor is separately provided for the two inverters.   5. The switch means further connected between the load transistor and the storage transistor connected in series and electrically connecting (turning on) or shutting off (off) the load transistor and the storage transistor. Nonvolatile semiconductor memory device according to   6. A switch means further connected between the load transistor and the storage transistor connected in series and electrically connecting (turning on) or blocking (off) the load transistor and the storage transistor is provided. Nonvolatile semiconductor memory device according to   8. The nonvolatile semiconductor memory device according to claim 1, wherein conduction resistances of load transistors of the two inverters are unbalanced.   8. The nonvolatile semiconductor memory device according to claim 1, wherein capacitances of the two inverters with respect to a power supply voltage line or a ground are unbalanced. 9.   8. The nonvolatile semiconductor memory device according to claim 1, wherein the conduction resistances of the memory transistors of the two inverters are unbalanced. 9. Using the nonvolatile semiconductor memory device according to claim 3,
Increasing the source voltage of the two storage transistors to turn off the storage transistors;
Applying the same precharge voltage to the two memory transistors via the precharge transistor;
Dropping the source voltages of the two storage transistors synchronously;
A method for determining the state of a non-volatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 3,
Turning on the precharge transistor and applying the same precharge voltage to the two storage transistors;
Turning off the precharge transistor to stop application of the precharge voltage;
A method for determining the state of a non-volatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 6 or 7,
A step of turning on the precharging transistor and applying the same precharge voltage to the two storage transistors in a state in which the switch means is off;
Turning on the switch means;
Turning off the precharge transistor to stop application of the precharge voltage;
A method for determining the state of a non-volatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 1,
Turning on the gate transistor and applying a precharge voltage from the bit line to the two storage transistors while the source voltage of the two load transistors is low;
Turning off the gate transistor to block a precharge voltage from the bit line;
Increasing the source voltage of the load transistor;
A method for determining the state of a non-volatile semiconductor memory device.   8. The non-volatile semiconductor memory device according to claim 3, wherein only one of the precharge transistors of the two inverters is turned on to force the state of the flip-flop. A method for determining a state of a nonvolatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 4 or 6,
Increasing the source potential of the two storage transistors to turn off the two storage transistors;
Applying different precharge voltages to the two memory transistors via the precharge transistor,
Lowering the source potential of the two storage transistors synchronously;
A method for determining the state of a non-volatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 5 or 7,
Increasing the source potential of the two storage transistors to turn off the two storage transistors;
Applying the same precharge voltage to the two memory transistors via the precharge transistor;
Lowering the source potential of the two storage transistors with a potential difference;
A method for determining the state of a non-volatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 3,
A method for measuring a state of a nonvolatile semiconductor memory device, wherein a measurement voltage is supplied to one of the memory transistors by turning on one of the two precharge transistors and turning off the other. Using the nonvolatile semiconductor memory device according to claim 5 or 7,
By turning on one of the two precharge transistors and turning off the other, supply a measurement voltage to one of the memory transistors,
Furthermore, a measuring voltage is supplied to the source of the other memory transistor, and a state measuring method for a nonvolatile semiconductor memory device. Using the nonvolatile semiconductor memory device according to claim 6 or 7,
By turning on one of the two precharge transistors and turning off the other, supply a measurement voltage to one of the memory transistors,
Furthermore, the state measuring method of the nonvolatile semiconductor memory device characterized by turning off the switch means. A nonvolatile semiconductor memory device according to any one of claims 1 to 8, a circuit to be repaired,
A repair circuit that replaces the circuit to be repaired,
A semiconductor integrated circuit device in which the nonvolatile memory device is a relief information memory circuit for specifying a to-be-relieved circuit to be replaced by the relief circuit. A nonvolatile semiconductor memory device according to any one of claims 1 to 8, an analog circuit, and a constant trimming circuit for adjusting a circuit constant thereof,
A semiconductor integrated circuit device, wherein the nonvolatile memory device is an information memory circuit for specifying the circuit constant of the constant trimming circuit. A nonvolatile semiconductor memory device according to any one of claims 1 to 8, an oscillation circuit, and a frequency trimming circuit for adjusting the oscillation frequency,
A semiconductor integrated circuit device, wherein the nonvolatile storage device is an information storage circuit for specifying the oscillation frequency of the frequency trimming circuit. A nonvolatile semiconductor memory device according to any one of claims 1 to 8, a reference voltage generation circuit, and a voltage trimming circuit that adjusts the generated reference voltage.
A semiconductor integrated circuit device, wherein the nonvolatile memory device is an information memory circuit for specifying the reference voltage of the voltage trimming circuit. A nonvolatile semiconductor memory device according to claim 1 and a security circuit for specifying a chip,
A semiconductor integrated circuit device, wherein the nonvolatile storage device is an information storage circuit for specifying a chip of the security circuit.

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