JP2005175411A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow reducing a cell area of a non-volatile memory composed of a single layer polysilicon gate and to enable operation of the memory in a superlow power consumption. <P>SOLUTION: A reverse bias voltage, such as -5V, is applied to a p-type impurity area 11 positioned on a substrate surface of an n-type well 4 of a lower portion of a floating gate 6 through a gate oxide film 5 and is applied to a junction constructed by the n-type well 4, and hot electrons produced from a tunnel phenomenon between bands is implanted into the floating gate 6, then, the write is carried out. It is designed that the write time is about 10 μs and the leakage current of the junction in writing is approximate 100 ns, therefore, the energy necessary for writing is reduced up to 5 pJ, that is, reduced to 1/100 or less, compared with a writing energy used in implantation of channel hot electron of the customary stacked gate type memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having an electrically erasable and writable nonvolatile memory element, which can be manufactured without adding a new process to a normal complementary MIS transistor manufacturing process, and has a low voltage, The present invention relates to a nonvolatile memory device capable of writing with low power consumption.

  A flash EEPROM (hereinafter referred to as a flash memory) is provided as a non-volatile storage device capable of electrically erasing data to be stored collectively in a predetermined unit and electrically writing data. In flash memory, memory cells are composed of electrically erasable and writable nonvolatile memory elements. Data and programs once written in the memory cells are erased, and new data and programs are rewritten in the memory cells. (Programming) is possible.

  Therefore, when this flash memory or a macro computer with built-in flash memory is incorporated into an application system, if data changes, program bug corrections, or program updates are required, they are stored in the flash memory. Since data and programs can be changed on the application system, the development period of the application system can be shortened, and flexibility in the program development of the application system can be obtained.

  On the other hand, in recent years, the application fields of IC (Integrated Circuits) cards are expanding dramatically, and in particular, an authentication method called a radio tag or RFID (Radio Frequency Identification) is used instead of a conventional barcode reading method. I'm starting. In an RFID system, a high frequency of about 10 MHz to 3 GHz transmitted from a reader device is received by an RFID chip existing within a range of several mm to 1 m, and a DC voltage is received from the high frequency received by an antenna provided in the chip. To generate and operate the internal circuit. The RFID chip stores authentication data in a non-volatile memory. This data is modulated into an RF signal, transmitted, and received by the reader device to authenticate the RFID chip. A nonvolatile memory mounted on an RFID chip has two major requirements. The first is ultra-low cost, which is inevitable because the market price of RFID chips is 50 yen or less. The second is to operate with ultra-low power consumption. This requirement is because the RFID chip receives high frequency and the power that can be generated inside the chip is extremely small. In addition to the non-volatile memory, it is necessary to simultaneously operate a logic circuit, a transmission circuit, etc. Because there is.

  After completing the present invention, the inventors conducted a survey of known examples for the following viewpoints A and B.

  Viewpoint A is whether a non-volatile memory transistor is composed of a single-layer polysilicon gate and can be manufactured without adding a new process to a normal complementary MIS transistor (hereinafter referred to as a CMOS transistor). That is, it is a viewpoint of whether it is low-cost, and viewpoint B is a viewpoint of the power consumption required for write / erase operation, and the time required for write / erase.

  As a result, for viewpoint A, Patent Literatures 1 to 4 and Non-Patent Literature 1 were discovered.

On the other hand, for viewpoint B, Patent Documents 5 and 6 and Non-Patent Document 2 were discovered.
US Pat. No. 5,440,159 US Pat. No. 5,504,706 JP-A-4-212471 US Patent No. 5,457,335 US Pat. No. 6,631,087 US Pat. No. 6,617,637 Osaki et al. "A single Ploy EEPROM Cell Structure for Usein Standard CMOS Processes", IEEE Journal of Solid State Circuits, VOL. 29, NO. 3, March 3 1994, p. J. et al. Hyde et al., “Floating-Gate Trimmcd, 14-Bit, 250 Ms / s Digital-to-Analog Converter in Standard 0.25 μm CMOS”, Symposium on VLSI Circuits, 2002, pp. 328-331

  As a first problem, the memory cell structure is complicated in a vertically stacked memory cell of a floating gate and a control gate, that is, a stacked gate type memory cell, which has been generally used in NOR flash memory products. It has been clarified by the present inventors that there is a problem that the manufacturing cost is increased due to the fact that In particular, in an RFID chip whose market is rapidly expanding in recent years, adopting a stacked gate type memory cell as a nonvolatile memory leads to an increase in manufacturing cost. According to the study of the present inventor, this is considered to be caused by an increase in the following photomask and manufacturing process. That is, since the tunnel oxide film of the flash memory is thicker than the gate oxide film of the logic circuit transistor or the DRAM cell transistor, the mask for forming the tunnel oxide film, the polysilicon film for the floating gate of the flash memory, Addition / processing mask, mask for processing word line of flash memory, mask for impurity implantation for forming drain region of flash memory, and low-concentration N type source / drain of high breakdown voltage transistor constituting write / erase circuit An impurity implantation mask for forming the region and the low-concentration P-type source / drain region is required, and the number of masks to be added is at least six. For this reason, it is difficult in terms of cost to provide an RFID chip equipped with a nonvolatile memory using stacked gate type memory cells. In order to solve this, a nonvolatile memory element having a single-layer polysilicon gate structure may be formed.

  According to the results of investigation and examination of the prior art by the present inventors, the following points have been clarified. First, in the electrically writable nonvolatile memory cell disclosed in US Pat. No. 5,440,159, as shown in FIG. 36, the active region 181 on the silicon substrate, and In the region 182, N-type impurity regions 190 and 191 are used as sources and drains, a select transistor comprising a select gate 183, and N-type impurity regions 191 and 192 are used as sources and drains and a memory transistor comprising a floating gate 184 The N-type impurity region 189 is configured as a control gate, and the region 186 in the pattern 185 is designed such that the gate oxide film thickness is thinner than the gate oxide film thickness of the select transistor. In the conventional nonvolatile memory cell write operation, 12 V is applied to the control gate 189 to raise the potential of the floating gate 184, and electron injection using the tunnel current from the substrate surface of the channel region 188 of the memory transistor is performed. Is done.

  In the conventional nonvolatile memory cell, in order to form the high-concentration N-type impurity region 189 on the silicon substrate surface below the floating gate 184, it is necessary to change the manufacturing process of a normal CMOS transistor, and Since a high voltage transistor is required for a circuit for controlling the operating voltage 12V necessary for writing, there is a second problem that a large process is required to be added to a normal CMOS transistor manufacturing process. As a result, an increase in manufacturing cost is inevitable.

  In addition, in the electrically writable nonvolatile memory cell disclosed in US Pat. No. 6,631,087, as shown in a cross-sectional structure in FIG. N-type impurity region 207, P-type impurity regions 208 and 209 provided in the N-type well 205 region. And 5 V is applied to raise the potential of the floating gate 215 through the electrostatic capacitance of the gate oxide film 206, and the ground potential is applied to the N-type impurity region 212 in the N-type well 204 region. -5V is applied to 213 and 214, and the junctions of the P-type impurity regions 213 and 214 are And injecting hot electrons generated by band-to-band tunneling phenomenon into the floating gate 215 in the depletion layer, it is writing operation. In the conventional memory cell structure, the N-type impurity regions 207 and 212 for fixing the potentials of the N-type wells 204 and 205 provided with two PMOSs are necessary. As a result, the cell area is large. The third problem has been found by the present inventors. The size of the memory cell area itself does not directly affect the manufacturing cost. However, since the area of the nonvolatile memory module increases according to the memory capacity, the chip area increases, and the number of chips that can be obtained from one wafer is reduced, resulting in an increase in the manufacturing cost of the chips.

  An object of the present invention is to provide a memory cell structure capable of writing with a low voltage and low power consumption in a nonvolatile memory composed of a single-layer polysilicon gate.

  Another object of the present invention is to provide a memory cell structure having a small cell area, that is, an inexpensive nonvolatile memory module even when the capacity is increased, in a nonvolatile memory composed of a single layer polysilicon gate. It is in.

  Another object of the present invention is a semiconductor equipped with a non-volatile memory capable of writing with low voltage and low power consumption without adding a new process to a normal logic circuit process, analog circuit process or general-purpose DRAM process. To provide an apparatus.

  Another object of the present invention is to provide a technique for using a nonvolatile memory cell composed of a single-layer polysilicon gate in a memory module, an analog circuit relief circuit, or a trimming circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] The first point of view is that it is not necessary to have a transistor structure as an element for injecting hot electrons into a floating gate due to a band-to-band tunneling (hereinafter referred to as BTBT) phenomenon. An N-type well region formed through a gate insulating film under a floating gate extending on the substrate, and a P-type impurity region is disposed adjacent to the lower end of the floating gate in the surface region of the N-type well. It is planned to reduce the cell area of the nonvolatile memory by providing the charge injection region.

  Since the N-type well region including the charge injection region is operated as a so-called floating potential in a state where the potential is not fixed from the outside at all times, it is not necessary to form an N-type impurity region for contact connection to the metal wiring. In particular, this contributes to a reduction in the memory cell area.

[2] A second aspect is to reduce the power consumption of the write operation by BTBT-induced hot electron injection from the P-type impurity region. “Novel Electron Injecting Method Band-to-Band Tunneling Induced Hot Electron (BHE) for Flash Memory with a Pt. Channel” by Ohnakado et al. As disclosed in H.279-282, a negative voltage is applied to the gate of the NMOS transistor and a positive voltage is applied to the drain to cause electron emission due to a tunnel current from the gate to the drain, and a positive voltage is applied to the gate of the PMOS transistor to the drain. Comparing BTBT-induced hot electron injection from the drain to the gate by applying a negative voltage, it can be seen that the ratio of the gate current to the current flowing from the drain to the substrate, the so-called injection efficiency, is 100 times higher in the PMOS transistor than in the NMOS transistor. ing. This is because the write method using the BTBT-induced hot electron injection from the P-type impurity region in the present invention has a constant write time as compared with the write method using the tunnel current that is normally used. The drain current can be reduced to 1/100 or less, and low power consumption is realized.

[3] A third aspect is that the control gate for controlling the potential of the floating gate is not a transistor structure, but is floated on the surface region of an N-type well formed on a P-type silicon substrate via a gate insulating film. A gate is arranged, and a P-type impurity region is arranged adjacent to one end of both ends of the floating gate and an N-type impurity region is arranged adjacent to the other end in the surface region of the N-type well. Therefore, the reduction of the memory cell area is planned.

[4] A fourth aspect is that, as a control gate for controlling the potential of the floating gate, a P-type well region is formed inside a deep N-type well region formed on a P-type silicon substrate instead of a transistor. A floating gate is disposed in the surface region of the P-type well via a gate insulating film, and a P-type impurity region is adjacent to one end of both ends of the floating gate in the surface region of the P-type well. As a result of arranging an N-type impurity region adjacent to each other, it is possible to apply either a positive voltage or a negative voltage to the control gate, expanding the freedom of selection in the operation method of the memory cell and lowering the operation voltage. It is intended to be designed.

[5] A fifth aspect is that when memory cells are arranged in an array, a select transistor connected in series to a non-volatile memory transistor connected to a floating gate is provided, so that an arbitrary bit connected to a certain bit line is provided. When a memory transistor accidentally enters an over-erased state (a state in which a threshold voltage becomes negative), it does not cause a read failure when reading memory cells on the same bit line other than the memory cell transistor. To do.

  In addition, when including a logic circuit and an external interface circuit each having a MIS transistor on the semiconductor substrate, the external interface circuit has a relatively thick gate insulating film for improving the electrostatic withstand voltage of the input MIS transistor whose gate is connected to the external terminal. In a semiconductor integrated circuit that steps down an operating power supply such as 3.3V supplied from the outside and uses it as an operating power supply for an internal circuit such as a logic circuit, an external interface that operates by receiving 3.3V The MIS transistor in the circuit has a thicker gate oxide film than the MIS transistor in the internal circuit. Paying attention to this, the gate insulating film under the floating gate and the gate insulating film of the nonvolatile memory transistor are substantially equal to the gate insulating film of the MIS transistor included in the external interface circuit (equal in an allowable error range due to process variations). ) What is necessary is just to set a film thickness. In short, the gate insulating film of the MIS transistor for the nonvolatile memory transistor and the gate insulating film of the MIS transistor included in the external interface circuit are manufactured together using the same process or a common photomask. Further, the gate insulating film of the select transistor may be set to a film thickness substantially equal to the gate insulating film of the MIS transistor constituting an internal circuit such as a logic circuit. As described above, priority is given to not complicating the manufacturing process of the semiconductor device by sharing the gate insulating film thickness in the nonvolatile memory circuit of the single-layer gate structure with the gate insulating film thickness of the MIS transistor of other circuits. Thus, long-term information retention performance by the nonvolatile memory circuit can be realized.

[6] The sixth aspect considers a relief information storage circuit as an application of the nonvolatile memory. At this time, the semiconductor device includes a relief circuit and a relief circuit that replaces the relief circuit on a semiconductor substrate, and the nonvolatile memory circuit specifies a relief circuit that should be replaced by the relief circuit. Used as an information storage circuit.

  As another relief information storage circuit for the relief circuit, a fuse program circuit for storing relief information according to the blown state of the fuse element may be further provided. Remedy for defects detected at the wafer stage is performed by a fuse program circuit, and the efficiency detected by using the electrical program circuit for defects detected after burn-in can be improved. In other words, the yield of the semiconductor integrated circuit is improved. A defect cannot be remedied after burn-in only by the fuse program circuit. The circuit scale or chip occupying area becomes larger with only the electrical programming circuit as compared with the combined use with the fuse program circuit.

The circuit to be relieved may be a memory cell array with a built-in DRAM. The circuit to be rescued may be a memory cell array of a microcomputer built-in DRAM.
The circuit to be relieved may be a memory cell array of a microcomputer built-in SRAM.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a nonvolatile memory composed of a single-layer polysilicon gate, a P-type impurity region provided with a gate oxide film interposed on the surface of the silicon substrate below the floating gate end and the P-type impurity region are included. Since the surface region of the junction formed by the N-type well is an electron injection region by band-to-band tunneling, it is possible to realize a nonvolatile memory capable of writing operation with ultra-low power consumption by reducing the memory cell area.

  The N-type well region in which the electron injection region is formed can be operated even when the potential is not forcibly fixed from the outside, that is, a floating potential, and a high-concentration impurity region for contact connection to the metal wiring is formed. Since it does not need to be formed, the memory cell area can be reduced, and a large-capacity nonvolatile memory can be provided at low cost.

  Non-volatile memory circuits are non-volatile memory transistors that use a single polysilicon layer, which can simplify the device structure and add a completely new process to the normal logic circuit process or general-purpose DRAM process. Thus, it is possible to realize a semiconductor device including a nonvolatile memory that operates with low power consumption.

FIG. 1 shows a cross-sectional structure of a memory cell for explaining the best mode for implementing a nonvolatile memory included in a semiconductor device according to the present invention. In the figure, an N-type well 4 having an average phosphorus concentration of 2 × 10 ¹⁷ cm ⁻³ and an average boron electrically isolated by a device isolation oxide film 2 having a depth of 300 nm on the surface region of a P-type silicon substrate 1 having a resistivity of 10 Ωcm. A P-type well 3 having a concentration of 3 × 10 ¹⁷ cm ⁻³ is formed, and a thickness of 200 nm and an average phosphorus concentration are formed on one surface region of the N-type well 4 via a gate insulating film 5 made of a silicon oxide film having a thickness of 7 nm. A floating gate 6 made of a polysilicon film of 2 × 10 ²⁰ cm ⁻³ is disposed, and an N-type impurity region 7 having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ is adjacent to one end of the floating gate 6 and adjacent to the other. and are arranged P-type impurity region 8 of the average boron concentration ^1x10 20 ^{cm -3,} wherein the N-type impurity region 7 P-type impurity region 8 is tangent Which is connected to the word line WL is, the surface region of the P-type well 3, the gate insulating film 5 and the floating gate 6 is arranged extending, N-type impurity regions with an average arsenic concentration 1x10 ²⁰ cm ^-3 A memory transistor is constituted by a source 9 made of and a drain 10 made of an N-type impurity region having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , the source 9 is connected to a source line Vss, and the drain 10 is connected to a read bit line RBL Further, the gate insulating film 5 and the floating gate 6 are extended and arranged on the other surface region of the N-type well 4, and a P-type impurity region 11 having an average boron concentration of 1 × 10 ²⁰ cm ⁻³ is formed. And the P-type impurity region 11 is connected to a write bit line (PBL) so that the ultra-low power consumption nonvolatile memory of the present invention Is configured.

  FIG. 2 shows an electrical equivalent circuit of the nonvolatile memory cell included in the semiconductor device according to the present invention shown in FIG. In the figure, a coupling capacitor C2 and a capacitor CJ in a charge injection region are connected to a floating gate of the memory transistor MT, a drain of the memory transistor MT is connected to a read bit line RBL, and the charge injection region is a write bit. Connected to the line PBL, the coupling capacitor C2 is connected to the word line WL. The coupling capacitor C2 is designed to be about five times or more the sum of the gate capacitance of the memory transistor MT and the capacitor CJ in the charge injection region, and the capacitance from the word line WL to the floating gate is designed. The coupling ratio is 0.83 or more.

  FIG. 3 shows a planar structure of a nonvolatile memory cell included in the semiconductor device according to the present invention shown in FIG. In the figure, the floating gate 6 is disposed on one surface region of the two N-type wells 4 via the gate insulating film 5, and the N-type impurity region 7 and the P-type impurity region 8 are The floating gate 6 is connected to the word line WL13 made of the first metal film through the contact hole 12, and the other surface region of the two N-type wells 4 extends through the gate insulating film 5. The P-type impurity region 11 adjacent to the end of the floating gate 6 is connected to the first metal film 16 through the contact hole 12, and the first metal film 16 is connected to the second metal film through the through hole 17. The surface region of the P-type well connected to the write bit line PBL18 and arranged in the middle of the two N-type wells 4 is also connected to the front via the gate insulating film 5. The floating gate 6 extends, the source 9 and the drain 10 are disposed adjacent to both ends of the floating gate 6, and the source 9 is connected to the source line Vss made of the first metal film through the contact hole 12. The drain 10 is connected to a first metal film 14 through a contact hole 12, and the first metal film 14 is connected to a read bit line RBL 19 made of a second metal film through a through hole 17. .

  FIG. 4 shows operating voltage conditions of the nonvolatile memory cell of the present invention shown in FIG. First, in a write operation (Program), a positive voltage such as 6V is applied to the word line WL, and then a negative voltage such as −5V is applied to the write bit line PBL. The junction formed by the P-type impurity region 11 and the N-type well 4 is applied with a reverse bias of −5V, and the potential of the floating gate 6 rises to about 5V due to electrostatic coupling with the word line. Therefore, a strong vertical electric field is generated in a region immediately below the gate oxide film in the depletion layer of the junction, and hot electrons are generated due to the BTBT phenomenon. The hot electrons are injected into the floating gate 6 according to the electric field direction. In this write operation, the write bit line current was about 100 nA, the write time was about 10 μs, and the threshold voltage of the memory transistor after the write was about 5V. The energy required for writing is 5V × 100 nA × 10 μs = 5 pJ. In the stacked gate type memory cell generally used in the conventional NOR type flash memory product, channel hot electron injection is adopted, and the write drain voltage is 5 V, the write current is 500 μA, and the write time is about 1 μs. Therefore, the energy required for writing is 5 V × 500 μA × 1 μs = 2500 pJ. Therefore, the write energy of the nonvolatile memory cell of the present invention can be reduced to 1/500 that of the prior art, and a write operation with ultra-low power consumption is realized.

  In the read operation (Read), a voltage such as about 1 V is applied to the read bit line, and then a voltage such as the power supply voltage 3.3 V is applied to the word line WL to determine the threshold voltage of the memory transistor. To do. In the written state, that is, when the floating gate 6 has electron accumulation, the threshold voltage of the memory transistor rises to 3.3 V or more and is turned off during reading, while the erased state, that is, the floating gate 6 When there is no electron storage in the memory cell, the threshold voltage of the memory transistor is lowered to 3.3 V or less, and is turned on at the time of reading.

  There are several means for the erase operation of the nonvolatile memory cell of the present invention. In the first erase (Erase (1)), the word line WL is set to 0 V, a voltage such as 6 V is applied to the write bit line PBL, and electrons are generated by a tunnel current from the floating gate 6 to the P-type impurity region 11. The time required for erasing was about 100 ms, and the threshold voltage of the memory transistor after erasing was about 2V. In the second erase (Erase (2)), the source line Vss is set in a floating state, and then a voltage such as 5V is applied to the word line WL, and then a voltage such as 5V is applied to the read bit line RBL. Then, BTBT hot holes generated at the junction of the drain 10 of the memory transistor are injected into the floating gate 6 to neutralize the accumulated electrons in the floating gate 6. The second erasing time was about 100 μs, and the threshold voltage of the memory transistor after erasing was about 1.5V. Further, in the third erase (Erase (3)), the word line WL is set to 0V, a voltage such as 6V is applied to the read bit line RBL, and electrons are emitted by the tunnel current from the floating gate 6 to the drain 10. The time required for erasing was about 50 ms, and the threshold voltage of the memory transistor after erasing was about 2V.

<< First Example of Ultra Low Power Consumption Nonvolatile Memory >>
FIG. 5 shows a cross-sectional structure of the first nonvolatile memory cell included in the semiconductor device according to the present invention. In this figure, a deep N-type well 251 having a depth of 2 μm and an average phosphorus concentration of 1 × 10 ¹⁷ cm ⁻³ is formed inside the deep N-type well 251 and is a P-type having a depth of 1 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ . The memory cell structure is the same as that of the first example of the nonvolatile memory of the present invention shown in FIG. 1 except that a so-called triple well structure in which the well 252 is disposed is used. To give a difference from the memory cell structure shown in FIG. 1, in the triple well structure, a film is formed on the surface region of the P-type well 252 via a gate insulating film 5 made of a silicon oxide film having a thickness of 7 nm. A floating gate 6 made of a polysilicon film having a thickness of 200 nm and an average phosphorus concentration of 2 × 10 ²⁰ cm ⁻³ is disposed, and an N-type impurity region having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ is adjacent to one of both ends of the floating gate 6. 7, a P-type impurity region 8 having an average boron concentration of 1 × 10 ²⁰ cm ⁻³ is disposed adjacent to the other, and the N-type impurity region 7 and the P-type impurity region 8 are connected and connected to the word line WL. Is a point.

  FIG. 6 shows the operating voltage conditions of the first nonvolatile memory cell of the present invention. First, in a write operation (Program), a positive voltage such as 6V is applied to the word line WL, and then a negative voltage such as −5V is applied to the write bit line PBL. Thus, similarly to the first example of the nonvolatile memory of the present invention, hot electrons generated by the BTBT phenomenon are injected into the floating gate 6. In this write operation, the write bit line current was about 100 nA, the write time was about 10 μs, therefore the write energy was 5 pJ, and the threshold voltage of the memory transistor after the write was about 5V. In this write operation, the junction formed by the P-type well 252 and the deep N-type well 251 is forward-biased. Therefore, the deep N-type well 251 is also subjected to the same 6V as the word line WL. It is necessary to apply a positive voltage.

  Similarly to the first example of the nonvolatile memory of the present invention, the read operation (Read) is performed by applying a voltage of about 1V to the read bit line RBL and then applying the word line WL to the power supply voltage of 3.3V. Such a voltage is applied to determine the threshold voltage of the memory transistor.

  There are several means for the erase operation of the first nonvolatile memory cell of the present invention. The first (Erase (1)), the second (Erase (2)), and the third erase (Erase (3)) are the same as in the first example of the nonvolatile memory of the present invention. In the fourth erase (Erase (4)), a negative voltage such as −6 V is applied to the word line WL, and the potential of the floating gate 6 is transferred to the negative potential side. The electric field strength of the gate insulating film 5 between the floating gates 6 is set to 10 MV / cm or more, and the stored electrons in the floating gate 6 are discharged to the P-type well 3 side by a tunnel current. The main erasing time was about 200 ms, and the threshold voltage of the memory transistor after erasing was about 2V. In this erasing, since a negative voltage such as −6 V is applied to the word line WL, the P-type well 252 also has a negative potential such as −6 V, and the P-type well 252 and the deep N-type well 251 The junction formed by is biased in the reverse direction. Therefore, during the main erase operation, the potential of the deep N-type well 251 may be a ground potential or a power supply voltage such as 3.3V. In the fifth erase (Erase (5)), a negative voltage such as −3 V is applied to the word line WL, a positive voltage such as 3.3 V is applied to the read bit line RBL, and the floating gate is applied. The stored electrons in 6 are emitted to the drain 10 side by a tunnel current. At this time, the erasing time was about 100 ms, and the threshold voltage of the memory transistor after erasing was about 2V. In the fifth erasing operation, a high voltage of about 6 to 8 V required for erasing can be divided and applied to the word line WL and the read bit line RBL, so that the operating voltage of the voltage control circuit And the long-term reliability of the transistor used can be significantly improved. In the sixth erase (Erase (6)), a positive voltage such as 3.3V is applied to the read bit line RBL in the fifth erase, whereas a voltage such as 3.3V is applied to the write bit line PBL. An erase operation is performed by applying a positive voltage. It goes without saying that the sixth erasure can provide the same effect as the fifth erasure.

  FIG. 7 shows a planar structure of the first nonvolatile memory cell included in the semiconductor device according to the present invention. In FIG. 3, the first embodiment of the non-volatile memory of the present invention shown in FIG. 3 except that a deep N-type well 251 and a P-type well 252 included in the deep N-type well 251 are added. The example has the same planar structure.

<< Second Example of Ultra Low Power Consumption Nonvolatile Memory >>
FIG. 8 shows a cross-sectional structure of a second nonvolatile memory cell included in the semiconductor device according to the present invention. In this figure, a polysilicon film having an average phosphorus concentration of 2 × 10 ²⁰ cm ⁻³ with a thickness of 200 nm is formed on the surface region of a P-type well 242 having an average boron concentration of 3 × 10 ¹⁷ cm ⁻³ via a gate insulating film 241 having a thickness of 7 nm. Except that a select gate 243 having a gate length of 0.4 μm is disposed and a select transistor composed of an N-type impurity region having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ and a drain 244 is added. Is a memory cell structure similar to the first example of the nonvolatile memory of the present invention shown in FIG. The source 245 of the select transistor is connected to the drain 10 of the memory transistor, and the drain 244 of the select transistor is connected to the read bit line RBL.

  FIG. 9 shows an electrical equivalent circuit of the second nonvolatile memory cell included in the semiconductor device according to the present invention. In the figure, a coupling capacitor C2 and a capacitor CJ in the charge injection region are connected to the floating gate of the memory transistor MT, the drain of the memory transistor MT is connected to the select transistor ST, and the drain of the select transistor ST is read. Connected to the bit line RBL, the gate of the select transistor ST is connected to the read word line RWL, the charge injection region is connected to the write bit line PBL, and the coupling capacitor C2 is connected to the write word line PWL. . The coupling capacitor C2 is designed to be about five times or more the sum of the gate capacitance of the memory transistor MT and the capacitor CJ in the charge injection region, and the capacitance from the word line WL to the floating gate is designed. The coupling ratio is 0.83 or more.

  FIG. 10 shows the operating voltage condition of the second nonvolatile memory cell of the present invention. First, in a write operation (Program), a positive voltage such as 6V is applied to the word line WL, and then a negative voltage such as −5V is applied to the write bit line PBL. Thus, similarly to the first example of the nonvolatile memory of the present invention, hot electrons generated by the BTBT phenomenon are injected into the floating gate 6. In this write operation, the write bit line current was about 100 nA, the write time was about 5 μs, therefore the write energy was 2.5 pJ, and the threshold voltage of the memory transistor after the write was about 2V.

  In the erase operation (Erase) of the second nonvolatile memory cell of the present invention, a voltage such as 6V is applied only to the write bit line PBL, and electrons are generated by the tunnel current from the floating gate 6 to the P-type impurity region 11. The time required for erasing was about 100 ms, and the threshold voltage of the memory transistor after erasing was about -1.5V.

  In the read operation (Read), the read bit line RBL is precharged to 3.3 V, then 3.3 V is applied to the read word line RWL to turn on the select transistor, and erase / write of the memory transistor. This is done by determining the on / off state corresponding to the state.

  FIG. 11 shows a circuit diagram of four cells in which the second nonvolatile memory cells of the present invention are arranged in an array. FIG. 12 shows a planar structure corresponding to the circuit diagram shown in FIG. The figure shows an N-type well 25, a P-type well 24, an active region 21 for forming a coupling capacitor, an active region 22 for forming a memory transistor and a select transistor, and an activity for forming a charge injection region. A region 23 is disposed, a floating gate 26, a select gate 27 of the select transistor, an N-type well connection region 32 composed of an N-type impurity region, a source 33 and a drain 34 of a memory transistor, a drain 35 of a select transistor, a P-type impurity Minority carrier injection regions 31 and charge injection regions 36 made of regions are arranged, and the N-type well connection region 32 and the minority carrier injection region 31 are connected to a word line 38 made of a first metal film through a contact hole 37. The source 33 of the memory transistor is The first metal film 41 is connected to the first metal film 41 through the tact hole 37, and the first metal film 41 is connected to the common source line Vss43 made of the second metal film through the through hole 42. The drain 35 of the select transistor is The first metal film 39 is connected to a first metal film 39 through a contact hole 37, and the first metal film 39 is connected to a read bit line RBL 44 made of a second metal film through a through hole 42. The charge injection region 36 is a contact. The first metal film 38 is connected to the first metal film 38 through the hole 37, and the first metal film 38 is connected to the write bit line PBL 45 made of the second metal film through the through hole 42.

The cell area of the second nonvolatile memory cell of the present invention is about 2.5 times the layout pitch of the second metal wiring in the direction parallel to the word line and about twice the layout pitch of the well in the direction parallel to the bit line. It is. According to the layout rule of the normal 3.3V CMOS transistor, the layout area of the second metal wiring and the well is about 1 μm and 4 μm, so the cell area is 2.5 × 8 = 20 μm ² .

13 to 15 show cross-sectional structures for each manufacturing process of the second nonvolatile memory of the present invention. Each cross-sectional view corresponds to a portion indicated by a symbol A → B in the planar structure shown in FIG. 11. First, in the manufacturing process shown in FIG. 13, a desired region of the surface region of the P-type silicon substrate 51 having a resistivity of 10 Ωcm is opened by dry etching, and a chemical vapor deposition method (hereinafter referred to as a CVD method). ) To form a trench type element isolation region (STI) 52 having a depth of 300 nm and planarized by a CMP (Chemical Mechanical Polishing) method, followed by a thermal oxidation method. growing a surface oxide film 72 of 10 nm, the energy 1MeV phosphorus ions by an ion implantation method, injection of 1 × ¹⁰ 13 ^{cm -2} energy 500 keV, implantation dose 3 × ¹⁰ 12 ^{cm -2,} and the energy 150 keV, implantation dose 1 × 1 ¹² cm ^-2 implanted to form the N-type well 54, the energy 500keV boron ions, implantation amount 1 × ¹⁰ 13 ^{cm -2,} energy 150 keV, implantation dose 3 × ¹⁰ 12 ^{cm -2,} and energy 50 keV, implantation dose A state in which a P-type well 53 is formed by implanting 1 × 10 ¹² cm ⁻² is shown.

In the manufacturing process shown in FIG. 14, after the surface oxide film 72 is removed by wet etching, a gate oxide film 55 having a thickness of 7 nm is grown by a thermal oxidation method, and polysilicon having a thickness of 200 nm deposited by a CVD method. After implantation of phosphorus ions having an acceleration energy of 10 keV into the film by an implantation amount of 2 × 10 ¹⁵ cm ⁻² by ion implantation, a polysilicon gate 56 is formed by lithography and dry etching, masked by lithography, and ion implantation After that, an arsenic ion with an acceleration energy of 50 keV is implanted at an implantation amount of 1 × 10 ¹⁵ cm ⁻² to form an N-type well connection region 58, a memory transistor source 60 and drain 61, and a select transistor drain 62, and then a film thickness by lithography. 1 μm resist film 73 is patterned And N'ningu to form a minority carrier injection region 59 and the charge injection region 63, and injection volume ^1x10 15 ^{cm -2} implanted 2 boron difluoride (BF2) ions 74 of an acceleration energy 50keV by ion implantation.

  In the manufacturing process shown in FIG. 15, the resist 73 is removed by the ashing method, washed, and then the oxide film side spacer 66 having a film thickness of 100 nm formed by the CVD method and processed by the etch back method is formed. A polysilicon silicide film 57 and a cobalt silicide film 57 having a thickness of 50 nm are grown on the exposed substrate surface, a silicon oxide film is deposited by a CVD method, and a contact interlayer film 67 having a thickness of 800 nm is formed by a CMP method. Then, a contact hole having a hole diameter of 0.3 μm is opened by lithography and dry etching, deposited by CVD, embedded with a tungsten (W) contact 68 planarized by CMP, and deposited by sputtering. First metal wiring 69 made of aluminum (Al) having a thickness of 500 nm by dry etching Then, a silicon oxide film is deposited by a CVD method and a first interlayer film 70 having a thickness of 800 nm is formed by a CMP method, and a hole diameter of 0.3 μm is formed by lithography and dry etching, although not shown. A through-hole is opened, deposited by CVD, planarized with tungsten (W) through contact planarized by CMP, deposited by sputtering, and formed of aluminum (Al) having a thickness of 500 nm by lithography and dry etching. A state in which two metal wirings 71 are formed is shown.

    FIG. 16 shows a direct peripheral circuit block of the second nonvolatile memory module of the present invention. The read word line RWL and the read bit line RBL connected to the select transistor ST are respectively connected to a word driver and a sense amplifier that operate at the power supply voltage Vcc, and the write word line PWL and the write bit line PBL are Each is controlled by a word driver and a write driver operating at a high voltage Vpp. The nonvolatile memory module operates using 3.3V as the power supply voltage Vcc for the read operation and 6V as the high voltage Vpp for the write / erase operation.

<< Third Example of Ultra Low Power Consumption Nonvolatile Memory >>
FIG. 17 shows a circuit diagram of eight cells of the third nonvolatile memory included in the semiconductor device according to the present invention. FIG. 18 shows a planar structure corresponding to the circuit diagram of FIG. The figure shows an N-type well 84, a P-type well 85, an active region 81 for forming a coupling capacitor, an active region 82 for forming a memory transistor, and an active region 83 for forming a charge injection region. A floating gate 86, an N-type well connection region 90 made of an N-type impurity region, a source 87 and a drain 88 of a memory transistor, a minority carrier injection region 89 made of a P-type impurity region, and a charge injection region 91, The N-type well connection region 90 and the minority carrier injection region 89 are connected to a word line 96 made of a first metal film via a contact hole 92, and the source 87 of the memory transistor is connected to the first metal via a contact hole 92. The first metal film 95 is connected to the metal film 95 and the first metal film 95 is connected to the first through the through hole 97. The charge injection region 91 is connected to the first metal film 94 through the contact hole 92, and the first metal film 94 is connected to the second metal through the through hole 97. Connected to a write bit line PBL99 made of a film, the drain 88 of the memory transistor is connected to a first metal film 93 through a contact hole 92, and the first metal film 93 is connected to a second metal through a through hole 97. It is connected to a read bit line RBL100 made of a film.

The cell area of the third nonvolatile memory cell of the present invention is 2.5 times the layout pitch of the second metal wiring in the direction parallel to the word line, and 1.5 times the layout pitch of the well in the direction parallel to the bit line. It is about twice. In the normal 3.3V CMOS transistor layout rule, since the layout pitch of the second metal wiring and well is about 1 μm and 4 μm, the cell area is 2.5 × 6 = 15 μm ² .

19 to 21 show a cross-sectional structure for each manufacturing process of the third nonvolatile memory of the present invention. Each cross-sectional view corresponds to a portion indicated by a symbol C → D in the planar structure shown in FIG. First, in the manufacturing process shown in FIG. 19, openings are formed in a desired region of the surface region of the P-type silicon substrate 101 having a resistivity of 10 Ωcm by dry etching, a silicon oxide film is deposited by CVD, and flattened by CMP. after forming the STI102 depth 300nm which ized by thermal oxidation to grow a surface oxide film 121 having a thickness of 10 nm, the energy 1MeV phosphorus ions by an ion implantation method, the injection amount 1 × ¹⁰ 13 ^{cm -2,} energy 500 keV, An implantation amount of 3 × 10 ¹² cm ⁻² and an energy of 150 keV, an implantation amount of 1 × 10 ¹² cm ^{−2 is} implanted to form an N-type well 54, and boron ions are energized with an energy of 500 keV, an implantation amount of 1 × 10 ¹³ cm ⁻² , Energy 150 keV, injection amount 3 × 10 ¹² cm ⁻² , energy 50 keV, injection amount 1 A state in which a P-type well 53 is formed by implanting × 10 ¹² cm ⁻² is shown.

In the manufacturing process shown in FIG. 20, after the surface oxide film 121 is removed by wet etching, a gate oxide film 105 having a thickness of 7 nm is grown by a thermal oxidation method, and polysilicon having a thickness of 200 nm deposited by a CVD method. After implantation of phosphorus ions having an acceleration energy of 10 keV into the film by an implantation amount of 2 × 10 ¹⁵ cm ⁻² by ion implantation, a polysilicon gate 106 is formed by lithography and dry etching, masking by lithography is performed, and ion implantation is performed. Then, an arsenic ion having an acceleration energy of 50 keV is implanted by an implantation amount x10 ¹⁵ cm ⁻² to form the N-type well connection region 108, the source 110 and the drain 111 of the memory transistor, and then a resist film 122 having a thickness of 1 μm is formed by lithography. Pattern and ion implantation Forming a minority carrier injection region 109 and the charge injection region 112, the 2 boron difluoride (BF2) ions 123 of an acceleration energy 50keV implant dose ^1x10 15 to ^{cm -2} injected by.

  In the manufacturing process shown in FIG. 21, the resist 122 is removed by the ashing method and washed, and then the oxide film side spacer 113 having a film thickness of 100 nm deposited by the CVD method and processed by the etch back method is formed. A polysilicon gate 106 and a cobalt silicide film 107 having a thickness of 50 nm are grown on the exposed substrate surface, a silicon oxide film is deposited by a CVD method, and a contact interlayer film 114 having a thickness of 800 nm is formed by a CMP method. Then, a contact hole having a hole diameter of 0.3 μm is opened by lithography and dry etching, deposited by CVD, embedded with a tungsten (W) contact 115 planarized by CMP, and deposited by sputtering. A first made of aluminum (Al) having a thickness of 500 nm by dry etching. A metal wiring 116 is formed, a silicon oxide film is deposited by CVD, a first interlayer film 117 having a thickness of 800 nm is formed by CMP, and a through hole having a hole diameter of 0.3 μm is formed by lithography and dry etching. The tungsten (W) through contact 118 is deposited by the CVD method, planarized by the CMP method, deposited by the sputtering method, and deposited by the sputtering method and dry etching, and is made of aluminum (Al) having a thickness of 500 nm. A state in which two metal wirings 119 are formed is shown.

  In the third nonvolatile memory included in the semiconductor device according to the present invention, the number of word lines is 32 and the number of write and read bit lines is 32, and the memory capacity is 1024 bits.

<< Nonvolatile memory for RFID >>
FIG. 22 shows a direct peripheral circuit block of the volatile memory module according to the present invention mounted on an RFID chip. Read bit line RBL is connected to a sense amplifier operating at power supply voltage Vcc, write bit line PBL is controlled by a write driver operating at high voltage Vpp, and word line WL includes a switching circuit between power supply voltage Vcc and high voltage Vpp. It is controlled by a word driver. The nonvolatile memory module operates using 1.5 V as the power supply voltage Vcc for the read operation and 6 V as the high voltage Vpp for the write / erase operation.

  In this nonvolatile memory module, 128 memory cells are connected on one word line WL (n = 128), and only one cell is connected on the bit lines RBL and PBL. Even when a memory cell accidentally causes overerasing, a read failure cannot occur.

  FIG. 23 shows a circuit block of an RFID chip on which a volatile memory module according to the present invention is mounted. An antenna L arranged outside the chip is connected to the pads P1 and P2 to receive an RF signal transmitted from an external reader, and a power capacitor CT having a capacity of 120 pF and a voltage clamp are connected between the pads P1 and P2. A circuit (Voltage Clamp), a power supply modulator (Modulator), and a bridge rectifier are connected to generate an internal power supply voltage (Vcc) and a high voltage (Vpp) from the output of the bridge rectifier (Vcc Detector). ), A Vpp booster circuit (Vpp Generator) is connected. In addition, the bridge rectifier supplies an operation mode included in the received RF signal to a circuit (Mode Selector), a clock detection circuit (Clock Extractor), and a nonvolatile memory (EEPROM: Electrically Easable and Programmable Read Only Memory). A circuit for extracting write data (Data Modulator) is connected, and the operation mode is sent to the controller (Controller) to control the operation of the nonvolatile memory. Writing The internal power supply voltage Vcc and the high voltage Vpp are supplied to the nonvolatile memory, and writing and reading operations are performed. A power supply stabilization capacitor CF is connected to the output of the first bridge rectifier, and a control signal of a voltage regulator (Regulator) for detecting the output voltage is fed back to the voltage clamp circuit to stabilize the power supply voltage. Yes.

  The RFID chip operates at an RF frequency of 2.45 GHz, and the total power that can be generated inside the chip is about 10 to 50 μW. Of this total power, the power supply capability that can be generated by the Vpp booster circuit is about 6 V and 1 μA, but since the write current of the memory cell is 200 nA or less, there is no problem in operation.

<< First Example of High-Speed Reading / Ultra Low Power Consumption Nonvolatile Memory >>
FIG. 24 shows a circuit diagram of four cells of the first high-speed readable nonvolatile memory included in the semiconductor device according to the present invention. In the figure, a coupling capacitor C2 and a capacitor CJ in the charge injection region are connected to the floating gate of the memory transistor MT, the drain of the memory transistor MT is connected to the select transistor ST, and the drain of the select transistor ST is read. Connected to the bit line RBL, the gate of the select transistor ST is connected to the read word line RWL, the charge injection region is connected to the write bit line PBL, and the coupling capacitor C2 is connected to the write word line PWL. . In this nonvolatile memory, a gate oxide film 1 (Tox1) having a film thickness of 3 nm for an internal logic circuit transistor operating at a power supply voltage of 1.5V and a film thickness of 7 nm for an external interface circuit transistor operating at a power supply voltage of 3.3V. Gate oxide film 2 (Tox2). The select transistor ST includes the gate oxide film 1 (Tox1) having a thickness of 3 nm, and the memory transistor MT, the coupling capacitor C2, and the capacitor CJ in the charge injection region include the gate oxide film 2 (with a thickness of 7 nm). Tox2).

  FIG. 25 shows operating voltage conditions of the first high-speed readable nonvolatile memory cell included in the semiconductor device according to the present invention. First, in a write operation (Program), a positive voltage such as 6V is applied to the word line WL, and then a negative voltage such as −5V is applied to the write bit line PBL. Thus, similarly to the first example of the nonvolatile memory of the present invention, hot electrons generated by the BTBT phenomenon are injected into the floating gate. In this write operation, the write bit line current was about 100 nA, the write time was about 5 μs, therefore the write energy was 2.5 pJ, and the threshold voltage of the memory transistor after the write was about 2V.

  In the erase operation (Erase), a voltage such as 6 V is applied only to the write bit line PBL, and electrons are emitted by a tunnel current from the floating gate to the charge injection region, and the time required for erase is about 100 ms. The threshold voltage of the memory transistor after erasing was about -1.5V.

  In the read operation (Read), the read bit line RBL is precharged to 1.5 V, then 1.5 V is applied to the read word line RWL to turn on the select transistor, and erase / write of the memory transistor. This is done by determining the on / off state corresponding to the state. The sense amplifier circuit connected to the read bit line and the word driver circuit connected to the read word line are both composed of a high-speed operation that operates at a power supply voltage of 1.5 V, and a read time of about 20 ns can be obtained. It was.

  FIG. 26 shows a planar structure of the first high-speed readable nonvolatile memory cell included in the semiconductor device according to the present invention. In the figure, the planar structure of the third nonvolatile memory cell of the present invention shown in FIG. 12 is the same except that a pattern 131 for changing the gate oxide film thickness of the select transistor ST is added. Are the same.

27 to 31 show cross-sectional structures for each manufacturing process of the first high-speed readable nonvolatile memory of the present invention. Each cross-sectional view corresponds to a location indicated by the symbol E → F in the planar structure shown in FIG. First, in the manufacturing process shown in FIG. 27, a desired region of the surface region of the P-type silicon substrate 51 having a resistivity of 10 Ωcm is opened by dry etching, a silicon oxide film is deposited by CVD, and flattened by CMP. after forming the STI52 depth 300nm which ized by thermal oxidation to grow a surface oxide film 72 having a thickness of 10 nm, the energy 1MeV phosphorus ions by an ion implantation method, the injection amount 1 × ¹⁰ 13 ^{cm -2,} energy 500 keV, Implantation amount 3 × 10 ¹² cm ⁻² and energy 150 keV, implantation amount 1 × 10 ¹² cm ^{−2 is} implanted to form an N-type well 54, boron ions are energy 500 keV, implantation amount 1 × 10 ¹³ cm ⁻² , energy 150 keV, implantation dose 3 × ¹⁰ 12 ^{cm -2,} and energy 50 keV, implantation dose 1 × 1 ¹² cm ^-2 injected into the formation of the P-type well 53 state is shown.

  In the manufacturing process shown in FIG. 28, after removing the surface oxide film 72 by wet etching, a gate oxide film 55 having a thickness of 5 nm is grown by a thermal oxidation method, and a resist film having a thickness of 1 μm is patterned by a lithography method. The gate oxide film 55 only in the region where the select transistor is to be formed is removed by wet etching using 133 as a mask.

  In the manufacturing process shown in FIG. 29, after removing the resist film 133 by ashing, a gate insulating film 132 having a thickness of 3 nm is grown by thermal oxidation. In this thermal oxidation process, additional oxidation of the gate oxide film 55 proceeds, resulting in an oxide film thickness of 7 nm.

In the illustrated manufacturing steps in FIG. 30, the polysilicon film having a thickness of 200nm was deposited by CVD, after implantation dose ^2x10 15 ^{cm -2} implanted phosphorus ions of acceleration energy 10keV by ion implantation, lithography and dry etching processed polysilicon gate 56 is formed, N-type well connection region 58 is masked to injection volume ^1x10 15 ^{cm -2} implanted arsenic ions acceleration energy 50keV by ion implantation by a lithography method, the source of the memory transistor by 60, the drain 61, and the drain 62 of the select transistor are formed, and then a resist film 73 having a thickness of 1 μm is patterned by lithography, and boron difluoride (BF2) ions 74 having an acceleration energy of 50 keV are implanted by ion implantation. The amount 1x10 ¹ cm ^-2 implanted to form the minority carrier injection region 59, and the charge injection region 63.

  In the manufacturing process shown in FIG. 31, the resist 73 is removed by the ashing method, washed, then deposited by the CVD method and processed by the etch back method to form an oxide film side spacer 66 having a thickness of 100 nm. A polysilicon silicide film 57 and a cobalt silicide film 57 having a thickness of 50 nm are grown on the exposed substrate surface, a silicon oxide film is deposited by a CVD method, and a contact interlayer film 67 having a thickness of 800 nm is formed by a CMP method. Then, a contact hole having a hole diameter of 0.3 μm is opened by lithography and dry etching, deposited by CVD, embedded with a tungsten (W) contact 68 planarized by CMP, and deposited by sputtering. First metal wiring 69 made of aluminum (Al) having a thickness of 500 nm by dry etching Then, a silicon oxide film is deposited by a CVD method and a first interlayer film 70 having a thickness of 800 nm is formed by a CMP method, and a hole diameter of 0.3 μm is formed by lithography and dry etching, although not shown. A through-hole is opened, deposited by CVD, planarized with tungsten (W) through contact planarized by CMP, deposited by sputtering, and formed of aluminum (Al) having a thickness of 500 nm by lithography and dry etching. A state in which two metal wirings 71 are formed is shown. Thereafter, although not shown, the chip is completed through a passivation process.

<< Second example of non-volatile memory with high-speed reading and ultra-low power consumption >>
FIG. 32 shows a cross-sectional structure of a second high-speed non-volatile memory cell included in the semiconductor device according to the present invention. In the figure, N-type wells 264 and 265 having an average phosphorus concentration of 2 × 10 ¹⁷ cm ⁻³ electrically isolated by a device isolation oxide film 262 having a depth of 300 nm on the surface region of a P-type silicon substrate 261 having a resistivity of 10 Ωcm. A P-type well 263 having an average boron concentration of 3 × 10 ¹⁷ cm ⁻³ is formed, and a film thickness of 200 nm is formed on one surface region of the N-type well 264 via a gate insulating film 266 made of a silicon oxide film having a thickness of 7 nm. A floating gate 267 made of a polysilicon film having an average phosphorus concentration of 2 × 10 ²⁰ cm ⁻³ is disposed, and an N-type impurity region 269 having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ is adjacent to one of both ends of the floating gate 267. distribution is P-type impurity region 268 of the average boron concentration ^1x10 20 ^{cm -3} adjacent to the other The N-type impurity region 269 and the P-type impurity region 268 are connected to the write word line PWL, and the gate insulating film 266 and the floating gate 267 extend in the surface region of the P-type well 263. The gate insulating film 266 is disposed on the surface region of the N-type well 265 and the source 270 made of an N-type impurity region having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ and an N-channel memory transistor MNT made of a drain 271. The floating gate 267 is extended, and includes a source 273 made of a P-type impurity region having an average boron concentration of 1 × 10 ²⁰ cm ⁻³ , and a P-channel memory transistor MPT made of a drain 272, and the N-channel memory transistor MNT drain 271 and P-channel The drain 272 of the channel memory transistor MPT is connected to form an inverter. The output of the inverter is connected to the source of the select transistor ST, the gate of the select transistor ST is connected to the read word line RWL, and the drain of the select transistor ST is connected to the read bit line RBL. The source 270 of the N-channel memory transistor MNT is connected to the source line Vss, the source 273 of the P-channel memory transistor MPT is connected to the write bit line PBL, and the gate insulation is formed on the surface region of the N-type well 265. The film 266 and the floating gate 267 are extended to be disposed, an N-type well connection region 274 having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ is disposed, and the N-type well connection region 274 is connected to the well power supply line VN. The second high-speed read / ultra-low power consumption nonvolatile memory of the present invention is configured.

  FIG. 33 shows an equivalent circuit of the second high-speed read / ultra-low power consumption nonvolatile memory of the present invention. In the figure, an N-channel memory transistor MNT and a P-channel memory transistor MPT are connected in series to form an inverter. The gates of both memory transistors are operated as floating gates, and the floating gate has a coupling capacitor C2 and charge injection. A region capacitor CJ is connected. The drain of the N-channel memory transistor MT is connected to the select transistor ST, the drain of the select transistor ST is connected to the read bit line RBL, the gate of the select transistor ST is connected to the read word line RWL, and the P-channel memory The drain of the transistor MPT is connected to the write bit line PBL and functions as a charge injection region. The N-type well in which the P-channel memory transistor MPT is disposed is connected to the well power supply line VN via the N-type well connection region. The coupling capacitor C2 is connected to the write word line PWL. The coupling capacitor C2 is designed to be about five times or more the sum of the input gate capacitance of the inverter and the capacitor CJ of the charge injection region, and the electrostatic capacitor from the word line WL to the floating gate. The ring ratio is 0.83 or more.

  FIG. 34 shows operating voltage conditions of the second high-speed readable nonvolatile memory cell included in the semiconductor device according to the present invention. In the write operation (Program), after applying a positive voltage such as 6V to the word line WL, a negative voltage such as −5V is applied to the write bit line PBL. Thus, similarly to the first example of the nonvolatile memory of the present invention, hot electrons generated by the BTBT phenomenon are injected into the floating gate. In this write operation, the write bit line current is about 200 nA, the write time is about 5 μs, therefore the write energy is 5 pJ, the N-channel memory transistor MNT after the write is turned off, and the P-channel memory transistor MPT is turned on. It was.

  In the erase operation (Erase), a voltage such as 6 V is applied only to the well feed line VN, and electrons are emitted by a tunnel current from the floating gate to the N-type well, and the time required for erase is about 200 ms. After the erase operation, the N-channel memory transistor MNT is turned on, and the P-channel memory transistor MPT is turned off.

  In the read operation (Read), the read bit line RBL is precharged to 3.3V, and then 3.3V is applied to the read word line RWL to turn on the select transistor and turn on / off the inverter. Determine. In the standby state (Standby), all terminals are set to the ground potential of 0 V. However, the read operation is performed after 3.3 V is applied to the write bit line PBL, the write word line PWL, and the well power supply line VN immediately before the read operation. Do.

<< Restoring nonvolatile memory for system LSI >>
FIG. 35 schematically shows a chip plan view of a system LSI which is an example of a semiconductor device according to the present invention. The system LSI shown in the figure is not particularly limited, but a large number of external connection electrodes 300 such as bonding pads are arranged on the periphery of the semiconductor substrate, and an external input / output circuit 301 and an analog input / output circuit 302 are provided inside thereof. ing. The external input / output circuit 301 and the analog input / output circuit 302 use an external power supply having a relatively high level such as 3.3V as an operation power supply. The level shift circuit 303 steps down the external power supply to an internal power supply voltage such as 1.8V. Inside the level shift circuit 303 are a static random access memory (SRAM) 304, a central processing unit (CPU) 305, a cache memory (CACH) 306, a logic circuit (LOG) 307, a phase locked loop circuit ( PLL) 308, an analog / digital conversion circuit (ADC) 309, a digital / analog conversion circuit (DAC) 310, and a system controller (SYSC) 311. Reference numerals 312, 313, and 314 denote electrically erasable and erasable nonvolatile memories (EPROMs) each including the nonvolatile memory cell described with reference to FIG.

  The SRAM 304, CPU 305, LOG 307, CACH 306, and SYSC 311 are operated using an internal power supply voltage such as 1.8 V supplied from the level shift circuit 303 as an operation power supply. However, the SRAM 304 boosts the internal power supply voltage to form a word line select level, which is used as an operation power supply such as a word driver. Non-volatile memories (EPROMs) 312, 313, and 314 operate using an internal power supply voltage in a data read operation, but a high voltage is required for an erase / write operation. The high voltage is formed by an internal booster circuit. Alternatively, it may be supplied from the outside via a predetermined external connection electrode in a predetermined operation mode such as the EPROM writer mode of the system LSI.

  The nonvolatile memory (EPROM) 312 is used for storing relief information (control information for replacing defective memory cells with redundant memory cells) in the SRAM 304, and the nonvolatile memory (EPROM) 313 is trimming data of the oscillation frequency of the analog circuit. Is used in place of the fuse, and is mounted in place of the fuse relief circuit. The nonvolatile memory (EPROM) 314 has a memory capacity of 1 kbit and is used for storing chip ID information, chip operation mode information, and desired data.

  The system LSI illustrated in FIG. 35 is not particularly limited, but is a complementary MIS transistor (insulated gate field effect transistor) formed on one semiconductor substrate such as single crystal silicon by a single layer polysilicon gate process. The gate oxide film thickness of the MIS transistor is classified into two types.

  The external input / output circuit 301, the analog input / output circuit 302, the SRAM 304, the ADC 309, the DAC 310, and the nonvolatile memories 312, 313, and 314 are not particularly limited. However, when the 0.2 μm process technology is used, the gate length is 0.4 μm. It has a MIS transistor with a gate oxide film thickness of 8 nm. In order to improve the information retention performance, it is desirable to set a relatively thick film thickness for the tunnel oxide film composed of the gate oxide film. In addition, a certain level of breakdown voltage is secured against the operating voltage of the MIS transistor. Because it is necessary to do. Therefore, the gate insulating film of the MIS transistor that constitutes the nonvolatile memory transistor of the nonvolatile memories 312, 313, and 314, the gate insulating film of the MIS transistor included in the external interface circuit 301, and the like are within an allowable error range due to process variations. Have the same film thickness. The allowable range due to the process variation of the gate insulating film thickness is not particularly limited, but in the process with the minimum processing dimension of 0.25 μm to 0.2 μm, it is about ± 0.5 nm with respect to the target film thickness of 8.0 nm. In a process having a minimum processing dimension of 0.18 μm to 0.15 μm, the thickness is about ± 0.3 nm with respect to a target film thickness of 7.0 nm.

  On the other hand, the circuit using the relatively low internal voltage that has been stepped down as the operation power supply, that is, the logic circuit 307, the cache memory 306, and the CPU 305 is configured by a MIS transistor having a gate length of 0.2 μm and a gate oxide film thickness of 4 nm. The Although the level shift circuit 303 is not particularly limited, the level shift circuit 303 includes MIS transistors having both gate oxide film thicknesses.

  The gate electrodes of the MIS transistors having different gate oxide thicknesses are composed of polysilicon layers having the same thickness. Here, the same film thickness of the polysilicon layer means an equal film thickness within an allowable range due to process variation, and the allowable range due to process variation of the gate film thickness is not particularly limited, but a target film of 30 nm to 200 nm. The thickness is about ± 10%. The gate oxide films described above can be formed using the same photomask with the same thickness, and the polysilicon gates described above can be generated using the same photomask with the same thickness. In this way, priority is given to not complicating the manufacturing process of the system LSI by sharing the gate oxide film thickness in the non-volatile memory element of the single-layer gate structure with the gate oxide film thickness of the MIS transistors of other circuits. Thus, the nonvolatile memory element of the flash memory can have a certain long information holding performance.

    The nonvolatile memory included in the semiconductor device according to the present invention is composed of a nonvolatile memory transistor using a single polysilicon layer, so that the device structure can be simplified, and a normal logic circuit process or general purpose It is possible to realize a semiconductor device equipped with a nonvolatile memory that operates with low power consumption without adding a completely new process to the DRAM process. For example, storage of color gradation trimming data performed after mounting a liquid crystal display driver (LCD: Liquid Crystal Driver) microcomputer on a liquid crystal panel substrate, and the interior of a low-cost microcomputer (called a one-dollar microcomputer) mounted on a home appliance Trimming data for transmitter frequency, trimming data for internal resistance and circuit constants of analog circuit-equipped microcomputers, SRAM relief information for high-performance microcomputers equipped with large-capacity SRAMs, contactless IC cards, It is optimal for storing ID information in inexpensive RFID, etc., and has a remarkable effect on strengthening its market competitiveness when mounted on a semiconductor device that requires a small capacity, low power consumption, and inexpensive nonvolatile memory.

It is explanatory drawing which shows roughly the cross-sectional structure of the memory cell explaining the best form for implementing the non-volatile memory which the semiconductor device which concerns on this invention has. FIG. 2 is an equivalent circuit diagram of the nonvolatile memory cell of FIG. 1. FIG. 2 is an explanatory diagram showing a planar structure of the nonvolatile memory cell of FIG. 1. FIG. 2 is an explanatory diagram illustrating voltage states at the time of writing, erasing, reading, and waiting for the nonvolatile memory cell of FIG. 1. It is explanatory drawing which shows roughly an example of the cross-sectional structure of the 1st non-volatile memory cell which the semiconductor device which concerns on this invention has. FIG. 6 is an explanatory diagram illustrating voltage states during writing, erasing, reading, and standby in the nonvolatile memory cell of FIG. 5. FIG. 6 is an explanatory diagram showing a planar structure of the nonvolatile memory cell of FIG. 5. It is explanatory drawing which shows roughly an example of the cross-sectional structure of the 2nd non-volatile memory cell which the semiconductor device which concerns on this invention has. FIG. 9 is an equivalent circuit diagram of the nonvolatile memory cell of FIG. 8. FIG. 9 is an explanatory diagram illustrating voltage states in writing, erasing, reading, and standby in the nonvolatile memory cell of FIG. 8; FIG. 9 is a circuit diagram illustrating a detailed example of a nonvolatile memory employing the nonvolatile memory cell of FIG. 8. It is explanatory drawing which shows the planar structure of the non-volatile memory cell of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-sectional structure in the 1st manufacturing process in the AB position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-sectional structure in the 2nd manufacturing process in the AB position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-section structure in the 3rd manufacturing process in the AB position of FIG. FIG. 12 is a circuit diagram showing a detailed example including a direct peripheral circuit of the nonvolatile memory of FIG. 11. It is a circuit diagram which shows an example of the 3rd non-volatile memory which the semiconductor device concerning this invention has. FIG. 18 is an explanatory diagram showing a planar structure of the nonvolatile memory cell of FIG. 17. It is a longitudinal cross-sectional view which shows the longitudinal cross-section structure in the 1st manufacturing process in the CD position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-section structure in the 2nd manufacturing process in the CD position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-sectional structure in the 3rd manufacturing process in the CD position of FIG. It is a circuit diagram which shows an example of the direct peripheral circuit block of the volatile memory module for RFID chips which the semiconductor device which concerns on this invention has. It is a block diagram which shows the circuit structure of the RFID chip | tip which mounts the non-volatile memory of FIG. 1 is a circuit diagram showing an example of a first high-speed read nonvolatile memory included in a semiconductor device according to the present invention. FIG. 25 is an explanatory diagram illustrating voltage states during writing, erasing, reading, and standby in the nonvolatile memory cell of FIG. 24; FIG. 25 is an explanatory diagram showing a planar structure of the nonvolatile memory cell of FIG. 24. It is a longitudinal cross-sectional view which shows the longitudinal cross-sectional structure in the 1st manufacturing process in the CD position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-sectional structure in the 2nd manufacturing process in the CD position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-sectional structure in the 31st manufacturing process in the CD position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-section structure in the 4th manufacturing process in the CD position of FIG. It is a longitudinal cross-sectional view which shows the longitudinal cross-section structure in the 5th manufacturing process in the CD position of FIG. It is sectional drawing which shows an example of the 2nd high-speed reading non-volatile memory which the semiconductor device which concerns on this invention has. FIG. 33 is an equivalent circuit diagram of the nonvolatile memory cell of FIG. 32. FIG. 33 is an explanatory diagram illustrating voltage states at the time of writing, erasing, reading, and waiting for the nonvolatile memory cell of FIG. 32; It is a block diagram which shows the circuit structure of the system LSI chip which mounts the non-volatile memory which concerns on this invention. It is a top view for explaining the 1st prior art concerning the present invention. It is sectional drawing for demonstrating the 2nd prior art which concerns on this invention.

Explanation of symbols

1, 51, 101, 261-P type silicon substrate 2, 262-element isolation oxide film 3, 24, 53, 85, 242, 252, 263-P type well 4, 25, 54, 84, 205, 264-N Type wells 5, 55, 105, 132, 241, 266-gate insulating films 6, 26, 86, 184, 215, 267-floating gates 7, 190, 191, 207, 212, 269-N-type impurity regions 8, 11 208, 209, 213, 214, 268-P-type impurity regions 9, 33, 60, 87, 110, 245, 270, 273-sources 10, 34, 35, 61, 62, 88, 111, 244, 271, 272-drains 12, 37, 92-contact holes 13, 38-word lines WL
16, 38, 39, 41, 93, 94, 95, 96-first metal film 17, 42, 97-through hole 18, 45, 99-write bit line PBL
19, 44, 100-read bit line RBL
21, 22, 23, 81, 82, 83, 181, 182- active regions 27, 183, 243-select gates 31, 59, 89, 109-minority carrier injection regions 32, 58, 90, 108, 274-N type Well connection regions 36, 63, 91, 112-charge injection regions 43, 98-common source line Vss
52, 102-STI
56, 106-polysilicon gate 57, 107-cobalt silicide film 66, 113-oxide side spacer 67, 114-contact interlayer 68, 115-tungsten contact 69, 116-first metal wiring 70, 117-first interlayer Films 71, 119-second metal wiring 72, 121-surface oxide films 73, 122, 133-resist film 74, 123-2 boron fluoride (BF2) ions 118-tungsten through contact 185-pattern 186-in-pattern region 188 Channel region 189 Control gate 251 Deep N-type well 300 External connection electrode 301 External input / output circuit 302 Analog input / output circuit 303 Level shift circuit 304 Static random access memory SRAM
305-Central processing unit CPU
306-cache memory CACH
307-Logic circuit LOG
308-Phase Locked Loop Circuit PLL
309-Analog-digital conversion circuit ADC
310-digital-analog converter circuit DAC
311-System Controller SYSC
313313, 314-nonvolatile memory EPROM

Claims (19)

  In an electrically writable nonvolatile memory element having a source and drain of a second conductivity type, a floating gate, a charge injection region, and a control gate in a first conductivity type semiconductor substrate, the charge injection region includes: A first second-conductivity-type semiconductor region formed via a gate insulating film under the floating gate extension portion, and the first-second-conductivity-type semiconductor region in the lower portion of the floating gate end A semiconductor device comprising: a first conductivity type semiconductor region formed adjacent to the first conductivity type semiconductor region, wherein the first conductivity type semiconductor region is connected to a programming bit line.   The control gate comprises a second second conductivity type semiconductor region formed in the first conductivity type semiconductor substrate via a gate insulating film under an extending portion of the floating gate, and the charge injection 2. The semiconductor device according to claim 1, wherein the semiconductor device is electrically isolated from the first second conductivity type semiconductor region constituting the region.   A first voltage that reversely biases a semiconductor junction formed by the first conductivity type semiconductor region and the first second conductivity type semiconductor region is applied to the program bit line, The second conductivity type semiconductor region is set to a floating potential, a second voltage having a polarity opposite to that of the first voltage is applied to the control gate, and electric charges are injected into the floating gate. 3. The semiconductor device according to claim 1, wherein writing is performed.   3. The floating gate and the gate insulating film, respectively, use a gate of a complementary MIS transistor constituting a logic circuit and a gate insulating film thereof. Item 4. The semiconductor device according to Item 3.   An electrically writable storage element region having a first second conductivity type source, a first second conductivity type drain, a floating gate, a charge injection region, and a control gate in a first conductivity type semiconductor substrate A select transistor having a second second conductivity type source connected to the first second conductivity type drain, a second second conductivity type drain connected to the read bit line, and a select gate. In the non-volatile memory element, the charge injection region includes a first second-conductivity-type semiconductor region formed via a gate insulating film under an extending portion of the floating gate, and the first second A conductive type semiconductor region is provided with a first conductive type semiconductor region formed adjacent to a lower end of the floating gate, and the first conductive type semiconductor region is a program bit. Wherein a connected to.   A first voltage that reversely biases a semiconductor junction formed by the first conductivity type semiconductor region and the first second conductivity type semiconductor region is applied to the program bit line, The second conductivity type semiconductor region is set to a floating potential, a second voltage having a polarity opposite to the first voltage is applied to the control gate, and electric charges are injected into the floating gate to electrically 6. The semiconductor device according to claim 5, wherein writing is performed, and reading is performed by applying a power supply voltage to the read bit line and the select gate.   In a semiconductor integrated circuit device including an external interface circuit and a logic circuit, the external interface circuit MIS transistor having a thick gate insulating film and the logic circuit MIS transistor having a thin gate insulating film, the first second conductivity type A source, a first second conductivity type drain, a floating gate, a control gate, a memory transistor using the thick gate insulating film as a gate insulating film, and the first under a floating gate extension A first second-conductivity-type semiconductor region formed via the gate insulating film, and a first-conductivity formed in the first-second-conductivity-type semiconductor region adjacent to the lower portion of the floating gate end. A charge injection region comprising a semiconductor region of a type, and a second second connected to the first second conductivity type drain A non-volatile memory element group having a conductive source, a second second conductivity type drain connected to a read bit line, a select gate, and a select transistor using the thick gate insulating film as a gate insulating film A semiconductor device comprising an electrically rewritable nonvolatile memory circuit.   In a semiconductor integrated circuit device including an external interface circuit and a logic circuit, the external interface circuit MIS transistor having a thick gate insulating film and the logic circuit MIS transistor having a thin gate insulating film, the first second conductivity type A source, a first second conductivity type drain, a floating gate, a control gate, a memory transistor using the thick film gate insulating film as a first gate insulating film, and an extension portion of the floating gate A first second-conductivity-type semiconductor region formed through the first gate insulating film; and a first-second-conductivity-type semiconductor region formed adjacent to the lower portion of the floating gate end. A charge injection region comprising a first conductivity type semiconductor region and a second connection connected to the first second conductivity type drain; Nonvolatile memory having a second conductivity type source, a second second conductivity type drain connected to a read bit line, a select gate, and a select transistor using the thin film gate insulating film as a second gate insulating film A semiconductor device comprising an electrically rewritable nonvolatile memory circuit including an element group.   The first conductivity type semiconductor region is connected to a program bit line, and the program bit line includes a semiconductor constituted by the first conductivity type semiconductor region and the first second conductivity type semiconductor region. A first voltage that reversely biases the junction is applied, a second voltage having a polarity opposite to that of the first voltage is applied to the control gate, and electric charges are injected into the floating gate to thereby form the nonvolatile memory. 9. The semiconductor device according to claim 7, wherein electrical writing is performed to the volatile memory circuit.   A third voltage for applying a forward bias to a semiconductor junction formed by the first conductivity type semiconductor region and the first second conductivity type semiconductor region is applied to the program bit line, The semiconductor device according to claim 9, wherein the non-volatile memory circuit is electrically erased by discharging the electric charge.   The semiconductor integrated circuit device includes a circuit to be repaired and a repair circuit that replaces the circuit to be repaired, and the nonvolatile memory circuit is a memory circuit for repair information that specifies a circuit to be repaired to be replaced by the repair circuit. The semiconductor device according to claim 9, wherein the semiconductor device is provided.   12. The semiconductor device according to claim 11, further comprising a fuse program circuit for storing relief information according to a blown state of a fuse element as another relief information storage circuit for the circuit to be repaired. .   13. The semiconductor device according to claim 11, wherein the circuit to be relieved is a DRAM memory cell array.   13. The semiconductor device according to claim 11, wherein the circuit to be relieved is a memory cell array of a DRAM with a built-in microcomputer.   13. The semiconductor device according to claim 11, wherein the circuit to be relieved is a memory cell array of a microcomputer built-in SRAM.   The semiconductor integrated circuit device includes an analog circuit and a constant trimming circuit for adjusting the circuit constant, and the nonvolatile memory circuit is an information storage circuit for specifying the circuit constant of the constant trimming circuit. The semiconductor device according to claim 9.   The semiconductor integrated circuit device includes an oscillation circuit and a frequency trimming circuit for adjusting the oscillation frequency, and the nonvolatile memory circuit is an information storage circuit for specifying the oscillation frequency of the frequency trimming circuit. The semiconductor device according to claim 9.   The semiconductor integrated circuit device includes a reference voltage generation circuit and a voltage trimming circuit that adjusts the generated reference voltage, and the nonvolatile memory circuit stores information for specifying the reference voltage of the voltage trimming circuit. The semiconductor device according to claim 9, wherein the semiconductor device is a memory circuit.   10. The semiconductor integrated circuit device includes a security circuit for specifying a chip, and the nonvolatile memory circuit is an information storage circuit for specifying a chip of the security circuit. Semiconductor device.

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