JP2007165505A - Semiconductor device, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable MRAM by solving a trade-off problem between securing the functions of TMR element and the conditions for forming an interlayer insulation film and a Cu interconnection. <P>SOLUTION: The interlayer insulation films 4-6 each consist of an SiOC film having a relative permittivity of 3.0 or below formed by plasma CVD method, and are formed at a temperature of 300°C or higher (not exceeding 450°C or around). The interlayer insulation films 13-15 and 17 each consist of an insulation film having a relative permittivity larger than 3.0, and are formed at a temperature of 300°C or lower (not lower than 200°C or around). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a nonvolatile memory array using a magnetic tunnel resistance element for each memory cell and a manufacturing method thereof.

  A structure in which an insulator is sandwiched between two ferromagnets is called a magnetic tunnel junction (MTJ), and an element having at least one magnetic tunnel junction is a magnetic tunnel resistance element or a magnetic tunnel. It is called a junction element.

  When a voltage is applied between two ferromagnets, when a current tunneling through the insulator is measured, a phenomenon is observed in which the current value varies depending on the direction of the magnetization vectors (spin) of the two ferromagnets. This phenomenon occurs because the magnetic tunnel resistance in the insulator changes, and is referred to as a tunnel magnetic resistance (TMR) effect.

  Of the two ferromagnets, the direction of one magnetization vector is fixed, and the direction of the other magnetization vector can be arbitrarily changed to the same or opposite direction. A device that stores information by correlating the magnetization direction of the body with bit 0 or bit 1 is an MRAM (Magnetic Random Access Memory).

  That is, of the two combinations of the magnetization directions of the two ferromagnets, the combination with the higher resistance is set to bit 1, the combination with the lower resistance is set to bit 0, or vice versa. Memory becomes possible.

  Such MRAM using magnetism is expected as a next-generation nonvolatile memory following the flash memory.

  The biggest feature of MRAM is that high-speed write and read operations are possible. As an application field that makes use of this feature, it is promising to be mounted in the form of SOC (System on Chip) in microcomputers for automobiles. Yes.

  Here, in the SOC manufactured after 130 nm node manufactured in recent years, Cu / Low-k wiring structure is applied in order to prevent performance deterioration due to wiring delay determined by the product (RC) of wiring resistance R and wiring capacitance C. Yes.

  The Cu / Low-k wiring structure reduces the wiring resistance R by using copper having a lower resistivity than aluminum as a wiring material, and has a low dielectric constant as an interlayer insulating film (dielectric constant of 3.0 or less). This refers to a wiring structure in which the wiring capacitance C is reduced by using “silicon oxide film containing carbon: SiOC”.

  By using this wiring structure, the wiring delay is suppressed and the device can be operated at high speed.

  Therefore, in order to manufacture an SOC on which MRAM is mounted, a technique for coexisting a Cu (copper) / Low-k wiring structure and MRAM is required.

  FIG. 29 shows a cross-sectional view of the MRAM portion of the SOC to which the Cu / Low-k wiring structure manufactured by using the conventional technique is applied.

  FIG. 29 shows only the magnetic tunnel resistance element (TMR element) and its vicinity in the MRAM.

  As shown in FIG. 29, an insulating film 104 is disposed so as to cover the interlayer insulating film 101, and a strap wiring 106 is selectively disposed on the insulating film 104. A flat TMR element 107 is selectively disposed on the strap wiring 106. The TMR element 107 has a multilayer structure in which an insulating film is sandwiched between two ferromagnetic films.

  As a specific configuration of the TMR element 107, for example, a cross-sectional photograph of the MTJ is shown in FIG. 1 of Non-Patent Document 1. From the first page to the second page, the tunnel insulating film has an alumina-based insulation such as AlOX. It is disclosed that a material is used and CoFe is used for the ferromagnetic film.

  The strap wiring 106 and the TMR element 107 are covered with an interlayer insulating film 105, a bit line 108 is disposed on the interlayer insulating film 105, and the bit line 108 is covered with an interlayer insulating film 109. The TMR element 107 is configured to be electrically connected to the bit line 108 through a contact portion 105 a that penetrates the interlayer insulating film 105 and reaches the TMR element 107.

  A digit line 102 is disposed in the surface of the interlayer insulating film 101 at a position corresponding to the lower side of the TMR element 107, and a lead wire 103 is disposed in the vicinity of the digit line 102.

  The lead wire 103 is configured to be electrically connected to the strap wiring 106 via a contact portion 104 a that penetrates the insulating film 104 and reaches the lead wire 103.

  The bit line 108 and the digit line 102 which are write wirings are arranged so as to be orthogonal to each other in a plan view without contact, and the TMR element 107 is sandwiched between the bit line 108 and the digit line 102. It is arranged like this.

  The lead wire 103 is a read wire, and the tunnel current flowing through the TMR element 107 is given to the lead wire 103 via the strap wire 106 that is a lead wire.

FIG. 30 shows a cross-sectional configuration along the line AA shown in FIG.
As shown in FIG. 30, a plurality of bit lines 108 are arranged in parallel, and a plurality of digit lines 102 are arranged so as to be orthogonal to the plurality of bit lines 108 in a plan view to form a matrix. Yes.

  Here, the digit line 102 and the lead wire 103 disposed below the TMR element 107 and the bit line 108 disposed above the TMR element 107 are made of Cu, and an interlayer covering these wirings. For the insulating films 105 and 107, a low dielectric constant film (Low-k film) having a relative dielectric constant of 3.0 or less such as a SiOC film is used as a material.

  Non-Patent Document 2 discloses a configuration in which a SiOC film and a SiC film are used as an interlayer insulating film of a low-k film that covers a Cu wiring.

  As a problem when manufacturing the MRAM, there is a problem of heat resistance of the TMR element. That is, when a ferromagnetic film used for a TMR element is subjected to a heat treatment at a temperature higher than 300 to 350 ° C., the regular arrangement of spins as a source of magnetism is disturbed, and the function as a TMR element cannot be performed. .

  Specifically, among the two ferromagnetic films, the magnetic characteristic of the ferromagnetic film whose magnetization vector should be fixed, that is, the pinned layer is deteriorated or disappears.

  Therefore, in the manufacturing process after forming the TMR element, it is necessary to set the heat treatment process to 300 ° C. or lower.

  However, for the following two reasons, it is difficult to perform the heat treatment step after forming the TMR element at 300 ° C. or less.

  First, as a first reason, as shown in FIG. 29, a step of forming a low dielectric constant interlayer insulating film is necessary even after the formation of the TMR element.

  That is, in the formation of a low dielectric constant interlayer insulating film, there are a coating method and a plasma CVD method as typical forming methods.

  In the former, an insulating film material dissolved in a solvent is applied onto a semiconductor substrate and then baked. Here, the key point for obtaining an insulating film having a stable film quality is a baking process for forming an insulating film having a network structure by cross-linking the materials in the solvent. In order to obtain it, heat treatment at 350 ° C. or higher, preferably 400 ° C. or higher is inevitable.

  On the other hand, the latter plasma CVD method assists the decomposition and synthesis reaction of the material gas molecules by the plasma, and thus has a possibility of lowering the temperature. However, in order to ensure a relative dielectric constant of 3.0 or less and strength to withstand the manufacturing process, it is extremely difficult to set the film formation temperature to 300 ° C. or less.

  As described above, it can be said that it is very difficult to set the heat treatment step to 300 ° C. or lower in the formation of the low dielectric constant interlayer insulating film.

  Next, as a second reason, after the formation of the Cu film for forming the Cu wiring, a step of applying a heat treatment at 300 ° C. or higher is necessary.

  That is, as a problem in reliability of the Cu wiring, there is a problem of a void (SIV: Stress-Induced Voiding) in a via hole portion generated due to stress in the film.

  Here, SIV is a phenomenon in which voids are generated in wirings or connection holes (via holes) connecting the wirings due to stress in the film accompanying a temperature change after the manufacturing process is completed, resulting in an increase in wiring resistance or disconnection. However, for this failure mode, a technique of increasing the SIV resistance by applying a predetermined heat treatment after forming a Cu film for forming a wiring is employed. In this heat treatment, heat treatment at 300 ° C. or higher is effective.

S. Ueno et al., “A 0.13μm MRAM with 0.26x0.44μm2 MTJ optimized on Universal MR-RA relation for 1.2V high-speed operation beyond 143MHz”, “Technology Digest of International Electron Devices Meeting 2004, pp.579- 582 ” M. Matsuura et al., “Robust Low-k SiOC Integration in Cu Damascene Interconnect for 90nm Node SoC Technology”, “Proceedings of Advanced Metallization Conference 2002, pp.493-499”

  As described above, a process for forming an interlayer insulating film having a low dielectric constant is necessary even after the formation of the TMR element. In order to obtain a predetermined relative dielectric constant and film quality, the heat treatment process should be 300 ° C. or lower. difficult. In order to obtain a highly reliable Cu wiring, a process of applying a heat treatment of 300 ° C. or higher after the Cu film is formed is effective. However, a TMR element can be obtained by applying a heat treatment at a temperature higher than 300 to 350 ° C. Since the function as an element cannot be achieved, there is a trade-off relationship that is difficult to solve between ensuring the function of the TMR element and the conditions for forming the interlayer insulating film and the Cu wiring.

  The present invention has been made to solve the above-described problems, and solves the trade-off relationship between ensuring the function of the TMR element and the formation conditions of the interlayer insulating film and the Cu wiring, thereby improving reliability. An object is to provide a high MRAM.

  According to a first aspect of the present invention, there is provided a semiconductor device comprising: a plurality of wiring layers arranged in multiple layers on a semiconductor substrate; a plurality of interlayer insulating films respectively arranged between the plurality of wiring layers; A magnetic tunnel resistance element including a magnetic tunnel junction disposed in a first interlayer insulating film forming one layer of the interlayer insulating films, and disposed below the first interlayer insulating film. In addition, at least one second interlayer insulating film is formed of an insulating film having a relative dielectric constant of 3.0 or less, and the first interlayer insulating film and a third layer disposed on the first interlayer insulating film. The interlayer insulating film is made of an insulating film having a relative dielectric constant greater than 3.0.

  According to a sixth aspect of the present invention, there is provided a semiconductor device comprising: a plurality of wiring layers disposed in multiple layers on a semiconductor substrate; a plurality of interlayer insulating films respectively disposed between the plurality of wiring layers; A method of manufacturing a semiconductor device, comprising: a magnetic tunnel resistance element including a magnetic tunnel junction, disposed in a first interlayer insulating film forming one layer of the interlayer insulating films, A step (a) of forming a second interlayer insulating film to be a lower layer film of the first interlayer insulating film, and forming a first copper wiring layer in the surface of the second interlayer insulating film; A step (b), a step (c) of forming a first insulating film for preventing diffusion of copper on the second interlayer insulating film, and a conductive layer selectively on the first insulating film. (D) forming the magnetic tunnel resistance element on the conductor layer after forming, the conductor layer and the magnetic layer Forming a first interlayer insulating film on the first insulating film so as to cover the tunnel resistance element; and forming a third interlayer insulating film on the first interlayer insulating film. A step (f) and a step (g) of forming a second copper wiring layer in the surface of the third interlayer insulating film, wherein the step (a) has a relative dielectric constant of 3.0 or less. A step of forming the second interlayer insulating film with an insulating film, and the step (e) includes a step of forming the first interlayer insulating film with an insulating film having a relative dielectric constant greater than 3.0. The step (f) includes a step of forming the third interlayer insulating film with an insulating film having a relative dielectric constant greater than 3.0.

  According to the semiconductor device of the first aspect of the present invention, at least one second interlayer insulating film disposed below the first interlayer insulating film is an insulating material having a relative dielectric constant of 3.0 or less. Since it is composed of a film, it is possible to reduce the wiring capacitance C and to suppress the wiring delay determined by the product (RC) of the wiring resistance R and the wiring capacitance C. In addition, since the first interlayer insulating film and the third interlayer insulating film disposed on the first interlayer insulating film are composed of insulating films having a relative dielectric constant of 3.0, the first and When the third interlayer insulating film is formed, a predetermined relative dielectric constant and film quality can be obtained even when formed at a temperature of 300 ° C. or lower. As a result, the temperature history applied to the magnetic tunnel resistance element can be made 300 ° C. or less, and the trade-off relationship between ensuring the function of the magnetic tunnel resistance element and the formation conditions of the interlayer insulating film can be solved.

  According to the method of manufacturing a semiconductor device according to the sixth aspect of the present invention, the temperature history applied to the magnetic tunnel resistance element can be set to 300 ° C. or less, the function of the magnetic tunnel resistance element is ensured, and the interlayer insulating film is formed. A semiconductor device in which the trade-off relationship between the conditions is solved can be obtained.

<Embodiment>
<A. Manufacturing method>
First, a method for manufacturing an MRAM (Magnetic Random Access Memory) according to an embodiment of the present invention will be described with reference to FIGS.

  1 to 24 are cross-sectional views for explaining the MRAM manufacturing method of the present embodiment in the order of steps, and FIG. 24 for explaining the final step shows the MRAM 100 according to the present invention. 1 to 24 partially show the memory cell portion and the logic circuit portion.

  First, in a step shown in FIG. 1, a semiconductor substrate 1 such as a silicon substrate is prepared, and a semiconductor integrated circuit is formed in a region corresponding to the memory cell portion and the logic circuit portion on the semiconductor substrate 1.

  In FIG. 1, MOS transistors 2 and 3 are shown in a memory cell portion and a logic circuit portion, respectively, as an example of a semiconductor element constituting a semiconductor integrated circuit.

  The MOS transistor 2 includes a gate electrode 22 disposed on the semiconductor substrate 1 via a gate insulating film 21, a sidewall insulating film 23 disposed on a side surface of the gate electrode 22, and a gate length direction of the gate electrode 22. The source / drain layers 24 are respectively disposed in the surface of the semiconductor substrate 1 outside the both side surfaces.

  The MOS transistor 3 includes a gate electrode 32 disposed on the semiconductor substrate 1 via a gate insulating film 31, a sidewall insulating film 33 disposed on a side surface of the gate electrode 32, and a gate of the gate electrode 32. A source / drain layer 34 is provided in the surface of the semiconductor substrate 1 outside both side surfaces in the longitudinal direction.

  Since semiconductor elements such as MOS transistors 2 and 3 are formed by a well-known technique, description of the manufacturing method is omitted.

  Next, an interlayer insulating film 4 (second interlayer insulating film) is formed on the entire surface of the semiconductor substrate 1 by forming a SiOC film having a relative dielectric constant of 3.0 or less formed by, for example, plasma CVD. The interlayer insulating film 4 is not limited to the SiOC film, and may be an insulating film having a relative dielectric constant of 3.0 or less (the lower limit is about 1.5). Here, in order to improve the filling failure caused by the step of the gate electrode 32, a silicon oxide film (SiO 2 film) having good filling characteristics such as a TEOS (tetraethyl orthosilicate) film may be used.

  In the memory cell portion, holes 4b reaching the source / drain layers 24 of the MOS transistor 2 through the interlayer insulating film 4 are provided, and in the logic circuit portion, the interlayer insulating film 4 is penetrated to form the MOS transistor. Hole 4b reaching the source / drain layer 34 is provided.

  Thereafter, in the step shown in FIG. 2, a TiN (titanium nitride) film or a Ti (titanium) film is formed so as to cover the entire surface of the interlayer insulating film 4 and the inner surface of the hole 4b by sputtering, and is formed on the inner surface of the hole 4b. A barrier metal layer BM is provided, and subsequently, the contact 4a is formed by filling the hole 4b with tungsten (W) by CVD.

  Next, in the step shown in FIG. 3, an SiOC film having a relative dielectric constant of 3.0 or less is formed on the entire surface of the interlayer insulating film 4 by, eg, plasma CVD to form an interlayer insulating film 5 (second interlayer insulating film). Provide. The interlayer insulating film 5 is not limited to the SiOC film, and may be an insulating film having a relative dielectric constant of 3.0 or less (the lower limit is about 1.5).

  Then, in the memory cell portion and the logic circuit portion, the wiring trenches 5b that penetrate through the interlayer insulating film 5 and reach the respective contact portions 4a are patterned using photolithography and etching.

  Thereafter, in the step shown in FIG. 4, a TaN (tantalum nitride) film or a Ta (tantalum) film is formed by sputtering to cover the entire surface of the interlayer insulating film 5 and the inner surface of the wiring groove 5b. A barrier metal layer BM1 is provided on the inner surface, and then a wiring layer 5a (first copper wiring layer) is formed by filling the wiring groove 5b with a Cu film by CVD or plating. Note that after the formation of the Cu film, heat treatment at 300 ° C. or higher (upper limit is about 450 ° C.) is applied.

  Next, in the step shown in FIG. 5, an insulating film such as a SiN film is formed by, for example, plasma CVD so as to cover the entire main surface of the interlayer insulating film 5 to prevent diffusion of Cu. A first insulating film) is formed. The diffusion preventing insulating film PD1 is not limited to the SiN film, and may be any insulating film that can provide etching selectivity with respect to the interlayer insulating film formed on the upper part. The diffusion preventing insulating film PD1 is composed of a SiC film or a SiCN film. May be.

  Thereafter, an interlayer insulating film 6 (second interlayer insulating film) is formed on the entire surface of the diffusion preventing insulating film PD1 by, for example, forming a SiOC film by a plasma CVD method.

  Then, a resist mask (not shown) is patterned on the interlayer insulating film 6 through a photolithography process, the interlayer insulating film 6 is etched using the resist mask, and the interlayer insulating film is formed in the memory cell portion and the logic circuit portion. A hole 6 b penetrating through 6 is provided. The hole 6b is provided at a position corresponding to the upper part of the wiring layer 5a.

  Next, a resist mask (not shown) is patterned on the interlayer insulating film 6 through a photoengraving process, and the interlayer insulating film 6 is etched using the resist mask. In the memory cell portion and the logic circuit portion, respectively. The wiring groove 7b communicating with the hole 6b is patterned.

  Next, under the conditions for etching the SiN film, the diffusion preventing insulating film PD1 exposed at the bottom of the hole 6b is removed so that the hole 6b reaches the wiring layer 5a.

  Thereafter, a TaN film or a Ta film is formed by sputtering so as to cover the entire surface of the interlayer insulating film 6 and to cover the inner surfaces of the wiring grooves 7b and the holes 6b.

  Subsequently, a Cu film is formed by CVD or plating so as to cover the entire surface of the interlayer insulating film 6, thereby filling the wiring trench 7b and the hole 6b with the Cu film. In addition, after formation of Cu film | membrane, the heat processing of 300 to 450 degreeC is added.

  Thereafter, unnecessary Cu film and TaN film or Ta film on the interlayer insulating film 6 are removed by using a CMP (Chemical Mechanical Polish) method or the like, and a barrier metal layer BM1 and a wiring layer 7a (as shown in FIG. A first copper wiring layer) and a contact portion 6a are obtained.

  Next, in the step shown in FIG. 7, an insulating film such as a SiN film is formed by plasma CVD, for example, so as to cover the entire main surface of the interlayer insulating film 6, and a diffusion preventing insulating film PD1 for preventing the diffusion of Cu is formed. Form.

  Thereafter, an interlayer insulating film 7 (second interlayer insulating film) is formed on the entire surface of the diffusion preventing insulating film PD1 by, for example, forming a SiOC film by a plasma CVD method.

  Then, a resist mask (not shown) is patterned on the interlayer insulating film 7 through a photolithography process, the interlayer insulating film 7 is etched using the resist mask, and the interlayer insulating film is formed in the memory cell portion and the logic circuit portion. 7 is provided. The hole 8b is provided at a position corresponding to the upper part of the wiring layer 7a.

  Next, a resist mask (not shown) is patterned on the interlayer insulating film 7 through a photoengraving process, and the interlayer insulating film 7 is etched using the resist mask. In the memory cell portion and the logic circuit portion, respectively. A plurality of wiring grooves 9b are patterned. Note that at least one of the plurality of wiring grooves 9b is arranged to communicate with the hole 8b.

  Next, under the conditions for etching the SiN film, the diffusion preventing insulating film PD1 exposed at the bottom of the hole 8b is removed so that the hole 8b reaches the wiring layer 7a.

  Thereafter, in the step shown in FIG. 8, a TaN film or a Ta film is formed so as to cover the entire surface of the interlayer insulating film 7 and cover the inner surfaces of the wiring grooves 9b and the holes 8b by sputtering, and the inner surfaces of the wiring grooves 9b and the holes 8b. A barrier metal layer BM1 is provided.

  Subsequently, a Cu film ML is formed by a CVD method or a plating method so as to cover the entire surface of the interlayer insulating film 7, thereby filling the wiring groove 9b and the hole 8b with the Cu film ML. Note that after the formation of the Cu film ML, a heat treatment at 300 ° C. to 450 ° C. is performed.

  Thereafter, unnecessary Cu film ML and barrier metal layer BM1 on interlayer insulating film 7 are removed by using a CMP (Chemical Mechanical Polish) method or the like, and wiring layer 9a (first copper wiring) as shown in FIG. Layer) and contact portion 8a.

  Subsequently, an insulating film such as a SiN film is formed by, for example, a plasma CVD method so as to cover the entire main surface of the interlayer insulating film 7, thereby forming a diffusion preventing insulating film PD1 for preventing diffusion of Cu.

  Next, in the step shown in FIG. 10, a resist mask (not shown) is patterned on the diffusion prevention insulating film PD1 through a photolithography process, and communicated with the contact portion 8a of the memory cell portion using the resist mask. The diffusion preventing insulating film PD1 located on the wiring layer 9a is etched to form an opening OP1 reaching the wiring layer 9a.

  Thereafter, a metal film such as a W (tungsten) film is formed by, eg, thermal CVD so as to cover the entire surface of the diffusion prevention insulating film PD1, thereby filling the opening OP1 with the metal film and forming the contact portion 10a. To do. The unnecessary metal film on the diffusion preventing insulating film PD1 is removed by using a CMP method or the like.

  Here, the metal film filled in the contact portion 10a may be a Ta film, a Cu film, or a multilayer film composed of at least two kinds of films among the Ta film, the Cu film, and the W film. A sputtering method may be used for forming the Ta film, and a plating method may be used for forming the Cu film.

  Next, in the step shown in FIG. 11, a metal film ML1 such as a Ta film or a TiN film is formed on the entire surface of the diffusion prevention insulating film PD1 by, for example, a sputtering method. Further, a composite film SL1 having a multilayer structure including at least a laminated film in which a tunnel insulating film is sandwiched between two ferromagnetic films is formed thereon.

  Of the two ferromagnetic films, the ferromagnetic film (pinned layer) whose magnetization vector direction should be fixed is made of, for example, a CoFe alloy and changes the magnetization vector direction. The (free layer) can be made of, for example, a NiFe alloy, and the tunnel insulating film can be made of Al 2 O 3.

  Note that the composite film SL1 is a film for forming a magnetic tunnel junction, and is not limited to the above-described configuration. In addition, it is not necessary to use a film having a new composition, and a film having a known composition is used. Adopt it.

  Next, in the process shown in FIG. 12, the metal film ML1 and the composite film SL1 are processed into a desired shape through a photolithography process and an etching process, and the strap wiring 11 is selectively formed on the diffusion prevention insulating film PD1 in the memory cell portion. The TMR element 12 is selectively disposed on the strap wiring 11. In the logic circuit portion, the metal film ML1 and the composite film SL1 are removed so as not to remain.

  The strap wiring 11 extends so as to cover the contact portion 10a penetrating the diffusion preventing insulating film PD1, and the strap wiring 11 is electrically connected to the wiring layer 9a through the contact portion 10a.

  Here, the wiring layer 9a electrically connected to the strap wiring 11 is a lead wire for reading a tunnel current flowing through the TMR element 12, and the tunnel current flowing through the TMR element 12 is passed through the strap wiring 11 which is a lead wiring. Given to the lead wire.

  The wiring layer 9a constituting the lead wire has a pad shape, and the wiring layers 7a and 5a existing below the wiring layer 9a also have a pad shape.

  The wiring layer 9a existing at a position below the TMR element 12 in the surface of the interlayer insulating film 7 is a write wiring (digit line) for generating data in the TMR element 12 by generating a magnetic field by the flowing current. Yes, extending in a direction perpendicular to the drawing.

  Next, in the step shown in FIG. 13, an interlayer insulating film 13 (first interlayer insulating film) is provided on the entire surface of the diffusion preventing insulating film PD1 by, for example, plasma CVD to provide an interlayer insulating film 13 (first interlayer insulating film). The element 12 is covered. Here, the interlayer insulating film 13 is formed of an insulating film having a relative dielectric constant larger than 3.0, and is formed at a temperature of 300 ° C. or lower (the lower limit is about 200 ° C.).

  Next, in the step shown in FIG. 14, after forming the opening OP2 penetrating the interlayer insulating film 13 and reaching the TMR element 12, W (tungsten) is formed by CVD, for example, so as to cover the entire surface of the interlayer insulating film 13. ) By forming a metal film such as a film, the opening OP2 is filled with the metal film to form the contact portion 11a. The unnecessary metal film on the interlayer insulating film 13 is removed by using a CMP method or the like.

  Here, the metal film filled in the contact portion 11a may be a Ta film, a Cu film, or a multilayer film composed of at least two kinds of films among the Ta film, the Cu film, and the W film. A sputtering method may be used for forming the Ta film, and a plating method may be used for forming the Cu film.

  Next, in the step shown in FIG. 15, an interlayer insulating film 14 (third interlayer insulating film) is formed on the entire surface of the interlayer insulating film 13 by forming a SiO film by, for example, plasma CVD. Here, the interlayer insulating film 14 is not limited to the SiO film, and may be an insulating film formed of an insulating film having a relative dielectric constant larger than 3.0 and formed at a temperature of 300 ° C. or lower.

  Next, in the process shown in FIG. 16, a resist mask (not shown) is patterned on the interlayer insulating film 14 through a photoengraving process, and the interlayer insulating films 14 and 13 are etched using the resist mask, whereby a logic circuit is formed. In the portion, a hole 13b that penetrates through the interlayer insulating films 14 and 13 and reaches the wiring layer 9a is provided.

  In FIG. 16, the hole 13b is provided at a position corresponding to the upper part of the wiring layer 9a that is not connected to the lower wiring layer 7a among the plurality of wiring layers 9a, but this is only an example.

  Subsequently, a resist mask (not shown) is patterned on the interlayer insulating film 14 through a photolithography process, the interlayer insulating film 14 is etched using the resist mask, and wiring is performed in the memory cell portion and the logic circuit portion. The groove 14b is patterned.

  In the memory cell portion, the wiring groove 14b is provided so as to expose the contact portion 11a, and the wiring groove 14b is flat on the wiring layer 9a serving as a digit line provided in the surface of the interlayer insulating film 7. It is provided so as to extend in a direction orthogonal to the view (horizontal direction with respect to the drawing).

  In the logic circuit portion, the wiring groove 14b is disposed so as to communicate with the hole 13b.

  Next, under the conditions for etching the SiN film, the diffusion preventing insulating film PD1 exposed at the bottom of the hole 13b is removed so that the hole 13b reaches the wiring layer 9a.

  Thereafter, in the step shown in FIG. 17, a TaN film or a Ta film is formed so as to cover the entire surface of the interlayer insulating film 14 and cover the inner surfaces of the wiring grooves 14b and the holes 13b by sputtering, and the inner surfaces of the wiring grooves 14b and the holes 13b. A barrier metal layer BM1 is provided.

  Subsequently, a Cu film ML is formed by a CVD method or a plating method so as to cover the entire surface of the interlayer insulating film 14, thereby filling the wiring groove 14b and the hole 13b with the Cu film ML. Note that after the formation of the Cu film ML, a heat treatment of less than 300 ° C. (the lower limit is about 100 ° C.) is applied.

  Next, in the step shown in FIG. 18, unnecessary Cu film ML and barrier metal layer BM1 on interlayer insulating film 14 are removed by using a CMP method or the like, and wiring layer 14a (second copper wiring layer) and Contact part 13a is obtained. In the memory cell portion, the wiring layer 14a electrically connected to the TMR element 12 via the contact portion 11a generates a magnetic field by a flowing current and writes data to the TMR element 12 (bit line). It is.

  Next, an insulating film such as a SiN film is formed by, for example, a plasma CVD method so as to cover the interlayer insulating film 14 and the wiring layer 14a, thereby preventing the diffusion preventing insulating film PD2 (second insulating film) Film). The diffusion preventing insulating film PD2 is not limited to the SiN film, and is an insulating film having a relative dielectric constant larger than 3.0, formed at a temperature of 300 ° C. or lower, and formed on the upper part. Any insulating film may be used as long as etching selectivity with the film is obtained.

  Next, in the step shown in FIG. 19, an interlayer insulating film 15 (fourth interlayer insulating film) is formed on the entire surface of the diffusion preventing insulating film PD2 by forming a SiO film by, for example, plasma CVD. Here, the interlayer insulating film 15 is not limited to the SiO film, and may be an insulating film formed of an insulating film having a relative dielectric constant larger than 3.0 and formed at a temperature of 300 ° C. or lower.

  Then, a resist mask (not shown) is patterned on the interlayer insulating film 15 through a photolithography process, the interlayer insulating film 15 is etched using the resist mask, and penetrates the interlayer insulating film 15 in the logic circuit portion. A hole 15b is provided. The hole 15b is provided at a position corresponding to the upper part of the wiring layer 14a. Here, the diameter of the hole 15b is 0.2 μm or more (the upper limit is about 0.5 μm).

  Next, a resist mask (not shown) is patterned on the interlayer insulating film 15 through a photolithography process, the interlayer insulating film 15 is etched using the resist mask, and communicates with the holes 15b in the logic circuit portion. The wiring trench 16b is patterned.

  Next, under the conditions for etching the SiN film, the diffusion preventing insulating film PD2 exposed at the bottom of the hole 15b is removed so that the hole 15b reaches the wiring layer 14a.

  Thereafter, in the step shown in FIG. 20, a TaN film or a Ta film is formed so as to cover the entire surface of the interlayer insulating film 15 and cover the inner surfaces of the wiring grooves 16b and the holes 15b by sputtering, and the inner surfaces of the wiring grooves 16b and the holes 15b. A barrier metal layer BM1 is provided.

  Subsequently, a Cu film ML is formed by a CVD method or a plating method so as to cover the entire surface of the interlayer insulating film 15, thereby filling the wiring groove 16b and the hole 15b with the Cu film ML. Note that after the formation of the Cu film ML, a heat treatment of less than 300 ° C. is performed.

  Next, in the step shown in FIG. 21, unnecessary Cu film ML and barrier metal layer BM1 on interlayer insulating film 15 are removed by using a CMP method or the like to obtain wiring layer 16a and contact portion 15a.

  Next, an insulating film such as a SiN film is formed by, for example, a plasma CVD method so as to cover the interlayer insulating film 15 and the wiring layer 16a, thereby forming a diffusion preventing insulating film PD2 for preventing Cu diffusion.

  Next, in the step shown in FIG. 22, an interlayer insulating film 17 (fourth interlayer insulating film) is formed on the entire surface of the diffusion preventing insulating film PD2 by forming a SiO film by, for example, plasma CVD. Here, the interlayer insulating film 17 is not limited to the SiO film, and may be an insulating film formed of an insulating film having a relative dielectric constant larger than 3.0 and formed at a temperature of 300 ° C. or lower.

  Then, a resist mask (not shown) is patterned on the interlayer insulating film 17 through a photolithography process, the interlayer insulating film 17 is etched using the resist mask, and penetrates the interlayer insulating film 17 in the logic circuit portion. A hole 17b is provided. The hole 17b is provided at a position corresponding to the upper part of the wiring layer 16a. Here, the diameter of the hole 17b is 0.2 μm or more (the upper limit is about 0.5 μm).

  Next, a resist mask (not shown) is patterned on the interlayer insulating film 17 through a photolithography process, the interlayer insulating film 17 is etched using the resist mask, and communicates with the hole 17b in the logic circuit portion. The wiring groove 18b is patterned.

  Next, under the conditions for etching the SiN film, the diffusion preventing insulating film PD2 exposed at the bottom of the hole 17b is removed so that the hole 17b reaches the wiring layer 16a.

  Thereafter, in the step shown in FIG. 23, a TaN film or a Ta film is formed so as to cover the entire surface of the interlayer insulating film 17 and cover the inner surfaces of the wiring grooves 18b and the holes 17b by sputtering, and the inner surfaces of the wiring grooves 18b and the holes 17b. A barrier metal layer BM1 is provided.

  Subsequently, a Cu film ML is formed by a CVD method or a plating method so as to cover the entire surface of the interlayer insulating film 17, thereby filling the wiring groove 18b and the hole 17b with the Cu film ML. Note that after the formation of the Cu film ML, a heat treatment of less than 300 ° C. is performed.

  Next, in the step shown in FIG. 24, unnecessary Cu film ML and barrier metal layer BM1 on interlayer insulating film 17 are removed by using a CMP method or the like to obtain wiring layer 18a and contact portion 17a.

  Finally, an insulating film such as a SiN film is formed by, for example, a plasma CVD method so as to cover the interlayer insulating film 17 and the wiring layer 18a, thereby forming a diffusion preventing insulating film PD2 for preventing the diffusion of Cu. , MRAM100 is obtained.

<B. Effect>
In the MRAM 100 obtained through the manufacturing steps described above, the effects described below can be obtained from the structural features and the manufacturing method.

<B-1. First effect>
First, since the insulating film having a relative dielectric constant of 3.0 or less is used for the interlayer insulating films 4 to 7 disposed below the TMR element 12, the wiring capacitance C should be reduced. As a result, the wiring delay determined by the product (RC) of the wiring resistance R and the wiring capacitance C can be suppressed.

  In forming the interlayer insulating films 4 to 7, it is not necessary to consider the thermal influence on the TMR element 12. Therefore, when the interlayer insulating films 4 to 7 are formed by using the plasma CVD method, the upper limit is about 450 ° C. ) And a relative dielectric constant of 3.0 or less and a strength for withstanding the manufacturing process can be secured.

<B-2. Second effect>
Second, the interlayer insulating film 13 covering the TMR element 12, the interlayer insulating films 14 to 17 and the diffusion preventing insulating film PD2 above the interlayer insulating film 13 are composed of insulating films having a relative dielectric constant larger than 3.0. Even when these insulating films are formed at a temperature of 300 ° C. or lower, a predetermined dielectric constant and film quality can be obtained, so that the temperature history applied to the TMR element 12 can be 300 ° C. or lower, The effect that the magnetic characteristics of the TMR element 12 can be maintained is obtained.

<B-3. Third effect>
Third, the effect of improving SIV resistance is obtained.
FIG. 25 is a diagram showing change characteristics of via hole resistance (via hole diameter: 0.14 μm) of a plurality of via holes by high temperature storage (200 ° C.), and the measurement result of via hole resistance measured before and after high temperature storage. The horizontal axis represents the variation rate (%) of the via hole resistance, and the horizontal axis represents the distribution of the relative cumulative frequency (%) of the heat treatment.

  The distribution X in FIG. 25 indicates that both the interlayer insulating film in which the wiring on the lower layer side is formed and the interlayer insulating film in which the via hole (that is, the contact portion) connecting the lower layer wiring and the upper layer wiring is formed. The distribution of the variation rate of the via hole resistance in the wiring structure X using an insulating film having a relative dielectric constant of 3.0 or less is shown.

  From FIG. 25, it can be seen that in the case of this wiring structure X, a phenomenon in which the via hole resistance increases due to heat treatment occurs. Such an increase in resistance value is caused by voids (SIV) generated by stress generated during high temperature storage.

  In the distribution Y in FIG. 25, an insulating film having a relative dielectric constant of 3.0 or less is used for the interlayer insulating film on which the lower layer side wiring (lower layer wiring) is formed, and the lower layer wiring and the upper layer side wiring (upper layer wiring). The distribution of the variation in the via hole resistance in the wiring structure Y in which the insulating film having a relative dielectric constant of 4.3 is used for the interlayer insulating film in which the via hole (contact portion) connecting the two is formed is shown.

  From FIG. 25, it can be seen that in this wiring structure Y, there is almost no increase in via hole resistance due to high temperature storage.

  This is because the upper part of the wiring on the lower layer side is covered with an insulating film having a high dielectric constant of 4.3 compared to an insulating film having a low dielectric constant, so that the stress gradient due to thermal stress is alleviated and SIV is generated. It seems that it became difficult.

  The third effect is that an insulating film having a relative dielectric constant of 3.0 or less is used for the interlayer insulating films 4 to 7 disposed below the TMR element 12, including the periphery of the TMR element 12, The insulating film disposed above the TMR element 12 is obtained by a structure unique to the present invention in which an insulating film having a relative dielectric constant larger than 3.0 is used.

<B-4. Fourth effect>
Fourth, heat treatment at 300 ° C. to 450 ° C. is performed after the formation of the Cu film for forming the wiring layers 4a, 7a and 9a below the TMR element 12, so that the effect of suppressing the generation of SIV is obtained. It is done.

FIG. 26 shows the correlation between the failure rate due to SIV and the heat treatment temperature after Cu film formation.
In FIG. 26, the horizontal axis represents the heat treatment temperature after Cu film formation, and the vertical axis represents the failure rate due to SIV generated by accelerated evaluation by storage at a high temperature (150 to 300 ° C.).

  As is clear from FIG. 26, the failure rate due to SIV becomes more pronounced as the heat treatment after Cu film formation is lowered, and conversely decreases as the temperature rises, and becomes almost zero at 400 ° C.

  Therefore, it can be seen that a process of applying a heat treatment at 300 ° C. or higher after forming the Cu film is effective for obtaining a highly reliable Cu wiring.

  Since a heat treatment at 300 ° C. or higher is performed when forming a wiring layer below the TMR element 12, it is not necessary to consider the thermal influence on the TMR element 12, and the magnetic characteristics of the TMR element 12 can be maintained. The effect is also obtained.

<B-5. Fifth effect>
Fifth, since the heat treatment after the formation of the Cu film for forming the wiring layers 14a, 16a and 18a above the TMR element 12 is performed at less than 300 ° C., the temperature history applied to the TMR element 12 is 300 ° C. or less. The magnetic characteristics of the TMR element 12 can be maintained.

  However, since the heat treatment after the formation of the Cu film for forming the upper wiring layer than the TMR element 12 is performed at less than 300 ° C., the SIV resistance deteriorates at the connection portion with the lower wiring layer than the TMR element 12. There is a concern to do.

Here, FIG. 27 shows a typical analysis result of a defective portion caused by SIV.
FIG. 27 shows a cross-sectional analysis photograph of the lower layer wiring 201 and the upper layer wiring 203 and the via hole 202 connecting them. As can be seen from this photograph, the void VD due to SIV is generated in the lower layer wiring portion immediately below the via hole 202.

  The reason why the SIV resistance is improved by the high-temperature heat treatment after the formation of the Cu film is thought to be because the generation of voids is suppressed by the grain growth of the Cu film and the reduction of vacancies. Since it is generated in 201, it can be seen that if the Cu film for forming the lower layer wiring 201 is heat-treated at a high temperature (300 ° C. to 450 ° C.), the SIV resistance does not deteriorate. Therefore, in the MRAM 100 shown in FIG. 24, if the Cu film for forming the lower wiring layer 9a of the TMR element 12 is heat-treated at a high temperature (300 ° C. to 450 ° C.), the upper wiring layer 14a of the TMR element 12 is formed. Even if the heat treatment after the formation of the Cu film for forming the film is performed at less than 300 ° C., it is possible to prevent the SIV resistance from deteriorating.

<B-6. Sixth effect>
Further, as a sixth effect, for the wiring layers 16a and 18a above the wiring layer 14a, the contact portion 15a (via hole) connecting the wiring layer 14a and the wiring layer 16a, and the wiring layer 16a and the wiring layer 18a Since the diameter of the contact portion 17a (via hole) for connecting is set to 0.2 μm or more (the upper limit is about 0.5 μm), it is possible to suppress a decrease in SIV resistance.

  FIG. 28 shows the relationship between the failure rate due to SIV and the via hole diameter.

  In FIG. 28, the horizontal axis represents the via hole diameter (μm), and the vertical axis represents the failure rate (arbitrary unit) due to SIV.

  From FIG. 28, it can be seen that the failure due to SIV occurs remarkably in the via hole of less than 0.2 μm, and the failure rate is lowered by increasing the via hole diameter.

  Therefore, the Cu film for forming the wiring above the TMR element 12 is subjected to a heat treatment at less than 300 ° C., but the increase in the via hole diameter can suppress the decrease in SIV resistance.

<C. Modification>
In the MRAM 100 described above, an example in which the TMR element 12 is provided between the wiring layer 9a corresponding to the third layer counted from the semiconductor substrate 1 side and the wiring layer 14a corresponding to the fourth layer is shown. The arrangement position of 12 is not limited to this.

  For example, between the wiring layer corresponding to the first layer counted from the semiconductor substrate side and the wiring layer corresponding to the second layer, or the wiring layer corresponding to the uppermost layer counted from the semiconductor substrate side, and one layer below the wiring layer A TMR element may be disposed between the two wiring layers.

It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is sectional drawing explaining the manufacturing process of the semiconductor device of embodiment which concerns on this invention. It is a figure showing the change characteristic of via-hole resistance of a plurality of via holes by high temperature preservation. It is a figure which shows the correlation with the failure rate resulting from SIV, and the heat processing temperature after Cu film formation. It is a figure which shows the typical analysis result of the defect location resulting from SIV. It is a figure which shows the relationship between the failure rate by SIV, and a via-hole diameter. It is sectional drawing of the MRAM part of SOC to which a Cu / Low-k wiring structure is applied. It is sectional drawing of the MRAM part of SOC to which a Cu / Low-k wiring structure is applied.

Explanation of symbols

4-7, 13-15, 17 Interlayer insulating film, 9a, 14a wiring layer, 11 strap wiring, 12 TMR element.

Claims (9)

A plurality of wiring layers arranged in multiple layers on a semiconductor substrate;
A plurality of interlayer insulating films respectively disposed between the plurality of wiring layers;
A magnetic tunnel resistance element including a magnetic tunnel junction disposed in a first interlayer insulating film forming one layer of the plurality of interlayer insulating films,
At least one second interlayer insulating film disposed below the first interlayer insulating film is composed of an insulating film having a relative dielectric constant of 3.0 or less;
The semiconductor device, wherein the first interlayer insulating film and the third interlayer insulating film disposed on the first interlayer insulating film are formed of an insulating film having a relative dielectric constant of 3.0. The at least one second interlayer insulating film is formed at a temperature higher than 300 ° C .;
The semiconductor device according to claim 1, wherein the first and third interlayer insulating films are formed at a temperature of 300 ° C. or lower. The plurality of wiring layers include a first copper wiring layer disposed in a surface of at least one second interlayer insulating film;
The first copper wiring layer is formed through a heat treatment of 300 ° C. or higher,
The plurality of wiring layers include a second copper wiring layer disposed in the surface of the third interlayer insulating film,
The semiconductor device according to claim 1, wherein the second copper wiring layer is formed through a heat treatment at less than 300 ° C. 3. At least one fourth interlayer insulating film disposed above the third interlayer insulating film; and
A contact portion disposed in the at least one fourth interlayer insulating film and connecting the wiring layers in a vertical relationship;
The semiconductor device according to claim 1, wherein a diameter of the contact portion is 0.2 μm or more. The at least one fourth interlayer insulating film is formed at a temperature of 300 ° C. or less, and the second copper wiring layer is also disposed in the surface of the at least one fourth interlayer insulating film. The semiconductor device according to claim 4. A plurality of wiring layers disposed in multiple layers on the semiconductor substrate; a plurality of interlayer insulating films respectively disposed between the plurality of wiring layers; and a first layer forming one of the plurality of interlayer insulating films A method of manufacturing a semiconductor device comprising: a magnetic tunnel resistance element including a magnetic tunnel junction disposed in an interlayer insulating film;
(a) forming a second interlayer insulating film to be a lower layer film of the first interlayer insulating film above the semiconductor substrate;
(b) forming a first copper wiring layer in the surface of the second interlayer insulating film;
(c) forming a first insulating film for preventing diffusion of copper on the second interlayer insulating film;
(d) after selectively forming a conductor layer on the first insulating film, forming the magnetic tunnel resistance element on the conductor layer;
(e) forming the first interlayer insulating film on the first insulating film so as to cover the conductor layer and the magnetic tunnel resistance element;
(f) forming a third interlayer insulating film on the first interlayer insulating film;
(g) forming a second copper wiring layer in the surface of the third interlayer insulating film,
The step (a)
Forming the second interlayer insulating film with an insulating film having a relative dielectric constant of 3.0 or less,
The step (e) includes a step of forming the first interlayer insulating film with an insulating film having a relative dielectric constant greater than 3.0,
The method (f) includes a step of forming the third interlayer insulating film with an insulating film having a relative dielectric constant greater than 3.0. The step (a)
Forming the second interlayer insulating film at a temperature higher than 300 ° C .;
The step (e)
Forming the first interlayer insulating film at a temperature of 300 ° C. or lower;
The step (f)
The method of manufacturing a semiconductor device according to claim 6, comprising a step of forming the third interlayer insulating film at a temperature of 300 ° C. or lower. The step (b)
Removing the surface of the second interlayer insulating film to a predetermined depth and patterning the first wiring groove;
Forming a copper layer on the second interlayer insulating film, filling the copper layer in the first wiring trench, and then subjecting the copper layer to a heat treatment of 300 ° C. or higher,
The step (g)
Removing the surface of the third interlayer insulating film to a predetermined depth and patterning the second wiring trench;
Forming a copper layer on the third interlayer insulating film and filling the second wiring trench with the copper layer, and then subjecting the copper layer to a heat treatment of less than 300 ° C. A method for manufacturing a semiconductor device according to claim 7. After step (g)
(h) forming a second insulating film for preventing copper diffusion on the third interlayer insulating film;
(i) forming at least one fourth interlayer insulating film on the second insulating film;
(j) further comprising the step of forming a contact portion connecting the wiring layers in a vertical relationship in the at least one fourth interlayer insulating film,
The step (j)
The method for manufacturing a semiconductor device according to claim 6, comprising a step of setting the diameter of the contact portion to 0.2 μm or more.