CN112420918B

CN112420918B - Semiconductor element and manufacturing method thereof

Info

Publication number: CN112420918B
Application number: CN201910778695.9A
Authority: CN
Inventors: 郭致玮; 许家彰; 赖育聪; 廖俊雄
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2023-08-15
Anticipated expiration: 2039-08-22
Also published as: CN112420918A; US20210057637A1; US11121307B2

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, wherein the manufacturing method of the semiconductor element comprises the steps of firstly forming a first magnetic tunneling junction (magnetic tunneling junction, MTJ) and a second MTJ on a substrate, then forming a first upper electrode on the first MTJ and a second upper electrode on the second MTJ, and forming a shielding layer on the first MTJ and the second MTJ; forming a protective layer on the covering layer; removing a portion of the protective layer to form a recess between the first MTJ and the second MTJ; forming a reflection layer on the protection layer and filling the groove; and removing the reflecting layer, the protecting layer and the covering layer to form a first contact hole.

Description

Semiconductor element and manufacturing method thereof

Technical Field

The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM) and a method for fabricating the same.

Background

As known, the Magnetic Resistance (MR) effect is an effect that the resistance of a material changes with the change of an applied magnetic field, and the physical quantity is defined by dividing the resistance difference with or without the magnetic field by the original resistance to represent the resistance change rate. Currently, the magneto-resistance effect has been successfully applied to hard disk production, and has important commercial application value. In addition, by utilizing the characteristic that giant magnetoresistance substances have different resistance values in different magnetization states, the Magnetic Random Access Memory (MRAM) can be manufactured, and has the advantage of continuously retaining stored data under the condition of no power.

The magneto-resistive effect is also used in the field of magnetic field sensing (magnetic field sensor), such as electronic compass (electronic compass) components of mobile phone with global positioning system (global positioning system, GPS) for providing information of the mobile azimuth of the user. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (anisotropic magnetoresistance, AMR) sensing elements, giant Magnetoresistive (GMR) sensing elements, magnetic tunneling junction (magnetic tunneling junction, MTJ) sensing elements, and the like. However, the drawbacks of the above prior art generally include: further improvements are needed, such as more chip area, more expensive fabrication processes, more power consumption, insufficient sensitivity, and susceptibility to temperature variations.

Disclosure of Invention

One embodiment of the present invention discloses a method for fabricating a semiconductor device. First forming a first magnetic tunnel junction (magnetic tunneling junction, MTJ) and a second MTJ on a substrate, then forming a first upper electrode on the first MTJ and a second upper electrode on the second MTJ, forming a cap layer on the first MTJ and the second MTJ; forming a protective layer on the covering layer; removing a portion of the protective layer to form a recess between the first MTJ and the second MTJ; forming a reflection layer on the protection layer and filling the groove; and removing the reflecting layer, the protecting layer and the covering layer to form a first contact hole.

In another embodiment of the present invention, a semiconductor device is disclosed, which mainly comprises: a first MTJ and a second MTJ disposed on a substrate; a first upper electrode disposed on the first MTJ and a second upper electrode disposed on the second MTJ; a shielding layer disposed on the first MTJ and the second MTJ; an ultralow dielectric constant dielectric layer disposed on the shielding layer and surrounding the first MTJ and the second MTJ; and a first metal interconnect is disposed between the first MTJ and the second MTJ, wherein one sidewall of the first metal interconnect contacts the ultra low dielectric constant dielectric layer and the other sidewall of the first metal interconnect contacts the ultra low dielectric constant dielectric layer and the capping layer.

Drawings

Fig. 1 to 9 are schematic views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention.

Description of the main reference signs

12. Substrate 14 MTJ region

16. Interlayer dielectric layer of logic region 18

20. Metal interconnect structure 22 metal interconnect structure

24. Intermetallic dielectric layer 26 metal interconnect

28. Stop layer 30 inter-metal dielectric layer

32. Barrier layer of metal interconnect 34

36. Metal layer 38 MTJ stack structure

40. Masking layer 42 masking layer

44. First electrode layer 46 fixing layer

48. Barrier layer 50 free layer

52. Second electrode layer 54 patterning mask

56. Organic dielectric layer 58 silicon-containing hard mask and anti-reflective layer

60. Patterned photoresist 62 MTJ

64. First inclined side wall 66 second inclined side wall

68. Capping layer 72 MTJ

76. Upper electrode of lower electrode 78

80. Protective layer 82 groove

84 BARC 86 patterned mask

88. Opening 90 contact hole

92. Ultra low k dielectric 94 metal interconnect

Detailed Description

Referring to fig. 1 to 9, fig. 1 to 9 are schematic views illustrating a method for fabricating a semiconductor device, or more specifically an MRAM cell, according to an embodiment of the invention. As shown in fig. 1-7, a substrate 12, such as a substrate 12 of semiconductor material selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide (silicon carbide), gallium arsenide (gallium arsenate), etc., is provided, and a magnetic tunnel junction (magnetic tunneling junction, MTJ) region 14 and a logic region 16 are preferably defined on the substrate 12.

Substrate 12 may include active (active) devices such as metal-oxide semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric layer (interlayer dielectric, ILD) 18 overlying the active devices. More specifically, the substrate 12 may include a planar or non-planar (e.g., fin structure transistor) MOS transistor device, wherein the MOS transistor may include a gate structure (e.g., metal gate) and a transistor device such as a source/drain region, a spacer, an epitaxial layer, a contact hole etch stop layer, and the like, the interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 18 may have a plurality of contact plugs electrically connected to the gate and/or source/drain regions of the MOS transistor. Because the related manufacturing processes of planar or non-planar transistors and inter-layer dielectric layers are well known in the art, the description thereof is omitted herein.

Then, the metal interconnect structures 20 and 22 are formed on the interlayer dielectric 18 of the MTJ region 14 and the logic region 16 in sequence to electrically connect the contact plugs, wherein the metal interconnect structure 20 includes an inter-metal dielectric 24 and metal interconnects 26 embedded in the inter-metal dielectric 24, and the metal interconnect structure 22 includes a stop layer 28, an inter-metal dielectric 30 and a plurality of metal interconnects 32 embedded in the stop layer 28 and the inter-metal dielectric 30.

In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and each metal interconnect 32 in the metal interconnect structure 22 disposed in the MTJ region 14 preferably includes a via conductor. In addition, each of the metal interconnects 26, 32 in each of the metal interconnect structures 20, 22 may be embedded in the inter-metal dielectric layer 24, 30 and/or the stop layer 28 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each of the metal interconnects 26, 32 may comprise a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, coWP), and the like, but is not limited thereto. Since single damascene or dual damascene fabrication processes are well known in the art, additional description is omitted herein. Furthermore, in this example, the metal layer 36 preferably comprises copper, the intermetal dielectric layers 24, 30 preferably comprise silicon oxide, and the stop layer 28 comprises a nitrogen doped carbide layer (nitrogen doped carbide, NDC), silicon nitride, or silicon carbide nitride (silicon carbon nitride, siCN), but is not limited thereto.

An MTJ stack structure 38 is then formed over the metal interconnect structure 22, a cap layer 40 over the MTJ stack structure 38, and another cap layer 42 over the cap layer 40. In this embodiment, the MTJ stack structure 38 is formed by sequentially forming a first electrode layer 44, a fixed layer 46, a barrier layer 48, a free layer 50 and a second electrode layer 52. In the present embodiment, the first electrode layer 44 and the second electrode layer 52 preferably comprise conductive materials, such as but not limited to tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al). The pinned layer 46 may be made of an Antiferromagnetic (AFM) material, such as ferro-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the magnetic moment direction of the adjacent layers. The barrier layer 48 may be composed of an insulating material including oxide, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but is not limited thereto. The free layer 50 may be made of a ferromagnetic material, such as iron, cobalt, nickel, or alloys thereof, for example, cobalt-iron-boron (CoFeB), but is not limited thereto. Wherein the magnetization direction of the free layer 50 is "free" to change by an external magnetic field. The capping layer 40 and the capping layer 42 preferably comprise different materials, for example, the capping layer 40 of the present embodiment preferably comprises silicon nitride and the capping layer 42 preferably comprises silicon oxide, but is not limited thereto.

A patterned mask 54 is then formed over capping layer 42. In this embodiment, the patterned mask 54 may include an organic dielectric layer (organic dielectric layer, ODL) 56, a silicon-containing hard mask and anti-reflective (SHB) layer 58, and a patterned photoresist 60.

As shown in fig. 2, one or more etching processes are then performed using the patterned mask 54 as a mask to remove portions of the cap layers 40, 42, portions of the MTJ stack structure 38, and portions of the inter-metal dielectric layer 30 to form the MTJ 62, 72 in the MTJ region 14, wherein the first electrode layer 44 is preferably the lower electrode 76 of the MTJ 62, 72 at this stage, the second electrode layer 52 is preferably the upper electrode 78 of the MTJ 62, 72, and the cap layers 40, 42 may be removed together during the etching process. It should be noted that the present embodiment may first perform a reactive ion etching (reactive ion etching, RIE) process using the patterned mask 54 to remove a portion of the capping layers 40, 42 and a portion of the MTJ stack structure 38, then remove the patterned mask 54, and then use the patterned capping layer 42 as a mask to remove a portion of the MTJ stack structure 38 and a portion of the inter-metal dielectric layer 30 to form the MTJ 62, 72. Due to the nature of the ion beam etching process, the top surface of the remaining intermetal dielectric layer 30 is preferably slightly lower than the top surface of the interconnect 32 and the top surface of the intermetal dielectric layer 30 preferably exhibits an arcuate or curved shape.

It should be noted that, in this embodiment, when removing a portion of the intermetal dielectric layer 30 by using the ion beam etching process, a portion of the metal interconnect 32 is preferably removed together, so that the first inclined sidewall 64 and the second inclined sidewall 66 are formed at the interface of the metal interconnect 32 near the MTJs 62 and 72.

Then, as shown in FIG. 3, a cap layer 68 is formed over the MTJs 62, 72 and covers the surface of the IMD layer 30. In this embodiment, capping layer 68 preferably comprises silicon nitride, but may comprise other dielectric materials, such as silicon oxide, silicon oxynitride, or silicon carbide nitride, depending on the processing requirements.

As shown in fig. 4, a protective layer 80 is then formed on the cap layer 68, wherein the top of the protective layer 80 disposed directly above the MTJs 62, 72 is preferably slightly higher than the top of the protective layer 80 between the MTJs 62, 72. In this embodiment, the protective layer 80 may include, but is not limited to, tetraethoxysilane (Tetraethyl orthosilicate, TEOS), silicon oxide, silicon nitride, or a combination thereof, for example.

Subsequently, as shown in FIG. 5, a portion of the protective layer 80 is removed to form a recess 82 between the MTJs 62, 72. In detail, the present stage preferably utilizes etching to remove portions of the protective layer 80 without forming any patterned mask, such that a recess 82 is formed between the MTJ 62 and the MTJ 72 or directly above the metal interconnect 26 of the logic region 16, wherein the bottom of the recess 82 is preferably above the bottom of the MTJ 62, 72 and below the top of the upper electrode 78.

Next, as shown in fig. 6, an anti-reflective layer, such as a bottom anti-reflective coating (BARC) 84, is formed on the passivation layer 80 and fills the recess 82, and then a patterned mask 86, such as a patterned photoresist, is formed on the BARC 84, wherein the patterned mask 86 includes an opening 88 exposing a portion of the surface of the BARC 84 in the logic region 16.

As shown in fig. 7, a patterned mask 86 is then used to mask away portions of BARC 84, portions of protective layer 80, portions of cap layer 68, and even portions of inter-metal dielectric layer 30 to form a contact hole 90 directly over metal interconnect 26 in logic region 16. It should be noted that, although the bottom of the contact hole 90 is slightly lower than the bottom of the covering layer 68 in the present embodiment, but not limited thereto, the bottom of the contact hole 90 may be optionally aligned with the bottom of the covering layer 68 according to an embodiment of the present invention, and the variation is also included in the scope of the present invention.

Subsequently, as shown in FIG. 8, the patterned mask 86 and the BARC 84 are sequentially removed, and an ultra low k dielectric layer 92 is formed on the passivation layer 80 and fills the contact hole 92. In this embodiment, the ultralow dielectric constant dielectric layer 92 may comprise a porous dielectric material such as, but not limited to, silicon oxycarbide (silicon oxycarbide, siOC). A planarization process, such as a chemical mechanical polishing (chemical mechanical polishing, CMP) process, is then performed to remove a portion of the low-k dielectric layer 92 so that the top of the capping layer 68 of the MTJ region 14 is aligned with the top of the low-k dielectric layer 92 of the logic region 16.

As shown in fig. 9, one or more photolithography and etching processes are then performed to remove portions of the ultra-low k dielectric layer 92 and portions of the inter-metal dielectric layer 30 in the logic region 16 to form another contact hole (not shown) exposing the underlying metal interconnect 26. Conductive material is then filled into the contact holes and a planarization process, such as CMP, is performed to form metal interconnects 94 that connect to underlying metal interconnects 26.

As with the metal interconnect 26 formed as described above, the metal interconnect 94 disposed between the MTJs 62, 72 or the logic region 16 may be embedded within the inter-metal dielectric layer according to a single damascene process or a dual damascene process. For example, the metal interconnect 90 may further comprise a barrier layer (not shown) selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and a metal layer (not shown) selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, coWP), and the like. Since single damascene or dual damascene fabrication processes are well known in the art, additional description is omitted herein. Thus, the manufacture of the semiconductor device according to the embodiment of the invention is completed.

Referring to fig. 9 again, fig. 9 also discloses a structure of a semiconductor device according to an embodiment of the invention. As shown in fig. 9, the semiconductor device mainly includes an inter-metal dielectric layer 24 disposed on a substrate 12, an inter-metal dielectric layer 26 disposed in the inter-metal dielectric layers of the MTJ region 14 and the logic region 16, an inter-metal dielectric layer 30 disposed on the inter-metal dielectric layer 24, an inter-metal interconnect 32 disposed in the inter-metal dielectric layer 30 and connected to the underlying inter-metal interconnect 26, MTJs 62 and 72 disposed on the inter-metal interconnect 32, upper electrodes 78 disposed on the MTJs 62 and 72, respectively, a capping layer 68 disposed on the MTJs 62 and 72, a protection layer 80 surrounding the MTJs 62 and 72, an inter-metal interconnect 94 disposed between the MTJs 62 and 72, and an ultra-low dielectric constant dielectric layer 92 disposed between the protection layer 80 and the inter-metal interconnect 94.

In this embodiment, one sidewall of metal interconnect 94, such as the right sidewall, preferably contacts cap layer 68 while the other sidewall of metal interconnect 94, such as the left sidewall, does not contact cap layer 68. More specifically, the right side wall of the metal interconnect 94 preferably contacts the passivation layer 80, the capping layer 68 and the inter-metal dielectric layer 30 at the same time, while the left side wall contacts only the ultra-low k dielectric layer 92 and the inter-metal dielectric layer 30 but does not contact any capping layer 68. The top of cap layer 68 is preferably cut Ji Chao to the top of low k dielectric layer 92 and to the top of metal interconnect 94.

In general, in the current process of fabricating MRAM devices, especially when forming logic region metal interconnects or contact plugs, the metal interconnects often have a line width that is too large to be accurately connected to the underlying interconnects due to misalignment. To improve this problem, the present invention preferably interconnects the lower interconnect with the metal interconnect 94 of a desired size or line width in a segmented fashion when preparing the logic region or metal interconnect between the two MTJs 62, 72 as in the previous embodiment. In addition, it should be noted that, in fig. 8 to 9, when the portion of the ultralow dielectric constant dielectric layer 92 is removed by photolithography and etching, a patterned photomask may be disposed on the protection layer 80 and simultaneously a portion of the ultralow dielectric constant dielectric layer 92 and a portion of the protection layer 80 are exposed, and then the size of the metal interconnect is defined by using the selection ratio between the ultralow dielectric constant dielectric layer 92 and the protection layer 80, so that the interconnect structure aligned to the underlying interconnect can be manufactured more accurately.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a first magnetic tunneling junction (magnetic tunneling junction, MTJ) and a second magnetic tunneling junction on a substrate;

forming a first upper electrode on the first magnetic tunneling junction and a second upper electrode on the second magnetic tunneling junction;

forming a capping layer over the first magnetic tunnel junction and the second magnetic tunnel junction;

forming a protective layer on the covering layer;

removing part of the protection layer to form a groove between the first magnetic tunneling junction and the second magnetic tunneling junction;

forming an anti-reflection layer on the protection layer and filling the groove; and

removing the anti-reflection layer, the protection layer and the cover layer to form a first contact hole, wherein the anti-reflection layer comprises a bottom anti-reflective coating (BARC),

wherein the substrate includes a magnetic tunnel junction region and a logic region, the method further comprising:

forming an inter-metal dielectric layer on the substrate;

forming a first metal interconnect and a second metal interconnect in the magnetic tunnel junction region and a third metal interconnect in the logic region;

forming the first magnetic tunneling junction on the first metal interconnection and the second magnetic tunneling junction on the second metal interconnection;

forming the cover layer on the first magnetic tunneling junction and the second magnetic tunneling junction;

forming the protective layer on the covering layer;

forming the bottom anti-reflection layer on the protection layer;

removing the bottom anti-reflection layer, the protection layer and the covering layer to form the first contact hole right above the third metal interconnection line;

removing the bottom anti-reflection layer;

forming an ultralow dielectric constant dielectric layer on the protective layer;

removing the ultra-low dielectric constant dielectric layer to form a second contact hole exposing the third metal interconnect; and

forming a fourth metal interconnect in the second contact hole.

2. The method of claim 1, further comprising:

planarizing the ultra-low k dielectric layer prior to forming the second contact hole such that the top of the capping layer of the magnetic tunnel junction region is aligned with the top of the ultra-low k dielectric layer of the logic region; and

forming the fourth metal interconnect.

3. The method of claim 1, wherein one sidewall of the fourth metal interconnect contacts the ultra-low k dielectric layer and another sidewall of the fourth metal interconnect contacts the protective layer and the capping layer.

4. The method of claim 1, wherein one sidewall of the fourth metal interconnect contacts the cap layer and the other sidewall of the fourth metal interconnect does not contact the cap layer.

5. A semiconductor device, comprising:

a first magnetic tunneling junction (magnetic tunneling junction, MTJ) and a second magnetic tunneling junction disposed on the substrate;

the first upper electrode is arranged on the first magnetic tunneling junction, and the second upper electrode is arranged on the second magnetic tunneling junction;

the shielding layer is arranged on the first magnetic tunneling junction and the second magnetic tunneling junction;

a protective layer surrounding the first magnetic tunneling junction and the second magnetic tunneling junction;

the first metal interconnection line is arranged between the first magnetic tunneling junction and the second magnetic tunneling junction, wherein one side wall of the first metal interconnection line is contacted with the covering layer, and the other side wall of the first metal interconnection line is not contacted with the covering layer; and

an ultra-low dielectric constant dielectric layer disposed between the passivation layer and the first metal interconnect,

wherein the substrate includes a magnetic tunnel junction region and a logic region, and the semiconductor device further includes:

an inter-metal dielectric layer disposed on the substrate;

the second metal interconnection line and the third metal interconnection line are arranged in the magnetic tunneling junction region and the fourth metal interconnection line is arranged in the logic region, wherein the fourth metal interconnection line is arranged right below the first metal interconnection line, and the first metal interconnection line is connected with the fourth metal interconnection line.

6. The semiconductor device of claim 5, wherein one sidewall of the first metal interconnect contacts the cap layer and the protective layer and the other sidewall of the first metal interconnect contacts the ultra-low k dielectric layer.

7. The semiconductor device of claim 5, wherein the top of the cap layer is level with the top of the ultra low k dielectric layer.

8. The semiconductor device of claim 5, wherein the top of the capping layer is level with the top of the ultra-low k dielectric layer and the top of the first metal interconnect.