JP2005197328A - Non-volatile storage device, semiconductor integrated circuit device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile memory at a low cost in which the manufacturing process of a CMOS process is not changed normally and completely, and which is not affected by the thickness of a gate oxide film. <P>SOLUTION: A bipolar transistor structure uses a first conductivity type impurity diffusion layer as a collector electrode, a second conductivity type well as a base electrode, and a first conductivity type impurity diffusion layer as the second as an emitter electrode. In the bipolar transistor structure, a base-emitter junction is forward-biassed under the state in which a backward bias is applied between a collector and a base, and an information is stored by trapping minority carriers injected in a base region in an insulating film in an element isolation in the vicinity of a collector electrode. Accordingly, since a conventional floating gate is not used as a charge storage region in the non-volatile memory cell, data-retention characteristics are not affected completely by the thickness of the gate oxide film. It is because the non-volatile memory at the low cost can be loaded even on a transistor used as the non-volatile memory cell such as one having a gate length of 50 nm by a 65 nm technique and a gate oxide-film thickness of 1.2 nm without changing its manufacturing process even in any technical generation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having an electrically erasable and writable nonvolatile memory element, and can be manufactured without adding a new process to a normal complementary MIS transistor (hereinafter referred to as a CMOS transistor). The present invention relates to a nonvolatile memory device that can be written with low voltage and ultra-low power consumption.

  A flash EEPROM (hereinafter referred to as a flash memory) is provided as a non-volatile storage device capable of electrically erasing data to be stored collectively in a predetermined unit and electrically writing data. In flash memory, memory cells are composed of electrically erasable and writable nonvolatile memory elements. Data and programs once written in the memory cells are erased, and new data and programs are rewritten in the memory cells. (Programming) is possible.

  Therefore, when this flash memory or a macro computer with built-in flash memory is incorporated into an application system, if data changes, program bug corrections, or program updates are required, they are stored in the flash memory. Since data and programs can be changed on the application system, the development period of the application system can be shortened, and flexibility in program development of the application system can be obtained.

  On the other hand, in recent years, the application fields of IC (Integrated Circuits) cards are expanding dramatically, and in particular, an authentication method called a radio tag or RFID (Radio Frequency Identification) is used instead of a conventional barcode reading method. I'm starting. In an RFID system, a high frequency of about 10 MHz to 3 GHz transmitted from a reader device is received by an RFID chip existing within a range of several mm to 1 m, and a DC voltage is received from the high frequency received by an antenna provided in the chip. To generate and operate the internal circuit. The RFID chip stores authentication data in a non-volatile memory. This data is modulated into an RF signal, transmitted, and received by the reader device to authenticate the RFID chip. A nonvolatile memory mounted on an RFID chip has two major requirements. The first is ultra-low cost, which is inevitable because the market price of RFID chips is 50 yen or less. The second is to operate with ultra-low power consumption. This requirement is because the RFID chip receives high frequency and the power that can be generated inside the chip is extremely small. In addition to the non-volatile memory, it is necessary to simultaneously operate a logic circuit, a transmission circuit, etc. Because there is.

  After completing the present invention, the present inventors conducted a survey of known examples from the following viewpoints.

  The viewpoint of the investigation is a nonvolatile memory transistor that can be manufactured without adding a new process to the manufacturing process of the CMOS transistor, and is a viewpoint that does not have a special floating gate for storing information.

  As a result, Patent Literatures 1 to 3 and Non-Patent Literature 1 were discovered.

  US Pat. No. 5,408,115   US Pat. No. 5,969,383   JP 2001-156188 A   Fukuda et al., “New Nonvolatile Memory With Charge-Tapping Sidewall”, IEEE Electron Device Letters, Vol. 24, no. 8, July 2003, pp490-492

As a first problem, the memory cell structure is complicated in a vertically stacked memory cell of a floating gate and a control gate, that is, a stacked gate type memory cell, which has been generally used in NOR flash memory products. It has been clarified by the present inventors that there is a problem that the manufacturing cost is increased due to the fact that In particular, in an RFID chip whose market is rapidly expanding in recent years, adopting a stacked gate type memory cell as a nonvolatile memory leads to an increase in manufacturing cost. According to the study of the present inventor, this is considered to be caused by an increase in the following photomask and manufacturing process. That is, since the tunnel oxide film of the flash memory is thicker than the gate oxide film of the logic circuit transistor or the DRAM cell transistor, the mask for forming the tunnel oxide film, the polysilicon film for the floating gate of the flash memory, Addition / processing mask, mask for processing word line of flash memory, mask for impurity implantation for forming drain region of flash memory, and low-concentration N type source / drain of high breakdown voltage transistor constituting write / erase circuit An impurity implantation mask for forming the region and the low-concentration P-type source / drain region is required, and the number of masks to be added is at least six. For this reason, it is difficult in terms of cost to provide an RFID chip equipped with a nonvolatile memory using stacked gate type memory cells. In order to solve this problem, a non-volatile memory transistor that can be manufactured without adding a new process to the CMOS transistor manufacturing process may be employed, and a structure that does not have a special floating gate for storing information. do it.

  According to the results of investigation and examination of the prior art by the present inventors, the following points have been clarified. First, U.S. Pat. No. 5,408,115 and U.S. Pat. No. 5,969,383 disclose splitting using side spacers, as shown in FIG. There is disclosed a memory cell system in which a gate is provided, a side spacer is composed of an oxide film / silicon nitride film / oxide film (Oxide Nitride Oxide, hereinafter referred to as ONO), and charges are accumulated in the ONO film. In the conventional first memory cell, as shown in FIG. 23, a select gate 143 is arranged via a gate oxide film 142 on the surface of a substrate 141, and a lower oxide film 145, silicon nitride is formed around the select gate 143. After the film 146 and the upper oxide film 147 are stacked, a side spacer-shaped control gate 148 is disposed. Since the source 144 of the conventional first memory cell is formed immediately after the processing of the select gate 143 and the drain 149 is formed after the processing of the control gate 148, only the control gate 148 on the drain 149 side is used as the gate electrode. Function.

  In this conventional write operation to the first memory cell, 5V is applied to the drain 149, 1V is applied to the select gate 143, and 10V is applied to the control gate 148 to turn on the channel, and the electrons 150 traveling from the source 144 are selected. Accelerates into hot electrons in a strong horizontal electric field generated in the channel region below the boundary between the gate 143 and the control gate 148, penetrates through the lower oxide film 145, and is injected into the silicon nitride film 147 for trapping. Is done. This operation is generally called a source-side injection (SSI) method because the hot electron injection position is not near the drain. The threshold voltage measured from the control gate 148 is raised by the electrons 151 trapped in the silicon nitride film 147 to obtain a written state.

  In the first conventional memory cell, it is necessary to add a manufacturing process for forming a side spacer having an ONO structure and a control gate 148, and a circuit for controlling an operating voltage 10V necessary for writing. Therefore, there is a second problem that a large process is required to be added to a normal CMOS transistor manufacturing process. As a result, an increase in manufacturing cost is inevitable.

  In addition, the conventional electrically writable second nonvolatile memory cell disclosed in Japanese Patent Application Laid-Open No. 2001-156188 has a gate oxide film 162 on the surface of the substrate 161 as shown in a sectional structure in FIG. The gate 163 is disposed through the gate electrode 163. After the lower oxide film 164, the silicon nitride film 165, and the upper oxide film 166 are stacked on the periphery of the gate 163, the side spacer-shaped side gate 167 and the low concentration source / drain 168 are formed. , The drain 170 and the source 171 are arranged, the gate 163 and the side gate 167 are connected by a salicide film 172, and a silicide film 172 is also formed on the source 171 and the drain 170 outside the oxide film side spacer 169. Has been.

  In the conventional second memory cell, an appropriate voltage is applied to the gate 163 and the drain 170 to turn on the transistor, and hot electrons 174 generated near the drain 170 are injected into the silicon nitride film 165. Write by trapping. By performing a write operation with the source and drain switched, hot electrons 173 can be injected and trapped into the silicon nitride film 165 on the source 171 side, so that 2-bit information can be stored in one cell.

  Also in the first conventional memory cell, it is necessary to change the manufacturing process of a normal CMOS transistor in order to form the side spacer and the side gate 167 having the ONO structure, and as a result, an increase in manufacturing cost is inevitable.

Furthermore, “New Nonvolatile Memory With Charge-Traping Sidewall” by Fukuda et al., IEEE Electron Device Letters, Vol. 24, no. 8, July 2003, pp 490-492, an electrically writable third conventional nonvolatile memory cell has a film thickness of 7 on the surface of a P-type substrate 181 as shown in a cross-sectional structure in FIG. A gate 183 having a length of 0.4 μm is disposed through a gate oxide film 182 having a thickness of .6 nm, a lower oxide film 184 having a thickness of 4.5 nm is formed around the gate 183, and then a silicon nitride film having a thickness of 20 nm is formed. 185 and an upper oxide film 186 having a film thickness of 50 nm are formed in a side spacer shape, and a source 187 and a drain 188 are disposed on the substrate surface immediately below the silicon nitride film 185.
In addition, another feature of the memory cell by Fukuda et al. Is the deterioration of data retention characteristics due to the thinning of the gate oxide film, which has been a problem in the past, because it uses nonvolatile memory by injecting charges into the sidewall. It is to be able to avoid this problem. On the other hand, since channel hot electron injection is used, in a cell formed without changing the normal CMOS process, write / erase characteristics are desired.

  In writing to the conventional third memory cell, a channel hot electron 189 generated in the vicinity of the drain 188 is applied by applying a programming voltage of 4.3 V to the gate 183 and the drain 188 for a programming time of 1 ms, Implanting into the silicon nitride film 185 is performed. The read operation is performed by applying a positive voltage of 1.2 V to the source 187 side and determining the threshold voltage of the memory cell. Under the above write conditions, a change in threshold voltage of about 1V is obtained.

In the conventional third memory cell, the gates corresponding to the control gate 148 and the side gate 167, which are necessary for the conventional first and second memory cells, are unnecessary. However, in order to form an electric field distribution in the direction in which the channel hot electrons 189 are injected into the silicon nitride film 185, the lower oxide film 184 is made thinner than the gate oxide film 182 to increase the fringe electric field strength. There is a need. Further, the fringe electric field strength is very sensitively influenced by the junction position of the drain 188 immediately below the silicon nitride film 185 having a width of 20 nm. Accordingly, in order to obtain stable and uniform writing characteristics, the ion implantation amount for forming the drain 188 and the subsequent formation conditions such as heat treatment are optimized, and the length of the side spacer-like upper oxide film 186 is precise. Control is necessary. Therefore, the manufacturing process peculiar to the above-mentioned conventional third memory cell is unlikely to match the manufacturing process of the existing CMOS transistor as it is, and it is necessary to change the manufacturing conditions. As a result, the performance of the existing CMOS transistor is changed. Reaches a third problem of degradation or fluctuations.

  An object of the present invention is to provide a non-volatile memory that does not use a floating gate without changing the manufacturing process of a normal CMOS transistor.

  Another object of the present invention is to provide a highly reliable non-volatile memory without changing the manufacturing process of a normal CMOS transistor.

  Another object of the present invention is to provide a semiconductor device equipped with an inexpensive non-volatile memory without adding a completely new process to a normal logic circuit process, analog circuit process, or general-purpose DRAM process.

  Another object of the present invention is to provide a technique for using a non-volatile memory cell formed without changing the manufacturing process of a normal CMOS transistor as a memory module, an analog circuit relief circuit, or a trimming circuit. It is in.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] The first point of view is that the first conductivity type impurity diffusion layer is a collector electrode, the second conductivity type well is a base electrode, and the second first conductivity type impurity diffusion layer is an emitter electrode. In the transistor structure, with the reverse bias applied between the collector and base, the base-emitter junction is forward-biased and minority carriers injected into the base region are injected into the insulating film near the collector electrode, for example, into the floating gate. Writing is performed by trapping, so-called substrate hot electron injection, and it operates as a nonvolatile memory cell without changing the transistor structure by appropriately setting the reverse bias condition of the collector and the forward bias condition of the emitter. It is intended to be made.

[2] A second aspect proposes a nonvolatile memory cell structure that does not use a floating gate insulated from a substrate region through a thin oxide film of 10 nm or less.

[3] A third aspect is a non-volatile memory cell having a floating gate insulated from a substrate region through a thin oxide film of 10 nm or less, and a structure in which the edge portion of the floating gate is not disposed on the thin oxide film This is a proposal.

[4] A fourth aspect is that a non-volatile memory having a floating gate insulated from a substrate region through a thick oxide film of 12 nm or more uses a hot carrier injection method for writing to and erasing the memory. is there.

[5] A fifth aspect considers a storage circuit for RFID chip authentication information and a storage circuit for relief information as applications of the semiconductor integrated circuit device. At this time, the semiconductor device includes a repair target circuit and a repair circuit that replaces the repair target circuit on a semiconductor substrate, and the semiconductor integrated circuit device specifies a repair circuit to be replaced by the repair circuit. Used as an information storage circuit.

  The circuit to be relieved may be a memory cell array with a built-in DRAM, and the circuit to be relieved may be a memory cell array of a DRAM with a built-in microcomputer. The circuit to be relieved may be a memory cell array of a microcomputer built-in SRAM.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a bipolar transistor structure having a first conductivity type impurity diffusion layer as a collector electrode, a second conductivity type well as a base electrode, and a second first conductivity type impurity diffusion layer as an emitter electrode, A so-called substrate hot electron that forward biases the base-emitter junction with a reverse bias applied between them and injects and traps minority carriers injected into the base region into the insulating film near the collector electrode or into the floating gate. Writing is performed by implantation, and by appropriately setting the reverse bias condition of the collector and the forward bias condition of the emitter, it is possible to operate as a nonvolatile memory cell without changing the transistor structure. A non-volatile memory can be provided.

  The charge trap region is in the insulating film in the element isolation, and may be an oxide film, a nitride film, or a laminated film thereof. Therefore, in the nonvolatile memory cell of the present invention, since the conventional floating gate is not used as the charge storage region, the data retention characteristic is not affected at all by the gate oxide film thickness. This is because the transistor used as the nonvolatile memory cell of the present invention may be of any technology generation. For example, a transistor having a gate length of 50 nm and gate oxide film thickness of 1.2 nm by 65 nm technology is inexpensive without changing the manufacturing process. A non-volatile memory can be installed.

  FIG. 1 shows an example of a cross-sectional structure of a memory cell for explaining the best mode for implementing a nonvolatile memory included in a semiconductor device according to the present invention. In the figure, an element isolation 4 and a silicon nitride film 41 that also functions as a charge trap layer disposed in the element isolation, and P-type wells 201 and 202 are disposed in the surface region of a P-type silicon substrate 1. An element isolation 400 that functions as a non-volatile memory element, a gate 6, a low concentration N-type diffusion layer 7, a low concentration P-type diffusion layer 8, and a source or collector on the surface region of the substrate 1 where the wells 201 and 202 are not formed. An N-type diffusion layer 701 functioning as a drain, a collector, an N-type diffusion layer 702 functioning as an emitter, and a P-type diffusion layer 80 functioning as a base or substrate electrode. In the initial state, the element isolation 400 formed in the P-type silicon substrate region 1 grounds the gate electrode 6 and the source electrode 701 and applies 3 V to the drain electrode 702 so that the source electrode 701 and the drain electrode 702 are separated. Is conducted. This is because the element isolation 400 is formed on a low impurity concentration P-type silicon substrate, so that the isolation capability is weak, and the parasitic MOS transistor formed by the adjacent N-type diffusion layer regions 701 and 702 is in the ON state. Because.

  In FIG. 1 and FIG. 2, writing to the nonvolatile memory included in the semiconductor device according to the present invention is performed by applying a forward bias voltage of about −1 V (Ve) to the N-type diffusion layer 703 serving as the emitter electrode. A ground potential (Vb) is applied to the P-type diffusion layer 80 serving as the base electrode, approximately 3 V (Vc) is applied to the N-type diffusion layers 701 and 702 serving as the collector electrodes, and a positive voltage is applied to the gate electrode 6. This is performed by applying a high voltage of about 20 V (Vg). According to the voltage condition, electrons which are minority carriers are injected from the emitter electrode 703 into the P-type wells 202 and 201 forming the base region and the P-type silicon substrate region 1 and serve as a collector. A voltage Vc = 3V applied to the layers 701 and 702 is drawn and flows. When the potential Vg applied to the gate 6 is sufficiently high, some of the injected electrons become hot electrons, are accelerated in the P-type silicon substrate, and travel toward the gate 6. A part of the hot electrons is injected into the element isolation 400 and trapped by the silicon nitride film 41 in the element isolation 400. As a result of modulating the interface state between the lower portion of the element isolation 400 and the P-type silicon substrate 1 by trapped electrons, the resistance is increased, and when reading is performed by applying, for example, 3 V to the drain, the writing state is reduced as the drain current decreases. Is confirmed.

  In FIGS. 1 and 3, erasing the nonvolatile memory included in the semiconductor device according to the present invention is performed by applying about 7 V to the N-type diffusion layer 701 serving as the source electrode, and applying a negative high voltage to the gate electrode 6. This is done by applying -20V. According to the voltage condition, in the N-type diffusion layer region forming the source electrode 701, hot holes generated by band-to-band tunneling or avalanche phenomenon are attracted by the electric field due to the voltage applied to the gate electrode 6, and a part thereof is drawn. It is injected into the element isolation 400 and trapped by the silicon nitride film 41 in the element isolation 400. As a result of modulating the interface state between the lower part of the device isolation 400 and the P-type silicon substrate 1 by the trapped holes, the resistance is lowered, and if, for example, 3V is applied to the drain, the erase state is increased as the drain current increases. Is confirmed. Here, as the structure of the N-type diffusion layer 701 for forming the source electrode, in addition to a structure in which a normal high-concentration N-type diffusion layer is surrounded by a low-concentration N-type diffusion layer, a junction where band-to-band tunneling or avalanche phenomenon is likely to occur. Erase operation by adopting a structure, for example, a structure having only the high-concentration N-type diffusion layer without the low-concentration N-type diffusion layer 7 or surrounding the high-concentration N-type diffusion layer with the low-concentration P-type diffusion layer Can improve the efficiency.

  FIG. 4 shows an outline of a planar structure of the nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 2 and an N-type well 3 are disposed in a desired region, a P-channel transistor constituting an emitter selection gate 62 is disposed in the N-type well region, and an emitter line (EL) The emitter selection gate 63 (ESG) is connected to the local emitter line 112, and the local emitter line 112 is connected to the emitter electrode 703. An N-channel transistor constituting a selection gate 61 is disposed in the P-type well 2, and a bit line (BL) is connected to the drain region 702 through the selection gate 61. A memory gate 63 is disposed on the element isolation disposed in the P-type silicon substrate region sandwiched between the drain region 702 and the source region 701 formed in the P-type silicon substrate region 1. A source line (SL) is connected to the source region 701. Between the adjacent memory elements, electrons injected from the emitter electrode at the time of writing flow to the adjacent memory elements and the N-type well 3 or the N-type diffusion layer 70 is arranged so as not to cause erroneous writing, and a ground potential is applied at the time of writing. This serves to prevent electrons from flowing to adjacent elements.

  FIG. 5 shows operating voltage conditions of the nonvolatile memory cell of the present invention shown in FIGS. First, when performing a write operation (Program), 3 V is applied to all the bit lines (BL), 3 V is applied to all the select gates (SG), and they are connected to the emitters of the elements to be written. Common to all the memory gates (MG) of all elements by applying -1V to the emitter line (EL) and applying -3V to the emitter selection gate (ESG) for selecting the local emitter line connected to the element to be written. A high voltage of 20 V is applied, and 3 V is applied in common to the source lines (SL) of all elements. Under this operating condition, a writing operation is performed by applying a potential of −1 V for injecting electrons only to the emitter of the element to be written and injecting substrate hot electrons.

  In the erase operation (Erase), all bit lines (BL), all selection gates (SG), all emitter lines (EL), all emitter selection gates (ESG) are grounded, and all memory gates (MG). A negative high voltage of −20V is applied to the source line, and a positive high voltage of 7V is applied to all the source lines (SL). Under these operating conditions, holes are injected into all elements at once and an erasing operation is performed.

  In the read operation (Read), 3 V is applied to the selected bit line (BL), 3 V is applied to the selected selection gate (SG), all the emitter lines (EL) are grounded, and all the emitters are connected. The selection gate (ESG) is grounded, all the memory gates (MG) are grounded or opened, and all the source lines (SL) are grounded. Due to this operating condition, the element in which writing is performed has a high element resistance, and the element in the erased state or the initial state has a low element resistance. Information can be read out.

  According to these operating conditions, in all operating states, a high voltage is only applied to the gate at a time, so that a transistor that handles the high voltage is not required on the chip, for example, applied directly to the gate from the outside of the chip. It is possible to perform such an operation. Further, according to the structure of the nonvolatile memory cell of the present invention, since all the gate electrodes are disposed on the isolation oxide film, it is possible to apply a high voltage regardless of the thickness of the gate insulating film.

<Metal gate element separation type non-volatile memory>
FIG. 6 shows a cross-sectional structure of a metal gate element isolation type nonvolatile memory cell included in the semiconductor device according to the present invention. This is a variant of the best mode. In the figure, an element isolation 4 and a silicon nitride film 41 that also functions as a charge trap layer disposed in the element isolation, and P-type wells 201 and 202 are disposed in the surface region of a P-type silicon substrate 1. An element isolation 400 that functions as a nonvolatile memory element in the surface region of the substrate 1 where the wells 201 and 202 are not formed, a metal plug and a first metal wiring layer 11 in the contact hole 10 that forms a gate, and a low concentration N-type diffusion Layer 7, low-concentration P-type diffusion layer 8, N-type diffusion layer 701 functioning as a source or collector, N-type diffusion layer 702 functioning as a drain or collector, N-type diffusion layer 703 functioning as an emitter, base or substrate A P-type diffusion layer 80 that functions as an electrode is provided. In the initial state, the element isolation 400 formed in the P-type silicon substrate region 1 is configured such that the gate electrodes 10 and 11 and the source electrode 701 are grounded, and 3 V is applied to the drain electrode 702 so that the source electrode 701 and the drain electrode 702 702 conducts. This is because the element isolation 400 is formed on a low impurity concentration P-type silicon substrate, so that the isolation capability is weak, and the parasitic MOS transistor formed by the adjacent N-type diffusion layer regions 701 and 702 is in the ON state. Because. By using the first metal wiring 11 having the contact hole 10 as the gate electrode, the element isolation oxide film is thinned by etching the oxide film of the element isolation 400 when the contact hole 10 is formed. As a result, the absolute value of the voltage applied to the gate electrode during writing and erasing operations can be reduced. The operating conditions of the non-volatile memory cell of this metal gate element isolation type are the same as those shown in FIG.

<< Element Isolation Nonvolatile Memory with Deep N-type Well >>
FIG. 7 shows a cross-sectional structure of an element isolation type nonvolatile memory cell having a deep N-type well included in the semiconductor device according to the present invention. This is a variant of the best mode. In the figure, there are an element isolation 4 on the surface region of a P-type silicon substrate 1, a silicon nitride film 41 that also functions as a charge trap layer disposed in the element isolation, a deep N-type well 31, and P-type wells 201 and 202. An element isolation 400 that functions as a nonvolatile memory element, a gate 6, a low concentration N-type diffusion layer 7, and a low concentration P-type diffusion layer 8 are disposed on the surface region of the substrate 1 where the P-type wells 201 and 202 are not formed. N-type diffusion layer 701 functioning as a source or collector, N-type diffusion layer 702 functioning as a drain or collector, N-type diffusion layer 703 functioning as an emitter, and P-type diffusion layer 80 functioning as a base or substrate electrode Is provided. In the initial state of the element isolation 400 formed in the P-type silicon substrate region 1, the gate 6 and the source electrode 701 are grounded, and 3 V is applied to the drain electrode 702 so that the source electrode 701 and the drain electrode 702 can be connected to each other. Conduct. This is because the element isolation 400 is formed on a low impurity concentration P-type silicon substrate, so that the isolation capability is weak, and the parasitic MOS transistor formed by the adjacent N-type diffusion layer regions 701 and 702 is in the ON state. Because. By disposing the deep N-type well 31, it is possible to prevent electrons injected from the emitter at the time of writing from flowing into other than the memory cell to be written. The operating conditions of the element-isolated nonvolatile memory cell having the deep N-type well are the same as those shown in FIG. Further, a structure using a contact hole and a first metal wiring as a gate may be applied to this structure.

<Channel hot electron writing element separation type non-volatile memory>
FIG. 8 shows a cross-sectional structure of a channel hot electron writing element isolation type nonvolatile memory cell included in the semiconductor device according to the present invention. This is a variant of the best mode. In the figure, an element isolation 4, a silicon nitride film 41 that also functions as a charge trap layer disposed in the element isolation, and a P-type well 2 are disposed on the surface region of the P-type silicon substrate 1. An element isolation 400 that functions as a nonvolatile memory element, a gate 6, a low-concentration N-type diffusion layer 7, an N-type diffusion layer 701 that functions as a source, and an N that functions as a drain, on the surface region of the substrate 1 where no substrate is formed. A mold diffusion layer 702 is provided. In the initial state, the element isolation 400 formed in the P-type silicon substrate region 1 grounds the gate electrode 6 and the source electrode 701 and applies 3 V to the drain electrode 702 so that the source electrode 701 and the drain electrode 702 are separated. Is conducted. This is because the element isolation 400 is formed on a low impurity concentration P-type silicon substrate, so that the isolation capability is weak, and the parasitic MOS transistor formed by the adjacent N-type diffusion layer regions 701 and 702 is in the ON state. Because.

  8 and 9, when writing to the channel hot electron writing element separation type non-volatile memory of the semiconductor device according to the present invention, a positive high voltage of about 7 V is applied to the N type diffusion layer 702 serving as the drain electrode ( Vd), a ground potential (Vs) is applied to the N-type diffusion layer 701 serving as the source electrode, and a positive high voltage of about 20 V (Vg) is applied to the gate electrode 6. According to the voltage condition, electrons flow from the source electrode 701 to the drain electrode 702. When the potential Vg applied to the gate 6 is sufficiently high, some of the injected electrons become hot electrons, are accelerated in the P-type silicon substrate, and travel toward the gate 6. A part of the hot electrons is injected into the element isolation 400 and trapped by the silicon nitride film 41 in the element isolation 400. As a result of modulating the interface state between the lower portion of the element isolation 400 and the P-type silicon substrate 1 by trapped electrons, the resistance is increased, and when reading is performed by applying, for example, 3 V to the drain, the writing state is reduced as the drain current decreases. Is confirmed.

  In erasing the channel hot electron writing element separation type non-volatile memory of the semiconductor device according to the present invention, about 7 V is applied to the N-type diffusion layer 701 serving as the source electrode, and a negative high voltage of about 7 V is applied to the gate electrode 6. This is done by applying -20V. According to the voltage condition, in the N-type diffusion layer region forming the source electrode 701, hot holes generated by band-to-band tunneling or avalanche phenomenon are attracted by the electric field due to the voltage applied to the gate electrode 6, and a part thereof is drawn. It is injected into the element isolation 400 and trapped by the silicon nitride film 41 in the element isolation 400. As a result of modulating the interface state between the lower part of the device isolation 400 and the P-type silicon substrate 1 by the trapped holes, the resistance is lowered, and if, for example, 3V is applied to the drain, the erase state is increased as the drain current increases. Is confirmed. Here, as the structure of the N-type diffusion layer 701 for forming the source electrode, in addition to a structure in which a normal high-concentration N-type diffusion layer is surrounded by a low-concentration N-type diffusion layer, a junction where band-to-band tunneling or avalanche phenomenon is likely to occur. Erase operation by adopting a structure, for example, a structure having only the high-concentration N-type diffusion layer without the low-concentration N-type diffusion layer 7 or surrounding the high-concentration N-type diffusion layer with the low-concentration P-type diffusion layer Can improve the efficiency.

  FIG. 10 shows an outline of a planar structure of the channel hot electron writing element isolation type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 2 is arranged in a desired region, an N-channel transistor constituting a selection gate 61 is arranged in the P-type well 2, and a bit line (BL) 110 is connected via the selection gate 61. To the drain region 702. A memory gate 63 is disposed on the element isolation disposed in the P-type silicon substrate region sandwiched between the drain region 702 and the source region 701 formed in the P-type silicon substrate region 1. A source line (SL) 131 is connected to the source region 701.

  FIG. 11 shows operating voltage conditions of the channel hot electron writing element separation type non-volatile memory cell shown in FIGS. First, when performing a write operation (Program), 7V is applied to the bit line (BL) connected to the cell to be written, 7V is applied to the selection gate (SG) for washing the cell to be written, A high voltage of 20 V is applied commonly to the memory gates (MG) of all elements, and a ground potential is applied commonly to the source lines (SL) of all elements. Under this operating condition, a write operation is performed by applying a write potential of 7 V only to the drain of the element to be written and injecting channel hot electrons.

  In the erase operation (Erase), all the bit lines (BL) and all the selection gates (SG) are grounded, a negative high voltage of −20 V is applied to all the memory gates (MG), and all the source lines (SL) ) Is applied with a positive high voltage of 7V. Under these operating conditions, holes are injected into all elements at once and an erasing operation is performed.

    In the read operation (Read), 3V is applied to the selected bit line (BL), 3V is applied to the selected selection gate (SG), and all the memory gates (MG) are grounded or opened. Source line (SL) is grounded. Due to this operating condition, the element in which writing is performed has a high element resistance, and the element in the erased state or the initial state has a low element resistance. Information can be read out.

  FIG. 12 shows a cross-sectional structure of the semiconductor device according to the present invention using the metal plug in the contact hole 10 and the first metal wiring 11 as the gate electrode of the channel hot electron writing element isolation type nonvolatile memory cell. It is. In the figure, an element isolation 4, a silicon nitride film 41 that also functions as a charge trap layer disposed in the element isolation, and a P-type well 2 are disposed on the surface region of the P-type silicon substrate 1. Element isolation 400 functioning as a non-volatile memory element in the surface region of the substrate 1 where no substrate is formed, the metal plug and first metal wiring 11 in the contact hole 10 used as the gate electrode, the low-concentration N-type diffusion layer 7, and , An N-type diffusion layer 701 functioning as a source and an N-type diffusion layer 702 functioning as a drain are provided. In the initial state, the element isolation 400 formed in the P-type silicon substrate region 1 grounds the gate electrode 6 and the source electrode 701 and applies 3 V to the drain electrode 702 so that the source electrode 701 and the drain electrode 702 are separated. Is conducted. This is because the element isolation 400 is formed on a low impurity concentration P-type silicon substrate, so that the isolation capability is weak, and the parasitic MOS transistor formed by the adjacent N-type diffusion layer regions 701 and 702 is in the ON state. Because. By using the first metal wiring 11 having the contact hole 10 as the gate electrode, the element isolation oxide film is thinned by etching the oxide film of the element isolation 400 when the contact hole 10 is formed. As a result, the absolute value of the voltage applied to the gate electrode during writing and erasing operations can be reduced. The operating conditions of the non-volatile memory cell of this metal gate element isolation type are the same as those shown in FIG.

<Gate edgeless nonvolatile memory>
FIG. 13 shows a cross-sectional structure of a gate edgeless nonvolatile memory cell included in a semiconductor device according to the present invention. This is a variant of the best mode. In the figure, an element isolation 4, P-type wells 201, 202, 203 and N-type wells 3, 301, 302 are arranged in the surface region of a P-type silicon substrate 1, and a floating gate 64 and N functioning as a source or collector. Type diffusion layer 701 and N type well 301, N type diffusion layer 702 and N type well 302 functioning as a drain or collector, N type diffusion layer 703 functioning as an emitter, P type diffusion layer 80 functioning as a base or substrate electrode, An N-type diffusion layer 704 functioning as a control gate and an N-type well 3 are provided. All the edge portions of the floating gate 64 are disposed on the thick isolation oxide film 4. With this structure, it is possible to avoid deterioration of reliability due to leakage from the gate edge portion. The N-channel MOS transistor used in this cell has a structure in which N-type diffusion layers 701 and 702 for forming a source and a drain are surrounded by N-type wells 301 and 302 in order not to place a gate edge on the active region. By adopting this structure, the source and drain regions beyond the element isolation can be formed, and the gate edge can be arranged on the element isolation region.

  13 and 14, the writing to the gate edgeless nonvolatile memory included in the semiconductor device according to the present invention is performed by applying a forward bias voltage of about −1 V to the N-type diffusion layer 703 serving as the emitter electrode (Ve). ), A ground potential (Vb) is applied to the P-type diffusion layer 80 serving as the base electrode, about 3 V (Vc) is applied to the N-type diffusion layers 701 and 702 serving as the collector electrodes, and the control gate This is performed by applying a positive high voltage of about 10 V (Vcg) to the electrode 704. According to the voltage condition, electrons which are minority carriers are injected from the emitter electrode 703 into the P-type wells 202 and 201 forming the base region and the P-type silicon substrate region 1 and serve as a collector. A voltage Vc = 3V applied to the layers 701 and 702 is drawn and flows. When the potential Vcg applied to the control gate 704 is sufficiently high, some of the injected electrons become hot electrons and are accelerated in the P-type well region 203 and injected into the floating gate 64. As a result of modulating the state of the channel region under the floating gate 64 by the electrons injected into the floating gate, the resistance is increased, and if reading is performed by applying, for example, 3 V to the drain and the control gate, writing is performed as a decrease in drain current. The status is confirmed.

    13 and FIG. 15, the gate edgeless nonvolatile memory included in the semiconductor device according to the present invention is erased by applying approximately 10 V to the N-type diffusion layer 701 serving as the source electrode, the emitter electrode 703, the drain This is performed by applying a ground potential to the electrode 702, the base electrode 80, and the control gate electrode 704. According to the above voltage condition, electrons in the floating gate 64 form an N-type region where the source electrode is formed due to a Fowler-Nordheim (FN) tunnel phenomenon between the N-type region where the source electrodes 701 and 301 are formed and the floating gate 64. Pulled away. As a result, the state of the channel region under the floating gate 64 is modulated. As a result, the resistance is lowered. When reading is performed by applying, for example, 3 V to the drain and the control gate, the erased state is confirmed as an increase in drain current.

  FIG. 16 shows an outline of a planar structure of a gate edgeless nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 2 and an N-type well 3 are arranged in a desired region, and a P-channel type transistor constituting an emitter selection gate 62 is arranged in the N-type well region 3, and an emitter line (EL) 110. Is connected to the local emitter line 112 through the emitter selection gate 63 (ESG), and the local emitter line 112 is connected to the emitter electrode 703. An N-channel transistor constituting the selection gate 61 is disposed in the P-type well 2, and the bit line (BL) 111 is connected to the drain regions 702 and 302 via the selection gate 61. A floating gate 64 is disposed on an active region sandwiched between the drain region 702 and the source regions 701 and 301. The floating gate 64 extends to cover the active region 42 in the N-type well that functions as a control gate. A source line (SL) 131 is connected to the source regions 701 and 301. Between the adjacent memory elements, electrons injected from the emitter electrode at the time of writing flow to the adjacent memory elements and the N-type well 3 or the N-type diffusion layer 70 is arranged so as not to cause erroneous writing, and a ground potential is applied at the time of writing. This serves to prevent electrons from flowing to adjacent elements.

  FIG. 17 shows operating voltage conditions of the gate edgeless nonvolatile memory cell of the present invention shown in FIGS. First, when performing a write operation (Program), 3 V is applied to all the bit lines (BL), 3 V is applied to all the select gates (SG), and they are connected to the emitters of the elements to be written. Common to the control gates (CG) of all elements by applying -1V to the emitter line (EL), applying -3V to the emitter selection gate (ESG) for selecting the local emitter line connected to the element to be written. A high voltage of 10 V is applied, and 3 V is applied in common to the source lines (SL) of all elements. Under this operating condition, a writing operation is performed by applying a potential of −1 V for injecting electrons only to the emitter of the element to be written and injecting substrate hot electrons.

  In the erase operation (Erase), all bit lines (BL), all select gates (SG), all emitter lines (EL), all emitter select gates (ESG), all control gates (CG) are grounded. A positive high voltage of 10 V is applied to all the source lines (SL). Under these operating conditions, electrons are collectively extracted from the floating gates of all elements by the FN tunnel, and an erasing operation is performed.

    In the read operation (Read), 3 V is applied to the selected bit line (BL), 3 V is applied to the selected selection gate (SG), all the emitter lines (EL) are grounded, and all the emitters are connected. The selection gate (ESG) is grounded, 3V is applied to the selected control gate (CG), and all the source lines (SL) are grounded. Due to this operating condition, the element in which writing is performed has a high element resistance, and the element in the erased state or the initial state has a low element resistance. Information can be read out.

《Thick gate oxide nonvolatile memory》
FIG. 18 shows a cross-sectional structure of a thick gate oxide film type nonvolatile memory cell included in the semiconductor device according to the present invention. This is a variant of the best mode. In the figure, an element isolation 4, a P-type well 2 and an N-type well 3 are arranged in a surface region of a P-type silicon substrate 1, a floating gate 64, an N-type diffusion layer 701 functioning as a source or collector, a drain or collector An N-type diffusion layer 702 that functions as an emitter, an N-type diffusion layer 703 that functions as an emitter, a P-type diffusion layer 80 that functions as a base or substrate electrode, an N-type diffusion layer 704 that functions as a control gate, and an N-type well 3. ing.

  18 and 19, writing into the thick gate oxide nonvolatile memory included in the semiconductor device according to the present invention is performed by applying a forward bias voltage of about −1 V to the N-type diffusion layer 703 serving as the emitter electrode. (Ve) is applied, a ground potential (Vb) is applied to the P-type diffusion layer 80 serving as the base electrode, and about 3 V (Vc) is applied to the N-type diffusion layers 701 and 702 serving as the collector electrodes, This is performed by applying a positive high voltage of about 10 V (Vcg) to the N-type diffusion layer 704 to be the control gate electrode. According to the voltage condition, electrons as minority carriers are injected from the emitter electrode 703 into the P-type well 2 forming the base region, and the voltage Vc applied to the N-type diffusion layers 701 and 702 acting as collectors. = It draws into 3V and flows. When the potential Vcg applied to the control gate 704 is sufficiently high, some of the injected electrons become hot electrons and are injected into the floating gate 64. As a result of modulating the interface state under the floating gate by electrons injected into the floating gate 64, the resistance is increased, and when reading is performed by applying, for example, 3V to the drain, the writing state is confirmed as a decrease in drain current. .

  18 and 20, the erase to the thick gate oxide nonvolatile memory included in the semiconductor device according to the present invention is performed by applying about 10 V to the N-type diffusion layer 701 serving as the source electrode, The N-type diffusion layer 703 to be grounded or opened, the N-type diffusion layer 702 to be the drain electrode is grounded or opened, the P-type diffusion layer 80 to be the base electrode is grounded, and the N-type diffusion layer 702 to be the control gate electrode This is done by grounding the diffusion layer 704. According to the voltage condition, a part of hot holes generated by the band-band tunneling phenomenon or the avalanche phenomenon in the N-type diffusion layer region forming the source electrode 701 is injected into the floating gate electrode 64. As a result of modulating the interface state between the lower part of the floating gate electrode 64 and the P-type well 2 by the holes injected into the floating gate electrode 64, the resistance is lowered, and for example 3V is applied to the drain and 3V to the control gate. When reading is performed, the erased state is confirmed as an increase in drain current. Here, as the structure of the N-type diffusion layer 701 for forming the source electrode, in addition to a structure in which a normal high-concentration N-type diffusion layer is surrounded by a low-concentration N-type diffusion layer, a junction where band-to-band tunneling or avalanche phenomenon is likely to occur. By eliminating the structure, for example, without the low-concentration N-type diffusion layer 7, the high-concentration N-type diffusion layer is formed only by the high-concentration N-type diffusion layer or by surrounding the high-concentration N-type diffusion layer with the low-concentration P-type diffusion layer 8 The operation efficiency can be increased.

  FIG. 21 shows an outline of a planar structure of the thick gate oxide film type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 2 and an N-type well 3 are disposed in a desired region, a P-channel transistor constituting an emitter selection gate 62 is disposed in the N-type well region, and an emitter line (EL) 110 is The emitter selection gate 63 (ESG) is connected to a local emitter line 112, and the local emitter line 112 is connected to an emitter electrode 703. An N-channel transistor constituting the selection gate 61 is disposed in the P-type well 2, and the bit line (BL) 111 is connected to the drain region via the selection gate 61. A floating gate 64 and a source region are disposed in series with the drain region. A source line (SL) 131 is connected to the source region. Between the adjacent memory elements, electrons injected from the emitter electrode at the time of writing flow to the adjacent memory elements and the N-type well 3 or the N-type diffusion layer 70 is arranged so as not to cause erroneous writing, and a ground potential is applied at the time of writing. This serves to prevent electrons from flowing to adjacent elements.

    FIG. 22 shows operating voltage conditions of the thick gate oxide nonvolatile memory cell of the present invention shown in FIGS. First, when performing a write operation (Program), 3 V is applied to all the bit lines (BL), 3 V is applied to all the select gates (SG), and they are connected to the emitters of the elements to be written. A voltage of -1 V is applied to the emitter line (EL), a voltage of -3 V is applied to the emitter selection gate (ESG) for selecting a local emitter line connected to the element to be written, and a high voltage is applied to the selected control gate (CG). 10 V is applied, and 3 V is applied in common to the source lines (SL) of all elements. Under this operating condition, a writing operation is performed by applying a potential of −1 V for injecting electrons only to the emitter of the element to be written and injecting substrate hot electrons.

    In the erase operation (Erase), all bit lines (BL), all select gates (SG), all emitter lines (EL), all emitter select gates (ESG), and all control gates (CG) are grounded. A positive high voltage of 10 V is applied to all the source lines (SL). Under these operating conditions, holes are injected into all elements at once and an erasing operation is performed.

    In the read operation (Read), 3 V is applied to the selected bit line (BL), 3 V is applied to the selected selection gate (SG), all the emitter lines (EL) are grounded, and all the emitters are connected. The selection gate (ESG) is grounded, 3V is applied to the selected control gate (CG), and all the source lines (SL) are grounded. Due to this operating condition, the element in which writing is performed has a high element resistance, and the element in the erased state or the initial state has a low element resistance. Information can be read out. By this operation, it becomes possible to perform writing and erasing operations at a relatively low voltage with respect to a nonvolatile memory element having a thick gate oxide film of 12 nm or more.

<< Channel hot electron writing thick film gate oxide nonvolatile memory >>
FIG. 23 shows a cross-sectional structure of a channel hot electron write thick gate oxide film type nonvolatile memory cell included in the semiconductor device according to the present invention. This is a variant of the best mode. In the figure, an element isolation 4, a P-type well 2, and an N-type well 3 are arranged in a surface region of a P-type silicon substrate 1, and a floating gate 64, an N-type diffusion layer 701 that functions as a source, and an N that functions as a drain. A type diffusion layer 702, an N type diffusion layer 704 functioning as a control gate, and an N type well 3 are provided.

  23 and 24, the channel hot electron writing thick film gate oxide nonvolatile memory included in the semiconductor device according to the present invention is written to the N-type diffusion layer 702 serving as the drain electrode by a positive high voltage, about 10 V is applied (Vd), a ground potential (Vs) is applied to the N-type diffusion layer 701 serving as the source electrode, and a positive high voltage of about 10 V is applied to the N-type diffusion layer 704 serving as the control gate electrode (Vcg). ) Apply by applying. According to the voltage condition, electrons flow from the source electrode 701 toward the drain region. When the potential Vcg applied to the control gate 704 is sufficiently high, some of the injected electrons become hot electrons and are injected into the floating gate 64. As a result of modulating the interface state under the floating gate by the electrons injected into the floating gate 64, the resistance is increased, and when reading is performed by applying, for example, 3 V to the drain and the control gate, the writing state is reduced as the drain current decreases. It is confirmed.

  FIG. 25 shows an outline of a planar structure of a channel hot electron writing thick gate oxide film type nonvolatile memory cell circuit included in the semiconductor device according to the present invention shown in FIG. In the figure, a P-type well 2 and an N-type well 3 are arranged in a desired region, an N-channel type transistor constituting a selection gate 61 is arranged in the P-type well 2, and the bit line (BL) 111 is It is connected to the drain region via the selection gate 61. A floating gate 64 and a source region are disposed in series with the drain region. A source line (SL) 131 is connected to the source region.

  FIG. 26 shows operating voltage conditions of the channel hot electron writing thick film gate oxide nonvolatile memory cell of the present invention shown in FIGS. First, when performing a write operation (Program), 10 V is applied to a selected bit line (BL), 10 V is applied to a selection gate (SG) for selecting an element to be written, and the element to be written is written. A voltage of 10 V is applied to the control gate connected to the control gate, and an installation potential is applied to the source lines (SL) of all elements. Under these operating conditions, channel hot electrons are injected only into the element to be written, so that the write operation is performed. The erase operation and read operation are the same as those of the previous thick gate oxide film type nonvolatile memory cell.

  Note that although a semiconductor device using an N-channel transistor as a memory element has been described in this embodiment, similar characteristics can be obtained even in a memory element using a P-channel transistor.

  Since the nonvolatile memory included in the semiconductor device according to the present invention is a method in which programming / erasing is performed by injecting substrate hot carriers into an insulating film near the source of a transistor, a normal logic circuit process or a general-purpose DRAM process is used. An inexpensive semiconductor device equipped with a non-volatile memory can be provided without adding a completely new process. In addition, since the nonvolatile memory included in the semiconductor device according to the present invention does not use a floating gate for storing electric charge, it does not require a tunnel insulating film that is essential in a conventional nonvolatile memory, and even in a fine CMOS process. It can be easily formed. The non-volatile memory of the present invention is a low-cost microcomputer (one dollar) that stores trimming data of color gradation that is performed after mounting a liquid crystal display driver (LCD) built-in microcomputer on a liquid crystal panel substrate, and that is installed in a home appliance. Trimming data of the oscillation frequency of the internal oscillator (called a microcomputer), trimming data of the internal resistance and circuit constants of the microcomputer equipped with the analog circuit, storage of SRAM relief information in a high performance microcomputer equipped with a large capacity SRAM, Ideal for non-contact IC cards, especially for storing ID information in low-priced RFID, etc., and mounting on semiconductor devices that require low-capacity, low-power consumption, low-cost non-volatile memory to enhance its market competitiveness Has a significant effect.

It is explanatory drawing which shows roughly the cross-sectional structure of the memory cell explaining the best form for implementing the non-volatile memory which the semiconductor device which concerns on this invention has. FIG. 2 is an explanatory diagram schematically showing a write operation of a nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 1. FIG. 2 is an explanatory diagram schematically showing an erase operation of a nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 1. FIG. 4 is an explanatory view illustrating the planar structure of the nonvolatile memory cell of the present invention shown in FIGS. 1 to 3; FIG. 5 is an explanatory diagram illustrating operating voltage conditions of the nonvolatile memory cell of the present invention shown in FIGS. 1 to 4; It is explanatory drawing which shows roughly the cross-section of the metal gate element isolation | separation type non-volatile memory cell which the semiconductor device concerning this invention has. It is explanatory drawing which shows roughly the cross-section of the element isolation | separation type non-volatile memory cell which has a deep N type well which the semiconductor device concerning this invention has. It is explanatory drawing which shows roughly the cross-section of the channel hot electron write element isolation | separation type non-volatile memory cell which the semiconductor device concerning this invention has. FIG. 9 is an explanatory diagram schematically showing a write operation of the channel hot electron write element separated nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 8. FIG. 10 is an explanatory view illustrating the planar structure of the channel hot electron writing element isolation type nonvolatile memory cell of the present invention shown in FIGS. 8 to 9. It is explanatory drawing which illustrates the operating voltage conditions of the channel hot electron write element isolation | separation type non-volatile memory cell of this invention shown by FIGS. 8-10. FIG. 9 is an explanatory diagram schematically showing a cross-sectional structure of a modified example in which the gate electrode of the channel hot electron writing element-separated nonvolatile memory cell shown in FIG. 8 is formed by a contact hole and a first metal wiring. It is explanatory drawing which shows roughly the cross-sectional structure of the gate edge type non-volatile memory cell which the semiconductor device concerning this invention has. FIG. 14 is an explanatory diagram schematically showing a write operation of the gate edgeless nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 13; FIG. 14 is an explanatory diagram schematically showing an erasing operation of the gate edgeless nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 13; FIG. 16 is an explanatory view illustrating the planar structure of the gate edgeless nonvolatile memory cell of the present invention shown in FIGS. 13 to 15; FIG. 17 is an explanatory diagram illustrating operating voltage conditions of the gate edgeless nonvolatile memory cell of the present invention shown in FIGS. 13 to 16; It is explanatory drawing which shows roughly the cross-section of the thick film gate oxide film type non-volatile memory cell which the semiconductor device concerning this invention has. FIG. 19 is an explanatory diagram schematically showing a write operation of the thick gate oxide nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 18. FIG. 19 is an explanatory diagram schematically showing an erase operation of the thick gate oxide nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 18. It is explanatory drawing which illustrates the planar structure of the thick film gate oxide film type non-volatile memory cell of this invention shown by FIGS. It is explanatory drawing which illustrates the operating voltage conditions of the thick film gate oxide type non-volatile memory cell of this invention shown by FIGS. 18-21. It is explanatory drawing which shows roughly the cross-sectional structure of the channel hot electron write thick film gate oxide type non-volatile memory cell which the semiconductor device concerning this invention has. FIG. 24 is an explanatory diagram schematically showing a write operation of the channel hot electron write thick gate oxide nonvolatile memory included in the semiconductor device according to the present invention shown in FIG. 23; FIG. 25 is an explanatory view illustrating the planar structure of the channel hot electron writing thick film gate oxide nonvolatile memory cell of the present invention shown in FIGS. 23 to 24; It is explanatory drawing which illustrates the operating voltage conditions of the channel hot electron writing thick film gate oxide type non-volatile memory cell of this invention shown by FIGS. 23-25. It is sectional drawing for demonstrating the 1st prior art which concerns on this invention. It is sectional drawing for demonstrating the 2nd prior art which concerns on this invention. It is sectional drawing for demonstrating the 3rd prior art which concerns on this invention.

Explanation of symbols

1-P-type silicon substrate 2, 201, 202, 203-P-type well 3, 301, 302-N-type well 4, 400-element isolation 5-gate oxide film 6-gate electrode 7-low-concentration N-type diffusion layer 8 -Low concentration P-type diffusion layer 9-Side spacer 10-Contact hole 11-First metal wiring 12-Via hole 13-Second metal wiring 31-Deep N-type well 41-Silicon nitride film 42 in isolation-Active region 61-Selection Gate 62-Emitter selection gate 63-Memory gate 64-Floating gate 70-N type diffusion layer 71-Dark N type diffusion layer 80-P type diffusion layer 81-Dark P type diffusion layer 110-Bit line 111-Emitter line 112- Local emitter line 130 -word (memory gate) line 131 -source line 701 -source (collector) N-type diffusion layer 702 -drain (collector) N Diffusion layer 703-Emitter N type diffusion layer 704-Control gate N type diffusion layer BL-Bit line SG-Selection gate EL-Emitter line ESG-Emitter selection gate MG-Memory gate SL-Source line CG-Control gate Unit Cell-Unit Memory cell area

Claims (15)

  A second conductivity type first impurity diffusion layer functioning as a source and a second conductivity type second impurity diffusion layer functioning as a drain; and the first and second conductivity types in a first conductivity type semiconductor substrate. In a storage transistor having an element isolation sandwiched between impurity diffusion layers, having a conductive layer functioning as a gate on the element isolation region, and using the element isolation lower surface interface as a channel, in an insulating film in the element isolation A nonvolatile memory device, wherein information is written or erased by injecting a charge into the memory.   A second conductivity type first impurity diffusion layer functioning as a source or a first collector and a second conductivity type second impurity diffusion functioning as a drain or a second collector in a first conductivity type semiconductor substrate A first conductivity type fourth impurity diffusion layer functioning as a part of a base, a second conductivity type third impurity diffusion layer functioning as an emitter, and the first and second impurities In a memory transistor having element isolation sandwiched between diffusion layers, having a conductive layer forming a gate electrode on the element isolation region, and using the element isolation lower surface interface as a channel, the second conductivity type third A first potential for biasing the impurity diffusion layer and the first conductivity type semiconductor substrate in a forward direction is applied to the third impurity diffusion layer of the second conductivity type, and the first and second conductivity type Second impure A second potential that reversely biases the diffusion layer is applied to the first and second impurity diffusion layers of the second conductivity type, and the first conductivity type of the second conductivity type is applied from the third impurity diffusion layer of the second conductivity type. Information is written by injecting minority carriers into the semiconductor substrate and injecting the minority carriers into the insulating film in the element isolation by applying a third potential opposite to the minority carriers to the gate. 2. The nonvolatile memory device according to claim 1, wherein erasing is performed.   In a first conductivity type semiconductor substrate, a second conductivity type first well functioning as a source, a second conductivity type first impurity diffusion layer formed in the first well, and a drain A second well of the second conductivity type that functions, a second impurity diffusion layer of the second conductivity type formed in the second well, and a third well of the second conductivity type that functions as a control gate A third impurity diffusion layer of the second conductivity type formed in the third well, and a first conductivity type fourth of the first conductivity type forming a channel region sandwiched between the first well and the second well. In the memory element having the conductive layer for forming the floating gate so as to cover the well, the element isolation region, the channel region and the control gate region, the outer periphery of the floating gate is all disposed on the element isolation region. The Nonvolatile memory device according to symptoms.   A first conductivity type first well functioning as a source or a first collector and a second conductivity type first impurity diffusion formed in the first well in the first conductivity type semiconductor substrate. A second conductivity type second well that functions as a drain or a second collector, a second conductivity type second impurity diffusion layer formed in the second well, and a control gate A second well of the second conductivity type, a third impurity diffusion layer of the second conductivity type formed in the third well, and a channel region sandwiched between the first well and the second well A fourth well of the first conductivity type that forms the second conductivity, a fourth impurity diffusion layer of the second conductivity type that functions as an emitter, and a fifth impurity diffusion layer of the first conductivity type that functions as a part of the base Channel region and control gate region A non-volatile memory device having a conductive layer forming a floating gate as described above, wherein the outer peripheral portion of the floating gate is entirely disposed on the element isolation region. A first potential for forward biasing is applied to the second conductivity type fourth impurity diffusion layer, and a second potential for reverse biasing the second conductivity type first and second wells functioning as the collector is Applying to the first and second wells of the second conductivity type, the minority carriers are injected from the fourth impurity diffusion layer of the second conductivity type into the semiconductor substrate of the first conductivity type. Information is written or erased by injecting the minority carriers into the floating gate by applying a polar third potential to the control gate. The device according to claim 3, wherein the performing.   A first conductivity type first well; a second conductivity type first impurity diffusion layer functioning as a source formed in the first well; and the first conductivity type semiconductor substrate. A second impurity diffusion layer of a second conductivity type functioning as a drain formed in one well, a second well of a second conductivity type functioning as a control gate, and formed in the second well. In the memory element having the third impurity diffusion layer of the second conductivity type and the conductive layer forming the floating gate, the gate oxide film formed under the floating gate has a thickness of 12 nm or more. A non-volatile memory device, wherein writing and erasing are performed by hot carrier injection.   A first conductivity type first well and a second conductivity type first impurity diffusion functioning as a source or a first collector formed in the first well in the first conductivity type semiconductor substrate. A second conductivity type second impurity diffusion layer functioning as a drain or a second collector formed in the first well, and a second conductivity type second well functioning as a control gate, A second conductivity type third impurity diffusion layer formed in the second well, and a second conductivity type fourth impurity diffusion layer functioning as an emitter formed in the first well; In the memory element having the first conductivity type fifth impurity diffusion layer functioning as a part of the base formed in the first well and the conductive layer forming the floating gate, a shape is formed below the floating gate. A second conductivity type that has a gate oxide film thickness of 12 nm or more and that applies a first potential for forward biasing to the fourth impurity diffusion layer of the second conductivity type that functions as the emitter, and functions as the collector A second potential that reversely biases the first and second impurity diffusion layers is applied to the first and second impurity diffusion layers of the second conductivity type, and the fourth impurity diffusion of the second conductivity type is applied. Injecting minority carriers from a layer into the first conductivity type semiconductor substrate, and injecting the minority carriers into the floating gate by applying a third potential opposite to the minority carriers to the control gate, 6. The nonvolatile memory device according to claim 5, wherein information is written or erased.   The semiconductor integrated circuit device includes a circuit to be repaired and a repair circuit that replaces the circuit to be repaired, and the nonvolatile memory device is a memory circuit for repair information that specifies a circuit to be repaired to be replaced by the repair circuit. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   8. The semiconductor device according to claim 7, further comprising a fuse program circuit for storing relief information according to a blown state of the fuse element as another relief information storage circuit for the circuit to be repaired. .   9. The semiconductor device according to claim 7, wherein the circuit to be relieved is a memory cell array with a built-in DRAM.   9. The semiconductor device according to claim 7, wherein the circuit to be relieved is a memory cell array of a microcomputer built-in DRAM.   9. The semiconductor device according to claim 7, wherein the circuit to be relieved is a memory cell array of a microcomputer built-in SRAM.   The semiconductor integrated circuit device includes an analog circuit and a constant trimming circuit for adjusting the circuit constant, and the nonvolatile memory circuit is an information storage circuit for specifying the circuit constant of the constant trimming circuit. The semiconductor device according to claim 1, wherein:   The semiconductor integrated circuit device includes an oscillation circuit and a frequency trimming circuit for adjusting the oscillation frequency, and the nonvolatile memory circuit is an information storage circuit for specifying the oscillation frequency of the frequency trimming circuit. The semiconductor device according to claim 1, wherein:   The semiconductor integrated circuit device includes a reference voltage generation circuit and a voltage trimming circuit that adjusts the generated reference voltage, and the nonvolatile memory circuit stores information for specifying the reference voltage of the voltage trimming circuit. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a memory circuit.   The semiconductor integrated circuit device includes a security circuit for specifying a chip, and the nonvolatile memory circuit is an information storage circuit for specifying a chip of the security circuit. 6. The semiconductor device according to 6.

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