JP2007157183A - Nonvolatile storage device and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost nonvolatile memory which can be manufactured without changing the manufacturing steps of a standard C-MOS process, and which is not affected by a gate oxide film thickness. <P>SOLUTION: A nonvolatile storage device includes a pair of series circuits of load transistors T11, T21 and storage transistors T12, T22, which are connected in the static latch form to constitute a flip-flop, and transfer gates T13, T23 are connected between input/output parts P1, P2 of this flip-flop and bit lines BLT, BLB. Further, C-MOS inverters INV1, INV2 which are buffer circuits are connected to two input/output parts P1, P2 of the flip-flop. Also, leak current interruption elements T16, T26 are arranged between sources of two load transistors T11, T21 of the flip-flop and a power source line VCC to interrupt the T16, T26 at the time of writing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electrically erasable and writable nonvolatile memory device and a semiconductor integrated circuit device including the same.

  For example, the need for redundancy (redundancy) due to the increase in the capacity of the built-in SRAM, the need for individual tuning after board mounting such as an LCD driver, personal identification information (ID code, decryption key, IC card) The need for low-cost fuses is increasing along with the expansion of various applications.

  Conventionally, as fuse elements that can be formed by a standard C-MOS process, there are ones in which a polysilicon or a wiring metal layer is blown by a laser or current, an insulation gate film or the like is destroyed by voltage, and the like. However, such a fusing or dielectric breakdown can be programmed only once and is not suitable for the above-mentioned use.

  On the other hand, if a floating gate type non-volatile element that can be formed by a C-MOS process is used, an electrically erasable and programmable fuse can be realized. Introducing special processes such as flash memory is not worth the cost. Further, the floating gate type element in the standard C-MOS process has a problem that the data retention characteristic is deteriorated when the insulating film is thinned with high integration.

Therefore, for example, Patent Document 1 and Patent Document 2 show a nonvolatile memory device that can be manufactured by a standard C-MOS process and a nonvolatile memory device that does not have a special floating gate.
US Pat. No. 6,518,614 JP 2004-56095 A

  In order to eliminate the instability of the data retention characteristics of a nonvolatile semiconductor memory device manufactured by such a C-MOS process, a pair of series circuits of a load transistor and a storage transistor (nonvolatile element) are provided as in an S-RAM. It is effective to provide a flip-flop by providing them and connecting them in a static latch configuration.

  On the other hand, the drain side junction with respect to the well has an LDD structure having a low concentration region with a low impurity concentration, and the source side junction with respect to the well has a structure in which the low concentration region is not formed. Although it is a transistor formed by a MOS process, it can be made non-volatile.

  However, when an LDD structure in which a series circuit of a first conductivity type load transistor and a second conductivity type memory transistor is cross-coupled and the memory transistor has the offset is employed, the memory transistor will be described later. There arises a problem that an unnecessary leak current flows at the time of writing / erasing.

Here, the problem of the leakage current will be described with reference to FIG.
This nonvolatile memory has a pair of series circuits of load transistors T11, T21 and storage transistors T12, T22, which are connected in a static latch configuration. The memory transistors T12 and T22 are N-type MOS transistors configured in a P-type well WP on a semiconductor substrate. The load transistors T11 and T21 are P-type MOS transistors configured in an N-type well WN on a semiconductor substrate. Transfer gates T13 and T23 are connected between the input / output portion of the flip-flop and the two bit lines BLT and BLB, respectively.

  Now, when writing to the storage transistor T12, for example, if the bit line BLT is set to 0V, BLB is set to 6V, and the transfer gates T13 and T23 are turned on, the power supply voltage VCC is lower than the high voltage supplied from the bit line BLB. Therefore, not only the write current CP1 flows from the storage transistor T12 → the transfer gate T13 → the bit line BLT but also the leak current CP2 flows through the path of the bit line BLB → transfer gate T23 → load transistor T21 → VCC.

  As a result, a sufficient voltage cannot be supplied to the desired writing transistor T12, and a high-voltage leak path exists in addition to the transistor T12 that performs writing, and an unnecessary current supply is required. turn into.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a nonvolatile memory device and a semiconductor integrated circuit device having the nonvolatile memory device which solves the problems of the nonvolatile memory formed by the standard C-MOS process and the problem at the time of writing to the memory transistor. There is.

A typical configuration of the present invention is as follows.
(1) A semiconductor transistor of the second conductivity type is formed by a standard C-MOS process to reduce the absolute value of the negative potential applied to the gate electrode when erasing the storage transistor (for low voltage operation). The substrate is provided with a first conductivity type deep well and a second conductivity type well in the deep well. The nonvolatile memory has a pair of series circuits of a load transistor and a storage transistor, which are statically connected. The memory transistor has a first conductivity type source / drain in a second conductivity type well, and has a gate insulation on the channel between the source and drain. It has a gate electrode through the film, has an insulating film side spacer on the side of the gate electrode, and has a junction with the second conductivity type well on the drain side. A LDD structure having a low low density regions pure object density, a structure in which the junction to the second conductivity type well of the source side is not formed low concentration regions LDD structure portion (non LDD structure).

  The driving circuit for driving the nonvolatile memory applies a positive voltage to the gate electrode and the source with respect to the drain of the storage transistor, injects channel hot electrons into the insulating film side spacer, writes information, On the other hand, a negative voltage is applied to the gate electrode, a positive voltage is applied to the first conductivity type well, and an avalanche hot hole is injected into the insulating film side spacer to erase information.

  In addition, a leakage current cutoff element is provided that blocks leakage current from flowing to the power supply side of the flip-flop through the load transistor during writing.

  (2) A write selection transfer gate is provided between the input / output of the flip-flop and the write signal line (bit line), and a buffer circuit including a C-MOS inverter is provided at the input / output portion of the flip-flop.

  (3) The differential operation point of the flip-flop in a state in which the circuit configuration of the two series circuits connected to the static latch form constituting the flip-flop is asymmetric and the nonvolatile memory is not written / erased Is deviated in advance.

Typical effects of the invention disclosed in the present application are as follows.
[1] The characteristics of the non-volatile element obtained by making an offset structure on only one side of a transistor formed by a normal C-MOS process is poor in stability and reproducibility, and is likely to cause malfunction. According to the present invention, the operational stability is greatly improved by the flip-flop operation / structure of four transistors.

  [2] By enclosing the second conductivity type well in which the nonvolatile element is formed with the first conductivity type deep well (bottom well), the memory transistor is electrically isolated from the semiconductor substrate, and the nonvolatile memory It becomes possible to apply a potential to the second conductivity type well in the write / erase operation of the element, and the operation characteristics are improved.

  [3] Unnecessary leakage current does not flow to the power supply side of the flip-flop through the load transistor when writing to the nonvolatile memory, and a sufficient voltage can be supplied to the gate of the memory transistor to be written. Supply is unnecessary, and stable nonvolatile memory control is possible.

  [4] Since a buffer circuit including a C-MOS inverter is provided in the input / output section of the flip-flop, the state stored in the nonvolatile memory is always output (without being selected by a select signal or the like). It can be used as a so-called fuse.

  [5] The circuit configuration of the two series circuits connected to the static latch configuration constituting the flip-flop is made asymmetrical so that the differential operating point of the flip-flop in the state where writing and erasing are not performed in the nonvolatile memory is preliminarily displaced. By doing so, a predetermined state can be taken in the initial state of writing / erasing, and control program processing using this nonvolatile memory device becomes easy.

A nonvolatile memory device according to a first embodiment and a semiconductor integrated circuit device including the nonvolatile memory device will be described with reference to FIGS.
2A and 2B are circuit diagrams of the nonvolatile memory portion of the nonvolatile memory device. (A) is a circuit diagram of a nonvolatile memory portion according to the present invention, and (B) is a circuit diagram of a nonvolatile memory portion as a comparative example.

As shown to (A), it has a pair of series circuit of load transistor T11, T21 and storage transistor T12, T22, and they are connected to the static latch form, and comprise the flip-flop. Each of the storage transistors T12 and T22 is an N-type MOS transistor configured in a P-type well different from other N-type MOS transistors. A leakage current cutoff element T6, which is a P-type MOS transistor, is provided between the power supply side of the flip-flop and the power supply line VCC. A gate control signal PGATE line is connected to the gate of the leakage current cutoff element T6. A select line SL is connected to the memory transistor side of the flip-flop.

  Transfer gates T13 and T23, which are N-type (or P-type) MOS transistors, are provided between the two input / output portions of the flip-flop and the two bit lines BLT (BitLine-True) and BLB (BitLine-Bar), respectively. ing. A word line WL is connected to the gates of these transfer gates T13 and T23.

  Two input / output portions of the flip-flop are connected to C-MOS inverters INV1 and INV2, respectively, comprising P-type MOS transistors T14 and T24 and N-type MOS transistors T15 and T25. The power supply line VCC is connected to the power supply side of these inverters, and the output signal of the storage state of this nonvolatile storage device is taken out from one inverter INV2.

All of the N-type MOS transistors shown in FIGS. 2-1 and 2-2 are provided in the P-type well WP, and the P-type well is surrounded by the N-type well so as to be electrically independent. Connected to.
FIG. 2B is a configuration example in the case where the leakage current cutoff element T3 shown in FIG. 2A is not provided.

  FIG. 3 is a block diagram of the nonvolatile memory device shown in FIG. The storage transistors T12 and T22 shown in FIG. 2A constitute a nonvolatile storage means B1, and the load transistors T11 and T21 constitute a detection means B2. The leakage current interruption element T3 constitutes leakage current interruption means B3. Transfer gates T13 and T23 constitute selection means B4 and B5. The inverters INV1 and INV2 constitute reading means B6 and B7, respectively. This nonvolatile storage means B1 and detection means B2 constitute a flip-flop.

  FIG. 15 shows an example of voltages applied to the signal lines shown in FIGS. 2-1 and 2-2. In the configuration shown in FIGS. 2-1 and 2-2, when writing to the storage transistor T12, the voltage is applied to each signal line as shown in FIGS. 15 and 2-1 and 2-2. Apply.

  As shown in FIG. 2A, when the leakage current cut-off element T6 is not provided, a current flows in the path of SL → T12 → T13 → BLT during writing, and the drain of the writing transistor T12 passes through the insulating film side spacer. Channel hot electrons are injected and writing is performed. (The channel hot electron injection will be described later.) However, an unnecessary leak path is generated along the BLB → T23 → T21 → VCC path, and the high voltage supplied from the BLB leaks to the VCC, so that the memory transistor T12 A sufficient voltage cannot be supplied to the gate. In addition, an unnecessary current supply is required.

  Further, as shown in FIG. 2-2 (B), when the leakage current cut-off element T6 is not provided, at the time of erasing, the path of VCC (3V) → load transistor T11 → transfer gate T13 → BLT (−3V), and VCC Unnecessary leak paths occur in the path of (3V) → load transistor T21 → transfer gate T23 → BLB (−3V). Therefore, −3V of BLB and BLT cannot be supplied to the gates of the storage transistors T12 and T22, and reliable erasure cannot be performed.

  On the other hand, as shown in FIG. 2A, a leakage current cut-off element T6 is provided between the load transistors T11 and T21 of the flip-flop and the power supply VCC, and a high voltage (6V) is applied to the gate signal PGATE during writing / erasing. Is applied to turn off the leakage current cutoff element T6. As a result, all the unnecessary leak paths can be blocked.

4 to 6 are cross-sectional views of main parts showing the configuration of the memory transistor on the semiconductor substrate.
In FIG. 4, a deep N-type well 103 having a depth of 2 μm and an average phosphorus concentration of 1 × 10 ¹⁷ cm ⁻³ is arranged on the surface region of a P-type silicon substrate 101 having a resistivity of 10 Ωcm, and inside the deep N-type well 103. A P-type well 104 having a depth of 0.8 μm and an average boron concentration of 2 × 10 ¹⁷ cm ⁻³ is disposed. The P-type well 104 constitutes an N-channel transistor which is a memory element separated by a trench (element isolation) 102 having a depth of 250 nm. This N-channel transistor includes a gate oxide film 105 having a thickness of 5 nm, a gate electrode 106 made of a polysilicon film having a thickness of 200 nm and a phosphorus concentration of 2 × 10 ²⁰ cm ⁻³ , an average arsenic concentration of 5 × The drain extension 107 is formed of 10 ¹⁸ cm ⁻³ , the drain 109 and the source 115 each have an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ , and the insulating film side spacer 108 having a film thickness of 50 nm. Further, an N-type diffusion layer 110 having an average arsenic concentration of 1 × 10 ²⁰ cm ⁻³ for connection to the deep N-type well 103 and an average boron concentration of 1 × 10 ²⁰ cm ⁻ for connection to the P-type well 104. ^Three P-type diffusion layers 111 are arranged.

  Since the N-channel transistor as the storage transistor does not have an extension on the source side, the initial threshold voltage is 1.2V. This initial threshold voltage is due to the special structure of the transistor and varies greatly.

  FIG. 4 shows a voltage arrangement at the time of writing. In the write operation, 0V is applied to the N-type drain line VD, a positive voltage (6V) lower than the junction breakdown voltage is applied to the N-type source line VS, and channel hot electrons HE are injected into the insulating film side spacer 108. The threshold voltage is increased by trapped electrons (that is, a write state is obtained). The threshold voltage in the written state also depends on the special structure of the transistor and varies greatly.

  FIG. 5 shows an example of voltage arrangement at the time of reading. The read operation is performed by setting the N-type source line VS to 0 V and reading the voltage of the N-type drain line (VD) when a voltage 1.8 V lower than the write state threshold is applied to the gate line VG. . That is, when the drain line VD is 1.8V, it is regarded as a writing state, and when it is 0V, it is regarded as a non-writing state (erasing state).

  FIG. 6 shows a voltage arrangement at the time of erasing. In the erasing operation, a positive voltage (6V) lower than the junction breakdown voltage is applied to the N-type source line VS, a negative voltage (-3V) is applied to the gate line VG, and the avalanche hot hole HH is transferred from the N-type source to the insulating film side. By injecting into the spacer 108, the trapped hot electrons are neutralized to lower the threshold voltage.

Next, another configuration of the nonvolatile memory device according to the second embodiment is shown in FIG. 7 as a circuit diagram. In the example shown in FIG. 2A, the source sides of the two load transistors T11 and T21 are connected in common and connected to the power supply line VCC via one leakage current cutoff element T6. In the example shown in FIG. Two leakage current cutoff elements T16 and T26 are provided. The P-channel transistors T16, T26, T11, T21, T14, and T24 are configured as a common N-type well, and a voltage of 6 V (VP6) is applied to the N-type well.
In this way, two leakage current interrupting elements may be provided.

Next, the configuration of the non-volatile storage device according to the third embodiment will be described with reference to FIGS.
In the example shown in FIG. 2A or FIG. 7, the configuration of the circuit connected to the flip-flop is symmetric, but in each of the examples shown in FIGS. In the state where neither writing nor erasing is performed, the differential operating point of the flip-flop is previously deviated.

  In the example shown in FIG. 8, as indicated by V in the drawing, a circuit corresponding to the C-MOS inverter INV1 in FIG. 7 is not provided. As a result, the load weights of the input / output units in the left-right direction in the drawing of the flip-flop become unbalanced, and the differential operating point of the flip-flop is preliminarily displaced. That is, when the power is turned on without writing or erasing any of the two storage transistors T12 and T22, the capacity connected from the first input / output unit P1 to the second input / output unit P2 of the flip-flop is increased. Since it is large, the potential of P1 rises more quickly than P2, and T11 and T22 are turned on and T12 and T21 are turned off and stabilized.

  In the example shown in FIG. 9, the channel widths of the two load transistors T11 and T21 are unbalanced. In this example, the channel width of the load transistor T11 is set to be twice the channel width of the load transistor 21, and the resistance value when the load transistor T11 is ON is halved compared to T21. Therefore, when the power is turned on in a state where both of the storage transistors T12 and T22 are not stored / erased, the potential rise of P1 is faster than that of P2, and similarly to the case of FIG. ON state, T12 and T21 are OFF and stable. Note that the channel length may be unbalanced instead of the above channel width unbalance.

  In the example shown in FIG. 10, a capacitor is connected to each of the two input / output units P1 and P2 of the flip-flop. In this example, a capacitor C11 is provided between P1 and the power supply line VCC, and a capacitor C22 is provided between P2 and the ground. The capacitance of these capacitors is about 50 fF, for example.

  As a result, if the power is turned on in a state where neither of the memory transistors T12 and T22 is written / erased, the potential rise at the P1 point immediately after the power is turned on becomes faster and the potential rise at the P2 point becomes slower. , T11, T22 are in the ON state, and T12, T21 are in the OFF state, so that it is stable.

  In the example shown in FIG. 10, a capacitor is connected to both P1 and P2, but the circuit connected to the flip-flop can be made asymmetric even if only one is connected.

  In the example shown in FIG. 11, the channel widths of the leakage current cutoff elements T16 and T26 are unbalanced without commonly connecting the source sides of the two load transistors T11 and T21. In this example, the channel width of T16 is doubled compared to T26, and the resistance value at the time of ON is halved. Therefore, if the power is turned on while neither of the two storage transistors T12, T22 is written or erased, the potential rise at the point P1 is faster than the point P1 immediately after the power is turned on. The states T12 and T21 are in the OFF state and become stable. Note that the channel length may be unbalanced instead of the above channel width unbalance.

  Next, FIG. 12 is a circuit diagram showing the configuration of the nonvolatile memory device according to the fourth embodiment. The fourth embodiment also shows an example in which the configuration of the circuit connected to the flip-flop is asymmetric. In the example of FIG. 12A, a capacitor C12 is provided between P1 and the ground without connecting a C-MOS inverter to one input / output unit P1 of the flip-flop, and C− is connected to the other input / output unit P2. A capacitor C21 is provided between the MOS inverter INV2 and the power supply line VCC.

  In this way, the asymmetric structure shown in the third embodiment may be combined. As a result, the differential operating point of the flip-flop can be largely deviated in advance by the synergistic effect of asymmetry.

  In the example shown in FIG. 12B, the transfer gates T13 and T23 in FIG. 12A are both configured by P-channel transistors.

  If the transfer gates T13 and T23 are N-channel transistors as shown in FIG. 12A, the threshold voltage rises by the threshold voltage, but the potential rise at points P1 and P2 after power-on is delayed. If the transfer gates T13 and T23 are formed of P-channel type transistors, the T13 and T23 pass 6V applied to the bit lines BLT and BLB through the input / output parts P1 and P2 of the flip-flop as they are. The potential increase at the subsequent points P1 and P2 can be accelerated, and the time from when the power is turned on until an appropriate output is obtained can be shortened.

Next, the configuration of the RFID chip according to the fifth embodiment will be described with reference to FIG.
FIG. 13 is a circuit block of an RFID chip on which the nonvolatile memory device according to the present invention is mounted. An antenna L disposed outside the chip is connected to the pads P1 and P2 in order to receive an RF signal transmitted from an external reader. A power supply capacitor CT having a capacitance of 120 pF, a voltage clamp circuit (Voltage Clamp), a power supply modulator (Modulator), and a bridge rectifier (Bridge Rectifier) are connected between the pads P1 and P2. A power supply stabilization capacitor CF is connected to the output of the bridge rectifier, and a control signal of a voltage regulator (Regulator) for detecting the output voltage is fed back to the voltage clamp circuit to stabilize the power supply voltage. The output of the bridge rectifier is connected to a Vcc detection circuit (Vcc Detector) that generates an internal power supply voltage (Vcc) and a booster circuit (Vpp Generator) that generates various voltages other than Vcc. The output of the bridge rectifier includes a circuit (Mode Selector) for detecting an operation mode included in the RF signal received by the bridge rectifier, a clock detection circuit (Clock Extractor), and a nonvolatile memory device module (EEPROM). A circuit (Data Modulator) that takes out the data written to is provided. The controller receives the operation mode data and controls the operation of the module (EEPROM) of the nonvolatile memory device.

  The module (EEPROM) of the non-volatile storage device mounted on the RFID chip has an ID number for chip authentication, an address for courier service, and product information (price, date of production, production location, production) that replaces the barcode. The required information (e.g. flight number, owner name, boarding place, destination).

Next, the configuration of the system LSI repair nonvolatile memory according to the sixth embodiment will be described with reference to FIG.
FIG. 14 is a schematic chip plan view of a system LSI which is an example of a semiconductor integrated circuit device according to the present invention. The system LSI shown in the figure is not particularly limited, but a large number of external connection electrodes 120 such as bonding pads are arranged on the periphery of the semiconductor substrate, and an external input / output circuit 121 and an analog input / output circuit 122 are provided inside thereof. Yes. The external input / output circuit 121 and the analog input / output circuit 122 use an external power supply having a relatively high level such as 3.3V as an operation power supply. The level shift circuit 123 steps down the external power supply to an internal power supply voltage such as 1.8V. Inside the level shift circuit 123 are a static random access memory (SRAM) 124, a central processing unit (CPU) 125, a cache memory (CACH) 126, a logic circuit (Logic) 127, and a phase locked loop circuit ( PLL) 128, an analog / digital conversion circuit (ADC) 129, a digital / analog conversion circuit (DAC) 130, and a system controller (SYSC) 131. Reference numerals 132, 133, and 134 denote electrically erasable and writable nonvolatile memories (EEPROMs), respectively, each having a predetermined capacity of the nonvolatile memory device of the present invention.

  The nonvolatile memory 132 is used for storing relief information (control information for replacing defective memory cells with redundant memory cells) of the SRAM 124.

  The nonvolatile memory 133 is used for storing information for specifying the circuit constant of the constant trimming circuit for adjusting the circuit constant of the analog circuit, or for storing trimming data of the oscillation frequency of the analog circuit. Further, it is used for storing information for specifying the reference voltage of the voltage trimming circuit, and is mounted in place of the relief program circuit by the fuse.

  The nonvolatile memory 134 has a memory capacity of 256 bits and is used for storing chip ID information, chip operation mode information, and desired data.

It is a figure which shows the structure of the non-volatile memory device by a prior art. 1 is a circuit diagram of a nonvolatile memory device according to a first embodiment. FIG. FIG. 3 is a circuit diagram of a nonvolatile memory device as a comparative example of the nonvolatile memory device according to the first embodiment. FIG. 2 is a block diagram of the nonvolatile memory device shown in FIG. It is a fragmentary sectional view showing the composition on the semiconductor substrate of the memory transistor used for the nonvolatile memory device, and is a figure showing voltage arrangement at the time of writing. It is a fragmentary sectional view which shows the structure on the semiconductor substrate of the memory transistor used for the non-volatile memory | storage device, and is a figure which shows the voltage arrangement | positioning at the time of read-out. It is a fragmentary sectional view which shows the structure on the semiconductor substrate of the memory transistor used for the non-volatile memory device, and is a figure which shows the voltage arrangement at the time of erasing. It is a circuit diagram which shows the structure of the non-volatile memory device which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the non-volatile memory device which concerns on 3rd Embodiment. It is a circuit diagram which shows the other structure of the non-volatile memory device which concerns on 3rd Embodiment. It is a circuit diagram which shows the other structure of the non-volatile memory device which concerns on 3rd Embodiment. It is a circuit diagram which shows the other structure of the non-volatile memory device which concerns on 3rd Embodiment. It is a circuit diagram which shows the structure of the non-volatile memory device which concerns on 4th Embodiment. It is a figure which shows the structure of the RFID chip which concerns on 5th Embodiment. FIG. 10 is a schematic plan view of a system LSI chip according to a sixth embodiment. It is a figure which shows the example of the voltage applied to each signal line shown to FIGS. 2-1 and 2-2.

Explanation of symbols

101-P type silicon substrate (second conductivity type semiconductor substrate)
102-trench 103-deep N type well (first conductivity type deep well)
104-P type well (second conductivity type well)
105-gate oxide film 106-gate electrode 107-drain extension 108-insulating film side spacer 109-drain 110-N-type diffusion layer 111-P-type diffusion layer 115-source T11, T21-load transistor T12, T22-memory transistor T13 , T23-Transfer gate INV1, INV2- Inverter (buffer circuit)
T6, T16, T26-Leakage current blocking element WP-P type well WN-N type well HE-channel hot electron HH-avalanche hot hole VDN-deep N type well line VS-source line VD-drain line VG-gate line

Claims (13)

Provided on a semiconductor substrate is a non-volatile memory having a flip-flop formed by connecting a series circuit of a load transistor and a memory transistor and connecting them in a static latch form, and a driving circuit for driving the non-volatile memory A non-volatile storage device,
The semiconductor substrate is of a second conductivity type, and includes a first conductivity type deep well in the semiconductor substrate, and a second conductivity type well in the first conductivity type deep well,
The memory transistor has a source / drain of the first conductivity type in the well of the second conductivity type, and has a gate electrode above the channel between the source / drain through a gate insulating film, and the gate An LDD structure having an insulating film side spacer on a side portion of the electrode and having a low-concentration region having a low impurity concentration at a junction portion with respect to the second conductivity type well on the drain side, The junction with the two conductivity type well is a structure in which the low concentration region of the LDD structure portion is not formed,
The drive circuit applies a positive voltage to the gate electrode and the source with respect to the drain of the memory transistor, injects channel hot electrons into the insulating film side spacer, and writes information to the source. A circuit for erasing information by applying a negative voltage to the gate electrode, applying a positive voltage to the first conductivity type well, and injecting avalanche hot holes into the insulating film side spacer,
The nonvolatile memory device includes a leakage current interrupting element connected to a current path through which a leakage current flows to the power supply side of the flip-flop via the load transistor during writing / erasing.   2. A write selection transfer gate transistor is provided between an input / output portion of the flip-flop and a write signal line, and a buffer circuit including a C-MOS inverter is provided at the input / output portion of the flip-flop. The non-volatile memory device described in 1.   3. The differential operation point of the flip-flop in a state in which writing and erasing are not performed in the nonvolatile memory is preliminarily deviated by making the configuration of the circuit connected to the flip-flop asymmetric. The non-volatile memory device described in 1.   The nonvolatile memory device according to claim 3, wherein the differential operation point of the flip-flop is shifted by providing the buffer circuit only in one of two input / output units of the flip-flop.   4. The nonvolatile memory device according to claim 3, wherein the differential operation point of the flip-flop is shifted by unbalanced the length or width of the channel of the load transistor included in each of the pair of series circuits.   The non-volatile memory device according to claim 3, wherein the differential operating point of the flip-flop is shifted by unbalanced additional capacitances for the two input / outputs of the flip-flop.   The leakage current cut-off element is connected to each load transistor included in the pair of series circuits, and the differential operating point of the flip-flop is set by unbalanced the length or width of the channel of the leak current cut-off element. The nonvolatile memory device according to claim 3, wherein the nonvolatile memory device is biased.   8. A nonvolatile memory device according to claim 1, comprising a repaired circuit and a repair circuit that replaces the repaired circuit, wherein the repair circuit replaces the nonvolatile memory device. A semiconductor integrated circuit device which is a storage circuit for repair information for specifying a circuit to be repaired.   9. The semiconductor integrated circuit device according to claim 8, wherein the circuit to be relieved is a memory cell array built in a RAM.   A non-volatile memory device according to claim 1, an analog circuit, and a constant trimming circuit that adjusts a circuit constant thereof, wherein the non-volatile memory circuit is included in the constant trimming circuit. A semiconductor integrated circuit device as an information storage circuit for specifying a circuit constant.   8. A nonvolatile memory device according to claim 1, an oscillation circuit, and a frequency trimming circuit that adjusts an oscillation frequency thereof, wherein the nonvolatile memory circuit is connected to the frequency trimming circuit. A semiconductor integrated circuit device as an information storage circuit for specifying an oscillation frequency.   A non-volatile memory device according to claim 1, a reference voltage generating circuit, and a voltage trimming circuit for adjusting the generated reference voltage, wherein the non-volatile memory circuit is the voltage A semiconductor integrated circuit device as an information storage circuit for specifying the reference voltage of the trimming circuit.   A non-volatile memory device according to claim 1, and a security circuit for specifying a chip, wherein the non-volatile memory circuit includes information for specifying a chip of the security circuit. A semiconductor integrated circuit device as a memory circuit.

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